Test system and method for chip aging test based on FPGA

Abstract

The application discloses a test system and method for chip aging test based on FPGA, and relates to the technical field of chip aging test.The test system comprises a host computer, an FPGA core board and a chip to be tested, the FPGA core board is directly connected with the chip to be tested through a slot of pin-to-pin, supports IO and read-write operation on internal registers of the chip; the host computer takes a test excitation file as an input file of an excitation module; the FPGA core board inputs test excitation data of the aging test to a chip PAD end through an IO pin according to the input file to directly test excitation; the test excitation data of the aging test comprises external test excitation data used in a scene of externally connecting a load device of the chip, at this time, the FPGA core board replaces the externally connecting load device to apply excitation to the chip to be tested.The application effectively solves the problem of complex aging test environment construction while solving the problems of too long aging test time and test reliability.

Description

Technical Field

[0001] This invention relates to the field of chip aging test technology, and in particular to a test system and method for chip aging test based on FPGA. Background Technology

[0002] With the continuous development of communication technology, semiconductor chips are widely used in numerous fields. During the early manufacturing stages of semiconductor chips, including packaging, some unavoidable minor defects may be introduced. These defects may be exposed after the product is delivered to the user, affecting the chip's reliability. This situation is becoming increasingly common as the scale and complexity of chip circuits increase. To improve chip reliability, burn-in testing is required before mass production. Burn-in testing is one of the important inspection processes before chips leave the factory. Its purpose is to evaluate the chip's reliability and stability under long-term use and load conditions to determine its reliability and stability indicators. Burn-in testing typically uses high temperature and high voltage to expose defective products at an early stage (accelerating the exposure of internal defects), thereby eliminating products that may have early defects.

[0003] Traditional aging tests are generally performed by automated test equipment (ATE) or specially designed aging test equipment (with voltage and temperature stress capabilities). They mainly use electrical excitation (such as providing test excitation voltage) to accelerate the testing of chip electrical faults under high temperature conditions. They evaluate the reliability and lifespan of the chip by simulating the working environment and stress conditions of the chip in actual application. During the test, test sockets (corresponding to the chip) and external related sensors are used on the actual working circuit board. The chip's test qualification is determined by collecting feedback data from the chip. However, although testing via ATE (Automatic Test Equipment) machines offers comprehensive coverage, it suffers from the following drawbacks: 1) Full-temperature testing takes an excessively long time, often requiring tens of hours; 2) Aging tests involve numerous steps, typically requiring external test stimulus circuits and the connection of actual test sensors and measuring devices to simulate the chip's operation in real-world application scenarios, thereby evaluating its performance and reliability. This increases the complexity of setting up the aging test environment, and the degree of automation is difficult to guarantee. Consequently, the efficiency and reliability of chip aging tests are significantly compromised. For instance, sometimes malfunctions in external test stimulus or unreliable connections lead to incorrect aging test results, wasting valuable test resources (ATE machines are relatively expensive) and reducing the accuracy and timeliness of chip selection.

[0004] Accordingly, to improve the reliability and efficiency of chip aging tests, existing technologies have proposed optimized designs for chip aging tests. Among these, FPGAs (Field Programmable Gate Arrays), due to their excellent real-time control and data acquisition capabilities, have been applied in chip aging tests as a test and control module for control adjustment and data acquisition, accelerating test time. For example, Chinese patent application CN202310184334.8 discloses a semiconductor device aging test control system, comprising: a host computer for sending control commands and acquiring aging status information of semiconductor devices; a motherboard for forwarding aging status information and control commands, including a master control unit and a slave control unit, the master control unit communicating with the host computer and connected to the slave control unit via a communication interface, the master control unit using an FPGA logic chip for programming and designing a communication interface controller IP core; and a slave computer connected to the slave control unit for acquiring aging status information of the semiconductor device under test and controlling the corresponding semiconductor device according to control commands; the slave computer includes a communication unit that communicates with the corresponding semiconductor device. The aforementioned system connects to the slave control unit via an expanded communication interface using an FPGA logic chip. The slave control unit then connects to the lower-level machine, which in turn connects to the semiconductor device under test via a communication unit. This improves the scalability and versatility of the semiconductor device aging test control system. However, this approach requires cooperation between the host and slave computers, and the communication between the host and slave computers, as well as between the slave computer and the semiconductor device, introduces high communication costs to the aging test.

[0005] For example, Chinese patent application CN202310286184.1 discloses a chip aging test system, including: a main control chip (specifically an FPGA chip); a power supply component including a power chip that receives power supply commands sent by the main control chip and supplies power to the chip under test according to the power supply commands; a temperature control component including a temperature control chip that receives temperature measurement commands sent by the main control chip, measures the temperature of the chip under test according to the temperature measurement commands, and returns the measured temperature data to the main control chip; and a temperature adjustment device that receives adjustment commands sent by the main control chip and adjusts the temperature of the chip under test in response to the adjustment commands; and a data transmission component including a level conversion circuit that sends the test data sent by the main control chip to the chip under test for aging test. The above system solves the problem of low efficiency caused by the need for manual monitoring and adjustment in chip aging tests. However, the communication between the main control chip and the chip under test through the power supply component, temperature control component, and data transmission component still has the disadvantage of high communication cost, and the configuration and operation of the above components increase the complexity of setting up the aging test environment.

[0006] In summary, when designing a chip aging test system using FPGA, the urgent technical problem to be solved is how to balance improving the reliability and efficiency of aging tests while reducing the complexity of setting up the aging test environment. Summary of the Invention

[0007] The purpose of this invention is to overcome the shortcomings of existing technologies and provide a test system and method for chip aging testing based on FPGA. The chip aging test system provided by this invention includes a host computer and an aging test environment. The aging test environment includes an FPGA core board and a chip under test (DUT). The FPGA and DUT are directly connected via slots to avoid poor contact. Test stimulus data can be directly input into the DUT's PAD pins through the FPGA core board's I / O pins. Furthermore, when the test stimulus data includes external test stimulus data for scenarios involving external load devices, the FPGA core board can replace the external load device to apply the aforementioned external test stimulus data to the DUT to simulate communication between the external load device and the DUT. Thus, by using an FPGA stimulus module to replace the actual connected external load device for aging testing, the problems of excessively long aging test times and reliability are solved, while also effectively addressing the complexity of environment setup in current aging test processes.

[0008] To achieve the above objectives, the present invention provides the following technical solution: A test system based on FPGA for chip aging test is provided. The test system includes a host computer and an aging test environment. The aging test environment includes an FPGA core board and a chip under test (DUT). The FPGA core board serves as the excitation module for chip aging test, which applies test excitation to the DUT. The FPGA core board is directly connected to the DUT via pin-to-pin slots, supporting input / output I / O and read / write operations on the chip's internal registers. The host computer is configured to: generate a test stimulus file required for chip aging test, and use the test stimulus file as an input file for the stimulus module; the test stimulus file contains the test stimulus data for aging test; The FPGA core board is configured to: input the aging test stimulus data to the chip PAD terminal of the chip under test through the IO pin of the FPGA core board according to the input file, so as to directly apply test stimulus to the chip under test; wherein, the aging test stimulus data includes external test stimulus data for the scenario of chip external load device, in which case the FPGA core board acts as an external load device to apply the aforementioned external test stimulus data to the chip under test to simulate the communication interaction between the external load device and the chip under test.

[0009] Furthermore, the test stimulus file is generated by converting the pattern test file of the ATE machine, and the host computer is configured as follows: Obtain the ATE machine pattern test file for aging testing; The ATE instrument pattern test file is converted to obtain a synthesizable Verilog file for aging tests; The synthesizable Verilog file is subjected to netlist synthesis and place-and-route (PR) processing to obtain a binary bitfile file for aging tests. The binary bitfile is burned onto the aforementioned FPGA core board, enabling the FPGA core board to act as an external test load device to apply test stimuli to the chip under test.

[0010] Furthermore, the FPGA core board is also configured to: after completing the transmission of test stimulus data, read the actual state parameters of the chip under test according to the test requirements, compare the actual state parameters with the preset theoretical state parameters, and display the test results of the aging test based on the comparison results.

[0011] Furthermore, the FPGA core board, acting as an external load device, applies external test stimulus data to the chip under test, including test stimulus data for I / O testing, test stimulus data for clock testing, and test stimulus data for register testing. The register testing includes register read / write operation testing.

[0012] Furthermore, the data configuration for IO is performed in the synthesizable Verilog file. The IO can be configured as input, output, or inout type. By configuring different IO values ​​in the synthesizable Verilog file, the chip under test can be set to different functional test modes.

[0013] Furthermore, external crystal oscillator information is input into the clock management module of the FPGA core board for clock configuration, and clock signals of different frequencies are input to the relevant PAD terminals of the chip under test through the IO ports of the FPGA core board to simulate the actual operation process by using PLL frequency division.

[0014] Furthermore, the chip under test has reserved register read / write ports. The enable bits, read / write address bits, and data bits of the registers are configured through the ports. The relevant timing information of the read / write operations is configured in the synthesizable Verilog file. When test stimuli are applied, the FPGA core board performs read / write operations on the internal registers of the chip under test.

[0015] Furthermore, the test system is configured with multiple FPGA core boards of different models, and also includes an FPGA optional module, which is configured as follows: Obtain the functional test resource information of the chip under test, determine the level of test resources based on the functional test resource information of the chip under test, select the model of the FPGA core board for aging test of the chip under test based on the level of test resources, and ensure that the computing resources provided by the selected FPGA core board can cover the functional test resource level of the chip under test.

[0016] This invention also provides a method for FPGA-based chip aging testing, comprising the following steps: An aging test environment is set up, which includes an FPGA core board and a chip under test. The FPGA core board serves as the excitation module for chip aging test, which applies test excitation to the chip under test. The FPGA core board is directly connected to the chip under test through pin-to-pin slots, supporting input / output I / O and read / write operations on the chip's internal registers. The aging test environment receives the test stimulus file sent by the host computer and uses the test stimulus file as the input file of the stimulus module; the test stimulus file contains the test stimulus data for the aging test. According to the input file, the FPGA core board inputs the test stimulus data of the aging test to the chip PAD terminal of the chip under test through the IO pin, so as to directly apply the test stimulus to the chip under test; when the test stimulus data of the aging test includes external test stimulus data for the scenario of chip external load device, the FPGA core board acts as an external load device to apply the aforementioned external test stimulus data to the chip under test to simulate the communication interaction between the external load device and the chip under test.

[0017] Furthermore, the test stimulus file is generated by converting the pattern test file of the ATE machine, and also includes a simulation step for aging test based on the pattern test file of the ATE machine, as follows: Update the pattern test file used by the ATE machine according to the test stimulus requirements of chip aging test; Obtain the updated ATE instrument pattern test file for aging test, convert the ATE instrument pattern test file into a simulation testbench file through a script, instantiate the chip under test in the simulation testbench file, and use the simulation testbench file for aging test simulation. Run the simulation tool to compile and run the simulation testbench file to obtain the aging test simulation results; The simulation results of the aging test are compared with the actual aging test results of the chip under test, and the comparison results are output.

[0018] Compared with existing technologies, this invention, by adopting the above technical solution, has the following advantages and positive effects, as an example: The chip aging test system provided by this invention includes a host computer and an aging test environment. The aging test environment includes an FPGA core board and a chip under test (DUT). The FPGA end and the DUT end are directly connected via slots, avoiding poor contact. Test stimulus data can be directly injected into the PAD end of the DUT through the IO pins of the FPGA core board. Simultaneously, when the test stimulus data includes external test stimulus data for scenarios involving external load devices, the FPGA core board can replace the external load device to apply the aforementioned external test stimulus data to the DUT to simulate the communication interaction between the external load device and the DUT. Thus, by using an FPGA stimulus module to replace the actual connected external load device for aging testing, the problems of excessively long aging test time and test reliability are solved, while also effectively addressing the problem of complex environment setup in current aging test processes.

[0019] Furthermore, the test stimulus file is preferably generated by converting the pattern test file of the ATE machine. A simulation method for aging testing based on the pattern test file of the ATE machine is also provided, and the obtained aging test simulation results are compared with the chip aging test results. The aging test environment is simplified and the stimulus signal is traceable through multiple dimensions.

[0020] As needed, a user interface can be set for the corresponding test stimulus file (which can be synthesized Verilog file) and simulation stimulus file (testbench file). Through the user interface, users can modify the test stimulus file and simulation stimulus file online, thereby simulating various external load scenarios of the chip according to actual test needs. This further improves the flexibility and applicability of the test system and can meet the needs of various chip aging tests. Attached Figure Description

[0021] Figure 1 The diagram shows the module connection of a test system based on FPGA for chip aging testing, as provided in an embodiment of the present invention.

[0022] Figure 2 This is a logic diagram for information processing in chip aging tests provided in an embodiment of the present invention.

[0023] Figure 3 A flowchart of a method for chip aging test based on FPGA provided in an embodiment of the present invention. Detailed Implementation

[0024] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed account of the FPGA-based chip aging test system and method disclosed in this invention. It should be noted that techniques (including methods and apparatus) known to those skilled in the art may not be discussed in detail, but where appropriate, such known techniques are considered part of the specification. Furthermore, other examples of exemplary embodiments may have different values. The structures, proportions, sizes, etc., depicted in the accompanying drawings are merely illustrative of the content disclosed in this specification for the understanding and reading of those skilled in the art, and are not intended to limit the conditions under which the invention can be implemented.

[0025] In the description of the embodiments of this application, " / " means "or", and "and / or" is used to describe the relationship between related objects, indicating that there can be three relationships. For example, "A and / or B" means: A and B exist alone, B exists alone, and A and B exist simultaneously. In the description of the embodiments of this application, "multiple" refers to two or more. Example

[0026] See Figure 1 As shown, this invention provides a test system for chip aging testing based on a programmable gate array (FPGA). The test system includes a host computer and an aging test environment. The host computer is preferably a sampling PC (personal computer), see [link to documentation]. Figure 1 The PC shown.

[0027] The aging test environment includes an FPGA terminal and a chip terminal, respectively corresponding to... Figure 1 The FPGA core board and the chip under test.

[0028] The FPGA core board serves as the excitation module for chip aging testing, applying test stimuli to the chip under test (DUT). In this embodiment, the FPGA core board is directly connected to the DUT via pin-to-pin slots, supporting input / output I / O and read / write operations to the chip's internal registers.

[0029] The host computer is configured to generate a test stimulus file required for chip aging test and use the test stimulus file as an input file for the stimulus module; the test stimulus file contains the test stimulus data for aging test.

[0030] The FPGA core board is configured to: input the aging test stimulus data to the chip PAD terminal of the chip under test through the FPGA core board's IO pins, according to the input file, so as to directly apply test stimuli to the chip under test. The aging test stimulus data includes external test stimulus data for scenarios involving external load devices. In this case, the FPGA core board acts as an external load device, applying the aforementioned external test stimulus data to the chip under test to simulate the communication interaction between the external load device and the chip under test.

[0031] Thus, by replacing the actual external load device with an FPGA excitation module, the workload of the chip under test (DUT) in real-world application scenarios can be simulated, as well as the communication and interconnection scenarios between the DUT and external load devices (such as external sensors, peripheral devices, or other chips). This allows for a comprehensive evaluation of the DUT's performance and reliability. During testing, the FPGA core board follows the DUT in an aging test environment. A series of input excitation signals are applied through the FPGA core board, and data monitoring and recording are provided to obtain relevant data—such as key parameters and performance indicators. This data is used to analyze the chip's performance in the aging test and assess its reliability. The FPGA's abundant logic resources and extremely high response speed can meet the application scenarios of repeatedly executing I / O configuration and register read / write operations.

[0032] In this embodiment, the test stimulus file is generated by converting the pattern test file of the ATE (Automatic Test Equipment). The pattern test file is used to screen whether the chip's functions meet the design requirements. The pattern test file can simulate the actual chip test function stimulus, or it can simulate the actual communication interaction between the chip and the external load device.

[0033] The test stimuli required for the aging test of the chip under test (DUT) are first collected on the PC. The PC uses a script to convert the acquired ATE (Automatic Test Equipment) pattern test file into a synthesizable Verilog file, which serves as the test stimulus file for aging testing. Then, an EDA (Electronic Design Automation) tool performs synthesis and placement and routing (PR) processing on the synthesizable Verilog file to obtain a binary bitfile for aging testing. This binary bitfile is then burned onto the FPGA core board. When the test stimuli include test stimulus data for an external load, the corresponding binary bitfile is burned onto the FPGA core board. The FPGA core board then functions as a load device that can be connected to the chip. Thus, the FPGA core board, instead of the actual external load device, applies test stimuli to the DUT and performs testing alongside the DUT in the aging test environment.

[0034] See Figure 2 As shown, the PC is configured to: acquire the ATE (Automatic Test Equipment) pattern test file for aging testing; convert the ATE pattern test file using a script to obtain a synthesizable Verilog file for aging testing, wherein the Verilog file is a synthesizable code file based on the synthesizable Verilog language; perform netlist synthesis and place-and-route (PR) processing on the synthesizable Verilog file to obtain a binary bitfile file for aging testing, for example, using the synthesis tool Synplify and the PR tool Vivado; and burn the binary bitfile file onto the aforementioned FPGA core board, enabling the FPGA core board to act as an external test load device to apply test stimuli to the chip under test. The script is preferably a Python script.

[0035] In this embodiment, the FPGA core board can also be configured to: after sending the test stimulus data, read the actual state parameters of the chip under test according to the test requirements, compare the actual state parameters with the preset theoretical state parameters, and display the aging test results based on the comparison results. This is an example, not a limitation; for instance, the test results may include PASS and FAIL, representing test pass and test failure, respectively. In specific implementation, the status indicator LEDs on the FPGA core board can be controlled to display the results intuitively, thus facilitating user judgment of the aging test results.

[0036] When using an FPGA core board instead of an external load device for aging testing as a stimulus test module, various test stimulus data are sent to the chip under test, including I / O data configuration, clock configuration, and read / write control related data. In this case, the corresponding test stimulus data types are test stimulus data for I / O testing, test stimulus data for clock testing, and test stimulus data for register testing. The register testing can include register read / write operation testing.

[0037] Specifically, I / O data can be configured in the synthesizable Verilog file. The I / O can be configured as input, output, or inout type. By configuring different I / O values—such as logic 1 and logic 0—in the synthesizable Verilog file, the chip under test can be set to different functional test modes.

[0038] Meanwhile, external crystal oscillator information is input into the clock management module of the FPGA core board for clock configuration, and clock signals of different frequencies are fed into the relevant PAD terminals of the chip under test through the IO ports of the FPGA core board by PLL frequency division. This part is mainly used for the actual external crystal oscillator port of the chip, and the actual operation process is simulated by the clock input of the FPGA core board.

[0039] The chip under test (DUT) has reserved register read / write ports. The enable bits, read / write address bits, and data bits of the registers are configured through these ports. The relevant timing information for the read / write operations is configured in the synthesizable Verilog file. When test stimuli are applied, the FPGA core board performs read / write operations on the internal registers of the DUT. The internal register read / write operations can be implemented using a pre-defined specific protocol, which is existing technology and will not be elaborated upon here.

[0040] In another embodiment of this invention, the test system may be configured with multiple FPGA core boards of different models. In this case, the system may also include an FPGA selection module. The FPGA selection module is configured to perform the following steps: obtain the functional test resource information of the chip under test; determine the level of test resources based on the functional test resource information of the chip under test; select the model of the FPGA core board used for the aging test of the chip under test based on the level of test resources, wherein the computing resources provided by the selected FPGA core board can cover the level of functional test resources of the chip under test.

[0041] In this way, the FPGA model of the core board in the system can be selected according to the functional size of the chip under test being tested, and a model that can cover the level of chip functional test resources can be selected.

[0042] In another embodiment of this example, see below. Figure 2 As shown, the host computer can also be configured to: convert the ATE machine pattern test file used for aging test into a simulation testbench file through a script; instantiate the chip under test in the simulation testbench file; the simulation testbench file is used for aging test simulation; and run a simulation tool to compile and run the simulation testbench file, obtain the aging test simulation results, compare the aging test simulation results with the actual aging test results of the chip under test, and output the comparison results.

[0043] In this way, the aging test scheme is simplified and the signal traceability is made through both forward and reverse dimensions. Furthermore, the test stimulus file (which can synthesize Verilog files) and simulation stimulus file (testbench file) can be modified online through the user interface of the system settings to simulate the chip being subjected to different load stimuli, thereby meeting various chip aging test requirements.

[0044] Preferably, users can also debug, compile, and distribute test stimulus files (which can be integrated with Verilog files) online through the user interface, and burn the debugged test stimulus files to the stimulus module.

[0045] Another embodiment of the present invention also provides a method for chip aging testing based on FPGA. See [link to relevant documentation] Figure 3 As shown, the method includes the following steps.

[0046] S100, setting up an aging test environment, which includes an FPGA core board and a chip under test. The FPGA core board serves as the excitation module for chip aging test, used to apply test excitation to the chip under test. The FPGA core board is directly connected to the chip under test through pin-to-pin slots, supporting input / output I / O and read / write operations on the chip's internal registers.

[0047] S200, the aging test environment receives the test stimulus file sent by the host computer and uses the test stimulus file as the input file of the stimulus module; the test stimulus file contains the test stimulus data for aging test.

[0048] S300, according to the input file, the FPGA core board inputs the aging test test stimulus data to the chip PAD terminal of the chip under test through the IO pin to directly apply test stimulus to the chip under test; when the aging test test stimulus data includes external test stimulus data for the scenario of chip external load device, the FPGA core board acts as an external load device to apply the aforementioned external test stimulus data to the chip under test to simulate the communication interaction between the external load device and the chip under test.

[0049] Preferably, the test stimulus file is generated by converting the pattern test file of the ATE machine. In this case, a simulation step of aging test based on the pattern test file of the ATE machine may also be included, specifically as follows: S410 updates the pattern test file used by the ATE machine according to the test stimulus requirements of the chip aging test. That is, the pattern test file used by the ATE machine is updated to meet the stimulus requirements of the aging test. Preferably, it mainly performs repeated function triggering, I / O port control and register read and write operations on the chip under test to simulate the long-term working conditions of the chip under test.

[0050] S420: Obtain the updated ATE instrument pattern test file for aging test, convert the ATE instrument pattern test file into a simulation testbench file through a script, instantiate the chip under test in the simulation testbench file (instantiate the chip under test as a module and configure the connection according to the interface signal), the simulation testbench file is used for aging test simulation, and the simulation testbench file directly injects the excitation signal into the chip under test.

[0051] S430, run a simulation tool (such as VCS tool) to compile and run the simulation testbench file to obtain the aging test simulation results.

[0052] S440, compare the aging test simulation results with the actual aging test results of the chip under test, and output the comparison results.

[0053] Based on the simulation results, users can intuitively view the signal states and waveforms inside the chip under test, and compare the simulation results with the previously obtained aging test results. If the comparison is consistent, the aging test simulation is determined to be consistent with the aging test results; if the comparison is inconsistent, the simulation results can provide a reference for the actual aging test.

[0054] In this embodiment, the modification information of the test stimulus file (synthesizable Verilog file) and the simulation stimulus file (testbench file) by the user can also be collected through the user interface, and the synthesizable Verilog file and the simulation testbench file can be updated according to the modification to simulate the application scenario of the chip being connected to different load stimuli, which can flexibly meet various chip aging test needs.

[0055] Other technical features are described in the preceding embodiments and will not be repeated here.

[0056] In the above description, the disclosure of this invention is not intended to limit itself to these aspects. Rather, within the scope of the objectives of this disclosure, components can be selectively and operationally combined in any number. Furthermore, terms such as “comprising,” “encompassing,” and “having” should be interpreted by default as inclusive or open-ended, rather than exclusive or closed, unless explicitly defined as such. All technical, scientific, or other terms are to be understood by those skilled in the art, unless defined as such. Public terms found in dictionaries should not be interpreted in the context of the relevant technical documents in an overly idealistic or impractical manner, unless explicitly defined as such in this disclosure. Any modifications or alterations made by those skilled in the art based on the foregoing disclosure are within the scope of the claims.

Claims

1. A test system based on FPGA for chip aging testing, characterized in that: The system includes a host computer and an aging test environment. The aging test environment includes an FPGA core board and a chip under test (DUT). The FPGA core board serves as the excitation module for chip aging testing, applying test stimuli to the DUT. The FPGA core board is directly connected to the DUT via pin-to-pin slots, supporting input / output I / O and read / write operations on the chip's internal registers. The host computer is configured to: generate a test stimulus file required for chip aging test, and use the test stimulus file as an input file for the stimulus module; the test stimulus file contains the test stimulus data for aging test; The FPGA core board is configured to: input the aging test stimulus data to the chip PAD terminal of the chip under test through the IO pins of the FPGA core board according to the input file, so as to directly apply test stimulus to the chip under test; wherein, the aging test stimulus data includes external test stimulus data for the scenario of chip external load device, and the binary bitfile file corresponding to the external load test stimulus data is burned into the FPGA core board. At this time, the FPGA core board replaces the external load device to apply the aforementioned external test stimulus data to the chip under test to simulate the communication interaction between the external load device and the chip under test.

2. The testing system according to claim 1, characterized in that: The test stimulus file is generated by converting the pattern test file of the ATE machine, and the host computer is configured as follows: Obtain the ATE machine pattern test file for aging testing; The ATE instrument pattern test file is converted to obtain a synthesizable Verilog file for aging tests; The synthesizable Verilog file is subjected to netlist synthesis and place-and-route (PR) processing to obtain a binary bitfile file for aging tests. The binary bitfile is burned onto the aforementioned FPGA core board.

3. The testing system according to claim 2, characterized in that: The FPGA core board is also configured to: after completing the transmission of test stimulus data, read the actual state parameters of the chip under test according to the test requirements, compare the actual state parameters with the preset theoretical state parameters, and display the test results of the aging test based on the comparison results.

4. The testing system according to claim 2, characterized in that: The external test stimulus data applied by the FPGA core board to the chip under test includes test stimulus data for I / O testing, test stimulus data for clock testing, and test stimulus data for register testing, wherein the register testing includes register read and write operation testing.

5. The testing system according to claim 4, characterized in that: The synthesizable Verilog file contains I / O data configurations. The I / O can be configured as input, output, or inout types. By configuring different I / O values ​​in the synthesizable Verilog file, the chip under test can be set to different functional test modes.

6. The testing system according to claim 4, characterized in that: The external crystal oscillator information is input into the clock management module of the FPGA core board for clock configuration, and clock signals of different frequencies are input to the relevant PAD terminals of the chip under test through the IO ports of the FPGA core board to simulate the actual operation process by using PLL frequency division.

7. The testing system according to claim 4, characterized in that: The chip under test has a reserved register read / write port. The enable bit, read / write address bit and data bit of the register are configured through the port. The relevant timing information of the read / write operation is configured in the synthesizable Verilog file. When test stimulus is applied, the FPGA core board performs read / write operations on the internal registers of the chip under test.

8. The testing system according to claim 1, characterized in that: The test system is configured with multiple FPGA core boards of different models, and also includes an FPGA optional module, which is configured as follows: Obtain the functional test resource information of the chip under test, determine the level of test resources based on the functional test resource information of the chip under test, select the model of the FPGA core board for aging test of the chip under test based on the level of test resources, and ensure that the computing resources provided by the selected FPGA core board can cover the functional test resource level of the chip under test.

9. A method for chip aging testing based on FPGA, characterized in that: An aging test environment is set up, which includes an FPGA core board and a chip under test. The FPGA core board serves as the excitation module for chip aging test, which applies test excitation to the chip under test. The FPGA core board is directly connected to the chip under test through pin-to-pin slots, supporting input / output I / O and read / write operations on the chip's internal registers. The aging test environment receives the test stimulus file sent by the host computer and uses the test stimulus file as the input file of the stimulus module; the test stimulus file contains the test stimulus data for the aging test. According to the input file, the FPGA core board inputs the test stimulus data of the aging test to the chip PAD terminal of the chip under test through the IO pin to directly apply test stimulus to the chip under test; when the test stimulus data of the aging test includes external test stimulus data for the scenario of chip external load device, the binary bitfile file corresponding to the test stimulus data of the external load is burned into the FPGA core board, and the FPGA core board applies the aforementioned external test stimulus data to the chip under test in place of the external load device to simulate the communication interaction between the external load device and the chip under test.

10. The method according to claim 9, characterized in that: The test stimulus file is generated by converting the pattern test file of the ATE machine, and also includes a simulation step for aging test based on the pattern test file of the ATE machine, as follows: Update the pattern test file used by the ATE machine according to the test stimulus requirements of chip aging test; Obtain the updated ATE instrument pattern test file for aging test, convert the ATE instrument pattern test file into a simulation testbench file through a script, instantiate the chip under test in the simulation testbench file, and use the simulation testbench file for aging test simulation. Run the simulation tool to compile and run the simulation testbench file to obtain the aging test simulation results; The simulation results of the aging test are compared with the actual aging test results of the chip under test, and the comparison results are output.

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