A via bridge defect prediction method, apparatus, and computer readable medium

Abstract

The application discloses a via bridge defect prediction method, device and computer readable medium, wherein the method comprises: constructing a calculation unit based on a via of an integrated circuit via layer located on two layers of layout, each calculation unit corresponding to a via pair, each via pair formed by two vias located on two layers of layout; according to a fluctuation range of overlay error, predicting a via position demarcation line of bridging and non-bridging of each calculation unit; according to the via position demarcation line, predicting a safety area of the via pair of each calculation unit; according to a change statistical characteristic of the overlay error, determining a probability of no bridging defect of the via of each calculation unit in the safety area, so as to determine a prediction result of the via bridge defect probability. By introducing the change statistical characteristic of the overlay error into the prediction of the via bridge defect, the application can realize fast and efficient prediction of the via bridge defect probability under the double exposure technology, and can be applied in large-scale integrated circuit manufacturing.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a method, apparatus and computer-readable medium for predicting through-hole bridging defects. Background Technology

[0002] As the minimum feature size shrinks, the introduction of double patterning (DPT) has further pushed the physical limits of photolithography. Among them, lithography-etching-lithography-etching (LELE) is the most commonly used double patterning technique in the fabrication of logic circuits.

[0003] Predicting via bridging defects using dual-exposure technology is of guiding significance for layout design, lithography process selection, and layout and process optimization. However, traditional methods for predicting via bridging defects using dual-exposure technology suffer from technical problems such as low accuracy, high time consumption, and inability to be applied to large-scale integrated circuit manufacturing. Summary of the Invention

[0004] In view of this, this application provides a method, apparatus and computer-readable medium for predicting through-hole bridging defects, which solves at least some of the technical problems existing in the conventional technology by introducing the statistical characteristics of overlay error into the prediction of through-hole bridging defects under double exposure technology.

[0005] The specific plan is as follows:

[0006] A method for predicting defects in through-hole bridging includes:

[0007] The computational unit is constructed based on the vias located on two layout layers within the area to be processed in the integrated circuit via layer. Each computational unit corresponds to a via pair, and each via pair is formed by two vias located on the two layout layers respectively. The two layout layers are two layouts split from the circuit diagram of the integrated circuit through a double exposure process.

[0008] Based on the overlay error fluctuation range, predict the boundary line between the bridging and non-bridging via positions corresponding to each computing unit;

[0009] Based on the boundary line between the bridged and non-bridged via positions corresponding to each computing unit, the target safe area for each via pair corresponding to each computing unit is predicted; the target safe area is the area formed by the via positions that ensure that the via pairs corresponding to each computing unit are not bridged.

[0010] Based on the statistical characteristics of the overlay error variation, the probability of non-bridging of via pairs corresponding to each computing unit within the target safety area is determined, and the via bridging defect probability prediction result is determined based on the obtained probability.

[0011] Optionally, the linewidth corresponding to the vias on the two-layer layout is determined based on the linewidth variation after etching.

[0012] Optionally, predicting the boundary line between the bridged and non-bridged via positions corresponding to each calculation unit based on the variation range of the overlay error includes:

[0013] For each computing unit, determine the relationship type of the positional relationship between the two through holes in the through hole pair corresponding to the computing unit;

[0014] The first through-hole of the through-hole pair on the first layout is fixed, and the second through-hole of the through-hole pair on the second layout is moved within a preset moving range according to the relationship type, so as to traverse the distance between each position of the second through-hole and the first through-hole within the preset moving range; the first layout and the second layout are layouts contained in the two-layer layout; the preset moving range is a moving range set according to the variation range of the overlay error;

[0015] Based on the distance between the second through hole and the first through hole at each position, predict the boundary point between the bridging and non-bridging through hole positions corresponding to each computing unit, and obtain the boundary point set;

[0016] Curve fitting is performed on the set of boundary points to obtain the boundary lines between the bridging and non-bridging via positions corresponding to the computing unit.

[0017] Optionally, the preset moving range of the second through hole includes: the movable range in the horizontal and vertical directions determined by the Gaussian probability density distribution corresponding to the overlay error.

[0018] Optionally, the curve fitting process for the boundary point set includes:

[0019] Based on the set of boundary points, construct the corresponding objective function, constraints, and logarithmic barrier augmentation function; the objective function is used to limit the distance between points on the fitted curve and corresponding points in the set of boundary points, and the constraints are used to limit one-sided fitting so that the points on the fitted curve can make the two vias in the corresponding via pair non-bridged.

[0020] Select an initial point, a penalty factor, and a decay coefficient. The initial point includes the initial values ​​of the function coefficients corresponding to the curve function of the fitted curve.

[0021] The logarithmic barrier augmentation function is updated based on the penalty factor, the decay coefficient, the objective function, the constraints, and the current values ​​of the function coefficients.

[0022] Solve the current logarithmic barrier augmentation function, update the value of the function coefficients according to the solution, until the stopping condition is met, take the current solution as the optimal solution of the function coefficients, and take the fitting curve corresponding to the optimal solution of the function coefficients as the dividing line between the bridging and non-bridging via positions of the corresponding computing unit.

[0023] Optionally, before performing curve fitting on the set of boundary points, the method further includes:

[0024] Based on the relationship type, the boundary points in the boundary point set are filtered to obtain the target boundary point set formed by the unfiltered boundary points, and then the target boundary point set is subjected to curve fitting.

[0025] Optionally, predicting the target safe area of ​​each computing unit's corresponding via pair based on the boundary line between the bridged and non-bridged via positions for each computing unit includes:

[0026] Based on the safe region representing the non-bridging of vias corresponding to the via location boundary line of each computing unit, predict the target safe region of the via pair corresponding to each computing unit.

[0027] Optionally, determining the probability of non-bridging via pairs corresponding to each calculation unit within the target safety area based on the statistical characteristics of the overlay error variation, and determining the via bridging defect probability prediction result based on the obtained probability, includes:

[0028] Based on the probability density functions followed by the fluctuations of the overlay error in the horizontal and vertical directions, the probability of non-bridging of the via pairs corresponding to each computing unit within the target security area is determined.

[0029] Based on the non-bridging probability of the via pairs corresponding to each computing unit within the target security area, the potential bridging hotspot locations and the bridging probabilities corresponding to the bridging hotspot locations are determined.

[0030] A through-hole bridging defect prediction device, comprising:

[0031] The construction module is used to construct calculation units for vias located on two layout layers within the processing area of ​​the integrated circuit via layer. Each calculation unit corresponds to a via pair, and each via pair is formed by two vias located on the two layout layers respectively. The two layout layers are two layouts split from the circuit diagram of the integrated circuit through a double exposure process.

[0032] The first prediction module is used to predict the boundary line between the bridging and non-bridging via positions corresponding to each calculation unit based on the variation range of the overlay error.

[0033] The second prediction module is used to predict the target safe area of ​​the via pairs corresponding to each computing unit based on the boundary line between the bridged and non-bridged via positions of the via pairs corresponding to each computing unit; the target safe area is the area formed by the via positions that make the via pairs corresponding to each computing unit non-bridged.

[0034] The determination module is used to determine the probability of non-bridging of via pairs corresponding to each computing unit within the target safety area based on the statistical characteristics of the variation of overlay error, and to determine the via bridging defect probability prediction result based on the obtained probability.

[0035] A computer-readable medium having a computer program stored thereon, the computer program comprising program code for performing the methods described in any of the preceding descriptions.

[0036] In summary, this application provides a method, apparatus, and computer-readable medium for predicting via bridging defects. The method includes: constructing via construction calculation units located on two layout layers within the processing area of ​​an integrated circuit via layer, each calculation unit corresponding to a via pair, each via pair being formed by two vias located on the two layout layers respectively; the two layout layers are two layouts split from the circuit diagram of the integrated circuit through a double exposure process; predicting the boundary line between bridging and non-bridging via positions for each calculation unit's via pair based on the variation range of overlay error; predicting the target safe region for each calculation unit's via pair based on the boundary line between bridging and non-bridging via positions for each calculation unit's via pair; the target safe region is the area formed by each via position that ensures that the via pairs corresponding to each calculation unit are not bridged; determining the probability of non-bridging of each calculation unit's via pair within the target safe region based on the statistical characteristics of overlay error variation, and determining the via bridging defect probability prediction result based on the obtained probability.

[0037] The applicant discovered that in advanced nodes, at extreme dimensions, process fluctuations have a significant and non-negligible impact on the final yield, and overlay error is a crucial determining factor. Based on this, this application, by considering overlay error as a determining factor, introduces the statistical characteristics (statistical properties) of overlay error variation into the prediction of via bridging defects, solving the problems of traditional technologies. It can quickly and efficiently predict the probability of via bridging defects under dual-exposure technology, improving the prediction rate and accuracy of via bridging defects, and can be applied to large-scale integrated circuit manufacturing. Attached Figure Description

[0038] The above and other features, advantages, and aspects of the embodiments of this application will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0039] Figure 1 This is a schematic diagram showing the layout breakdown of the LELE solution in the dual-exposure process provided in this application;

[0040] Figure 2 This is a flow chart of the LELE photolithography process provided in this application;

[0041] Figure 3 This is a schematic diagram of the dual-exposure separation scheme for the via layer provided in this application;

[0042] Figure 4 This is a flowchart illustrating the through-hole bridging defect prediction method provided in this application;

[0043] Figure 5 This is a schematic diagram showing the location where bridging defects are most likely to occur in the through-hole layer provided in this application (from the smallest corner to the corner through-hole location);

[0044] Figure 6 This is a schematic diagram of the hotspot layout in the via layer under the double exposure process provided in this application, which is most prone to bridging problems.

[0045] Figure 7 This is an exemplary construction process diagram of the computing unit provided in this application;

[0046] Figure 8 This is a schematic diagram of the constructed computing unit provided in this application;

[0047] Figure 9 This is an exemplary implementation flowchart of determining the set of boundary points provided in this application;

[0048] Figure 10 This is an example graph of the fitted curve provided in this application;

[0049] Figure 11 This is a schematic diagram of the filtering process for filtering the boundary point set provided in this application;

[0050] Figure 12 This is a schematic diagram of the prediction of the target safe area D based on each fitted curve provided in this application;

[0051] Figure 13 This is a schematic diagram of the integration result based on the target security region D provided in this application;

[0052] Figure 14 This is a structural diagram of the through-hole bridging defect prediction device provided in this application. Detailed Implementation

[0053] Embodiments of this application will now be described in more detail with reference to the accompanying drawings. While some embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this application. It should be understood that the drawings and embodiments of this application are for illustrative purposes only and are not intended to limit the scope of protection of this application.

[0054] The term "comprising" and its variations as used herein are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0055] It should be noted that the concepts of "first" and "second" mentioned in this application are only used to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0056] It should be noted that the terms "one" and "multiple" used in this application are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0057] As the minimum feature size shrinks, the introduction of double exposure technology has further pushed the physical limits of photolithography. In the fabrication of logic circuits, photolithography-etching-photolithography-etching is the most commonly used double exposure technique, such as... Figure 1 , Figure 2 and Figure 3 As shown, the via layer of integrated circuits generally adopts a double exposure scheme such as LELE.

[0058] in, Figure 1 This document provides a schematic diagram of the LELE scheme layout splitting in a double-exposure process. Because the line cycle to be manufactured is too small, the single-exposure limit is insufficient to achieve this manufacturing goal. Therefore, the pattern needs to be split into two layouts and manufactured using a special photolithography process. Figure 1 It can be seen that the graphic was split into mask A and mask B for manufacturing. Figure 2 This is the actual LELE lithography process flow, specifically showing how the LELE process takes the patterns split into two layouts, mask A and mask B, and ultimately fabricates them onto a single wafer substrate. This is to provide a more intuitive understanding of the essence of LELE. Figure 2 Line graphics were used. Figure 3 The diagram provided is a schematic of a dual-exposure splitting scheme for the via layer. The via layer is a critical layer for circuit interconnection in the chip manufacturing process. Since the critical via layer size of 14nm and below nodes is too small, it cannot be manufactured in one step using a DUV lithography machine. Therefore, it also needs to be split into two layouts for manufacturing.

[0059] Predicting via bridging defects using dual-exposure technology is instructive for layout design, lithography process selection, and layout and process optimization. Traditional via bridging defect prediction schemes typically involve using a lithography model to calculate the via outline pattern after optical proximity effect correction, obtaining the lithographic via contour pattern, subtracting the corresponding etching deviation from the simulated lithographic contour pattern, and merging the etched contour patterns of the two separate layouts into the same layer. Then, the distance between the contour patterns is detected, and the detected distance is compared with a distance threshold determined based on the actual chip manufacturing process capability. Distances below this threshold are considered to indicate short circuits (i.e., bridging), and the two vias involved in this distance are highlighted for lithography process optimization or layout design optimization.

[0060] The above-mentioned traditional methods have two main drawbacks:

[0061] 1) The applicant found that in advanced nodes, under extreme dimensions, process fluctuations have a significant and non-negligible impact on the final yield. Under the double exposure process, overlay error is a very important and decisive factor. Simply setting a distance threshold without considering the statistical characteristics of overlay error variation to determine whether there is a risk of bridging / short circuit is insufficient to support the judgment of the final defect, resulting in low accuracy of bridging defect prediction.

[0062] 2) Using traditional methods to calculate the probability of a successful final circuit layout, only the Monte Carlo method can be introduced. This method is extremely time-consuming and cannot be applied to large-scale integrated circuit manufacturing.

[0063] Based on this, this application provides a method, apparatus and computer-readable medium for predicting through-hole bridging defects, in order to solve at least some of the technical problems existing in the conventional technology.

[0064] See Figure 4 This application provides a flowchart illustrating a method for predicting through-hole bridging defects, which includes at least the following:

[0065] Step 401: Based on the via layer of the integrated circuit, construct calculation units for vias located on two layers of the layout within the area to be processed. Each calculation unit corresponds to a via pair, and each via pair is formed by two vias located on the two layers of the layout. The two layers of the layout are two layouts that are split from the circuit diagram of the integrated circuit through a double exposure process.

[0066] See also Figure 5 The minimum distance between via layers typically occurs at the corner-to-corner (C2C) position, where bridging defects are extremely prone to occur under double exposure processes. Figure 5 The meanings of each character in the Chinese character set are as follows:

[0067] Mx: The xth metal layer;

[0068] Vx: Through-hole in the xth layer;

[0069] Mx+1: The (x+1)th metal layer;

[0070] A: The graphic on mask A after splitting;

[0071] B: The graphic on mask B after splitting;

[0072] C: C2C is the minimum diagonal distance between the through holes.

[0073] The applicant discovered that the combined effects of the implemented via process, overlay errors, pattern shift caused by mask 3D effects (M3D), and defects in the optical proximity correction strategy all contribute to via bridging defects under LELE double exposure. The success of advanced nodes hinges on the manufacturer's ability to meet extremely stringent edge placement error (EPE) budgets. Linewidth (CD) variations and overlay errors are contributing factors to bridging defects in double exposure processes, with overlay error being a particularly crucial determinant.

[0074] Based on this, this application proposes a compact model under a dual-exposure process to predict potential via bridging locations. Considering the post-etching linewidth variation and the statistical characteristics of overlay errors, the model calculates the success (no bridging) probability and failure (bridging) probability at these locations. This model can quantitatively guide layout design, lithography process selection, and the control range requirements of related processes, and can quantitatively compensate for negative effects caused by mask 3D effects or overlay errors.

[0075] Among them, nodes of 14nm and below can be called "advanced nodes". Nodes of 14nm and below require the introduction of double exposure technology, such as the introduction of LELE. The critical via layer size of nodes of 14nm and below is too small to be manufactured in one step using a DUV lithography machine, so it needs to be split into two layouts for manufacturing.

[0076] This application takes into account the linewidth variation after etching (photolithography CD variation), and specifically determines the linewidth corresponding to the via on the two-layer layout based on the linewidth variation after etching.

[0077] This step specifically utilizes the via construction calculation units located on two different layout layers within the area to be processed in the integrated circuit via layer. Taking the hotspot layout where bridging problems are most likely to occur in the integrated circuit via layer under a double-exposure process as an example, see [link to relevant documentation]. Figure 6 The hotspot layout diagram shown assumes that ViaA, ViaB1, ViaB2, ..., ViaBn are vias located on two different layout layers within the area to be processed in the integrated circuit via layer. ViaA is located on layer A (layout A), and ViaBi is located on layer B (layout B). ViaBi is distributed around ViaA. In practice, the value of n usually does not exceed 4.

[0078] In this step, multiple vias (Via) can be split into combinations of ViaA-ViaBi to form via pairs, thereby constructing the computational unit (also called the "unit to be computed") corresponding to each via pair. Figure 6 Taking the hotspot map as an example, the construction process of the computing unit is as follows: Figure 7 As shown, the process includes: traversing the vias ViaBi on layer B of the vias to be calculated, and combining ViaBi with vias ViaA on layer A to form a calculation unit / to-be-calculated unit ViaA-ViaBi. Assuming n=4, then four calculation units are ultimately constructed. The four calculation units can be found in [reference needed]. Figure 8 As shown.

[0079] Step 402: Based on the variation range of the overlay error, predict the boundary line between the bridging and non-bridging via positions corresponding to each calculation unit.

[0080] Optionally, step 402 can be further implemented through the following processing procedure:

[0081] 11) For each computing unit, determine the relationship type of the positional relationship between the two through holes in the through hole pair corresponding to the computing unit.

[0082] 12) Fix the first through hole of the through hole pair on the first layout, and move the second through hole of the through hole pair on the second layout within a preset movement range of the second through hole according to the relationship type, so as to traverse the distance between the second through hole and the first through hole at each position of the second through hole within its preset movement range; the first layout and the second layout are the layouts contained in the two-layer layout.

[0083] 13) Based on the distance between the second through hole and the first through hole at each position, predict the boundary point between the bridging and non-bridging through hole positions corresponding to each computing unit, and obtain the boundary point set.

[0084] Here, the distance between the second through hole and the first through hole at a certain position refers to the minimum distance between the second through hole and the first through hole at that position.

[0085] 14) Perform curve fitting on the set of boundary points to obtain the boundary line between the bridging and non-bridging via positions corresponding to the computing unit.

[0086] The preset moving range of the second through hole is a moving range set according to the variation range of the overlay error. Specifically, it includes the movable ranges in the horizontal and vertical directions determined by the Gaussian probability density distribution corresponding to the overlay error.

[0087] The first and second vias belong to different masks, MASKA and MASKB, after double exposure. There is an overlay error between these two masks, and the overlay error is independent of each other in the x and y directions, each having its own Gaussian probability density distribution. Therefore, for the preset movement range of the second via, this embodiment further divides it into movable ranges corresponding to the x-axis direction (lateral) and the y-axis direction (vertical), and sets them according to the Gaussian probability density distribution of the overlay error in the x and y directions, respectively.

[0088] Optionally, the movable range in the x-direction can be set to N times the standard deviation of the Gaussian probability density distribution of the overlay error in the x-direction, such as from -3sigma_x to +3sigma_x. Similarly, the movable range in the y-direction can be set to N times the standard deviation of the Gaussian probability density distribution of the overlay error in the y-direction, such as from -3sigma_y to +3sigma_y. Here, N is an integer not less than 3, and sigma_x and sigma_y represent the standard deviations of the Gaussian probability density distributions of the overlay error in the x and y directions, respectively.

[0089] Accept Figure 6For example, specifically, the positional relationship type (Type) can be determined based on the positional relationship information of the two vias in the via pair corresponding to each calculation unit ViaA-ViaBi. The possible values ​​for each Type are: 1, 2, 3, and 4. The type corresponding to each calculation unit ViaA-ViaBi specifically represents the relative position of via ViaBi in layer B and via ViaA in layer A. The four values ​​represent four quadrants. See also... Figure 8 The type corresponding to the calculation unit ViaA-ViaB1 is 2, the type corresponding to the calculation unit ViaA-ViaB2 is 1, the type corresponding to the calculation unit ViaA-ViaB3 is 4, and the type corresponding to the calculation unit ViaA-ViaB4 is 3. Different values ​​of type represent different quadrants.

[0090] Then, based on the via position relationship type corresponding to each computing unit ViaA-ViaBi, the boundary point set Mi′ for bridging and security (non-bridging) of each computing unit ViaA-ViaBi is predicted. Specifically, ViaBi (the first via) can be fixed, while ViaA (the second via) can be moved within the range of [-3σx, 3σx] and [-3σy, 3σy] in the XY (horizontal and vertical axes) directions according to the Gaussian probability density distribution. The minimum distance between each position of ViaA within the movable range and ViaBi is traversed, and the boundary point set Mi′ corresponding to the computing unit ViaA-ViaBi is determined based on this distance. Optionally, an exemplary implementation process for determining the point set Mi′ is as follows: Figure 9 As shown in the figure, step represents the step size when traversing the position of ViaA within its movable range, stepx and stepy represent the step sizes in the x-axis (horizontal axis) and y-axis (vertical axis) directions, respectively, dis represents the minimum distance between the corresponding traversal position of ViaA and ViaBi during the position traversal process, and threshold represents the set threshold.

[0091] Based on this, the set of boundary points Mi′ corresponding to each computational unit ViaA-ViaBi is further fitted. Optionally, an exemplary fitting process is as follows:

[0092] 21) For each computing unit, construct an objective function, constraints, and logarithmic barrier augmentation function based on its corresponding set of boundary points; the objective function is used to limit the distance between points on the fitted curve and corresponding points in the set of boundary points, and the constraints are used to limit one-sided fitting so that the points on the fitted curve can make the two vias in the corresponding via pair non-bridged.

[0093] 22) Select an initial point, a penalty factor, and a decay coefficient, wherein the initial point includes the initial value of the function coefficient corresponding to the curve function of the fitted curve;

[0094] 23) Update the logarithmic barrier augmenting function based on the penalty factor, decay coefficient, and the current values ​​of the objective function, constraints, and function coefficients;

[0095] 24) Solve the current logarithmic barrier augmentation function, update the value of the function coefficients according to the solution results, until the stopping condition is met, take the current solution as the optimal solution of the function coefficients, and take the fitting curve corresponding to the optimal solution of the function coefficients as the dividing line between the bridging and non-bridging via positions of the corresponding computing unit.

[0096] The aforementioned stopping conditions may be, but are not limited to, constraints in terms of accuracy, number of calculations / iterations, or calculation time / iteration time.

[0097] See Figure 10 An example diagram of the fitted curve is provided, in which one side of the fitted curve represents the location region where the via pair corresponding to the computing unit is successful (non-bridging), and the other side represents the location region where the via pair corresponding to the computing unit fails (bridging).

[0098] Optionally, in other embodiments, before performing curve fitting on the set of boundary points corresponding to each computing unit, the boundary points in the set of boundary points corresponding to each computing unit can be filtered according to the relationship type between the positional relationship between the two through holes in the through hole pair of each computing unit, so as to obtain the target set of boundary points formed by the unfiltered boundary points, thereby improving the reference value of the boundary points. Subsequently, curve fitting can be performed on the target set of boundary points corresponding to each computing unit.

[0099] Based on the example above, an optional filtering process is as follows: Figure 11 As shown, it includes: directly storing points with different x values ​​in the boundary point set Mi′ into the target boundary point set Mi through a filter; when there are points with the same x value, if type = 1 or 2, the point with the smallest y value among the points with the same x value is stored into the point set Mi through a filter; if Type = 3 or 4, the point with the largest y value among the points with the same x value is stored into the point set Mi through a filter.

[0100] Step 403: Based on the boundary line between the bridged and non-bridged via positions corresponding to each computing unit, predict the target safe area for each via pair corresponding to each computing unit; the target safe area is the area formed by each via position that makes each via pair corresponding to each computing unit non-bridged.

[0101] Specifically, the safe area representing the non-bridging of vias can be defined by the boundary line of the via location of each computing unit (e.g., Figure 11(The region corresponding to success in the middle) predicts the target security region of the via pairs corresponding to each computing unit.

[0102] See Figure 12 The example provided above shows the target safe area D of each through-hole pair corresponding to each calculation unit, based on the safe areas corresponding to the fitting curves (through-hole position boundaries) fun0, fun1, fun3, and fun4 of the calculation units ViaA-ViaB1, ViaA-ViaB2, ViaA-ViaB3, and ViaA-ViaB4, respectively.

[0103] Step 404: Based on the statistical characteristics of the variation of overlay error, determine the probability of non-bridging of the through-hole pairs corresponding to each calculation unit within the target safety area, and determine the through-hole bridging defect probability prediction result based on the obtained probability.

[0104] This step determines the probability of non-bridging of via pairs corresponding to each computing unit within the target safety area based on the probability density functions followed by the overlay error fluctuations in the horizontal and vertical directions. Based on the non-bridging probabilities of via pairs corresponding to each computing unit within the target safety area, it determines the potential bridging hotspot locations and the bridging probabilities corresponding to the bridging hotspot locations.

[0105] Generally, the probability density of overlay errors fluctuating in both the lateral and longitudinal directions follows a Gaussian distribution. Given that the overlay error follows a Gaussian probability density distribution, the determined target safety area D can be used as the integration region for integration calculations ∫∫ D The probability of success (P) is obtained by ∫∫ f(x)f(y)dxdy, where the vias within the target safe area are not bridged / short-circuited. D The integral result of f(x)f(y)dxdy can be found in [reference]. Figure 13 The diagram shows that P is usually a value close to 1, such as a value between 0.7 and 1. Here, f(x) and f(y) represent the probability density functions of the overlay error in the x and y directions, respectively. In general, they both follow a Gaussian distribution.

[0106] Based on this, the location outside the target safe area within the processing area of ​​the integrated circuit via layer can be identified as a potential bridging hotspot location, and its corresponding bridging probability can be determined as 1-P.

[0107] In summary, this patent proposes a compact model for dual-exposure processes (the processing flow of the method in this application can be regarded as the processing flow of the model) to predict potential via bridging locations. Considering the post-etching linewidth variation and the statistical characteristics of overlay error, the model calculates the success and failure probabilities at these locations. The model incorporates the decisive factors affecting the prediction of via layer bridging hotspots in dual-exposure processes: lithographic CD variation and overlay variation. In the proposed model, the statistical characteristics of overlay error and the post-etching pattern contour are introduced. This model can quickly and efficiently predict via bridging defects under dual-exposure technology and can evaluate the failure / success probabilities of various typical via patterning processes. Based on this model, feasible designs, patterning solutions, process capabilities, and various computational lithography options can be quantitatively analyzed and optimized. This provides quantitative guidance for layout design, lithography process selection, and related process control range requirements. It can also quantitatively compensate for negative effects caused by mask 3D effects or overlay errors. Furthermore, the compact model proposed in this application can quickly calculate the success and failure probabilities at specified locations. Tests have shown that this application has a computation speed at least 50 times faster than the Monte Carlo method and is more suitable for large-scale layout applications.

[0108] Corresponding to the above method, this application embodiment also provides a through-hole bridging defect prediction device, the composition of which is as follows: Figure 14 As shown, it includes:

[0109] The construction module 10 is used to construct calculation units for vias located on two layout layers within the area to be processed in the integrated circuit via layer. Each calculation unit corresponds to a via pair, and each via pair is formed by two vias located on the two layout layers respectively. The two layout layers are two layouts split from the circuit diagram of the integrated circuit through a double exposure process.

[0110] The first prediction module 20 is used to predict the boundary line between the bridging and non-bridging via positions corresponding to each calculation unit based on the variation range of the overlay error.

[0111] The second prediction module 30 is used to predict the target safe area of ​​the via pairs corresponding to each computing unit based on the boundary line between the bridged and non-bridged via positions of the via pairs corresponding to each computing unit; the target safe area is the area formed by the via positions that make the via pairs corresponding to each computing unit non-bridged.

[0112] The determination module 40 is used to determine the probability of non-bridging of through-hole pairs corresponding to each calculation unit within the target safety area based on the statistical characteristics of the variation of overlay error, and to determine the through-hole bridging defect probability prediction result based on the obtained probability.

[0113] In one embodiment, the linewidth corresponding to the via on the two-layer layout is determined based on the linewidth variation after etching.

[0114] In one embodiment, the first prediction module 20 is specifically used for:

[0115] For each computing unit, determine the relationship type of the positional relationship between the two through holes in the through hole pair corresponding to the computing unit;

[0116] The first through-hole of the through-hole pair on the first layout is fixed, and the second through-hole of the through-hole pair on the second layout is moved within a preset moving range according to the relationship type, so as to traverse the distance between each position of the second through-hole and the first through-hole within the preset moving range; the first layout and the second layout are layouts contained in the two-layer layout; the preset moving range is a moving range set according to the variation range of the overlay error;

[0117] Based on the distance between the second through hole and the first through hole at each position, predict the boundary point between the bridging and non-bridging through hole positions corresponding to each computing unit, and obtain the boundary point set;

[0118] Curve fitting is performed on the set of boundary points to obtain the boundary lines between the bridging and non-bridging via positions corresponding to the computing unit.

[0119] In one embodiment, the preset movement range of the second through hole includes: the movable ranges in the horizontal and vertical directions determined for the second through hole based on the Gaussian probability density distribution corresponding to the overlay error.

[0120] In one embodiment, the first prediction module 20, when performing curve fitting processing on the set of boundary points, is specifically used for:

[0121] Based on the set of boundary points, construct the corresponding objective function, constraints, and logarithmic barrier augmentation function; the objective function is used to limit the distance between points on the fitted curve and corresponding points in the set of boundary points, and the constraints are used to limit one-sided fitting so that the points on the fitted curve can make the two vias in the corresponding via pair non-bridged.

[0122] Select an initial point, a penalty factor, and a decay coefficient. The initial point includes the initial values ​​of the function coefficients corresponding to the curve function of the fitted curve.

[0123] The logarithmic barrier augmentation function is updated based on the penalty factor, the decay coefficient, the objective function, the constraints, and the current values ​​of the function coefficients.

[0124] Solve the current logarithmic barrier augmentation function, update the value of the function coefficients according to the solution, until the stopping condition is met, take the current solution as the optimal solution of the function coefficients, and take the fitting curve corresponding to the optimal solution of the function coefficients as the dividing line between the bridging and non-bridging via positions of the corresponding computing unit.

[0125] In one embodiment, before performing curve fitting processing on the set of boundary points, the first prediction module 20 is further configured to: filter the boundary points in the set of boundary points according to the relationship type to obtain a target set of boundary points formed by unfiltered boundary points, so as to perform curve fitting processing on the target set of boundary points.

[0126] In one embodiment, the second prediction module 30 is specifically used to: predict the target safe area of ​​the via pair corresponding to each computing unit based on the safe area representing the non-bridging of vias corresponding to the via position boundary line of each computing unit.

[0127] In one embodiment, the determining module 40 is specifically used for:

[0128] Based on the probability density functions followed by the fluctuations of the overlay error in the horizontal and vertical directions, the probability of non-bridging of the via pairs corresponding to each computing unit within the target security area is determined.

[0129] Based on the non-bridging probability of the via pairs corresponding to each computing unit within the target security area, the potential bridging hotspot locations and the bridging probabilities corresponding to the bridging hotspot locations are determined.

[0130] The through-hole bridging defect prediction device provided in this application embodiment is described simply because it corresponds to the through-hole bridging defect prediction method provided in the above method embodiment. For related similarities, please refer to the description of the above method embodiment, which will not be detailed here.

[0131] This application also provides a computer-readable medium having a computer program stored thereon, the computer program comprising program code for performing the through-hole bridging defect prediction method provided in any of the above method embodiments.

[0132] In the context of this application, a computer-readable medium (machine-readable medium) can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0133] It should be noted that the computer-readable medium described above in this application can be a computer-readable signal medium, a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0134] The aforementioned computer-readable medium may be contained within an electronic device or may exist independently without being assembled into an electronic device.

[0135] It should be noted that although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

[0136] While several specific implementation details are included in the foregoing discussion, these should not be construed as limiting the scope of this application. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0137] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described application concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions claimed in this application.

Claims

1. A method for predicting defects in through-hole bridging, characterized in that, include: The computational unit is constructed based on the vias located on two layout layers within the area to be processed in the integrated circuit via layer. Each computational unit corresponds to a via pair, and each via pair is formed by two vias located on the two layout layers respectively. The two layout layers are two layouts split from the circuit diagram of the integrated circuit through a double exposure process. Based on the range of overlay error variation, predict the boundary line between the bridging and non-bridging via positions corresponding to each computing unit. Based on the boundary line between the bridged and non-bridged via positions corresponding to each computing unit, the target safe area for each via pair corresponding to each computing unit is predicted; the target safe area is the area formed by the via positions that ensure that the via pairs corresponding to each computing unit are not bridged. Based on the statistical characteristics of the overlay error variation, the probability of non-bridging of via pairs corresponding to each computing unit within the target safety area is determined, and the via bridging defect probability prediction result is determined based on the obtained probability.

2. The method according to claim 1, characterized in that, The linewidth corresponding to the vias on the two-layer layout is determined based on the linewidth variation after etching.

3. The method according to claim 1, characterized in that, The step of predicting the boundary line between the bridged and non-bridged via positions for each calculation unit based on the variation range of the overlay error includes: For each computing unit, determine the relationship type of the positional relationship between the two through holes in the through hole pair corresponding to the computing unit; The first through-hole of the through-hole pair on the first layout is fixed, and the second through-hole of the through-hole pair on the second layout is moved within a preset moving range according to the relationship type, so as to traverse the distance between each position of the second through-hole and the first through-hole within the preset moving range; the first layout and the second layout are layouts contained in the two-layer layout; the preset moving range is a moving range set according to the variation range of the overlay error; Based on the distance between the second through hole and the first through hole at each position, predict the boundary point between the bridging and non-bridging through hole positions corresponding to each computing unit, and obtain the boundary point set; Curve fitting is performed on the set of boundary points to obtain the boundary lines between the bridging and non-bridging via positions corresponding to the computing unit.

4. The method according to claim 3, characterized in that, The preset moving range of the second through hole includes: the movable range in the horizontal and vertical directions determined by the Gaussian probability density distribution corresponding to the overlay error.

5. The method according to claim 3, characterized in that, The curve fitting process for the boundary point set includes: Based on the set of boundary points, construct the corresponding objective function, constraints, and logarithmic barrier augmentation function; the objective function is used to limit the distance between points on the fitted curve and corresponding points in the set of boundary points, and the constraints are used to limit one-sided fitting so that the points on the fitted curve can make the two vias in the corresponding via pair non-bridged. Select an initial point, a penalty factor, and a decay coefficient. The initial point includes the initial values ​​of the function coefficients corresponding to the curve function of the fitted curve. The logarithmic barrier augmentation function is updated based on the penalty factor, the decay coefficient, the objective function, the constraints, and the current values ​​of the function coefficients. Solve the current logarithmic barrier augmentation function, update the value of the function coefficients according to the solution, until the stopping condition is met, take the current solution as the optimal solution of the function coefficients, and take the fitting curve corresponding to the optimal solution of the function coefficients as the dividing line between the bridging and non-bridging via positions of the corresponding computing unit.

6. The method according to claim 3, characterized in that, Before performing curve fitting on the set of boundary points, the process further includes: Based on the relationship type, the boundary points in the boundary point set are filtered to obtain the target boundary point set formed by the unfiltered boundary points, and then the target boundary point set is subjected to curve fitting.

7. The method according to claim 1, characterized in that, The step of predicting the target safe area of ​​each computing unit's corresponding via pair based on the boundary line between the bridged and non-bridged via positions includes: Based on the safe region representing the non-bridging of vias corresponding to the via location boundary line of each computing unit, predict the target safe region of the via pair corresponding to each computing unit.

8. The method according to claim 1, characterized in that, The step of determining the probability of non-bridging via pairs corresponding to each calculation unit within the target safety area based on the statistical characteristics of the overlay error variation, and determining the via bridging defect probability prediction result based on the obtained probability, includes: Based on the probability density functions followed by the fluctuations of the overlay error in the horizontal and vertical directions, the probability of non-bridging of the via pairs corresponding to each computing unit within the target security area is determined. Based on the non-bridging probability of the via pairs corresponding to each computing unit within the target security area, the potential bridging hotspot locations and the bridging probabilities corresponding to the bridging hotspot locations are determined.

9. A through-hole bridging defect prediction device, characterized in that, include: The construction module is used to construct calculation units for vias located on two layout layers within the processing area of ​​the integrated circuit via layer. Each calculation unit corresponds to a via pair, and each via pair is formed by two vias located on the two layout layers respectively. The two layout layers are two layouts split from the circuit diagram of the integrated circuit through a double exposure process. The first prediction module is used to predict the boundary line between the bridging and non-bridging via positions corresponding to each calculation unit based on the variation range of the overlay error. The second prediction module is used to predict the target safe area of ​​the via pairs corresponding to each computing unit based on the boundary line between the bridged and non-bridged via positions of the via pairs corresponding to each computing unit; the target safe area is the area formed by the via positions that make the via pairs corresponding to each computing unit non-bridged. The determination module is used to determine the probability of non-bridging of via pairs corresponding to each computing unit within the target safety area based on the statistical characteristics of the variation of overlay error, and to determine the via bridging defect probability prediction result based on the obtained probability.

10. A computer-readable medium, characterized in that, It stores a computer program thereon, the computer program containing program code for performing the method as described in any one of claims 1-8.

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