A processor remote debugging method and device based on optical fiber transmission

Abstract

This invention proposes a method and apparatus for remote processor debugging based on fiber optic transmission. The method includes: an external processing board sampling the output pins of the emulator's JTAG port; the external processing board transmitting the sampled data to a second optical module on an internal processing board via a first optical module; the internal processing board decoding the data and reproducing it to the corresponding pins; in response to the signal output generated by the processor receiving a correct JTAG signal, the internal processing board sampling the output pins of the processor's JTAG port; the internal processing board transmitting the sampled data to a first optical module on the external processing board via the second optical module; the external processing board receiving the data, decoding it, and reproducing it to the corresponding pins, so that the emulator receives the corresponding feedback signal, realizing the transfer of the JTAG signal. This invention reduces space requirements while providing remote download and debugging capabilities.

Description

Technical Field

[0001] This invention relates to the field of remote debugging technology for processors, and more particularly to a method and apparatus for remote debugging of processors based on fiber optic transmission. Background Technology

[0002] Before the servo turntable leaves the factory, it can be connected to an emulator at close range for downloading and debugging its internal processor. However, after the turntable is installed in a working environment (such as a high tower or other environments where on-site debugging is difficult), if problems occur, it is not easy to disassemble the system and connect to an emulator at close range for debugging. Therefore, a method / device for remote processor debugging needs to be designed. The processor download and debugging device includes a PC, a USB cable, an emulator, a JTAG cable, and a target board. The method of remote processor debugging is divided into wired and wireless methods depending on whether a transmission cable is required. The wireless method achieves remote download by eliminating the USB cable. Since this method performs wireless processing at the USB cable connection, the subsequent emulator functions also need to be integrated, and different processors require different emulation systems. Currently, there are devices on the market that use high-speed 2.4G transceiver chips to achieve USB wireless transmission and integrate JLINK functions using the DAPLINK open-source software, achieving long-distance downloads of about tens of meters. However, the transmission distance of such devices is greatly affected by the environment and is only suitable for JLINK processors such as ARM and microcontrollers. Wired connections can also achieve remote downloading by designing a USB cable for long distances. A common method is to convert the USB interface transmission to a network interface transmission at the sending end, connect it to the receiving end via a network cable, and then convert the network interface back to a USB interface at the receiving end to connect to the emulator. This method enables long-distance downloading and debugging, but the receiving end and emulator need to be placed inside the system, occupying a lot of space and affecting practical applications. Summary of the Invention

[0003] The technical problem this invention aims to solve is how to reduce the space occupied by the implementation device while ensuring relevant remote debugging functions. In view of this, this invention provides a processor remote debugging method and device based on fiber optic transmission.

[0004] The technical solution adopted in this invention is a remote debugging method for processors based on optical fiber transmission, comprising:

[0005] Step S1: The external processing board samples the output pins of the JTAG port of the emulator, wherein the external processing board and the emulator are disposed outside the main body of the implementation device.

[0006] In step S2, the external processing board transmits the sampled data to the second optical module of the internal processing board through the first optical module. The first optical module and the second optical module are transceivers, and the two are connected by optical fiber to realize data interaction.

[0007] Step S3: After receiving the data, the internal processing board decodes the data and reproduces it to the corresponding pin of the internal processing board. The pin of the internal processing board is connected to the JTAG port of the processor. The internal processing board and the processor are disposed inside the main body of the implementation device.

[0008] Step S4: In response to the signal output generated by the processor after receiving a correct JTAG signal, the internal processing board samples the output pin of the processor's JTAG port.

[0009] Step S5: The internal processing board transmits the sampled data to the first optical module of the external processing board through the second optical module;

[0010] Step S6: After receiving the data, the external processing board decodes the data and reproduces it to the corresponding pin of the external processing board so that the emulator receives the corresponding feedback signal and realizes the transfer of the JTAG signal.

[0011] In one implementation, the number of sampled signals obtained by sampling the output pin is no more than eight.

[0012] In one embodiment, after step S1, the method further includes: encoding the sampled data; wherein the data bit length is 32 bits, the lower eight bits of data are updated each time a sample is taken, and the previous sampled data is shifted eight bits to the right, that is, the 32-bit data contains 4 sampled data.

[0013] In one embodiment, the external processing board uses a high-speed transceiver to transmit current data to the optical module at a rate of 6.144G.

[0014] In one embodiment, in step S3, when the received 32-bit data is identical for every 8 bits from low to high, these 8 bits of data are restored to the corresponding pins of the internal processing board; otherwise, the relevant pin level remains unchanged.

[0015] Another aspect of the present invention provides a processor remote debugging device based on optical fiber transmission, comprising: an external processing board disposed outside the main body of the device, a first optical module disposed on the external processing board, and a simulator; an internal processing board disposed inside the main body of the device, a second optical module disposed on the internal processing board, and a processor; the device is used to implement the processor remote debugging method based on optical fiber transmission as described in any of the preceding claims.

[0016] By adopting the above technical solution, the present invention has at least the following advantages:

[0017] This invention provides a remote debugging method for processors based on optical fiber transmission, which reduces the space occupied while also providing remote download and debugging functions. Attached Figure Description

[0018] Figure 1 This is a flowchart of a processor remote debugging method based on fiber optic transmission according to an embodiment of the present invention;

[0019] Figure 2 This is a schematic diagram of the composition structure of a processor remote debugging device based on fiber optic transmission according to an embodiment of the present invention;

[0020] Figure 3 This is a schematic diagram of an application example structure according to an embodiment of the present invention. Detailed Implementation

[0021] To further illustrate the technical means and effects of the present invention in achieving its intended purpose, the present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments.

[0022] It should be understood that the terms "comprising," "including," "having," "containing," and / or "comprises," when used in this specification, indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire listed feature, not individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to an example or illustration.

[0023] As used herein, the terms “basically,” “approximately,” and similar terms are used as terms of approximation rather than terms of degree, and are intended to describe inherent biases in measured or calculated values ​​that will be recognized by those skilled in the art.

[0024] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that terms (e.g., those defined in common dictionaries) shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art and shall not be interpreted in an idealized or overly formal sense unless expressly so specified herein.

[0025] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The steps in the method flow description and flowcharts in the accompanying drawings are not necessarily strictly executed according to the step numbers; the execution order of the method steps can be changed. Furthermore, certain steps can be omitted, multiple steps can be combined into one step, and / or one step can be broken down into multiple steps.

[0026] The steps described in the specification and the flowcharts in the accompanying drawings of this invention are not necessarily to be strictly followed according to the step numbers; the execution order of the steps can be changed. Furthermore, certain steps can be omitted, multiple steps can be combined into one step, and / or one step can be broken down into multiple steps.

[0027] The first embodiment of the present invention provides a remote debugging method for processors based on optical fiber transmission, such as... Figure 1 As shown, the specific steps include the following:

[0028] Step S1: The external processing board samples the output pins of the JTAG port of the emulator, wherein the external processing board and the emulator are disposed outside the main body of the implementation device.

[0029] In step S2, the external processing board transmits the sampled data to the second optical module of the internal processing board through the first optical module. The first optical module and the second optical module are transceivers, and the two are connected by optical fiber to realize data interaction.

[0030] Step S3: After receiving the data, the internal processing board decodes the data and reproduces it to the corresponding pin of the internal processing board. The pin of the internal processing board is connected to the JTAG port of the processor. The internal processing board and the processor are disposed inside the main body of the implementation device.

[0031] Step S4: In response to the signal output generated by the processor after receiving a correct JTAG signal, the internal processing board samples the output pin of the processor's JTAG port.

[0032] Step S5: The internal processing board transmits the sampled data to the first optical module of the external processing board through the second optical module;

[0033] Step S6: After receiving the data, the external processing board decodes the data and reproduces it to the corresponding pin of the external processing board so that the emulator receives the corresponding feedback signal and realizes the transfer of the JTAG signal.

[0034] In this embodiment, the number of sampled signals obtained by sampling the output pin is no more than eight.

[0035] In this embodiment, after step S1, the sampled data can be encoded; wherein, the data bit length is 32 bits, and the lower eight bits of data are updated each time the sample is taken, and the previous sampled data is shifted eight bits to the right, that is, the 32-bit data contains 4 sampled data.

[0036] In this embodiment, the external processing board uses a high-speed transceiver to transmit the current data to the optical module at a rate of 6.144G. The optical module mainly converts high-speed differential electrical signals into optical signals, enabling high-speed transmission in optical fibers.

[0037] In this embodiment, in step S3, when the received 32-bit data is identical for every 8 bits from low to high, these 8 bits of data are restored to the corresponding pins of the internal processing board; otherwise, the relevant pin level remains unchanged.

[0038] Compared with the prior art, this embodiment has at least the following advantages:

[0039] 1) This embodiment provides a remote debugging method for processors based on optical fiber transmission, which reduces the space occupied while also having the functions of remote downloading and debugging;

[0040] 2) This embodiment uses fiber optic transmission, which can provide a sufficiently long communication distance; it is very suitable for applications where the equipment is difficult to access or disassemble.

[0041] 3) This embodiment can be used for function adjustment. The default state is remote download and debugging of the processor. Through the hardware resistor configuration, it can be set to the working state of 16-bit parallel data fiber optic transmission. It has a wide range of applications and high application value.

[0042] The second embodiment of the present invention, corresponding to the first embodiment, introduces a processor remote debugging device based on optical fiber transmission, such as... Figures 2 to 3 As shown.

[0043] In one possible instance, the device specifically includes: an external processing board, an emulator, an optical module, an internal processing board, and a processor.

[0044] This embodiment is specifically used for signal sampling, transmission, and restoration. It employs fiber optic transmission and requires an optical module that meets specific specifications, as well as an FPGA (Field-Programmable Gate Array) with a high-speed transceiver module. The FPGA primarily samples the signal and packages the data, then uses its internal high-speed transceiver module to convert it into a high-speed differential signal, which is then connected to the electrical terminals of the optical module. The optical module primarily converts the high-speed differential electrical signal into an optical signal, enabling high-speed transmission through the optical fiber.

[0045] In this embodiment, two processing boards are included: one internal to communicate with the processor under test, and the other external to communicate with the emulator. Specific signals include the JTAG signals of the FPGA emulator and the DSP emulator, and one serial port signal, namely FPGA_TDI, FPGA_TDO, FPGA_TCK, FPGA_TMS, DSP_TDI, DSP_TDO, DSP_TCK, DSP_TMS, FPGA_nRST, RS422_TXD, and RS422_RXD.

[0046] For the processing board that communicates with the emulator externally, the sampled input signals are FPGA_TDI, FPGA_TCK, FPGA_TMS, DSP_TDI, DSP_TCK, DSP_TMS, FPGA_nRST, and RS422_TXD. The output signals that need to be restored are FPGA_TDO, DSP_TDO, and RS422_RXD.

[0047] For the processing board located inside the system and responsible for communicating with the processor to be debugged, the sampled input signals are FPGA_TDO, DSP_TDO, and RS422_RXD, and the output signals that need to be restored are FPGA_TDI, FPGA_TCK, FPGA_TMS, DSP_TDI, DSP_TCK, DSP_TMS, FPGA_nRST, and RS422_TXD.

[0048] One processing board encodes the sampled signals (no more than eight samples), with a data length of 32 bits. Each sample updates the lower eight bits, and the previous sample data is shifted eight bits to the right, meaning the 32-bit data contains four sample data points. Then, a high-speed transceiver transmits the data at a rate of 6.144G to an optical module. The optical module converts the electrical signal into an optical signal, which is then transmitted via optical fiber to another processing board. The other processing board decodes the received data packets. If every 8 bits of the received 32-bit data are identical from low to high, these 8 bits are restored to the relevant pins; otherwise, the pin levels remain unchanged.

[0049] The processing board design mainly includes a power module circuit, an FPGA module circuit, a serial port module circuit, and an optical module circuit. The power module circuit provides the necessary power rails for the processing board, such as the FPGA's core voltage of 0.9V, auxiliary voltage of 1.8V, and general-purpose I / O port voltage of 3.3V; the two power rails (0.9V and 1.8V) required by the FPGA's internal high-speed transceiver; and the 3.3V required by the optical module. A four-channel DC / DC switching power supply chip and two LDO power chips provide six power rails. The FPGA module circuit houses the peripheral circuits required for FPGA operation, such as power filtering, system clock, download port, program storage, and high-speed transceiver circuits. The serial port module circuit primarily adds remote serial communication capabilities in addition to remote download and debugging functions. The optical module circuit houses the peripheral circuits required for the optical module's operation.

[0050] Through the description of specific embodiments, a more in-depth and specific understanding should be gained of the technical means and effects adopted by the present invention to achieve the intended purpose. However, the accompanying drawings are only provided for reference and illustration and are not intended to limit the present invention.

Claims

1. A method for remote debugging of a processor based on optical fiber transmission, characterized in that, include: Step S1: The external processing board samples the output pins of the JTAG port of the emulator, wherein the external processing board and the emulator are disposed outside the main body of the implementation device. In step S2, the external processing board transmits the sampled data to the second optical module of the internal processing board through the first optical module. The first optical module and the second optical module are transceivers, and the two are connected by optical fiber to realize data interaction. Step S3: After receiving the data, the internal processing board decodes the data and reproduces it to the corresponding pin of the internal processing board. The pin of the internal processing board is connected to the JTAG port of the processor. The internal processing board and the processor are disposed inside the main body of the implementation device. Step S4: In response to the signal output generated by the processor after receiving a correct JTAG signal, the internal processing board samples the output pin of the processor's JTAG port. Step S5: The internal processing board transmits the sampled data to the first optical module of the external processing board through the second optical module; Step S6: After receiving the data, the external processing board decodes the data and reproduces it to the corresponding pin of the external processing board so that the emulator receives the corresponding feedback signal and realizes the transfer of the JTAG signal.

2. The remote debugging method for processors based on fiber optic transmission according to claim 1, characterized in that, The number of sampled signals obtained by sampling the output pin is no more than eight.

3. The remote debugging method for processors based on fiber optic transmission according to claim 1, characterized in that, After step S1, the method further includes: encoding the sampled data; wherein the data bit length is 32 bits, the lower eight bits of data are updated each time a sample is taken, and the previous sampled data is shifted eight bits to the right, that is, the 32-bit data contains 4 sampled data.

4. The remote debugging method for processors based on fiber optic transmission according to claim 1, characterized in that, The external processing board uses a high-speed transceiver to transmit the current data to the first optical module at a rate of 6.144G.

5. The remote debugging method for processors based on fiber optic transmission according to claim 1, characterized in that, In step S3, when the received 32-bit data is identical for every 8 bits from low to high, these 8 bits of data are restored to the corresponding pins of the internal processing board; otherwise, the relevant pin level remains unchanged.

6. A processor remote debugging device based on fiber optic transmission, characterized in that, include: An external processing board disposed outside the main body of the device, a first optical module disposed on the external processing board, and an emulator; An internal processing board is disposed inside the main body of the device, a second optical module is disposed on the internal processing board, and a processor is disposed thereon; the device is used to implement the remote debugging method for processor based on optical fiber transmission as described in any one of claims 1 to 5.

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