A logic design method based on multi-channel LVDS data path preprocessing

Abstract

The present application relates to a kind of logic design method based on the preprocessing of multi-channel LVDS data path, the logic design method is based on LVDS architecture design, the logic design method obtains the video data of multiple video sources from upstream image processing unit, the video data obtained is distributed to corresponding one or more output channel numbers according to configuration, the video data needed to be transmitted is mapped according to the required protocol, and finally transmitted to downstream serdes;It includes the following steps: video source data mapping;Channel mapping under mode control;LVDS data protocol mapping.The logic design method of the present application, overcome the problem that LVDS module in the prior art usually supports 1 to 2 video output channels, and the compatibility of different video output devices is greatly improved.

Description

Technical Field

[0001] This invention relates to the field of chip design, and in particular to a logic design method based on multi-channel LVDS data path preprocessing. Background Technology

[0002] LVDS (Low Voltage Differential Signaling) is a low-level differential signal transmission technology that enables high-speed data transmission between circuit boards or within a system. LVDS technology is widely used in industrial, medical, video, and communication fields, especially for its excellent performance in high-speed and long-distance data transmission.

[0003] The development history of LVDS technology can be traced back to the 1980s. At that time, Soviet scientist V.S. Soloviev first proposed the concept of LVDS technology, but due to the limitations of technology at the time, LVDS technology was not widely used. It wasn't until the early 1990s, with the development of industrial automation, communication, and computer technologies, that LVDS technology gradually began to be applied. In 1994, the Institute of Electrical and Electronics Engineers (IEEE) released a standard recognizing LVDS technology as a new high-speed serial communication standard, which has been widely used in various fields.

[0004] The principle of LVDS technology is to transmit data using two opposite signals on a transmission line. The differential voltage between these two signals can reach hundreds to thousands of millivolts. Because differential signals have high anti-interference and anti-crosstalk capabilities, LVDS technology can achieve high-speed data transmission and long-distance transmission, while also reducing power consumption and EMI. In LVDS technology, the signal transmission rate between the transmitter and receiver can reach hundreds of megabits per second (Mbps) or even thousands of gigabits per second (Gbps), and the distance can reach hundreds of meters.

[0005] Because LVDS is primarily used in small to medium-sized touchscreen / display devices, a single ASIC chip typically had only one or two output channels in the past (dual channels were usually used in single-screen multiplier output mode). With the development of mobile portable devices, increasingly more intelligent usage scenarios are emerging in laptops, vehicles, and industrial production, where multiple small to medium-sized touchscreens or displays are used simultaneously. Furthermore, with the development of LVDS display devices, two major mapping protocols have gradually formed: the US standard SPWG and the Japanese standard JEIDA. Screens from different manufacturers generally only support their respective manufacturer's protocol mapping, and a single ASIC LVDS protocol transmission chip only supports one corresponding protocol. This mismatch between the two protocols cannot adequately meet the needs of today's era of rapidly expanding computing power, leading to the gradual replacement of dedicated ASIC chips with single LVDS protocol conversion modules by general-purpose processing chips. Summary of the Invention

[0006] To address the aforementioned technical problems, this invention provides a logical design method for preprocessing multi-channel LVDS data paths. This method is based on an LVDS architecture and involves acquiring video data from multiple video sources from an upstream image processing unit. The acquired video data is then allocated to one or more corresponding output channel numbers according to a configuration. The video data to be transmitted is then mapped according to the required protocol in accordance with the LVDS protocol, and finally transmitted to the downstream SERDES. The method includes the following steps: Step S1: Video source data mapping: One or more sets of video data obtained from upstream are distributed to the mode control module through four 4-to-1 muxes controlled by registers; Step S2: Channel mapping under mode control: This configuration is only performed in dual-channel frequency multiplication mode. During the configuration process, the video source needs to be assigned to output channel 0 or 2. Step S3: LVDS Data Protocol Mapping: The video source data transmitted from the mode control module is mapped to conform to the SPWG or JEIDA protocol according to the register configuration requirements; 3 groups of 8-bit RGB data (24 bits in total), 3 data control signals (row synchronization signal, column synchronization signal, and data enable signal), totaling 27 bits of video data, are transmitted to the downstream parallel-to-serial conversion module according to 4 groups of 7-bit protocol format (blank bits are padded with 0).

[0007] In one embodiment of the present invention, the dual-channel frequency multiplication output in step S2 will be fixed to be output by channel 0 or 1 and channel 2 or 3; other output modes are bypass modes, and the output channel labels are the same as the output channel labels.

[0008] In one embodiment of the present invention, in step S3, the polarity of the data control signal can be changed during the mapping process of the data mapping protocol according to the register configuration.

[0009] In one embodiment of the present invention, the LVDS architecture includes a channel mapping module, a mode control module, and a data mapping module; The channel mapping module is connected to the upstream video data transmission and processing module of LVDS, and the data mapping module is connected to the downstream serial-to-parallel conversion module of LVDS. The mode control module is connected to both the channel mapping module and the data mapping module.

[0010] Furthermore, the channel mapping module can connect to up to four video data sources and their data control signals. Data from any input channel can be simultaneously mapped to any number (up to four) of output channels.

[0011] Furthermore, the mode control module, based on the functions configured on the APB bus, either bypasses or down-frequency fans-out the video data of each group of connections to the corresponding connected output channels. In Bypass mode, input data from any channel can be routed to the corresponding output channel by the channel mapping module. In Down-Fan-Out mode, output channels 0 and 1 form one group, and output channels 2 and 3 form another group.

[0012] Furthermore, the data mapping module converts the input video data and its control signals into four sets of 7-bit LVDS-compliant video data according to the data format required by the SPWG or JEIDA protocol, and transmits them to the downstream serdes.

[0013] In one embodiment of the present invention, the channel mapping module can connect to up to 4 sets of RGB888 format video data and related data control signal inputs, and output up to 4 sets of video data mapped according to the LVDS related protocol.

[0014] In one embodiment of the present invention, the channel mapping module simultaneously maps the video data such as RGB data, row synchronization signals, column synchronization signals, and data enable signals of each connection to the corresponding output channel according to the configuration of the APB bus; any input video data can be simultaneously mapped to any output channel. The channel mapping module can select to output a low-level signal when the output channel does not require video data output, instead of leaving it floating and causing the propagation of the Z-state.

[0015] In one embodiment of the present invention, the mode control module configures the data after the channel mapping module according to the function of the APB bus. In single, dual, and separate modes, it is a bypass mode; the data on each input channel can be routed to any one or more output channels, enabling any input source to output on any number (up to 4) of output channels; in split mode, it is a down-frequency fan-out mode; according to the function of the APB bus configuration, in split mode, the video data transmitted by any input source can be fixedly fan-out to output channels 0 and 1 or output channels 2 and 3; The split mode function of the mode control module: When an ultra-high frequency pixel clock and its video data are transmitted to the design module inside the mode control module, the pixel clock is divided by two, and the video data is divided into two groups according to its odd and even pixels and transmitted to two output channels at the same time.

[0016] Compared with the prior art, the above-mentioned technical solution of the present invention has the following advantages: The logic design method described in the present invention overcomes the problem that LVDS modules in the prior art usually only support 1 to 2 video output channels, and greatly improves the compatibility with different video output devices. At the same time, it integrates many advantages of LVDS technology using differential signal transmission, such as high-speed transmission capability, long-distance transmission capability, low power consumption, strong anti-interference and anti-crosstalk capability, and high system integration. Attached Figure Description

[0017] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0018] Figure 1 This is the overall architecture diagram of the logical design method for multi-channel LVDS data path preprocessing of the present invention; Figure 2 This is the SPWG pattern data mapping diagram of the preprocessing logic design method described in this invention; Figure 3 This is the JEIDA pattern data mapping diagram of the logic design method described in this invention. Detailed Implementation Example 1

[0019] like Figure 1 As shown in the diagram, the multi-channel LVDS data path preprocessing logic design architecture involved in this embodiment includes a channel mapping module, a mode control module, a data mapping module, and an APB bus. The channel mapping module connects to the video output data interface of the upstream video processing module. The input interface of this module implements channel mapping preprocessing of four channels of RGB888 video data and their control signals, enabling the routing of any input video data channel to one or more output channel ports.

[0020] In the LVDS architecture, the channel mapping module is connected to the upstream video data transmission and processing module of LVDS, the data mapping module is connected to the downstream serial-to-parallel conversion module of LVDS, and the mode control module is connected to both the channel mapping module and the data mapping module.

[0021] Furthermore, the channel mapping module can connect to up to four video data sources and their data control signals. Data from any input channel can be simultaneously mapped to any number (up to four) of output channels.

[0022] Furthermore, the mode control module, based on the functions configured on the APB bus, either bypasses or down-frequency fans-out the video data of each group of connections to the corresponding connected output channels. In Bypass mode, input data from any channel can be routed to the corresponding output channel by the channel mapping module. In Down-Fan-Out mode, output channels 0 and 1 form one group, and output channels 2 and 3 form another group.

[0023] Furthermore, the data mapping module converts the input video data and its control signals into four sets of 7-bit LVDS-compliant video data according to the data format required by the SPWG or JEIDA protocol, and transmits them to the downstream serdes.

[0024] The mode control module is only used in split mode. In other modes, the mode control module operates in bypass mode, with a one-to-one correspondence between the input and output channels. In split mode, the four output channels are divided into two groups: output channels 0 and 1 form one group, and output channels 2 and 3 form another. When input data comes from output channel 0 or 1 of the channel mapping module, the corresponding pixel clock is divided by two, and the video data is divided into odd pixels and unodd pixels, which are then output to output channel 0 and output channel 1, respectively. When input data comes from output channel 2 or 3 of the channel mapping module, the corresponding pixel clock is divided by two, and the video data is divided into odd pixels and unodd pixels, which are then output to output channel 2 and output channel 3, respectively.

[0025] at the same time Figure 2 and Figure 3 This is a data mapping table for the SPWG and JEIDA multi-channel LVDS data path preprocessing logic design method involved in this embodiment of the invention. The data mapping module rearranges the 27-bit video data received from the mode control module into 28-bit video data packets according to the SPWG or JEIDA protocol. Example 2

[0026] This embodiment provides a logical design method for preprocessing data paths based on multi-channel LVDS. The method is based on an LVDS architecture and involves acquiring video data from multiple video sources from an upstream image processing unit, allocating the acquired video data to one or more corresponding output channel numbers according to configuration, mapping the video data to be transmitted according to the required protocol in accordance with the LVDS protocol, and finally transmitting it to the downstream SERDES. The method includes the following steps: Step S1: Video source data mapping: One or more sets of video data obtained from upstream are distributed to the mode control module through four 4-to-1 muxes controlled by registers.

[0027] Step S2: Channel Mapping under Mode Control: This configuration is only performed in dual-channel frequency multiplication mode. During the configuration process, the video source needs to be assigned to output channel 0 or 2. Dual-channel frequency multiplication output will be fixed to output via channel 0 or 1 and channel 2 or 3. Other output modes are bypass modes, where the output channel labels are the same as the output channel labels.

[0028] Step S3: LVDS Data Protocol Mapping: The video source data transmitted from the mode control module is mapped according to the register configuration requirements, conforming to the SPWG or JEIDA protocol. Three groups of 8-bit (24 bits total) RGB data, three data control signals (row synchronization signal, column synchronization signal, and data enable signal), totaling 27 bits of video data, are transmitted to the downstream parallel-to-serial conversion module according to four groups of 7-bit protocol formats (blank bits are padded with 0). The polarity of the data control signals can be changed during the data mapping process according to the register configuration.

[0029] The logic design method involves mapping video data from multiple channels to different output channels through a data mapping module based on the APB bus configuration, according to different functions. This enables functions such as single-input single-output, single-input multiple-output, multi-screen simultaneous display, multi-screen different display, and frequency multiplication output.

[0030] This embodiment utilizes LVDS technology to build a design method that can be widely applied in industrial, medical, video, and communication fields. Specifically, it can be used for video signal transmission in LCD displays and projectors, and for data transmission between high-speed AD converters and digital signal processors. Furthermore, LVDS technology can also be used in medical devices, industrial automation, and communication equipment.

[0031] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A logic design method based on multi-channel LVDS data path preprocessing, wherein the logic design method is based on LVDS architecture design, characterized in that, The logic design method obtains video data from multiple video sources from the upstream image processing unit, allocates the obtained video data to one or more corresponding output channel numbers according to the configuration, performs data mapping of the video data to be transmitted in accordance with the required protocol, and finally transmits it to the downstream SERDES; including the following steps: Step S1: Video source data mapping: One or more sets of video data obtained from upstream are distributed to the mode control module through four 4-to-1 muxes controlled by registers; Step S2: Channel mapping under mode control: This configuration is only performed in dual-channel frequency multiplication mode. During the configuration process, the video source needs to be assigned to output channel 0 or 2. Step S3: LVDS Data Protocol Mapping: The video source data transmitted from the mode control module is mapped to conform to the SPWG or JEIDA protocol according to the register configuration requirements; 3 groups of 8-bit RGB data (24 bits in total), 3 data control signals (row synchronization signal, column synchronization signal, and data enable signal), totaling 27 bits of video data, are transmitted to the downstream parallel-to-serial conversion module according to 4 groups of 7-bit protocol format. The mode control module uses the functions configured on the APB bus to route the data after the channel mapping module to bypass mode in single, dual, and separate modes. Data on each input channel can be routed to any one or more output channels, enabling any input source to output on any number of output channels. In split mode, it uses a down-frequency fan-out mode. According to the functions configured on the APB bus, in split mode, video data transmitted by any input source can be fixedly fan-out to output channels 0 and 1 or output channels 2 and 3.

2. The logic design method according to claim 1, characterized in that: In step S2, the dual-channel frequency multiplication output will be fixed to be output by channel 0 or 1 and channel 2 or 3; other output modes are bypass modes, and the output channel labels are the same as the output channel labels.

3. The logic design method according to claim 1, characterized in that: In step S3, the polarity of the data control signal can be changed during the mapping process of the data mapping protocol according to the register configuration.

4. The logic design method according to claim 1, characterized in that: The LVDS architecture includes a channel mapping module, a mode control module, and a data mapping module; The channel mapping module is connected to the upstream video data transmission and processing module of LVDS, and the data mapping module is connected to the downstream serial-to-parallel conversion module of LVDS. The mode control module is connected to both the channel mapping module and the data mapping module.

5. The logic design method according to claim 4, characterized in that: The channel mapping module can connect to up to 4 sets of RGB888 format video data and related data control signal inputs, and output up to 4 sets of video data mapped according to the LVDS related protocol.

6. The logic design method according to claim 4, characterized in that: Meanwhile, the channel mapping module maps the video data of each connection, such as RGB data, row synchronization signals, column synchronization signals, and data enable signals, to the corresponding output channels according to the configuration of the APB bus. Any input video data can be mapped to any output channel simultaneously; The channel mapping module can select to output a low-level signal when the output channel does not require video data output, instead of leaving it floating and causing the propagation of the Z-state.

7. The logic design method according to claim 4, characterized in that: The split mode function of the mode control module: When an ultra-high frequency pixel clock and its video data are transmitted to the design module inside the mode control module, the pixel clock is divided by two, and the video data is divided into two groups according to its odd and even pixels and transmitted to two output channels at the same time.

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