Processing device control method and apparatus, electronic device, and storage medium

Abstract

The present disclosure provides a processing device control method, device, electronic device and storage medium. A processing device control method is provided, the processing device comprising a first processor and a second processor connected in communication with each other, the second processor being connected in communication with a display component, the second processor being configured to receive a display image and send the display image to the display component for display, the control method comprising: in response to target information, the second processor stopping receiving the display image; the first processor reading a first preset image pre-stored outside the second processor and sending the first preset image to the display component for display without passing through a processing unit of the second processor; the second processor being reset; the first processor stopping sending the first preset image, and the second processor resuming receiving the display image and sending the display image to the display component for display. The display component is prevented from being blacked out during the reset of the second processor, thereby improving the user experience.

Description

Technical Field

[0001] This disclosure relates to the field of smart terminal technology, and in particular to a processing device method, apparatus, electronic device, and storage medium. Background Technology

[0002] Most mobile smart products, such as smartphones, use independent SOC (System-on-Chip) chip solutions. In these independent SOC chip solutions, the CPU (Central Processing Unit), DPU (Display Processing Unit), and Flash (Memory Processing Unit) are all located inside the SOC. With continuous product iteration and updates, solutions have emerged that combine these components by adding coprocessors. Summary of the Invention

[0003] This disclosure provides a processing device control method, apparatus, electronic device, and storage medium.

[0004] The following technical solution is adopted in this disclosure.

[0005] In some embodiments, this disclosure provides a method for controlling a processing device, the processing device including a first processor and a second processor communicatively connected to each other, the second processor being communicatively connected to a display component, the second processor being configured to receive a display image and send it to the display component for display, the control method including:

[0006] In response to the target information, the second processor stops receiving the display image;

[0007] The first processor reads a first preset image that is stored outside the second processor, and sends the first preset image to the display component for display without going through the processing unit of the second processor;

[0008] The second processor is reset;

[0009] The first processor stops sending the first preset image, and the second processor resumes receiving the display image and sends it to the display component for display.

[0010] In some embodiments, this disclosure provides a method for controlling a processing device, the processing device including a first processor and a second processor communicatively connected to each other, the second processor being communicatively connected to a display component, the control method including:

[0011] In response to power-on, the first processor initializes;

[0012] The first processor sends first information to the display component without going through the processing unit of the second processor, in order to initialize the display component;

[0013] The first processor reads the boot image;

[0014] Before the kernel system of the first processor starts up and before the display processing unit of the second processor is initialized, the first processor sends the boot image to the display component for display without going through the processing unit of the second processor.

[0015] In some embodiments, this disclosure provides a processing device control apparatus, the processing device including a first processor and a second processor that are communicatively connected to each other, the second processor being communicatively connected to a display component, the second processor being used to receive display images and send them to the display component for display, the control apparatus including: a first control module and a second control module;

[0016] The second control module is used to control the second processor to stop receiving and displaying images in response to target information;

[0017] The first control module is used to control the first processor to read a first preset image that is pre-stored outside the second processor, and to send the first preset image to the display component for display without going through the processing unit of the second processor;

[0018] The second control module is also used to control the second processor to reset;

[0019] The first control module is further configured to control the first processor to stop sending the first preset image;

[0020] The second control module is also used to control the second processor to resume receiving and displaying images and send them to the display component for display.

[0021] In some embodiments, this disclosure provides a processing device control apparatus, the processing device including a first processor and a second processor communicatively connected to each other, the second processor being communicatively connected to a display component, the control apparatus including:

[0022] The first control module is used to control the first processor to initialize in response to power-on;

[0023] The first control module is further configured to control the first processor to send first information to the display component without going through the processing unit of the second processor, so as to initialize the display component;

[0024] The first control module is also used to control the first processor to read the boot image;

[0025] The first control module is further configured to control the first processor to send the boot image to the display component for display without passing through the processing unit of the second processor before the kernel system of the first processor starts and before the display processing unit of the second processor is initialized.

[0026] In some embodiments, this disclosure provides an electronic device, including: at least one memory and at least one processor;

[0027] The memory is used to store program code, and the processor is used to call the program code stored in the memory to execute the above method.

[0028] In some embodiments, this disclosure provides a computer-readable storage medium for storing program code that, when run by a processor, causes the processor to perform the methods described above.

[0029] In some embodiments of this disclosure, when the second processor needs to be reset, a first preset image is read and sent to the display component. The first preset image is not located within the second processor and does not pass through the display component of the second processor, thereby avoiding a black screen on the display component during the reset of the second processor and improving the user experience. Attached Figure Description

[0030] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and elements are not necessarily drawn to scale.

[0031] Figure 1 This is a flowchart of a control method for a processing device according to an embodiment of the present disclosure.

[0032] Figure 2 This is a schematic diagram of the structure of the processing device according to an embodiment of the present disclosure.

[0033] Figure 3 This is an interactive diagram of the control method of the processing device according to an embodiment of the present disclosure.

[0034] Figure 4 This is an interactive diagram of the control method of the processing device according to an embodiment of the present disclosure.

[0035] Figure 5 This is an interaction diagram of the second processor detecting abnormal information in an embodiment of this disclosure.

[0036] Figure 6This is a flowchart of a control method for a processing device according to an embodiment of the present disclosure.

[0037] Figure 7 This is a schematic diagram of the structure of an independent SOC in an embodiment of this disclosure.

[0038] Figure 8 This is a timing diagram of the independent SOC displaying the boot image in an embodiment of this disclosure.

[0039] Figure 9 This is a schematic diagram of the structure of multiple SOC tiles at the board level in an embodiment of this disclosure.

[0040] Figure 10 This is a timing diagram of the power-on image displayed by a board-level multi-SOC tile display in an embodiment of this disclosure.

[0041] Figure 11 This is a schematic diagram of the structure of the processing device according to an embodiment of the present disclosure.

[0042] Figure 12 This is an interactive diagram of the control method of the processing device according to an embodiment of the present disclosure.

[0043] Figure 13 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0044] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0045] It should be understood that the various steps described in the method embodiments of this disclosure can be performed in sequence and / or in parallel. Furthermore, method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.

[0046] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0047] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0048] It should be noted that the use of the word "a" in this disclosure is illustrative rather than restrictive, and those skilled in the art should understand that it should be understood as "one or more" unless otherwise expressly indicated in the context.

[0049] The names of messages or information exchanged between multiple devices in the embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of such messages or information.

[0050] The solutions provided by the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0051] Example 1

[0052] This disclosure provides a method for controlling a processing device in some embodiments. The processing device includes a first processor and a second processor communicatively connected to each other. The second processor is communicatively connected to a display component and is used to receive display images and send them to the display component for display. Figure 1 As shown, Figure 1 This is a flowchart of a processing device control method according to an embodiment of the present disclosure, which includes the following steps.

[0053] S11. In response to the target information, the second processor stops receiving the display image.

[0054] In some embodiments, the processing device proposed in this disclosure can be a board-level multi-SoC tile, such as... Figure 2As shown, the first processor and the second processor can be interconnected main processors and coprocessors within a board-level multi-SoC chip. They can be connected and communicate via PCIe (peripheral component interconnect express, high-speed serial computer expansion bus standard), SPI (serial peripheral interface), and MIPI (Mobile Industry Processor Interface). The first processor can be the main processor of the board-level multi-SoC chip, and the second processor can be the coprocessor of the board-level multi-SoC chip. The first and second processors can be packaged in a single SoC chip. The first processor can include processing units such as a CPU (Central Processing Unit, also known as the main chip), DDR (Double Data Rate, memory processing unit), Flash (storage processing unit, also known as a storage controller), and DPU (display processing unit, also known as a display control chip). The second processor can be responsible for display functions and has processing units, specifically including CPU, DDR, and DPU, but may not have Flash memory. The second processor, specifically the display processing unit (DPU) within it, receives display images from an external processing device and transmits them to the display component. The display component, such as... Figure 2 The device may include a DDIC (Display Driver IC) and a Panel. The display components can communicate with the second processor via a MIPI interface (specifically, a MIPI DSI interface). Figure 2 In the interface between the main processor and coprocessor, RC (Root Complex) represents the root complex, and EP (Endpoint) represents the PCIe terminal device. TX represents the SPI transmitter, and RX represents the receiver. M represents the SIP master, and S represents the SPI slave. In some embodiments, the target information can be information indicating that the second processor needs to be reset, which can be received by either the first or second processor. The target information can be, for example, exception information detected by either the first or second processor and sent to either the first or second processor after detection. Alternatively, the target information can be control information indicating that the second processor needs to be reset, which can be sent to the second processor after the first processor receives the target information. Upon receiving the target information, the second processor will stop receiving and displaying images.

[0055] S12. The first processor reads a first preset image that is stored outside the second processor, and sends the second preset image to the second display unit for display without going through the processing unit of the second processor.

[0056] In some embodiments, because the second processor stops receiving display images, the first processor reads a pre-stored first preset image to prevent display malfunctions. Since the second processor needs to be reset, the first preset image is stored externally, possibly in the first processor's memory processing unit (DDR). The first preset image can be a static or dynamic image, and there can be one or more first preset images. Because the second processor is about to reset, its internal processing units, such as the CPU and DDR, may restart. Therefore, the first preset image bypasses the processing units (CPU, DDR, DPU) of the first processor and is directly sent to the display device for display.

[0057] S13, the second processor is reset.

[0058] In some embodiments, the second processor may be restarted while the first processor remains powered on and continues to read the first preset image and send it to the display component.

[0059] S14. The first processor stops sending the first preset image, and the second processor resumes receiving the display image and sends it to the display component for display.

[0060] In some embodiments, the first processor may stop reading and sending a first preset image, and the second processor may resume receiving and sending display images to the display component after a reset.

[0061] In some embodiments of this disclosure, when the second processor needs to be reset, a first preset image is read and sent to the display component. The first preset image is not located within the second processor and does not pass through the display component of the second processor, thereby avoiding a black screen on the display component during the reset of the second processor.

[0062] In some embodiments, taking a board-level multi-SoC tiled processing device as an example, the coprocessor is responsible for the display function. When the main processor is normal but the coprocessor fails, the coprocessor will perform a reset and restart operation, and the main processor will not lose power. If the display component is black, the user experience is poor. In some embodiments of this disclosure, when the coprocessor fails and needs to be reset and restarted, the display component can maintain the display of a first preset image, thereby improving the user experience.

[0063] In some embodiments of this disclosure, the second processor is communicatively connected to the first processor via a first communication interface, and the second processor is communicatively connected to the display component via a second communication interface, wherein there is a direct link between the first communication interface and the second communication interface;

[0064] Sending the first preset image to the display component for display without going through the processing unit of the second processor includes: the first processor sending the first preset image to the first communication interface, so that the first preset image is sent to the display component for display via the first communication interface, the direct link and the second communication interface.

[0065] In some embodiments, the first communication interface may be Figure 2 The first communication interface is a MIPI interface between the main processor and the coprocessor. The second communication interface can be a MIPI interface between the coprocessor and the display unit, as shown in Figure 2. There is a direct link between the first communication interface and the second communication interface. Figure 2 The dotted line (with the arrow indicating the transmission direction of the first preset image) in the diagram represents a direct connection mode achieved through a direct-through link. After the first preset image is read, it is sent to the display component via the first communication interface, the direct-through link, and the second communication interface, without passing through the display components such as the CPU, DDR, and DPU of the second processor.

[0066] In some embodiments of this disclosure, after the second processor stops receiving the display image in response to the target information and before the first processor sends the first preset image to the first communication interface, the method further includes: the first processor sending a first notification to the second processor through a third communication interface to inform the second processor to enable the pass-through link.

[0067] In some embodiments, the third communication interface may be Figure 2 In the SPI interface, the Master end of the SPI interface sends the first notification to the Slave end, and the Slave segment configures MIPI to select a straight-through link from MIPI's RX to MIPI's TX.

[0068] In some embodiments of this disclosure, after the second processor stops receiving display images, before sending the first preset image to the display component for display without passing through the processing unit of the second processor, the method further includes: the second processor reading a pre-stored second preset image and sending the second preset image to the display component for display, until the first preset image is sent to the display component for display. In some embodiments, the second preset image is stored in the memory processing unit of the second processor.

[0069] In some embodiments, after the second processor starts up, the second preset image is loaded into the DDR memory of the second processor. When the second processor detects abnormal information of a fault (such as a software fault or a watchdog fault), it will configure the display processing unit (DPU) to read the second preset image for display. In this way, the display component will not have a black screen with no display content before the first preset image is read.

[0070] In some embodiments of this disclosure, in response to target information, the second processor stops receiving display images, including: in response to the second processor detecting abnormal information or detecting information to reset the second processor, the second processor sends a second notification to the first processor and stops receiving display images; or, in response to the first processor detecting abnormal information or detecting information to reset the second processor, the first processor sends a third notification to the second processor to cause the second processor to stop receiving external display images.

[0071] In some embodiments, the application scenarios of the method proposed in this disclosure can be scenarios where the second processor detects a fault or where the second processor needs to be actively reset. Alternatively, it can be scenarios where the first processor needs to actively reset the second processor (e.g., the second processor is stuck and unresponsive, including keeplive timeout, watchdog exception, etc.). The second notification can be informing the first processor that abnormal information has been detected or that the second processor needs to be reset. The third notification can be informing the second processor that abnormal information has been detected or that the second processor needs to be reset.

[0072] Figure 4 and Figure 5 Two specific embodiments are illustrated below. They will be described separately. Figure 3 In this context, it addresses scenarios where the coprocessor (secondary processor) detects an internal fault or needs to be actively restarted.

[0073] During initialization, the main processor and coprocessor load the first and second preset images into their respective DDRs.

[0074] An exception occurs, and the CPU of the coprocessor receives an exception notification (Exception Notify).

[0075] The coprocessor's DPU stops receiving external display images and switches to read a second preset image from a fixed position. Data is then sent to the display unit via MIPI DSI.

[0076] The coprocessor's CPU notifies the main processor that an exception has occurred.

[0077] After receiving a notification of a fault, the main CPU configures the coprocessor to use the SPI interface to enable direct-through mode by SPI.

[0078] The main processor (DPU) reads the preset first image and sends it to the display unit for display via MIPI.

[0079] The main processor (CPU) controls the coprocessor to reset (warm reset).

[0080] After the coprocessor restarts and is reinitialized, the coprocessor CPU switches from pass-through mode to normal mode (disabledirect-through mode).

[0081] The main processor stops reading the first preset image and switches to normal image data for display.

[0082] The DPU (Digital Processing Unit) reads the preset memory to prevent the main processor from failing to handle coprocessor exceptions in time, which could cause a timeout and result in a black screen.

[0083] exist Figure 4 This mainly addresses scenarios where the main processor (first processor) needs to actively reset the coprocessor (second processor) or where the coprocessor is stuck and unable to respond (including keeplive timeout, watchdog exception, pmic exception, etc.). Figure 4 As shown:

[0084] During initialization, the main processor and coprocessor load the first and second preset images into their respective DDRs.

[0085] The main processor CPU receives a reset coprocessor signal or a coprocessor exception signal (Reset Signal or Exception Notify).

[0086] The main processor (CPU) notifies the coprocessor to perform a reset, and then configures the coprocessor to display pass-through mode via the SPI interface.

[0087] The main processor (DPU) reads the preset image data, transmits it to the pass-through link, and sends it to the display component for display.

[0088] The main processor CPU performs a warm reset on the coprocessor (the coprocessor pass-through link does not restart during this time).

[0089] After the coprocessor restarts, the display path is reinitialized and the pass-through mode is switched to normal mode.

[0090] After the coprocessor restarts, the main processor stops reading the first preset image and switches to displaying the normal data image.

[0091] In some embodiments of this disclosure, the second processor detects the abnormal information by acquiring the time interval from the current time to the last time an image was received for display.

[0092] If the time interval reaches a preset time threshold, then an abnormality is determined to have occurred.

[0093] In some embodiments, such as Figure 5 As shown, the second processor's DPU can initiate a continuous frame detection mechanism, setting a frame timeout period (which can be a multiple of the frame interval). When no external source image frame is received, the timeout count period increases. If no timeout occurs, normal display occurs. When a new frame image arrives, the timeout count is cleared. When the frame count reaches the frame timeout threshold, the display component DDIC / Panel receives no valid display through the MIPI DSI interface, then switches to test mode output, which can output a second preset image. After a new frame image arrives, the count is cleared, and the system switches to normal mode for continued normal display. In some embodiments of this disclosure, the second processor's DPU can integrate a test mode, simulating digital images for display through digital calculation. The DPU adds continuous no-image frame detection, which is performed by input counting. If no new frame is input for, for example, 30ms (the detection time is adjustable by software), the system switches to DPU test mode.

[0094] In some embodiments of this disclosure, when the second processor is reset, the display processing unit (DPU) in the second processor, the first communication interface between the second processor and the first processor, the second communication interface between the second processor and the display component, and the display component remain powered on.

[0095] In some embodiments, when the second processor is reset, the display processing unit, the first communication interface, the second communication interface, and the display component of the second processor are not reset, but remain powered on, so that the first preset image can still be sent to the display component during the second processor reset, without the screen going black.

[0096] In some embodiments of this disclosure, in scenarios where the second processor needs to be reset, preset images (static or dynamic) can continue to be displayed, avoiding prolonged user-perceptible black screens in such scenarios, thus improving user experience and product reliability competitiveness. The method proposed in this disclosure can eliminate or reduce the black screen time caused by the restart of the second processor from approximately 10 seconds to occasional black screen flickering, thereby significantly improving the user experience.

[0097] Example 2

[0098] In some embodiments of this disclosure, another processing device control method is also proposed. This device processing method can be combined with Embodiment 1 without conflict. After executing any of the processing device control methods in Embodiment 2, any of the processing device control methods in Embodiment 1 can be executed. The combination of Embodiment 2 and Embodiment 1 should also fall within the protection scope of this disclosure. The definitions and related descriptions in Embodiment 1 of this disclosure also apply to Embodiment 2 without conflict.

[0099] In related technologies, such as Figure 7 As shown, a standalone SOC processing device has a processor, including CPU, DDR, Flash, DPU, and other processing units. It communicates with the display component through a MIPI interface. During the system startup phase, the timing diagram for displaying the boot image (usually the boot logo) is as follows. Figure 8 As shown. The SOC powers on, the bootrom (Power-On Self-Test) initializes, initializing the Flash and CPU; it then enters the SPL stage, where the DDR is initialized. The CPU sends a command to the Flash to read the DPU image data (load dpu img), loading the DPU image data into the specified location (dpu imgdata), and then powers on the DPU (power on dpu). The DPU initializes, and simultaneously the CPU initializes the DDIC controller; after this stage, the system is capable of displaying images. The CPU sends a command to the Flash to read the boot logo data (load logo), storing the boot logo data into the specified location in the DDR. The DPU reads the boot logo data from the DDR and outputs it to the DDIC display; the boot logo is displayed normally; for an independent SOC, the time from power-on to normal boot logo display is less than 2 seconds.

[0100] For board-level multi-SoC chip products with added coprocessors, such as Figure 9As shown, it has a main processor and a coprocessor. Display control is located in the coprocessor. In this scenario, there are two hardware design approaches: one with a coprocessor containing independent Flash (higher cost) and another without Flash (Flashless solution, lower cost). The Flash-enabled solution adds independent Flash to the coprocessor. Its advantage is that the boot logo can be stored on the coprocessor side, and the boot logo display time is consistent with the independent SOC solution. The disadvantage is higher product cost. The Flashless solution uses shared Flash, with the Flash storage medium located on the main processor side. Its advantage is lower cost, but the disadvantage is a significant delay in the boot logo display time. The timing diagram for its boot image display is shown below. Figure 10 As shown ( Figure 10 The left side is the main processor, and the right side is the coprocessor. After the main processor powers on, the bootrom powers on, and the SP1 stage, in the bootloader stage, the main processor's CPU reads the image data from Flash and transmits it to the coprocessor. Then, the main processor enters the kernel stage, and the kernel system of the main processor starts. After the CPU and DDR of the coprocessor are initialized, the main processor and the coprocessor perform a handshake (PCIe handshake). The main processor enters the initialization process, loads the DPU image data of the coprocessor (load DPU image), and sends it to the coprocessor. The DPU of the coprocessor powers on and initializes. Then, the CPU of the main processor loads the logo and sends it to the DDR of the coprocessor. The DPU of the coprocessor loads the logo from the DDR of the coprocessor and displays it through the display driver chip DDIC of the display component. Compared with the independent SOC solution, the board-level multi-SOC chip product solution requires the main processor kernel system to finish booting and the init process to start before it can support the boot logo display. It is estimated that it will take more than 10 seconds from power-on to boot logo display, resulting in a poor user experience.

[0101] In some embodiments of this disclosure, the processing device includes a first processor and a second processor communicatively connected to each other, the second processor being communicatively connected to a display component, such as... Figure 6 As shown, the control method includes:

[0102] S21. In response to power-on, the first processor performs initialization.

[0103] In some embodiments, the processing device in this disclosure may be a board-level multi-SoC tile, such as... Figure 11As shown, the first processor and the second processor can be board-level multi-SoC chipsets, including interconnected main-processor and co-processor. They can be connected and communicate via PCIe, SPI, and MIPI interfaces. The first processor can be the main processor of the board-level multi-SoC chipet, and the second processor can be the co-processor of the board-level multi-SoC chipet. The first and second processors can be packaged in a single SoC chip. The first processor can include processing units such as CPU (Central Processing Unit), DDR (Double Data Rate), Flash (storage processing unit, also known as storage controller), and DPU (display processing unit). The second processor can be responsible for display functions and has processing units, specifically including CPU, DDR, and DPU, and may or may not have Flash. Display components such as... Figure 11 The device may include a DDIC (Display Driver IC) and a Panel. The display components can communicate with the second processor via a MIPI interface (specifically, a MIPI DSI interface). Figure 11 In the interface between the main processor and coprocessor, RC (Root Complex) represents the root complex, and EP (Endpoint) represents the PCIe terminal device. TX represents the SPI transmitter, and RX represents the receiver. M represents the SIP master, and S represents the SPI slave. In some embodiments, the method in this embodiment is used to process the device system startup phase. When the device is powered on, the first processor will be initialized; specifically, the Flash, CPU, and DDR in the first processor can be initialized at this time.

[0104] S22. The first processor sends first information to the display unit without going through the processing unit of the second processor to initialize the display unit.

[0105] In some embodiments, when step S22 is executed, the second processor may not have been initialized yet. In order to display the boot image, the display component needs to be initialized first so that the display component has the ability to display the boot image.

[0106] S23, The first processor reads the boot image.

[0107] In some embodiments, specifically, since initialization has already been performed, the central processing unit (CPU) of the first processor may read the boot image (e.g., boot logo) from the flash memory of the first processor.

[0108] S24. Before the kernel system of the first processor starts up and before the display processing unit of the second processor is initialized, the first processor sends the boot image to the display component for display without going through the processing unit of the second processor.

[0109] In some embodiments, the first processor sends the boot image to the display component without passing through the processing units of the second processor (including the CPU, DDR, DPU, etc. of the second processor), specifically to the display driver chip DDIC of the display component for display on the display panel. At this time, the kernel system of the first processor has not yet started, and the display processing unit of the second processor has not yet been initialized. In some embodiments, when S24 is executed, all processing units of the second processor (including CPU and DDR) may be uninitialized, or the CPU may have already been initialized.

[0110] In some embodiments of this disclosure, different Figure 10 The method of loading the boot image in the first processor does not involve the boot image processing unit of the second processor. Therefore, it does not need to wait for the kernel system of the first processor to start, nor does it need to wait for the display processing unit of the second processor to initialize. This differs from... Figure 10 The previous solution required waiting for the kernel system of the first processor to complete booting and the initialization process to start. In this embodiment, however, waiting for these processes to complete is unnecessary, thus accelerating the display of the boot image. This makes the boot image display time for multi-SoC panelization on a board similar to that of an independent SoC, improving the user experience. When this solution is used in scenarios where the second processor does not have Flash memory, it can reduce costs without increasing the boot image display time.

[0111] In some embodiments of this disclosure, the second processor and the first processor are communicatively connected via a first communication interface, such as... Figure 11 As shown, the first communication interface can be a MIPI interface, and the second processor and the display component are connected via a second communication interface, which can also be a MIPI interface. There is a direct link between the first and second communication interfaces. Figure 11 As shown, there is a direct-through link between the RX and TX ends of the MIPI interface, which allows the first processor to communicate directly with the display component without going through the processing unit of the second processor.

[0112] The first processor sends first information to the display component to initialize the display component without going through the processing unit of the second processor, including: the first processor sending the first information to the display component through the first communication interface, the pass-through link, and the second communication interface. In some embodiments, such as Figure 11 As shown, the CPU of the first processor can transmit first information through the MIPI interface between the first processor and the second processor. After the first information reaches the RX end of the second processor, it is transmitted to the TX end of the second processor through a direct link, and then transmitted to the DDIC of the display component through the MIPI interface between the second processor and the display component, so that the display component can be initialized.

[0113] In some embodiments of this disclosure, the first processor sends the boot image to the display device for display without passing through the processing unit of the second processor. This includes: the first processor sending the boot image to a first communication interface, so that the boot image is sent to the display device for display via the first communication interface, the pass-through link, and the second communication interface. In some embodiments, similar to the process of sending the first information, the first processor's DDR sends the boot image. After the boot image reaches the RX terminal of the second processor via the first communication interface, it is transmitted to the TX terminal of the second processor via the pass-through link, and then transmitted to the DDIC of the display device via the MIPI interface between the second processor and the display device, so that the display device displays the image.

[0114] In some embodiments of this disclosure, in response to power-on, after the first processor initializes, before the first processor initializes the display component without going through the processing unit of the second processor, the method further includes: the first processor sending second information to the second processor through a third communication interface to inform the second processor to enable the pass-through link.

[0115] In some embodiments, such as Figure 11 As shown, the second processor requires both a direct link between its RX and TX terminals and a path connected via the DPU. Therefore, it is necessary to enable the direct link. The third communication interface could be... Figure 11 In the SPI interface, the first processor sends second information to the Slave through the Master end of the SPI interface, and the Slave segment of the second processor configures the MIPI to select a direct link from the RX end of the second processor's MIPI to the TX end of the MIPI.

[0116] In some embodiments of this disclosure, in response to power-on, the first processor is initialized, including: in response to power-on, the central processing unit, storage processing unit and memory processing unit of the first processor are initialized.

[0117] After the first processor sends first information to the display component to initialize the display component without going through the processing unit of the second processor, before the first processor reads the boot image, the method further includes: the first processor's central processing unit reads the image data of the first processor's display processing unit from the first processor's storage processing unit, loads the image data, and the first processor's display processing unit is powered on and initialized.

[0118] In some embodiments, when the device is powered on, some processing units are initialized first. The display processing unit of the first processor, which has not yet been initialized, is initialized first. After the display component is initialized, it is guaranteed to have the ability to send the first information. After the first information is sent, the image data is read to initialize the display processing unit of the first processor. This allows the display processing unit of the first processor to be initialized in parallel with the initialization of the display component, thereby saving time.

[0119] In some embodiments of this disclosure, after the first processor sends the boot image to the display component for display without passing through the processing unit of the second processor, the method further includes: initializing the central processing unit and memory processing unit of the second processor; and starting the kernel system of the first processor. In some embodiments, after sending the boot image, the kernel system startup process of the first processor and the initialization process of the processing unit of the second processor are executed. By moving these processes after sending the boot image, the boot image is displayed quickly after power-on, avoiding user waiting and improving the user experience.

[0120] To better illustrate the method proposed in this disclosure, the following is combined with... Figure 12 A specific implementation example is proposed. Figure 12 The Flash, CPU, DDR, and DPU on the left belong to the first processor, while the CPU, DDR, and DPU on the right belong to the second processor, and the DDIC belongs to the display component.

[0121] After power-up, the system enters the bootrom stage. During this stage, the Flash and CPU of the first processor are initialized. Then, the system enters the SP1 stage, where the DDR of the first processor is initialized. Next, the bootloader stage begins. The CPU of the first processor enables direct-through mode us SPI via the SPI interface between the first and second processors and sends the first message to the DDIC through this direct-through link to initialize the display unit (Congif DDIC enable). Then, the CPU of the first processor loads the image data of the first processor's DPU from the Flash (load dpu img), powers up the DPU (power up dpu), initializes the first processor's DPU, and loads the boot image from the Flash (load logo) and sends it to the DDIC through the direct-through link, causing the display unit to display the boot image. After this, the kernel system of the first processor is started.

[0122] Example 3

[0123] This disclosure also proposes a processing device control apparatus, the processing device including a first processor and a second processor that are communicatively connected to each other, the second processor being communicatively connected to a display component, the second processor being used to receive display images and send them to the display component for display, the control apparatus including: a first control module and a second control module;

[0124] The second control module is used to control the second processor to stop receiving and displaying images in response to target information;

[0125] The first control module is used to control the first processor to read a first preset image that is pre-stored outside the second processor, and to send the first preset image to the display component for display without going through the processing unit of the second processor;

[0126] The second control module is also used to control the second processor to reset;

[0127] The first control module is further configured to control the first processor to stop sending the first preset image;

[0128] The second control module is also used to control the second processor to resume receiving and displaying images and send them to the display component for display.

[0129] In some embodiments, the second processor is communicatively connected to the first processor via a first communication interface, and the second processor is communicatively connected to the display component via a second communication interface, wherein there is a direct link between the first communication interface and the second communication interface;

[0130] Sending the first preset image to the display component for display without going through the processing unit of the second processor includes: controlling the first processor to send the first preset image to the first communication interface, so that the first preset image is sent to the display component for display via the first communication interface, the direct link and the second communication interface.

[0131] In some embodiments, after the second control module controls the second processor to stop receiving the display image in response to the target information, and before the first control module controls the first processor to send the first preset image to the first communication interface, the first control module is further configured to: control the first processor to send a first notification to the second processor through a third communication interface to inform the second processor to enable the pass-through link.

[0132] In some embodiments, in response to target information, after the second control module controls the second processor to stop receiving display images, before the first control module controls the first processor to send the first preset image to the display component without passing through the processing unit of the second processor for display, the second control module is further configured to: control the second processor to read a pre-stored second preset image and send the second preset image to the display component for display, until the first preset image is sent to the display component for display.

[0133] In some embodiments, the second preset image is stored in the memory processing unit of the second processor.

[0134] In some embodiments, in response to target information, controlling the second processor to stop receiving display images includes: in response to the second processor detecting abnormal information or detecting information to reset the second processor, controlling the second processor to send a second notification to the first processor and stop receiving display images; or,

[0135] In response to the first processor detecting abnormal information or detecting information to reset the second processor, the first control module controls the first processor to send a third notification to the second processor; in response to the third notification, the second control module controls the second processor to stop receiving external display images.

[0136] In some embodiments, the second control module is further configured to control the second processor to detect the abnormal information in the following manner: the second processor obtains the time interval from the current time to the last time an image was received for display; if the time interval reaches a preset time threshold, it is determined that abnormal information has been generated.

[0137] In some embodiments, when the second processor is reset, the display processing unit in the second processor, the first communication interface between the second processor and the first processor, the second communication interface between the second processor and the display component, and the display component remain powered on.

[0138] Example 4

[0139] This disclosure also provides a processing device control apparatus, the processing device including a first processor and a second processor communicatively connected to each other, the second processor being communicatively connected to a display component, the control apparatus including:

[0140] The first control module is used to control the first processor to initialize in response to power-on;

[0141] The first control module is further configured to control the first processor to send first information to the display component without going through the processing unit of the second processor, so as to initialize the display component;

[0142] The first control module is also used to control the first processor to read the boot image;

[0143] The first control module is further configured to control the first processor to send the boot image to the display component for display without passing through the processing unit of the second processor before the kernel system of the first processor starts and before the display processing unit of the second processor is initialized.

[0144] In some embodiments, the second processor is communicatively connected to the first processor via a first communication interface, and the second processor is communicatively connected to the display component via a second communication interface, wherein there is a direct link between the first communication interface and the second communication interface;

[0145] Controlling the first processor to send first information to the display component without going through the processing unit of the second processor to initialize the display component includes: controlling the first processor to send the first information to the display component through the first communication interface, the pass-through link and the second communication interface;

[0146] In some embodiments, controlling the first processor to send the boot image to the display component for display without passing through the processing unit of the second processor includes: controlling the first processor to send the boot image to a first communication interface, so that the boot image is sent to the display component for display via the first communication interface, the pass-through link, and the second communication interface.

[0147] In some embodiments, in response to power-on and after controlling the first processor to initialize, before controlling the first processor to initialize the display component without going through the processing unit of the second processor, the first control module is further configured to: control the first processor to send second information to the second processor through a third communication interface to inform the second processor to enable the pass-through link.

[0148] In some embodiments, in response to power-on, the first processor is controlled to initialize, including: in response to power-on, the central processing unit, storage processing unit and memory processing unit of the first processor are controlled to initialize;

[0149] After controlling the first processor to send first information to the display component without going through the processing unit of the second processor to initialize the display component, the first control module is further configured to: control the central processing unit of the first processor to read the image data of the display processing unit of the first processor from the storage processing unit of the first processor, load the image data, and control the display processing unit of the first processor to power on and initialize.

[0150] In some embodiments, after the first control module controls the first processor to send the boot image to the display component for display without passing through the processing unit of the second processor, the second control module is further configured to control the initialization of the central processing unit and memory processing unit of the second processor. The first control module is also configured to control the startup of the kernel system of the first processor.

[0151] For embodiments of the apparatus, since they basically correspond to the method embodiments, relevant details can be found in the descriptions of the method embodiments. The apparatus embodiments described above are merely illustrative, and the modules described as separate modules may or may not be separate. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0152] The methods and apparatus of this disclosure have been described above based on embodiments and application examples. Furthermore, this disclosure also provides an electronic device and a computer-readable storage medium, which are described below.

[0153] The following is for reference. Figure 13 The figure illustrates a structural schematic of an electronic device (e.g., a terminal device or server) 800 suitable for implementing embodiments of the present disclosure. The terminal device in the embodiments of the present disclosure may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. The electronic device shown in the figure is merely an example and should not be construed as limiting the functionality and scope of the embodiments of the present disclosure.

[0154] Electronic device 800 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 801, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 802 or a program loaded from storage device 808 into random access memory (RAM) 803. RAM 803 also stores various programs and data required for the operation of electronic device 800. The processing device 801, ROM 802, and RAM 803 are interconnected via bus 804. Input / output (I / O) interface 805 is also connected to bus 804.

[0155] Typically, the following devices can be connected to I / O interface 805: input devices 806 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 807 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 808 including, for example, magnetic tapes, hard disks, etc.; and communication devices 809. Communication device 809 allows electronic device 800 to communicate wirelessly or wiredly with other devices to exchange data. Although an electronic device 800 with various devices is shown in the figure, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively.

[0156] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 809, or installed from a storage device 808, or installed from a ROM 802. When the computer program is executed by a processing device 801, it performs the functions defined in the methods of embodiments of this disclosure.

[0157] It should be noted that the computer-readable medium described in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0158] In some implementations, clients and servers can communicate using any currently known or future-developed network protocol such as HTTP (Hypertext Transfer Protocol) and can interconnect with digital data communication (e.g., communication networks) of any form or medium. Examples of communication networks include local area networks (“LANs”), wide area networks (“WANs”), the Internet (e.g., the Internet of Things), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future-developed networks.

[0159] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device.

[0160] The aforementioned computer-readable medium carries one or more programs, which, when executed by the electronic device, cause the electronic device to perform the methods of the present disclosure.

[0161] Computer program code for performing the operations of this disclosure can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0162] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0163] The units described in the embodiments of this disclosure can be implemented in software or hardware. The names of the units are not, in some cases, intended to limit the specific unit.

[0164] The functions described above in this document can be performed at least in part by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SoCs), complex programmable logic devices (CPLDs), and so on.

[0165] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0166] According to one or more embodiments of this disclosure, a method for controlling a processing device is provided. The processing device includes a first processor and a second processor communicatively connected to each other. The second processor is communicatively connected to a display component. The second processor is used to receive a display image and send it to the display component for display. The control method includes:

[0167] In response to the target information, the second processor stops receiving the display image;

[0168] The first processor reads a first preset image that is stored outside the second processor, and sends the first preset image to the display component for display without going through the processing unit of the second processor;

[0169] The second processor is reset;

[0170] The first processor stops sending the first preset image, and the second processor resumes receiving the display image and sends it to the display component for display.

[0171] According to one or more embodiments of this disclosure, a processing device control method is provided, wherein a second processor is communicatively connected to a first processor via a first communication interface, and the second processor is communicatively connected to a display component via a second communication interface, wherein a direct link exists between the first communication interface and the second communication interface;

[0172] Sending the first preset image to the display component for display without going through the processing unit of the second processor includes: the first processor sending the first preset image to the first communication interface, so that the first preset image is sent to the display component for display via the first communication interface, the direct link and the second communication interface.

[0173] According to one or more embodiments of this disclosure, a processing device control method is provided. In response to target information, after the second processor stops receiving the display image, and before the first processor sends the first preset image to the first communication interface, the method further includes: the first processor sending a first notification to the second processor through a third communication interface to inform the second processor to enable the pass-through link.

[0174] According to one or more embodiments of this disclosure, a processing device control method is provided. In response to target information, after the second processor stops receiving display images, before sending the first preset image to the display component for display without passing through the processing unit of the second processor, the method further includes: the second processor reading a pre-stored second preset image and sending the second preset image to the display component for display, until the first preset image is sent to the display component for display.

[0175] According to one or more embodiments of the present disclosure, a processing device control method is provided, wherein the second preset image is stored in the memory processing unit of the second processor.

[0176] According to one or more embodiments of this disclosure, a processing device control method is provided, wherein in response to target information, a second processor stops receiving a display image, comprising:

[0177] In response to the second processor detecting abnormal information or detecting information indicating a reset of the second processor, the second processor sends a second notification to the first processor and stops receiving displayed images; or,

[0178] In response to the first processor detecting abnormal information or detecting information to reset the second processor, the first processor sends a third notification to the second processor to cause the second processor to stop receiving external display images.

[0179] According to one or more embodiments of this disclosure, a processing device control method is provided, wherein the second processor detects the abnormal information in the following manner:

[0180] The second processor obtains the time interval between the current time and the last time an image was received for display;

[0181] If the time interval reaches a preset time threshold, then an abnormality is determined to have occurred.

[0182] According to one or more embodiments of this disclosure, a processing device control method is provided, wherein when the second processor is reset, the display processing unit in the second processor, the first communication interface between the second processor and the first processor, the second communication interface between the second processor and the display component, and the display component remain powered on.

[0183] According to one or more embodiments of this disclosure, a processing device control method is provided, the processing device including a first processor and a second processor communicatively connected to each other, the second processor being communicatively connected to a display component, the control method including:

[0184] In response to power-on, the first processor initializes;

[0185] The first processor sends first information to the display component without going through the processing unit of the second processor, in order to initialize the display component;

[0186] The first processor reads the boot image;

[0187] Before the kernel system of the first processor starts up and before the display processing unit of the second processor is initialized, the first processor sends the boot image to the display component for display without going through the processing unit of the second processor.

[0188] According to one or more embodiments of this disclosure, a processing device control method is provided, wherein a second processor is communicatively connected to a first processor via a first communication interface, and the second processor is communicatively connected to a display component via a second communication interface, wherein a direct link exists between the first communication interface and the second communication interface;

[0189] The first processor sends first information to the display component to initialize the display component without going through the processing unit of the second processor, including: the first processor sending the first information to the display component through the first communication interface, the pass-through link, and the second communication interface; and / or,

[0190] The first processor sends the boot image to the display component for display without going through the processing unit of the second processor, including: the first processor sends the boot image to the first communication interface, so that the boot image is sent to the display component for display via the first communication interface, the pass-through link and the second communication interface.

[0191] According to one or more embodiments of this disclosure, a processing device control method is provided. In response to power-on, after the first processor initializes, and before the first processor initializes the display component without going through the processing unit of the second processor, the method further includes: the first processor sending second information to the second processor through a third communication interface to inform the second processor to enable the pass-through link.

[0192] According to one or more embodiments of this disclosure, a processing device control method is provided, wherein in response to power-on, the first processor is initialized, including: in response to power-on, the central processing unit, storage processing unit and memory processing unit of the first processor are initialized;

[0193] After the first processor sends first information to the display component to initialize the display component without going through the processing unit of the second processor, before the first processor reads the boot image, the method further includes: the first processor's central processing unit reads the image data of the first processor's display processing unit from the first processor's storage processing unit, loads the image data, and the first processor's display processing unit is powered on and initialized.

[0194] According to one or more embodiments of this disclosure, a processing device control method is provided, which further includes, after the first processor sends the boot image to the display component for display without passing through the processing unit of the second processor:

[0195] The central processing unit and memory processing unit of the second processor are initialized;

[0196] The kernel system of the first processor starts.

[0197] According to one or more embodiments of this disclosure, a processing device control apparatus is provided. The processing device includes a first processor and a second processor that are communicatively connected to each other. The second processor is communicatively connected to a display component. The second processor is used to receive display images and send them to the display component for display. The control apparatus includes a first control module and a second control module.

[0198] The second control module is used to control the second processor to stop receiving and displaying images in response to target information;

[0199] The first control module is used to control the first processor to read a first preset image that is pre-stored outside the second processor, and to send the first preset image to the display component for display without going through the processing unit of the second processor;

[0200] The second control module is also used to control the second processor to reset;

[0201] The first control module is further configured to control the first processor to stop sending the first preset image;

[0202] The second control module is also used to control the second processor to resume receiving and displaying images and send them to the display component for display.

[0203] According to one or more embodiments of the present disclosure, a processing device control apparatus is provided, the processing device including a first processor and a second processor communicatively connected to each other, the second processor being communicatively connected to a display component, the control apparatus including:

[0204] The first control module is used to control the first processor to initialize in response to power-on;

[0205] The first control module is further configured to control the first processor to send first information to the display component without going through the processing unit of the second processor, so as to initialize the display component;

[0206] The first control module is also used to control the first processor to read the boot image;

[0207] The first control module is further configured to control the first processor to send the boot image to the display component for display without passing through the processing unit of the second processor before the kernel system of the first processor starts and before the display processing unit of the second processor is initialized.

[0208] According to one or more embodiments of the present disclosure, an electronic device is provided, including: at least one memory and at least one processor;

[0209] The at least one memory is used to store program code, and the at least one processor is used to call the program code stored in the at least one memory to execute the method described in any one of the above.

[0210] According to one or more embodiments of the present disclosure, a computer-readable storage medium is provided for storing program code that, when executed by a processor, causes the processor to perform the methods described above.

[0211] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0212] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0213] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

Claims

1. A method for controlling a processing device, characterized in that, The processing device includes a first processor and a second processor that are communicatively connected to each other. The second processor is communicatively connected to a display component and is used to receive display images and send them to the display component for display. The control method includes: In response to the target information, the second processor stops receiving the display image; The first processor reads a first preset image that is stored outside the second processor, and sends the first preset image to the display component for display without going through the processing unit of the second processor; The second processor is reset; The first processor stops sending the first preset image, and the second processor resumes receiving the display image and sends it to the display component for display.

2. The method according to claim 1, characterized in that, The second processor is connected to the first processor via a first communication interface, and the second processor is connected to the display component via a second communication interface. There is a direct link between the first communication interface and the second communication interface. Sending the first preset image to the display component for display without going through the processing unit of the second processor includes: the first processor sending the first preset image to the first communication interface, so that the first preset image is sent to the display component for display via the first communication interface, the direct link and the second communication interface.

3. The method according to claim 2, characterized in that, In response to the target information, after the second processor stops receiving the display image, before the first processor sends the first preset image to the first communication interface, the method further includes: the first processor sending a first notification to the second processor through a third communication interface to inform the second processor to enable the pass-through link.

4. The method according to claim 1, characterized in that, In response to the target information, after the second processor stops receiving the display image, before sending the first preset image to the display component for display without going through the processing unit of the second processor, the method further includes: the second processor reading the pre-stored second preset image and sending the second preset image to the display component for display, until the first preset image is sent to the display component for display.

5. The method according to claim 4, characterized in that, The second preset image is stored in the memory processing unit of the second processor.

6. The method according to claim 1, characterized in that, In response to the target information, the second processor stops receiving the display image, including: In response to the second processor detecting abnormal information or detecting information indicating a reset of the second processor, the second processor sends a second notification to the first processor and stops receiving displayed images; or, In response to the first processor detecting abnormal information or detecting information to reset the second processor, the first processor sends a third notification to the second processor to cause the second processor to stop receiving external display images.

7. The method according to claim 6, characterized in that, The second processor detects the abnormal information in the following manner: The second processor obtains the time interval between the current time and the last time an image was received for display; If the time interval reaches a preset time threshold, then an abnormality is determined to have occurred.

8. The method according to claim 1, characterized in that, When the second processor is reset, the display processing unit in the second processor, the first communication interface between the second processor and the first processor, the second communication interface between the second processor and the display component, and the display component remain powered on.

9. A method for controlling a processing device, characterized in that, The processing device includes a first processor and a second processor that are communicatively connected to each other, the second processor being communicatively connected to a display component, and the control method includes: In response to power-on, the first processor initializes; The first processor sends first information to the display component without going through the processing unit of the second processor, in order to initialize the display component; The first processor reads the boot image; Before the kernel system of the first processor starts up and before the display processing unit of the second processor is initialized, the first processor sends the boot image to the display component for display without going through the processing unit of the second processor.

10. The method according to claim 9, characterized in that, The second processor is connected to the first processor via a first communication interface, and the second processor is connected to the display component via a second communication interface. There is a direct link between the first communication interface and the second communication interface. The first processor sends first information to the display component without going through the processing unit of the second processor to initialize the display component, including: the first processor sending the first information to the display component through the first communication interface, the pass-through link and the second communication interface; And / or, The first processor sends the boot image to the display component for display without going through the processing unit of the second processor, including: the first processor sends the boot image to the first communication interface, so that the boot image is sent to the display component for display via the first communication interface, the pass-through link and the second communication interface.

11. The method according to claim 10, characterized in that, In response to power-on, after the first processor initializes, before the first processor initializes the display component without going through the processing unit of the second processor, the method further includes: the first processor sending second information to the second processor through a third communication interface to inform the second processor to enable the pass-through link.

12. The method according to claim 9, characterized in that, In response to power-on, the first processor initializes itself, including initializing its central processing unit, storage processing unit, and memory processing unit in response to power-on. After the first processor sends first information to the display component to initialize the display component without going through the processing unit of the second processor, before the first processor reads the boot image, the method further includes: the first processor's central processing unit reads the image data of the first processor's display processing unit from the first processor's storage processing unit, loads the image data, and the first processor's display processing unit is powered on and initialized.

13. The method according to claim 9, characterized in that, After the first processor sends the boot image to the display unit for display without going through the processing unit of the second processor, it further includes: The central processing unit and memory processing unit of the second processor are initialized; The kernel system of the first processor starts.

14. A control device for a processing equipment, characterized in that, The processing device includes a first processor and a second processor that are communicatively connected to each other. The second processor is communicatively connected to the display component and is used to receive display images and send them to the display component for display. The control device includes a first control module and a second control module. The second control module is used to control the second processor to stop receiving and displaying images in response to target information; The first control module is used to control the first processor to read a first preset image that is pre-stored outside the second processor, and to send the first preset image to the display component for display without going through the processing unit of the second processor; The second control module is also used to control the second processor to reset; The first control module is further configured to control the first processor to stop sending the first preset image; The second control module is also used to control the second processor to resume receiving and displaying images and send them to the display component for display.

15. A control device for a processing equipment, characterized in that, The processing device includes a first processor and a second processor that are communicatively connected to each other, the second processor being communicatively connected to a display component, and the control device includes: The first control module is used to control the first processor to initialize in response to power-on; The first control module is further configured to control the first processor to send first information to the display component without going through the processing unit of the second processor, so as to initialize the display component; The first control module is also used to control the first processor to read the boot image; The first control module is further configured to control the first processor to send the boot image to the display component for display without passing through the processing unit of the second processor before the kernel system of the first processor starts and before the display processing unit of the second processor is initialized.

16. An electronic device comprising: At least one memory and at least one processor; The at least one memory is used to store program code, and the at least one processor is used to call the program code stored in the at least one memory to execute the method of any one of claims 1 to 13.

17. A computer-readable storage medium for storing program code that, when executed by a processor, causes the processor to perform the method of any one of claims 1 to 13.

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