A scanning driving circuit, a scanning signal output method and a display panel

Abstract

The application discloses a scanning driving circuit, a scanning signal output method and a display panel. The scanning driving circuit comprises an input module, a level transmission module and an output module. The input module is used for generating a first control signal at a first node. The level transmission module is used for generating a second control signal at a third node. The output module comprises a first control end and a second control end. The first control end and the second control end are respectively used for electrically connecting the input module and the level transmission module, so as to generate corresponding scanning output signals in response to the first control signal and the second control signal. A first isolation module is arranged between the second control end of the output module and the third node. The application provides a novel scanning driving circuit. The first isolation module is arranged between the second control end of the output module and the third node, so as to reduce the cross voltage between the level transmission module and the output module as much as possible, thereby stably outputting the scanning output signal and effectively improving the reliability of the circuit.

Description

Technical Field

[0001] This application relates to the field of display panel technology, and in particular to a scanning drive circuit, a scanning signal output method, and a display panel. Background Technology

[0002] Gate Driver on Array (GOA) technology integrates the gate driving circuit, also known as the scan driving circuit, onto the array substrate of the display panel to generate scan signals that are input to the pixel units, thereby enabling the pixel units to be scanned line by line.

[0003] However, existing scan drive circuits have poor reliability. Summary of the Invention

[0004] The main technical problem solved by this application is to provide a scanning drive circuit, a scanning signal output method, and a display panel, which can solve the problems of poor reliability under long-term use and large signal glitches in the output signal of the existing scanning drive circuit.

[0005] To solve the above-mentioned technical problems, one technical solution adopted in this application is: to provide a scan driving circuit, wherein the scan driving circuit includes: an input module for generating a first control signal at a first node; a level transmission module for generating a second control signal at a third node; an output module including a first control terminal and a second control terminal, wherein the first control terminal and the second control terminal are respectively used to electrically connect the input module and the level transmission module to generate corresponding scan output signals in response to the first control signal and the second control signal; and a first isolation module located between the second control terminal of the output module and the third node.

[0006] The input module samples the scan input signal in response to at least the third clock signal to generate a first control signal at the first node; the level transmission module samples the first level signal in response to the first clock signal and the second clock signal to generate a second control signal at the third node; wherein the first clock signal, the second clock signal and the third clock signal have the same period, the phase difference between the second clock signal and the first clock signal is half a cycle, and the rising edge of the third clock signal is not earlier than the falling edge of the second clock signal.

[0007] The system further includes an inverting module, which samples a second-level signal in response to a first control signal and a second clock signal on the first node, and transmits the signal to the third node.

[0008] The inverting module includes: an inverting unit connected to a first node, which samples a second-level signal in response to a first control signal on the first node; and a phase delay unit connected to the inverting unit and a third node, which delays the second-level signal output by the inverting unit in response to a second clock signal and transmits it to the third node. Preferably, the inverting unit includes a sixth transistor, and the phase delay unit includes a fifteenth transistor. The first terminal of the sixth transistor is connected to the terminal providing the second-level signal, the control terminal of the sixth transistor is connected to the first node, the second terminal of the sixth transistor is connected to the first terminal of the fifteenth transistor, the control terminal of the fifteenth transistor is connected to the terminal providing the second clock signal, and the second terminal of the fifteenth transistor is connected to the third node.

[0009] The output module includes: a first output unit, the control terminal of which serves as the first control terminal of the output module; a first terminal of which receives a first level signal; a second terminal of which is connected to the output terminal of the output module; and the first output unit transmitting the first level signal as a scan output signal to the output terminal of the output module in response to a first control signal; a second output unit, the control terminal of which serves as the second control terminal of the output module; a first terminal of which receives a third clock signal; a second terminal of which is connected to the output terminal of the output module in response to a second control signal; and a coupling unit, the first terminal of which is connected to the control terminal of the second output unit; and the second terminal of which is connected to the second terminal of the second output unit. Preferably, the first output unit includes a tenth transistor, the second output unit includes a ninth transistor, the coupling unit includes a third capacitor, the first terminal of the tenth transistor is connected to the terminal providing the first level signal, the control terminal of the tenth transistor is connected to the first control terminal, the second terminal of the tenth transistor is connected to the output terminal of the output module, the first terminal of the ninth transistor is connected to the terminal providing the third clock signal, the control terminal of the ninth transistor is connected to the first terminal and the second control terminal of the third capacitor, and the second terminal of the ninth transistor is connected to the second terminal of the third capacitor and the output terminal of the output module.

[0010] This further includes: a second isolation module, which is disposed between the first control terminal and the first node of the output module.

[0011] The input module includes: a first input unit that samples the scan input signal in response to a third clock signal; preferably, the input module further includes a second input unit connected in series between the first input unit and the first node, the second input unit transmitting the scan input signal output by the first input unit as a first control signal to the first node in response to the first clock signal; preferably, the first input unit includes a fourteenth transistor, the first terminal of the fourteenth transistor being connected to the providing terminal of the scan input signal, the control terminal of the fourteenth transistor being connected to the providing terminal of the third clock signal, and the second terminal of the fourteenth transistor being connected to the first node; preferably, the second input unit includes a first transistor, the first terminal of the first transistor being connected to the second terminal of the fourteenth transistor, and the control terminal of the first transistor being connected to the providing terminal of the first clock signal. The second terminal of the first transistor is connected to the first node; or, the input module includes: a first input unit and a second input unit, the second input unit being connected in series between the first input unit and the first node, the first input unit sampling the scan input signal in response to a first clock signal, and the second input unit transmitting the scan input signal output by the first input unit as a first control signal to the first node in response to a third clock signal; preferably, the first input unit includes a fourteenth transistor, the second input unit includes a first transistor, the first terminal of the fourteenth transistor is connected to the terminal providing the scan input signal, the control terminal of the fourteenth transistor is connected to the terminal providing the first clock signal, the second terminal of the fourteenth transistor is connected to the first terminal of the first transistor, the control terminal of the first transistor is connected to the terminal providing the third clock signal, and the second terminal of the first transistor is connected to the first node.

[0012] It further includes: a first control module, which samples the first clock signal in response to the potential of the first node and transmits it to the level transmission module.

[0013] The system further includes a second control module, which is connected to the first control terminal and the output terminal of the first control module. The second control module samples the second clock signal and the second level signal in response to the potential of the output terminal of the first control module and the potential of the first node, and transmits them to the first control terminal.

[0014] The scan input signal is either the scan output signal from the previous scan drive circuit or the scan start signal from the scan drive circuit.

[0015] To solve the above-mentioned technical problems, another technical solution adopted in this application is: providing a scanning signal output method, applied in the scanning drive circuit as described above, wherein the scanning signal output method includes: in a first stage, a scanning input signal is provided at a first level, and a second clock signal and a third clock signal are at a first level, so as to generate a first control signal at a first node, and an output module generates a first scanning output signal in response to the first control signal; in a second stage, the scanning input signal is provided at a second level, the first clock signal and the third clock signal are provided at a first level, and the output module continuously generates the first scanning output signal; in a third stage, the second clock signal is provided at a first level, so as to generate a second control signal at a third node, and the output module generates a second scanning output signal in response to the second control signal; in a fourth stage, the scanning input signal is provided at a first level, the second clock signal is provided at a second level, the first clock signal and the third clock signal are provided at a first level, so as to generate a first control signal at a first node, and the output module generates the first scanning output signal in response to the first control signal; in a fifth stage, the second clock signal is provided at a first level, and the output module continuously generates the first scanning output signal.

[0016] To solve the above-mentioned technical problems, another technical solution adopted in this application is: to provide a display panel, wherein the display panel includes a scan driving circuit and a pixel unit coupled together; wherein the scan driving circuit is the scan driving circuit as described in any of the above claims.

[0017] The beneficial effects of this application are as follows: Unlike the prior art, the input module of the scan driving circuit provided in this application is used to generate a first control signal at a first node, the level transmission module is used to generate a second control signal at a third node, and the output module includes a first control terminal and a second control terminal. The first control terminal and the second control terminal are respectively used to electrically connect the input module and the level transmission module so that they can generate corresponding scan output signals in response to the first control signal and the second control signal, respectively. Furthermore, a first isolation module is provided between the second control terminal of the output module and the third node to minimize the voltage difference between the level transmission module and the output module, thereby stabilizing the output scan signal and effectively improving the reliability of the scan driving circuit. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0019] Figure 1This is a schematic diagram of the structure of the first embodiment of the scanning drive circuit of this application;

[0020] Figure 2 This is a schematic diagram of the second embodiment of the scanning drive circuit of this application;

[0021] Figure 3 This is a schematic diagram of the third embodiment of the scanning drive circuit of this application;

[0022] Figure 4 This is a schematic diagram of the fourth embodiment of the scanning drive circuit of this application;

[0023] Figure 5 This is a schematic diagram of the fifth embodiment of the scanning drive circuit of this application;

[0024] Figure 6 This is a schematic diagram of the sixth embodiment of the scanning drive circuit of this application;

[0025] Figure 7 This is a schematic diagram of the seventh embodiment of the scanning drive circuit of this application;

[0026] Figure 8 This is a schematic diagram of the eighth embodiment of the scanning drive circuit of this application;

[0027] Figure 9 This is a schematic diagram of the ninth embodiment of the scanning drive circuit of this application;

[0028] Figure 10 This is a schematic diagram of the tenth embodiment of the scanning drive circuit of this application;

[0029] Figure 11 This is a schematic diagram of the eleventh embodiment of the scanning drive circuit of this application;

[0030] Figure 12 yes Figure 11 A schematic diagram of a specific embodiment of the mid-scan driving circuit;

[0031] Figure 13 yes Figure 12 A timing diagram of each input signal corresponding to the scan drive circuit in one embodiment;

[0032] Figure 14 yes Figure 12 A schematic diagram of a structure obtained by cascading the scanning drive circuits in one embodiment;

[0033] Figure 15 yes Figure 11 A schematic diagram of another specific embodiment of the scanning drive circuit;

[0034] Figure 16 yes Figure 11A schematic diagram of another specific embodiment of the scanning drive circuit;

[0035] Figure 17 This is a flowchart illustrating one embodiment of the scanning signal output method of this application;

[0036] Figure 18 This is a schematic diagram of the structure of one embodiment of the display panel of this application. Detailed Implementation

[0037] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0038] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0039] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0040] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0041] Please see Figure 1 , Figure 1This is a schematic diagram of the structure of the first embodiment of the scan driving circuit of this application. In this embodiment, the scan driving circuit 10 includes: an input module 11, a level transmission module 12, an output module 13, and a first isolation module 14.

[0042] It should be noted that, in the field of display technology, a display panel typically includes a display area and a non-display area surrounding the display area. The display area also includes a plurality of scan lines S1, S2…Sn (n being an integer greater than 1) and data lines D1, D2…Dm (m being an integer greater than 1) intersecting the scan lines, used to define multiple pixel units. The non-display area includes a scan drive circuit 10, a data drive circuit, an enable signal control circuit, and a timing control circuit. Specifically, the scan drive circuit 10 is connected to the scan lines to generate scan output signals that are input to the pixel units to control the writing of data signals. The data drive circuit is connected to the data lines to provide data signals to the pixel units, driving them to display corresponding images. The enable signal control circuit is connected to the transmit control lines EM1, EM2…EMn to provide enable signals to the pixel units. The timing control circuit provides clock signals to the pixel units. Furthermore, the scan drive circuit 10 includes multiple levels of circuits connected to the pixel row via multiple scan lines, i.e., a multi-level scan circuit; each scan circuit provides a scan signal to its corresponding scan line.

[0043] Specifically, the input module 11 is used to generate a first control signal at the first node, while the level transmission module 12 is used to generate a second control signal at the third node.

[0044] Specifically, the first node and the third node refer to two specific connection endpoints in the scanning drive circuit 10 that can generate the first control signal and the second control signal respectively.

[0045] Furthermore, the output module 13 includes a first control terminal 131 and a second control terminal 132. The first control terminal 131 is electrically connected to the input module 11 to receive a first control signal sent by the input module 11. The second control terminal 132 is electrically connected to the level transmission module 12 to receive a second control signal sent by the level transmission module 12. This causes the output module 13 to be triggered in response to the level states of the first and second control signals to generate a corresponding scan output signal.

[0046] Furthermore, the first isolation module 14 is correspondingly disposed between the second control terminal 132 of the output module 13 and the third node, so that the level transmission module 12 specifically sends the second control signal generated by the third node to the output module 13 via the first isolation module 14, thereby avoiding the large voltage drop caused by the change in the conduction state of the output module 13, which could cause impact damage to the level transmission module 12 and, in turn, affect the stable output of the scan output signal.

[0047] It is worth noting that the term "coupled" in this document includes any direct and indirect means of connection. Therefore, if the document describes a first element coupled to a second element, it means that the first element can be directly connected to the second element through electrical connections, communication connections, or signal connections such as wireless transmission or optical transmission, or indirectly connected to the second element electrically or through other elements or connection means.

[0048] The above solution provides a novel scanning drive circuit 10. By setting a first isolation module 14 between the second control terminal 132 of the output module 13 and the third node, the voltage across the level transmission module 12 and the output module 13 is reduced as much as possible, thereby stabilizing the output scanning signal and effectively improving the reliability of the circuit.

[0049] In one embodiment, the input module 11 is specifically used to receive a third clock signal provided by an external timing control circuit, as well as an externally input start signal or an output signal of the upper-level scan drive circuit 10, as a scan input signal, and to trigger an action in response to the level state of the third clock signal to sample the scan input signal, thereby generating a first control signal at the first node in the scan drive circuit 10.

[0050] The level transmission module 12 is used to receive the first clock signal and the second clock signal provided by the timing control circuit, and to trigger an action in response to the level state of the first clock signal and the second clock signal, so as to sample the first level signal and generate a second control signal at the third node in the scan drive circuit 10.

[0051] Understandably, the input module 11 is specifically coupled to a specific node of the timing control circuit, as well as the start signal providing terminal of the system processing circuit or the output terminal of the upper-level scan driving circuit 10, to receive the third clock signal sent by the timing control circuit and the scan input signal sent by the system processing circuit or the upper-level scan driving circuit 10; similarly, the level transmission module 12 is specifically coupled to two other specific nodes of the timing control circuit to receive the first clock signal and the second clock signal sent by the timing control circuit.

[0052] The first, second, and third clock signals have the same period, the phase difference between the second and first clock signals is half a cycle, and the rising edge of the third clock signal is no earlier than the falling edge of the second clock signal.

[0053] Optionally, the first clock signal, the second clock signal, and the third clock signal are square wave periodic signals, and in one cycle, the pulse width at the high level is twice the pulse width at the low level.

[0054] It is worth noting that the input module 11 and the level transmission module 12 specifically use the first clock signal, the second clock signal, the third clock signal and the first level signal to trigger actions, so as to generate a first control signal at the first node and a second control signal at the third node, and then use the first control signal and the second control signal to trigger the output module 13 to be turned on or off, so as to output a scan output signal with a high level or a low level, and send the scan output signal to the corresponding scan line to output to the corresponding pixel unit.

[0055] Please see Figure 2 , Figure 2 This is a schematic diagram of the second embodiment of the scan driving circuit of this application. This embodiment is based on the first embodiment of the scan driving circuit provided in this application, and the scan driving circuit 20 specifically includes an inverting module 25.

[0056] Specifically, the inverting module 25 is used to receive a first control signal sent by the first node and a second clock signal sent by the timing control circuit, to sample the second level signal in response to the first control signal and the second clock signal on the first node, and to transmit the second level signal to the third node.

[0057] Understandably, the first level signal can be a low level signal and the second level signal can be a high level signal; or, the first level signal can be a high level signal and the second level signal can be a low level signal. The inverting module 25 specifically uses a low-level first control signal and a low-level second clock signal to transmit the high-level second level signal to the third node; or, uses a high-level first control signal and a high-level second clock signal to transmit the low-level second level signal to the third node.

[0058] It is understood that in this embodiment, the input module 21, level transmission module 22, output module 23, first control terminal 231, second control terminal 232, and first isolation module 24 are the same as the input module 11, level transmission module 12, output module 13, first control terminal 131, second control terminal 132, and first isolation module 14, respectively. Please refer to [link / reference] for details. Figure 1 The relevant textual content will not be repeated here.

[0059] Please see Figure 3 , Figure 3 This is a schematic diagram of the third embodiment of the scan driving circuit of this application. This embodiment is based on the second embodiment of the scan driving circuit provided in this application, and the inverting module 35 in the scan driving circuit 30 further includes an inverting unit 351 and a phase delay unit 352.

[0060] Specifically, the inverting unit 351 is connected to the first node, and the phase delay unit 352 is connected to the inverting unit 351 and the third node. The inverting unit 351 is used to receive a first control signal sent by the first node, to sample a second level signal in response to the first control signal on the first node, and to transmit the second level signal to the phase delay unit 352. The phase delay unit 352 is also used to receive a second clock signal sent by the timing control circuit, to trigger an action in response to the level state of the second clock signal, to delay the second level signal in phase and transmit it to the third node.

[0061] Understandably, since the rising edge of the third clock signal is no earlier than the falling edge of the second clock signal, when the third clock signal is used to generate the first control signal at the first node, and then the first control signal is used to sample the second level signal, the phase delay unit 352 specifically responds to the second clock signal trigger action whose falling edge is no later than the rising edge of the third clock signal, so that after phase delay, the second level signal output by the inverting unit 351 is transmitted to the third node, thereby effectively reducing the signal glitches of the scan output signal corresponding to the output module 33.

[0062] Preferably, the inverting unit 351 specifically includes a sixth transistor, and the phase delay unit includes a fifteenth transistor. The first terminal of the sixth transistor is connected to the providing terminal of the second level signal, the control terminal of the sixth transistor is connected to the first node, the second terminal of the sixth transistor is connected to the first terminal of the fifteenth transistor, the control terminal of the fifteenth transistor is connected to the providing terminal of the second clock signal, and the second terminal of the fifteenth transistor is connected to the third node.

[0063] Understandably, the control terminal of the sixth transistor can be triggered by the first control signal on the first node to conduct the first and second terminals of the sixth transistor, so as to transmit the second level signal to the first terminal of the fifteenth transistor; and the control terminal of the fifteenth transistor can be triggered by the second clock signal to conduct the first and second terminals of the fifteenth transistor, thereby transmitting the second level signal to the third node; and by adjusting the level states of the first control signal and the second clock signal, the timing of the triggering actions of the sixth and fifteenth transistors can be adjusted, thereby effectively achieving the phase delay of the second level signal, which can also effectively reduce the signal glitches of the scan output signal corresponding to the output of the output module 33.

[0064] Optionally, each of the above transistors can be a P-type thin-film transistor, an N-type thin-film transistor, or a field-effect transistor, and the control terminal of each transistor can be the gate, while the first terminal of the transistor is the drain and the second terminal is the source; or, the control terminal of each transistor is the gate, while the first terminal of the transistor is the source and the second terminal is the drain; the same applies below, and will not be elaborated further.

[0065] Optionally, the aforementioned transistors may also be composite transistors or single transistors, and this application does not limit this.

[0066] In other embodiments, the transistor can be replaced with a bipolar junction transistor (BJT), with the control terminal of each BJT being the base, the first terminal being the collector, and the second terminal being the emitter; or, the control terminal of each BJT being the base, the first terminal being the emitter, and the second terminal being the collector. This application does not limit this to any particular embodiment.

[0067] It is understood that in this embodiment, the input module 31, level transmission module 32, output module 33, first control terminal 331, second control terminal 332, and first isolation module 34 are the same as the input module 21, level transmission module 22, output module 23, first control terminal 231, second control terminal 232, and first isolation module 24, respectively. Please refer to [link to documentation] for details. Figure 2 The relevant textual content will not be repeated here.

[0068] Please see Figure 4 , Figure 4 This is a schematic diagram of the fourth embodiment of the scan driving circuit of this application. This embodiment is based on the first embodiment of the scan driving circuit provided in this application, and the output module 43 in the scan driving circuit 40 further includes a first output unit 433 and a second output unit 434.

[0069] Specifically, the control terminal of the first output unit 433 serves as the first control terminal of the output module 43, and the control terminal of the second output unit 434 serves as the second control terminal of the output module 43. The first terminal of the first output unit 433 receives a first level signal, the second terminal of the first output unit 433 is connected to the output terminal of the output module 43, and the first terminal of the second output unit 434 receives a third clock signal. The second terminal of the second output unit 434 is connected to the output terminal of the output module 43.

[0070] The first output unit 433 is triggered by a first control signal to transmit a first level signal as a scan output signal to the output terminal of the output module 43, while the second output unit 434 is triggered by a second control signal to transmit a third clock signal as a scan output signal to the output terminal of the output module 43. This allows for the replication of a portion of the third clock signal, which is then output to the lower-level scan drive circuit 40 and the scan line to serve as the scan input signal for the lower-level scan drive circuit 40 and the drive signal for the pixel unit.

[0071] Furthermore, the output module 43 also includes a coupling unit 46. The first end of the coupling unit 46 is specifically connected to the control terminal of the second output unit 434, and the second end of the coupling unit 435 is connected to the second end of the second output unit 434, so as to effectively reduce the coupling effect of the output module 43, reduce the fluctuation of the scan output signal, and ensure the stable output of the scan output signal.

[0072] Preferably, the first output unit 433 includes a tenth transistor, the second output unit 434 includes a ninth transistor, the coupling unit 435 includes a third capacitor, and the first terminal of the tenth transistor is connected to the terminal providing the first level signal, the control terminal of the tenth transistor is connected to the first control terminal, the second terminal of the tenth transistor is connected to the output terminal of the output module 43, the first terminal of the ninth transistor is connected to the terminal providing the third clock signal, the control terminal of the ninth transistor is connected to the first terminal and the second control terminal of the third capacitor, and the second terminal of the ninth transistor is connected to the second terminal of the third capacitor and the output terminal of the output module 43.

[0073] Understandably, the control terminal of the tenth transistor can be triggered by a first control signal on the first control terminal to turn on the first and second terminals of the tenth transistor, so as to transmit the first level signal to the output terminal of the output module 43; while the control terminal of the ninth transistor can be triggered by a second control signal on the second control terminal to turn on the first and second terminals of the ninth transistor, so as to transmit the third clock signal to the output terminal of the output module 43, and to copy a portion of the third clock signal; the third capacitor is used to regulate the voltage at the output terminal of the output module 43.

[0074] It is understood that in this embodiment, the input module 41, the level transmission module 42, and the first isolation module 44 are the same as the input module 11, the level transmission module 12, and the first isolation module 14, respectively. Please refer to [link / reference] for details. Figure 1 The relevant textual content will not be repeated here.

[0075] Please see Figure 5 , Figure 5 This is a schematic diagram of the fifth embodiment of the scan driving circuit of this application. This embodiment is based on the first embodiment of the scan driving circuit provided in this application, and the scan driving circuit 50 specifically includes a second isolation module 56.

[0076] Specifically, the second isolation module 56 is specifically disposed between the first control terminal and the first node of the output module 53 to isolate the large voltage drop caused by the change in the conduction state of the output module 53, i.e., the extremely low level, so as to avoid impact damage to the input module 51 and, in turn, affect the stable output of the scan output signal.

[0077] It is understood that in this embodiment, the input module 51, level transmission module 52, output module 53, first control terminal 531, second control terminal 532, and first isolation module 54 are the same as the input module 11, level transmission module 12, output module 13, first control terminal 131, second control terminal 132, and first isolation module 14, respectively. Please refer to [link / reference] for details. Figure 1 The relevant textual content will not be repeated here.

[0078] Please see Figure 6 , Figure 6 This is a schematic diagram of the sixth embodiment of the scan driving circuit of this application. This embodiment is based on the first embodiment of the scan driving circuit provided in this application, and the input module 61 in the scan driving circuit 60 further includes a first input unit 611.

[0079] Specifically, the input module 61 uses the first input unit 611 to receive the third clock signal provided by the timing control circuit, as well as the start signal from the external input or the output signal from the upper-level scan drive circuit 60, in order to sample the scan input signal in response to the third clock signal.

[0080] It is understood that in this embodiment, the input module 61, level transmission module 62, output module 63, first control terminal 631, second control terminal 632, and first isolation module 64 are the same as the input module 11, level transmission module 12, output module 13, first control terminal 131, second control terminal 132, and first isolation module 14, respectively. Please refer to [link / reference] for details. Figure 1 The relevant textual content will not be repeated here.

[0081] Please see Figure 7 , Figure 7 This is a schematic diagram of the seventh embodiment of the scan driving circuit of this application. This embodiment is based on the sixth embodiment of the scan driving circuit provided in this application, and the input module 71 in the scan driving circuit 70 specifically includes a second input unit 712.

[0082] Specifically, the second input unit 712 is connected in series between the first input unit 711 and the first node. The first input unit 711 samples the scan input signal in response to the third clock signal, and the second input unit 712 receives the first clock signal provided by the timing control circuit. The second input unit 712 triggers the action in response to the level state of the first clock signal, and transmits the scan input signal output by the first input unit 711 as the first control signal to the first node, thereby enabling more stable transmission of the first control signal.

[0083] Preferably, the first input unit 711 includes a fourteenth transistor, the first terminal of which is connected to the terminal providing the scan input signal, the control terminal of which is connected to the terminal providing the third clock signal, and the second terminal of which is connected to the first node.

[0084] Preferably, the second input unit 712 includes a first transistor, the first terminal of the first transistor is connected to the second terminal of the fourteenth transistor, the control terminal of the first transistor is connected to the providing terminal of the first clock signal, and the second terminal of the first transistor is connected to the first node.

[0085] Understandably, the control terminal of the fourteenth transistor can be triggered in response to the third clock signal to turn on the first and second terminals of the fourteenth transistor to transmit the scan input signal to the first node or the first terminal of the first transistor; while the control terminal of the first transistor can be triggered in response to the first clock signal to turn on the first and second terminals of the first transistor to transmit the scan input signal to the first node.

[0086] It is understood that in this embodiment, the level transmission module 72, output module 73, first control terminal 731, second control terminal 732, and first isolation module 74 are the same as the level transmission module 62, output module 63, first control terminal 631, second control terminal 632, and first isolation module 64, respectively. Please refer to [link / reference] for details. Figure 6 The relevant textual content will not be repeated here.

[0087] Please see Figure 8 , Figure 8This is a schematic diagram of the eighth embodiment of the scan driving circuit of this application. This embodiment is based on the sixth embodiment of the scan driving circuit provided in this application, and the input module 81 in the scan driving circuit 80 specifically includes a second input unit 812.

[0088] Specifically, the second input unit 812 is connected in series between the first input unit 811 and the first node. The first input unit 811 samples the scan input signal in response to the first clock signal, and the second input unit 812 transmits the scan input signal output by the first input unit 811 as the first control signal to the first node in response to the third clock signal.

[0089] Preferably, the first input unit 811 includes a fourteenth transistor, the second input unit 812 includes a first transistor, the first terminal of the fourteenth transistor is connected to the terminal providing the scan input signal, the control terminal of the fourteenth transistor is connected to the terminal providing the first clock signal, the second terminal of the fourteenth transistor is connected to the first terminal of the first transistor, the control terminal of the first transistor is connected to the terminal providing the third clock signal, and the second terminal of the first transistor is connected to the first node.

[0090] Therefore, it can be seen that the control terminals of the fourteenth transistor and the first transistor can be interchanged with the third clock signal and the first clock signal, respectively, and only the fourteenth transistor or the first transistor that receives the third clock signal can be retained. This application does not limit this.

[0091] It is understood that in this embodiment, the level transmission module 82, output module 83, first control terminal 831, second control terminal 832, and first isolation module 84 are the same as the level transmission module 62, output module 63, first control terminal 631, second control terminal 632, and first isolation module 64, respectively. Please refer to [link to documentation] for details. Figure 6 The relevant textual content will not be repeated here.

[0092] Please see Figure 9 , Figure 9 This is a schematic diagram of the ninth embodiment of the scan driving circuit of this application. This embodiment is based on the first embodiment of the scan driving circuit provided in this application, and the scan driving circuit 90 specifically includes a first control module 97.

[0093] Specifically, the first control module 97 is connected to the first node so as to trigger an action in response to the potential of the first node, to sample the first clock signal, and to transmit the first clock signal to the level transmission module 92.

[0094] It is understood that in this embodiment, the input module 91, level transmission module 92, output module 93, first control terminal 931, second control terminal 932, and first isolation module 94 are the same as the input module 11, level transmission module 12, output module 13, first control terminal 131, second control terminal 132, and first isolation module 14, respectively. Please refer to [link / reference] for details. Figure 1 The relevant textual content will not be repeated here.

[0095] Please see Figure 10 , Figure 9 This is a schematic diagram of the tenth embodiment of the scan driving circuit of this application. This embodiment is based on the ninth embodiment of the scan driving circuit provided in this application, and the scan driving circuit 100 specifically includes a second control module 108.

[0096] Specifically, the second control module 108 is connected to the first control terminal, the first node, the output terminal of the first control module 107, and the second level signal providing terminal, so as to receive the second level signal and the second clock signal provided by the timing control circuit, and trigger an action in response to the potential of the output terminal of the first control module 107 and the potential of the first node, so as to sample the second clock signal and the second level signal and transmit them to the first control terminal.

[0097] It is understood that in this embodiment, the input module 101, level transmission module 102, output module 103, first control terminal 1031, second control terminal 1032, first isolation module 104, and first control module 107 are the same as the input module 91, level transmission module 92, output module 93, first control terminal 931, second control terminal 932, first isolation module 94, and first control module 97, respectively. Please refer to [link / reference] for details. Figure 9 The relevant textual content will not be repeated here.

[0098] For better understanding, please continue to refer to the following: Figures 11-13 ,in, Figure 11 This is a schematic diagram of the eleventh embodiment of the scanning drive circuit of this application. Figure 12 yes Figure 11 A schematic diagram of a specific embodiment of the scanning drive circuit. Figure 13 yes Figure 12 A timing diagram of each input signal corresponding to the scanning drive circuit in an embodiment.

[0099] It is understood that, in this embodiment, the scanning drive circuit 110 specifically includes: an input module 111, a level transmission module 112, an output module 113, a first isolation module 114, an inverting module 115, a second isolation module 116, a first control module 117, and a second control module 118; and the input module 111 includes a first input unit 1111 and a second input unit 1112, the inverting module 115 includes an inverting unit 1151 and a phase delay unit 1152, and the output module 113 includes a first output unit 1133, a second output unit 1134, and a coupling unit 1135.

[0100] It is worth noting that, in this embodiment, each module and unit in the scanning drive circuit is the same as shown below. Figures 1-10 For details on modules and units with the same name, their corresponding connections, and functions, please refer to [link / reference]. Figures 1-10 The relevant textual content will not be repeated here.

[0101] Further, in one embodiment, the first input unit 1111 includes a fourteenth transistor T14, the second input unit 1112 includes a first transistor T1, the inverting unit 1151 includes a sixth transistor T6, the phase delay unit 1152 includes a fifteenth transistor T15, the first output unit 1133 includes a tenth transistor T10, the second output unit 1134 includes a ninth transistor T9, the coupling unit 1135 includes a third capacitor C3, the level transmission module 112 includes a third transistor T3, an eleventh transistor T11, an eighth transistor T8, a seventh transistor T7, and a first capacitor C1, the first isolation module 114 includes a thirteenth transistor T13, the second isolation module 116 includes a twelfth transistor T12, the first control module 117 includes a second transistor T2, and the second transistor T2 is a composite transistor, that is, the second transistor T2 further includes a first single-cell transistor T2-1 and a second single-cell transistor T2-2, the second control module 118 includes a fourth transistor T4, a fifth transistor T5, and a second capacitor C2; and the connection relationship between the above transistors and capacitors is as follows: Figure 12 As shown, it is connected to the external timing control circuit, the providing terminal of the first level signal VGL, the providing terminal of the second level signal VGH, and the starting signal providing terminal of the system processing circuit or the output terminal Vout of the upper-level scan drive circuit 110, to receive the first level signal VGL, the second level signal VGH, the first clock signal ECK1, the second clock signal ECK2, and the third clock signal ECK3 provided by the timing control circuit, and the scan input signal EIN provided by the starting signal providing terminal of the system processing circuit or the upper-level scan drive circuit 110. The specific level states of each clock signal are as follows: Figure 4 As shown, please refer to the details. Figure 12and Figure 13 I will not go into details here.

[0102] In this case, taking the first level signal VGL as a low level signal and the second level signal VGH as a high level signal, and the aforementioned transistors as P-type transistors, i.e., triggering the conduction of the first and second terminals when their gate voltage is low, it can be seen that in the first stage, the scan input signal EIN is provided in the first level state, which is also a low level state, and the second clock signal ECK2 and the third clock signal ECK3 are in the first level state, so as to trigger the fourteenth transistor T14, the first transistor T1, the sixth transistor T6, the fifteenth transistor T15, the thirteenth transistor T13 and the tenth transistor T10 to be turned on, so that the first node N1 and the second node N2 are at a low level, and the third node N3 and the fourth node N4 are at a high level, so as to trigger the ninth transistor T9 to be turned off, thereby causing the output terminal Vout to output a low level signal.

[0103] In the second stage, the scan input signal EIN is provided in the second level state, that is, the high level state. The first clock signal ECK1 and the third clock signal ECK3 are provided in the first level state to trigger the fourteenth transistor T14, the first transistor T1, the third transistor T3, and the eleventh transistor T11 to turn on. The fifth node N5 and the sixth node N6 are at a low level, while the first node N1 and the second node N2 are at a high level to trigger the eighth transistor T8 to turn on. The second transistor T2, the sixth transistor T6, and the tenth transistor T10 are turned off, while the fourth node N4 remains at a high level to trigger the ninth transistor T9 to turn off. The output terminal Vout continuously outputs a low level signal.

[0104] In the third stage, the second clock signal ECK2 is provided as the first level state to trigger the seventh transistor T7 to turn on. The first level signal VGL on the sixth node N6 is transmitted to the third node N3 and the fourth node N4 through the eighth transistor T8 and the seventh transistor T7 to trigger the ninth transistor T9 to turn on, so that the output terminal Vout copies and outputs the third clock signal ECK3, that is, the third clock signal ECK3 which is currently in the high level state, to be output to the corresponding scan line, thereby outputting to the corresponding pixel unit through the scan line.

[0105] In the fourth stage, the scan input signal EIN is provided at the first level, the second clock signal ECK2 is provided at the second level, and the first clock signal ECK1 and the third clock signal ECK3 are provided at the first level to trigger the fourteenth transistor T14 and the first transistor T1 to turn on, while the fifteenth transistor T15 is turned off, so that the first node N1 and the second node N2 are at a low level, triggering the tenth transistor T10 to turn on. At this time, since the third node N3 and the fourth node N4 are at a low level in the third stage, the fourth node N4 will be coupled to an extremely low level by the falling edge of the third clock signal ECK3 through the coupling effect of the third capacitor C3, so as to trigger the ninth transistor T9 to turn on and fully open, so that the low level of the third clock signal ECK3 is fully transmitted to the output terminal Vout, so that the output terminal Vout outputs a low level signal.

[0106] Understandably, since the third node N3 is also at a low level at this time, the voltage difference (cross-voltage) between the fourth node N4, i.e., the ninth transistor T9, the seventh transistor T7, and the fifteenth transistor T15, can be effectively reduced by the thirteenth transistor T13. This is to avoid the extremely low level causing impact damage to the seventh transistor T7 and the fifteenth transistor T15, and in turn affecting the stable output of the scan output signal at the output terminal Vout.

[0107] In the fifth stage, the second clock signal ECK2 is provided in the first level state to trigger the fifteenth transistor T15 to turn on, so that the second level signal VGH is transmitted to the third node N3 and the fourth node N4 through the sixth transistor T6 and the fifteenth transistor T15 to trigger the ninth transistor T9 to turn off. At the same time, the second node N2 will be coupled to an extremely low level by the falling edge of the second clock signal ECK2 through the coupling effect of the second capacitor C2, thereby triggering the tenth transistor T10 to turn on and fully open, so that the first level signal VGL can be fully transmitted to the output terminal Vout, so that the output terminal Vout outputs a low level signal.

[0108] Similarly, since the first node N1 is also at a low level at this time, the voltage difference (cross voltage) between the second node N2, i.e. the tenth transistor T10 and the first transistor T1, can be effectively reduced by the action of the twelfth transistor T12, so as to avoid the extremely low level causing impact damage to the first transistor T1, and in turn affecting the stable output of the scan output signal by the output terminal Vout.

[0109] Please continue reading. Figure 14 , Figure 14 yes Figure 12 A schematic diagram of an embodiment obtained by cascading the scanning drive circuits.

[0110] It is understood that in this embodiment, the number of scan driving circuits 110 can be multiple and cascaded to connect to an external timing control circuit, the start signal providing terminal of the system processing circuit, and multiple scan lines, respectively. They receive the first initial clock signal SCK1, the second initial clock signal SCK2, the third initial clock signal SCK3, and the fourth initial clock signal SCK4 provided by the timing control circuit, as well as the scan start signal SIN sent by the start signal providing terminal. After being adjusted by multiple scan driving circuits 20, they output corresponding scan output signals to multiple scan lines, such as the first scan output signal SCN1, the second scan output signal SCN2, the third scan output signal SCN3, and the fourth scan output signal SCN4, and provide them to the corresponding pixel units through multiple scan lines.

[0111] Specifically, the scan input signal EIN of each scan driving circuit 110 is either the scan output signal output by the previous scan driving circuit 110 or the scan start signal SIN of the scan driving circuit 110.

[0112] Optionally, the number of the scanning drive circuits 110 can be any reasonable number, such as 4, 6 or 8, and this application does not limit this number.

[0113] Optionally, the first initial clock signal SCK1 and the third initial clock signal SCK3 have the same waveform and phase, and the second initial clock signal SCK2 and the fourth initial clock signal SCK4 have the same waveform and phase; the third initial clock signal SCK3 and the fourth initial clock signal SCK4 have the same waveform and the period of each is 2h, and the phase difference between the third initial clock signal SCK3 and the fourth initial clock signal SCK4 is 1h.

[0114] Please continue reading. Figure 15 , Figure 15 yes Figure 11 A schematic diagram of another specific embodiment of the scanning drive circuit.

[0115] It is understood that the scan drive circuit 110 in this embodiment and Figure 12 The difference in the scanning drive circuit 110 is that the clock signals connected to the control terminals of the first transistor T1 and the fourteenth transistor T14 are interchanged.

[0116] Please continue reading. Figure 16 , Figure 16 yes Figure 11 A schematic diagram of another specific embodiment of the scanning drive circuit.

[0117] It is understood that the scan drive circuit 110 in this embodiment and Figure 12The difference in the scanning drive circuit 110 is that the fourteenth transistor T14 has been removed.

[0118] This application also provides a method for outputting a scanning signal; please refer to [link to relevant documentation]. Figure 17 , Figure 17 This is a flowchart illustrating one embodiment of the scanning signal output method of this application. Specifically, it may include the following steps:

[0119] S31: In the first stage, the scan input signal is provided at a first level, and the second clock signal and the third clock signal are at a first level, so as to generate a first control signal at the first node, and the output module generates a first scan output signal in response to the first control signal.

[0120] It is understood that the scanning signal output method in this embodiment is specifically the scanning drive circuit in the display panel outputting the signal to the target area. Figure 4 For details on the method of outputting the scan signal by the scan drive circuit shown, please refer to [reference needed]. Figure 4 The relevant textual content will not be repeated here.

[0121] Among them, such as Figure 13 As shown, in the first stage, the scan input signal is provided at a first level, and the second clock signal and the third clock signal are at a first level to trigger the input module, the inverting unit and the phase delay unit to turn on, and generate a first control signal at the first node, so that the output module responds to the first control signal to generate a first scan output signal.

[0122] S32: In the second stage, the scan input signal is provided at the second level, the first clock signal and the third clock signal are provided at the first level, and the output module continuously generates the first scan output signal.

[0123] Furthermore, in the second stage, the scan input signal is provided at a second level, and the first clock signal and the third clock signal are provided at a first level to trigger the input module to turn on, thereby setting the first node and the third node high and triggering the inverting unit to turn off, so that the output module continuously generates the first scan output signal.

[0124] S33: In the third stage, the second clock signal is provided as the first level state to generate the second control signal at the third node, and the output module responds to the second control signal to generate the second scan output signal.

[0125] Furthermore, in the third stage, the second clock signal is provided as the first level state to trigger the level transmission module to turn on, and the first level signal is provided to the output module through the level transmission module to generate the second control signal at the third node, so that the output module responds to the second control signal to generate the second scan output signal.

[0126] S34: In the fourth stage, the scan input signal is provided as a first level state, the second clock signal is provided as a second level state, and the first clock signal and the third clock signal are provided as a first level state to generate a first control signal at the first node. The output module responds to the first control signal to generate a first scan output signal.

[0127] In the fourth stage, the scan input signal is provided at a first level, the second clock signal is provided at a second level, and the first clock signal and the third clock signal are provided at a first level to trigger the input module, the inverting unit, and the phase delay unit to turn on, so as to generate a first control signal at the first node, and cause the output module to respond to the first control signal to generate a first scan output signal.

[0128] S35: In the fifth stage, the second clock signal is provided at the first level, and the output module continuously generates the first scan output signal.

[0129] In the fifth stage, the second clock signal is provided at the first level state so that the output module continuously generates the first scan output signal.

[0130] It is understood that in some other embodiments, the scan driving circuit may further include other more specific features to enable the implementation of other more specific scan signal output methods; please refer to the relevant documentation for details. Figures 1-16 The relevant textual content will not be repeated here.

[0131] This application also provides a display panel; please refer to [link / reference]. Figure 18 , Figure 18 This is a schematic diagram of one embodiment of the display panel of this application. In this embodiment, the display panel 120 includes a scan driving circuit 121 and a pixel unit 122 coupled together.

[0132] It should be noted that the scan driving circuit 121 described in this embodiment is any of the scan driving circuits 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, or 110 described in the above embodiments. Please refer to the following for details. Figures 1-16 The relevant textual content will not be elaborated upon here.

[0133] The beneficial effects of this application are as follows: Unlike the prior art, the input module of the scan driving circuit provided in this application is used to generate a first control signal at a first node, the level transmission module is used to generate a second control signal at a third node, and the output module includes a first control terminal and a second control terminal. The first control terminal and the second control terminal are respectively used to electrically connect the input module and the level transmission module so that they can generate corresponding scan output signals in response to the first control signal and the second control signal, respectively. Furthermore, a first isolation module is provided between the second control terminal of the output module and the third node to minimize the voltage difference between the level transmission module and the output module, thereby stabilizing the output scan signal and effectively improving the reliability of the scan driving circuit.

[0134] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A scanning drive circuit, characterized in that, include: The input module is used to generate the first control signal at the first node; The input module at least responds to a third clock signal to sample the scan input signal in order to generate the first control signal at the first node; A level transmission module is used to generate a second control signal at the third node; The level transmission module samples the first level signal in response to the first clock signal and the second clock signal to generate the second control signal at the third node; wherein the first clock signal, the second clock signal and the third clock signal have the same period, the phase difference between the second clock signal and the first clock signal is half a cycle, and the rising edge of the third clock signal is not earlier than the falling edge of the second clock signal; The output module includes a first control terminal and a second control terminal, wherein the first control terminal and the second control terminal are respectively used to electrically connect the input module and the level transmission module to generate corresponding scan output signals in response to the first control signal and the second control signal; The first isolation module is located between the second control terminal of the output module and the third node.

2. The scanning drive circuit according to claim 1, characterized in that, Further includes: An inverting module, which samples a second level signal in response to the first control signal and the second clock signal on the first node, and transmits it to the third node.

3. The scanning drive circuit according to claim 2, characterized in that, The inverting module includes: An inverting unit, connected to the first node, samples the second level signal in response to the first control signal on the first node; A phase delay unit is connected to the inverting unit and the third node. The phase delay unit responds to the second clock signal, performs a phase delay on the second level signal output by the inverting unit, and transmits it to the third node.

4. The scanning drive circuit according to claim 3, characterized in that, The inverting unit includes a sixth transistor, and the phase delay unit includes a fifteenth transistor. The first terminal of the sixth transistor is connected to the providing terminal of the second level signal, the control terminal of the sixth transistor is connected to the first node, the second terminal of the sixth transistor is connected to the first terminal of the fifteenth transistor, the control terminal of the fifteenth transistor is connected to the providing terminal of the second clock signal, and the second terminal of the fifteenth transistor is connected to the third node.

5. The scanning drive circuit according to claim 1, characterized in that, The output module includes: The first output unit has a control terminal that serves as the first control terminal of the output module. The first terminal of the first output unit receives a first level signal, and the second terminal of the first output unit is connected to the output terminal of the output module. The first output unit responds to the first control signal by transmitting the first level signal as the scan output signal to the output terminal of the output module. The second output unit has a control terminal that serves as the second control terminal of the output module. The first terminal of the second output unit receives a third clock signal, and the second terminal of the second output unit is connected to the output terminal of the output module. The second output unit responds to the second control signal by transmitting the third clock signal as the scan output signal to the output terminal of the output module. A coupling unit, wherein the first end of the coupling unit is connected to the control terminal of the second output unit, and the second end of the coupling unit is connected to the second terminal of the second output unit.

6. The scanning drive circuit according to claim 5, characterized in that, The first output unit includes a tenth transistor, the second output unit includes a ninth transistor, the coupling unit includes a third capacitor, the first terminal of the tenth transistor is connected to the providing terminal of the first level signal, the control terminal of the tenth transistor is connected to the first control terminal, the second terminal of the tenth transistor is connected to the output terminal of the output module, the first terminal of the ninth transistor is connected to the providing terminal of the third clock signal, the control terminal of the ninth transistor is connected to the first terminal of the third capacitor and the second control terminal, and the second terminal of the ninth transistor is connected to the second terminal of the third capacitor and the output terminal of the output module.

7. The scanning drive circuit according to claim 1, characterized in that, Further includes: The second isolation module is located between the first control terminal of the output module and the first node.

8. The scanning drive circuit according to claim 1, characterized in that, The input module includes: The first input unit samples the scan input signal in response to the third clock signal.

9. The scanning drive circuit according to claim 8, characterized in that, The input module further includes a second input unit, which is connected in series between the first input unit and the first node. The second input unit responds to the first clock signal and transmits the scan input signal output by the first input unit to the first node as the first control signal.

10. The scanning drive circuit according to claim 9, characterized in that, The first input unit includes a fourteenth transistor, the first terminal of which is connected to the providing terminal of the scan input signal, the control terminal of which is connected to the providing terminal of the third clock signal, and the second terminal of which is connected to the first node.

11. The scanning drive circuit according to claim 10, characterized in that, The second input unit includes a first transistor, a first terminal of which is connected to the second terminal of the fourteenth transistor, a control terminal of which is connected to the terminal providing the first clock signal, and a second terminal of which is connected to the first node.

12. The scanning drive circuit according to claim 1, characterized in that, The input module includes: A first input unit and a second input unit are connected in series between the first input unit and the first node. The first input unit samples the scan input signal in response to a first clock signal, and the second input unit transmits the scan input signal output by the first input unit as the first control signal to the first node in response to a third clock signal.

13. The scanning drive circuit according to claim 12, characterized in that, The first input unit includes a fourteenth transistor, the second input unit includes a first transistor, the first terminal of the fourteenth transistor is connected to the providing terminal of the scan input signal, the control terminal of the fourteenth transistor is connected to the providing terminal of the first clock signal, the second terminal of the fourteenth transistor is connected to the first terminal of the first transistor, the control terminal of the first transistor is connected to the providing terminal of the third clock signal, and the second terminal of the first transistor is connected to the first node.

14. The scanning drive circuit according to claim 1, characterized in that, Further includes: The first control module samples the first clock signal in response to the potential of the first node and transmits it to the level transmission module.

15. The scanning drive circuit according to claim 14, characterized in that, Further includes: The second control module is connected to the first control terminal and the output terminal of the first control module. It samples the second clock signal and the second level signal in response to the potential of the output terminal of the first control module and the potential of the first node, and transmits them to the first control terminal.

16. The scanning drive circuit according to any one of claims 1-15, characterized in that, The scan input signal is either the scan output signal output by the scan driving circuit of the previous stage, or the scan start signal of the scan driving circuit.

17. A method for outputting a scanning signal, characterized in that, When applied in the scanning drive circuit of claim 3, it includes: In the first stage, the scan input signal is provided at a first level state, and the second clock signal and the third clock signal are at the first level state to generate a first control signal at the first node, and the output module generates a first scan output signal in response to the first control signal. In the second stage, the scan input signal is provided at a second level, the first clock signal and the third clock signal are provided at the first level, and the output module continuously generates the first scan output signal; In the third stage, the second clock signal is provided at the first level state to generate a second control signal at the third node, and the output module generates a second scan output signal in response to the second control signal; In the fourth stage, the scan input signal is provided at the first level state, the second clock signal is provided at the second level state, and the first clock signal and the third clock signal are provided at the first level state to generate a first control signal at the first node, and the output module generates the first scan output signal in response to the first control signal. In the fifth stage, the second clock signal is provided at the first level state, and the output module continuously generates the first scan output signal.

18. A display panel, characterized in that, The display panel includes a scan driving circuit and a pixel unit that are coupled together; The scanning drive circuit is the scanning drive circuit according to any one of claims 1-17.

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