Display panel, driving method thereof, and computer readable storage medium

Abstract

The application provides a display panel and a driving method thereof, and a computer readable storage medium. Specifically, the driving method of the display panel comprises the following steps: receiving a trigger instruction; setting a refresh rate of a first display area of the display panel as a first refresh rate in response to the trigger instruction, wherein a display frame of the first display area comprises a write frame and a hold frame; and keeping a data voltage of a data line unchanged in the same hold frame of the first display area. In the application, the driving chip keeps the data voltage of the data line unchanged in the same hold frame of the first display area, so that the power consumption of the driving chip can be reduced.

Description

Technical Field

[0001] This application belongs to the field of display technology, specifically relating to a display panel and its driving method, and a computer-readable storage medium. Background Technology

[0002] With the development of display technology, display panels are being used in more and more scenarios, and users' display needs for display panels are becoming more and more diversified. For example, display panels can now support multiple refresh rates.

[0003] Meanwhile, low power consumption has always been a hot topic in the display panel industry, but display panels that support multiple refresh rates still have the problem of high power consumption. Summary of the Invention

[0004] This application provides a display panel and its driving method, as well as a computer-readable storage medium, which can reduce the power consumption of the display panel.

[0005] To solve the above-mentioned technical problems, one technical solution adopted in this application is: to provide a driving method for a display panel, the driving method comprising: receiving a trigger instruction; in response to the trigger instruction, setting the refresh rate of a first display area of ​​the display panel to a first refresh rate, wherein the display frame of the first display area includes a write frame and a hold frame; and in the same hold frame of the first display area, keeping the data voltage of the data line unchanged.

[0006] Another technical solution adopted in this application is: providing a display panel, which includes a processor, a memory and a communication circuit. The processor is coupled to the memory and the communication circuit respectively. The memory stores program data. The processor executes the program data in the memory to implement the steps in any of the methods in the above method embodiments.

[0007] Another technical solution adopted in this application is to provide a computer-readable storage medium that stores a computer program, which can be executed by a processor to implement the steps as described in any of the above method embodiments.

[0008] The beneficial effect of this application is that the driver chip is configured to keep the data voltage of the data line unchanged in the same holding frame in the first display area, which can reduce the power consumption of the driver chip. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0010] Figure 1 This is a flowchart illustrating an embodiment of the display panel driving method of this application;

[0011] Figure 2 yes Figure 1 A flowchart illustrating step S2;

[0012] Figure 3 This is a schematic diagram of the structure of a display area in the display panel of this application;

[0013] Figure 4 yes Figure 3 A schematic diagram showing the composition of frames in the display panel shown;

[0014] Figure 5 This is a schematic diagram of another embodiment of the display area in the display panel of this application;

[0015] Figure 6 yes Figure 5 A schematic diagram of the SW signal in the display panel shown;

[0016] Figure 7 This is a schematic diagram of an embodiment of the display frame composition in the display panel of this application;

[0017] Figure 8 This is a schematic diagram of one embodiment of the display panel in this application;

[0018] Figure 9 This is a schematic diagram of the structure of one embodiment of the computer-readable storage medium of this application;

[0019] Explanation of reference numerals in the attached figures: 1 Data line; 2 First display area; 3 Second display area; 4 Driver chip; 20 Display panel; 21 Processor; 22 Memory; 23 Communication circuit; 400 Computer-readable storage medium; 410 Computer program. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0021] To better explain the solution of the present invention, the basic structure and driving process of the display panel will be briefly described below.

[0022] Display panels typically include a scan drive circuit and pixel circuits arranged in an array in the display area. The scan drive circuit includes multiple cascaded shift registers. Each pixel circuit, together with a light-emitting device, forms a sub-pixel. Each shift register is connected to a scan line and provides a scan signal to the corresponding row of sub-pixels through the scan line. Each column of sub-pixels is connected to a data line.

[0023] During screen display, data is written to each pixel circuit through a line-by-line scan. Specifically, the shift register provides scan signals to the pixel circuits via scan lines. Corresponding to the duration of the scan signal's on-state potential, the data voltage on the data lines is transmitted to the corresponding pixel circuit to achieve data writing. Each pixel circuit outputs a drive current based on the data voltage, driving the light-emitting device to emit light for display. When the scan line provides a cutoff potential, the data voltage on the data lines cannot be transmitted to the corresponding pixel circuit, and no data is written.

[0024] In existing technologies, for display panels capable of switching display frequencies, the display frames of sub-pixels can be divided into write frames and hold frames. In a write frame, the shift register provides an on-potential to the pixel circuit, allowing data voltage to be written to the pixel circuit; in a hold frame, the shift register provides an off-potential to the pixel circuit, and the pixel circuit no longer writes data.

[0025] Furthermore, in the embodiments of this application, the display panel supports multiple refresh rates. For ease of explanation, the highest refresh rate is referred to as the high refresh rate, and all other refresh rates are referred to as low refresh rates. The driving mode at the high refresh rate is called the high-frequency driving mode, and the driving mode at the low refresh rate is called the low-frequency driving mode. It can be understood that the frame rate (also known as refresh rate) of the high-frequency driving mode is higher than that of the low-frequency driving mode. Specifically, the frame rate (refresh rate) refers to the number of times the electron beam repeatedly scans the image on the screen per unit time.

[0026] In high-frequency drive mode, the display frame only includes write frames, while in low-frequency drive mode, the display frame includes both write frames and hold frames. The difference between write frames and hold frames is as follows: in a write frame, the shift register provides an on-state potential to the pixel circuit, allowing data voltage to be written to the pixel circuit; in a hold frame, the shift register provides an off-state potential to the pixel circuit, and the pixel circuit no longer writes data. In other words, the display data is refreshed in write frames, resulting in continuously changing images, while the images remain unchanged in hold frames.

[0027] The technical solution in this application will be described below. First, it should be noted that the driving method of the display panel in this application is executed by the driver chip 4. The driver chip 4 typically receives instructions from the control motherboard and drives the display screen to display according to the instructions.

[0028] Please see Figure 1 In one embodiment, the driving method for the display panel includes:

[0029] S1: Receive trigger command.

[0030] Specifically, the driver chip 4 receives the trigger command sent by the control motherboard, and then outputs data to the display screen according to the trigger command, so that the display screen displays the image.

[0031] S2: In response to the trigger command, the refresh rate of the first display area of ​​the display panel is set to the first refresh rate. The display frames of the first display area include write frames and hold frames.

[0032] Specifically, the first display area 2 of the display panel can be the entire display area or a part of the display area. The same display panel can contain several first display areas 2, which can be used to display different images. If the display area simultaneously includes multiple first display areas 2, then as long as an instruction is triggered to set the refresh rate corresponding to the first display area 2 to the first refresh frequency, subsequent steps will be executed for that first display area 2.

[0033] The first refresh rate is a low refresh rate, which is lower than the display panel's maximum refresh rate. For example, when the display panel's maximum refresh rate is 240Hz, the first refresh rate can be either 120Hz or 60Hz.

[0034] In one embodiment, when the refresh rate is 120Hz, the corresponding display area displays 120 frames per second, all of which are write frames. When the first refresh rate is less than the maximum refresh rate of the display panel, for example, when the first refresh rate is 60Hz, the corresponding display area still displays 120 frames per second, but 60 of these 120 frames are write frames and the other 60 are hold frames.

[0035] S3: In the same holding frame of the first display area, keep the data voltage of the data line unchanged.

[0036] Specifically, as can be seen from the above description, the display screen does not need to change during the hold frame, and the data voltage of data line 1 is not transmitted to the corresponding pixel circuit. Therefore, the specific value of the data voltage on data line 1 during the hold frame will not affect the display screen. In order to avoid the data voltage of data line 1 changing suddenly and increasing the power consumption of the driver chip 4, this embodiment is designed to keep the data voltage of data line 1 unchanged during the same hold frame in the first display area 2. That is to say, during the same hold frame, the data voltage on each data line 1 will not change suddenly.

[0037] As can be seen from the above, this application takes into account that the voltage on data line 1 in the holding frame will not affect the display screen. Therefore, keeping the data voltage of data line 1 unchanged in the holding frame can avoid the power consumption caused by the voltage change of the driver chip 4, avoid the battery draining too quickly, and improve the service life of the display panel and display device.

[0038] Optionally, in step S3, the step of keeping the data voltage of data line 1 constant within the same holding frame of the first display area 2 further includes:

[0039] S31: As the holding frame of the first display area switches, the write data voltage of the holding data line remains unchanged.

[0040] When switching from one hold frame to another, the write data voltage of the hold data line 1 remains unchanged. This ensures that the write data voltage of the hold data line 1 remains constant throughout the consecutive hold frames, thereby reducing power consumption, preventing the battery from draining too quickly, and extending the lifespan of the display panel and display device.

[0041] Optionally, in step S3, the step of keeping the data voltage of data line 1 unchanged in the same holding frame of the first display area 2 further includes:

[0042] S32: As the holding frame of the first display area switches, the write data voltage of the setting data line changes according to a preset rule.

[0043] When switching from one hold frame to another, the write data voltage of data line 1 is set to change according to a preset rule so that the write data voltage of data line 1 does not change randomly. Since the power consumption of the data voltage changing randomly is greater than the power consumption when the data voltage changes according to the preset rule, this setting can further reduce the power consumption of driver chip 4.

[0044] When the write data voltage of data line 1 changes according to a preset rule as the hold frame switches, the following design can be made: as the hold frame switches, the write data voltage of data line 1 gradually increases or decreases.

[0045] In summary, as the holding frame of the first display area 2 switches, the write data voltage of the setting data line 1 changes according to a preset rule, which can reduce the additional power consumption of the display panel caused by the random change of the write data voltage in the holding frame of the prior art, thereby reducing the power consumption of the display panel.

[0046] Optionally, in step S3, the step of keeping the data voltage of data line 1 constant within the same holding frame of the first display area 2 includes:

[0047] S33: In the same holding frame of the first display area, the write data voltage of the holding data line is kept at a preset fixed value.

[0048] The first refresh rate corresponds to the image displayed in the first display area 2. This image is written in the write frame and not written in the hold frame, but data line 1 is still active. By applying a fixed voltage to data line 1, this voltage is not written into the actual pixels, nor does it actually emit light. The fixed write potential allows data line 1 to remain stationary without affecting the image, thus reducing power consumption. The preset fixed value can be set according to actual needs, and this application does not impose any restrictions.

[0049] In one embodiment, the preset fixed value ranges from 0.2V to 7.9V. For example, the preset fixed value is 0.2V, 0.8V, 1V, 2V, 3V, 4V, 5V, 6V, 7V, or 7.9V.

[0050] Optionally, in step S3, the step of keeping the data voltage of data line 1 constant within the same holding frame of the first display area 2 includes:

[0051] S34: In the same holding frame of the first display area, the data line is kept in a high impedance state.

[0052] In the high-impedance Hi-Z setting, the driver chip 4 does not control the voltage in data line 1, leaving data line 1 floating and without assigning a value to it, thus not adjusting the display screen. The data voltage in data line 1 remains unchanged, reducing the power consumption of the driver chip 4 in the display panel.

[0053] Optionally, in step S3, the step of keeping the data voltage of the data line constant within the same holding frame of the first display area 2 includes:

[0054] S35: In response to the trigger command, the refresh rate of the second display area 3 is further set to a second refresh rate that is greater than the first refresh rate. In the same holding frame of the first display area 2, the data voltage of the data line 1 is kept unchanged, and the write data voltage of the data line 1 is set to be equal to the target data voltage.

[0055] Specifically, in the above scheme, the display area is divided into multiple different areas, and different refresh rates are set for different areas. During partitioning, the different areas are arranged along the extension direction of data line 1, and the different areas are connected to the same data line. The partitioning can be done by dividing the display area into 2 areas, 3, 4, or more; however, for ease of explanation, we will use 2 areas here, meaning the display area is divided into a first display area 2 and a second display area 3. The first display area 2 and the second display area 3 are then arranged adjacent to each other along the extension direction of the data line, and the first display area 2 and the third display area 3 are connected to the same data line.

[0056] At the same time, the second refresh rate is greater than the first refresh frequency. For example, if the first refresh frequency is 60Hz, the second refresh frequency is 120Hz.

[0057] Specifically, within the same scan cycle, if the second display area 3 is scanned first and then the first display area 2 is scanned, the target data voltage is the data voltage written to data line 1 during the last scan of the second display area 3, before scanning the first display area 2. Conversely, within the same scan cycle, if the first display area 2 is scanned first and then the second display area 3 is scanned, the target data voltage is the data voltage written to data line 1 during the first scan of the second display area 3, after scanning the first display area 2.

[0058] The following examples will illustrate this:

[0059] Assuming that before scanning the first display area 2, during the last scan of the second display area 3, the data voltage written to data line 1 is A (or, in the case of progressive scanning, the data voltage written to data line 1 when scanning the last pixel row of the second display area 3 is A), then during the holding frame of the first display area 2, the data voltage written to data line 1 remains A. Assuming that after scanning the first display area 2, during the first scan of the second display area 3, the data voltage written to data line 1 is B (or, in the case of progressive scanning, the data voltage written to data line 1 when scanning the first pixel row of the second display area 3 is B), then during the holding frame of the first display area 2, the data voltage written to data line 1 remains B.

[0060] The above design can keep the voltage of data line 1 constant during the switching process between the first display area 2 and the second display area 3, thus avoiding power consumption caused by sudden changes in the data voltage output by the driver chip 4.

[0061] Step S2 also includes:

[0062] S20: In response to the trigger command, the refresh rate of the second display area 3 is further set to a second refresh rate different from the first refresh rate, and an SW signal is generated, wherein the period of the SW signal is equal to the scanning period of the scan signal, and the first display area 2 and the second display area 3 are arranged in the extension direction of the data line 1; within the current scanning period, when the SW signal is at the first level, the display frame scanned to the first display area 2 is determined, and when the SW signal is at the second level, the display frame scanned to the second display area 3 is determined.

[0063] Specifically, the scan cycle is the time it takes to scan the display panel once. For example, if the display panel consists of 100 pixel rows, then the scan cycle is the time it takes to scan 100 pixel rows once. If the display panel's highest refresh rate is 120Hz, then there are 120 scan cycles per unit time. Figure 4 In this case, the scan period is T.

[0064] Based on the relative positions of the first display area 2 and the second display area 3 indicated by the trigger command, an SW signal is generated. The function of the SW signal is to indicate whether the first display area 2 or the second display area 3 is being scanned during the scanning process.

[0065] Within each scan cycle, when the SW signal is at the first level, a display frame in the first display area 2 is determined; when the SW signal is at the second level, a display frame in the second display area 3 is determined. In one application scenario, the first level is high and the second level is low; in other application scenarios, the first level can be low and the second level can be high. Specifically, when according to... Figure 3 When dividing the display area in this way, the waveform of the SW signal is as follows: Figure 4 As shown, when according to Figure 5 When dividing the display area in this way, the waveform of the SW signal is as follows: Figure 6 As shown.

[0066] After generating the SW signal, the display frames of the first display area 2 and the second display area 3 can be determined, and the display frames of the first display area 2 can be divided into write frames and hold frames.

[0067] Please see Figure 2 In step S2, the step of dividing the display frame of the first display area 2 into a write frame and a hold frame includes:

[0068] S21: Determine the ratio of the highest refresh rate to the first refresh rate.

[0069] Obtain the highest refresh rate and the first refresh rate of the display panel, and calculate the ratio between the two.

[0070] S22: Set the first frame in the display frames of the first display area 2 as the write frame, and set (K-1) hold frames between any two adjacent write frames in the display frames of the first display area 2, where K is the ratio.

[0071] See Figure 4 When the highest refresh rate of the display panel is 120Hz and the first refresh rate is 60Hz, the ratio K is 2. In the display frames of the first display area 2, the first frame is a write frame, and there is one hold frame between any two write frames.

[0072] See Figure 7 When the highest refresh rate of the display panel is 120Hz and the first refresh rate is 30Hz, the ratio K is 4. In the display frames of the first display area 2, the first frame is a write frame, and there are 3 hold frames between any two write frames.

[0073] It should be noted that the above description details the solution of this application by dividing the display area into multiple different regions and setting different refresh rates for each region. However, the solution of this application can also be applied to application scenarios where the display area is not divided into multiple different regions. For example, in one application scenario, during the first time period, the refresh rate of the entire display area of ​​the display panel is the highest refresh rate. However, during the second time period, triggered by a trigger command, the refresh rate of the entire display area of ​​the display panel becomes a first refresh rate lower than the highest refresh rate. That is to say, at this time, the first display area is the entire display area of ​​the display panel. Similarly, during the second time period, within the same holding frame of the first display area, keeping the data voltage of the data line unchanged can reduce the power consumption of the driver chip.

[0074] Please see Figure 8 This application also provides a display panel 20, which includes a processor 21, a memory 22, and a communication circuit 23. The processor 21 is coupled to the memory 22 and the communication circuit 23. The memory 22 stores program data. The processor 21 executes the program data in the memory 22 to implement the steps of any of the methods described in the above method embodiments. When the display panel 20 is in operation, it executes the method steps of any of the above embodiments. Detailed method steps can be found in the relevant content above and will not be repeated here.

[0075] The display panel 20 can be applied to mobile or fixed terminals such as electronic paper, mobile phones, tablets, televisions, monitors, laptops, digital photo frames, smart bracelets, smartwatches, supercomputers, or navigators.

[0076] Please see Figure 9This application also provides a computer-readable storage medium 400, wherein the computer-readable storage medium 400 stores a computer program 410, which can be executed by a processor to implement the steps as described in any of the above method embodiments.

[0077] Specifically, the computer-readable storage medium 400 can be a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, or a device that can store the computer program 410. Alternatively, it can be a server that stores the computer program 410, which can send the stored computer program 410 to other devices for execution, or it can run the stored computer program 410 itself.

[0078] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A driving method for a display panel, characterized in that, The method includes: Receive trigger command; In response to the trigger command, the refresh rate of the first display area of ​​the display panel is set to a first refresh rate, and the display frames of the first display area include write frames and hold frames; Within the same holding frame of the first display area, the data voltage of the data line remains unchanged; The step of keeping the data voltage of the data line constant within the same holding frame in the first display area further includes: As the holding frame of the first display area switches, the write data voltage of the data line is set to change according to a preset rule; The step of setting the write data voltage of the data line to vary according to a preset rule includes: The write data voltage of the data line is set to increase or decrease as the hold frame of the first display area switches.

2. The driving method according to claim 1, characterized in that, The step of keeping the data voltage of the data line constant within the same holding frame in the first display area includes: Within the same holding frame of the first display area, the write data voltage of the data line is kept at a preset fixed value.

3. The driving method according to claim 2, characterized in that, The preset fixed value ranges from 0.2V to 7.9V.

4. The driving method according to claim 1, characterized in that, The step of keeping the data voltage of the data line constant within the same holding frame in the first display area includes: Within the same hold frame of the first display area, the data line is kept in a high-impedance state.

5. The driving method according to claim 1, characterized in that, The step of keeping the data voltage of the data line constant within the same holding frame in the first display area includes: In response to the trigger command, the refresh rate of the second display area is further set to a second refresh rate that is greater than the first refresh rate. In the same hold frame of the first display area, the data voltage of the data line is kept constant, and the write data voltage of the data line is set to be equal to the target data voltage. The first display area and the second display area are arranged adjacent to each other along the extension direction of the data line, and the first display area and the second display area are connected to the same data line. In the same scanning cycle, the second display area is scanned first, and then the first display area is scanned. The target data voltage is the data voltage written to the data line during the last scan before scanning the first display area. Alternatively, in the same scanning cycle, the first display area is scanned first, and then the second display area is scanned. The target data voltage is the data voltage written to the data line during the first scan after scanning the first display area.

6. The driving method according to claim 1, characterized in that, Before the display frames in the first display area include the write frames and the hold frames, the following are also included: In response to the trigger command, the refresh rate of the second display area is further set to a second refresh rate different from the first refresh rate, and an SW signal is generated, wherein the period of the SW signal is equal to the scanning period of the scan signal, and the first display area and the second display area are arranged in the extension direction of the data line; During the current scanning cycle, when the SW signal is at the first level, the display frame scanned to the first display area is determined; when the SW signal is at the second level, the display frame scanned to the second display area is determined.

7. The driving method according to claim 1, characterized in that, The display frame of the first display area includes the steps of writing a frame and holding a frame, including: Determine the ratio of the highest refresh rate to the first refresh rate; The first frame in the display frames of the first display area is set as the write frame, and at the same time, in the display frames of the first display area, there are (K-1) hold frames between any two adjacent write frames, where K is the ratio.

8. A display panel, characterized in that, The method includes a processor, a memory, and a communication circuit. The processor is coupled to the memory and the communication circuit, respectively. The memory stores program data, and the processor executes the program data in the memory to implement the steps of the method as described in any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that can be executed by a processor to implement the steps of the method as described in any one of claims 1-7.

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