A non-volatile memory and its control method, and an electronic device

Abstract

This application provides a non-volatile memory and its control method, as well as an electronic device. The non-volatile memory includes a main memory array for writing and storing data, comprising multiple different word lines and multiple different bit lines, with the word lines and bit lines intersecting. Each word line corresponds to a memory address, and a single memory address includes multiple memory bit cells. Each word line and each bit line jointly define a memory bit cell. A counting array is configured to count the number of write operations to the memory address corresponding to a single word line; the counting array counts once each time data is written to one or more memory bit cells within the memory address corresponding to a single word line. A range selection array is configured to store range information of a reference current; each word line corresponds to a range information of a reference current. A range lookup table is configured to store the corresponding reference current information based on the range information of the range selection array.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a non-volatile memory and its control method, and an electronic device. Background Technology

[0002] Memory is a device used to store program information and data information. It typically digitizes the information and then stores it using media such as electricity, magnetism, or optics. Common memory devices store information in binary units on a chip, that is, as logic 0s or logic 1s. In physical devices, this is usually achieved through high or low voltage, high or low resistance, or large or small amounts of charge.

[0003] Based on whether the information stored in the memory persists after the external power supply is removed, memory can be divided into volatile memory and non-volatile memory. Volatile memory requires a continuous external power supply to store information. When the external power supply is removed, the stored information is lost. Non-volatile memory, on the other hand, retains its stored information even after the external power supply is removed.

[0004] Due to the different interface state properties of the memory storage material, the drain-source currents corresponding to the 0 and 1 states in non-volatile memory change with the increase of write operations. It's possible that the drain-source currents for both states increase simultaneously, decrease simultaneously, or that the drain-source current for one state increases while the drain-source current for the other decreases. However, as the number of write operations increases, when the drain-source currents corresponding to the 0 and 1 states in non-volatile memory increase (or decrease) simultaneously, if the reference current remains constant, the upper limit of the number of write operations is relatively low. Conversely, when the drain-source current for one state in non-volatile memory increases while the drain-source current for the other state decreases, the upper limit of the number of write operations is relatively high.

[0005] Therefore, when the drain-source currents corresponding to the 0 and 1 states stored in a non-volatile memory increase (or decrease) simultaneously, how to increase the upper limit of the number of write operations in the memory is a hot research topic for those skilled in the art. Summary of the Invention

[0006] This application provides a novel non-volatile memory and its control method and electronic device, which can effectively increase the upper limit of the number of write operations of the non-volatile memory.

[0007] To achieve the above objectives, this application adopts the following technical solution:

[0008] A first aspect of this application provides a non-volatile memory, which includes a main memory array for writing and storing data, comprising multiple different word lines and multiple different bit lines, wherein the word lines and bit lines intersect; each word line corresponds to a memory address, and a single memory address includes multiple memory bit cells, wherein each word line and each bit line jointly define a memory bit cell; a counting array configured to count the number of write operations for the memory address corresponding to a single word line, wherein the counting array counts once each time data is written to one or more memory bit cells in the memory address corresponding to a single word line; a range selection array configured to store range information of a reference current; each word line corresponds to a range information of a reference current; and a range lookup table configured to store the corresponding reference current information according to the range information of the range selection array.

[0009] In one possible implementation, a portion of the memory's word lines are used to store information about the gear lookup table unit.

[0010] In one possible implementation, the reference current information corresponding to each gear is written into the gear lookup table unit during chip factory testing.

[0011] In one possible implementation, the gear lookup table also stores reference current redundancy information.

[0012] In one possible implementation, the same word line within the main memory array corresponds to the same reference current.

[0013] In one possible implementation, the memory also includes a sensitive amplifier used to compare a reference current value with data read from the main memory array.

[0014] In one possible implementation, one end of the sensitive amplifier is coupled to a reference current value, and the other end is coupled to the current value data read from the main memory array.

[0015] In one possible implementation, the memory includes multiple sensitive amplifiers and multiple bit lines, each of the multiple sensitive amplifiers being coupled to each of the multiple bit lines.

[0016] In a second aspect of this application, a control method for a non-volatile memory is provided. This control method includes the following steps: writing data to be stored to a main memory array, where a counting array is used to count the number of times data is written to the memory address of a single word line; reading data from a selected word line; selecting a reference current range in a range selection array based on the word line; and finding the corresponding reference current in a range lookup table based on the range.

[0017] In a third aspect of the embodiments of this application, an electronic device is provided, the electronic device comprising: a circuit board and a non-volatile memory, the circuit board and the non-volatile memory being coupled together. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0019] Figure 2a A schematic diagram illustrating the relationship between leakage current and the number of times data is written to the memory, provided for an embodiment of this application.

[0020] Figure 2b A schematic diagram illustrating the relationship between leakage current and the number of times data is written to the memory, provided for an embodiment of this application.

[0021] Figure 3 A schematic diagram illustrating the relationship between leakage current and the number of times data is written to the memory, provided for an embodiment of this application.

[0022] Figure 4 A schematic diagram of the circuit structure of a non-volatile memory provided in an embodiment of this application;

[0023] Figure 5 A schematic diagram of the main storage array and counter array level selection circuit provided in the embodiments of this application;

[0024] Figure 6 This is a schematic diagram of the data writing process for the counting array provided in an embodiment of this application;

[0025] Figure 7 This is a schematic diagram of the circuit structure of another non-volatile memory provided in an embodiment of this application. Detailed Implementation

[0026] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0027] Hereinafter, the terms "second," "first," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "second," "first," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0028] Furthermore, in the embodiments of this application, directional terms such as "upper," "lower," "left," and "right" may be defined relative to the orientation in which the components are schematically placed in the accompanying drawings. It should be understood that these directional terms can be relative concepts, used for relative description and clarification, and can change accordingly based on the orientation of the components in the accompanying drawings.

[0029] In the embodiments of this application, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. Furthermore, the term "coupled connection" can be a direct electrical connection or an indirect electrical connection through an intermediate medium. The term "contact" can be direct contact or indirect contact through an intermediate medium.

[0030] In this embodiment, "and / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following associated objects have an "or" relationship. Below, some terms in this embodiment will be explained.

[0031] Volatile and non-volatile memory (NVM): Based on whether the stored information persists after the external power supply is removed, memory can be divided into volatile and non-volatile memory. Volatile memory is represented by static random access memory (SRAM) or dynamic random access memory (DRAM), which requires a continuous external power supply for information storage. When no external power is applied, the stored information is lost. Non-volatile memory is represented by traditional read-only memory (ROM), flash memory, ferroelectric random-access memory (FeRAM, ferroelectric field effect transistor (FeFET), magnetoresistive random access memory (MRAM), resistive random access memory (RRAM), and phase-change random access memory (PCRAM). These non-volatile memories all achieve the characteristic of not losing information after the power is turned off through their unique physical principles.

[0032] The working principle of non-volatile memory: The main difference between FeRAM, MRAM, RRAM, and PCRAM lies in the different dielectric films connected to the drains of their transistors. FeRAM, MRAM, RRAM, and PCRAM transistors use ferroelectric, ferromagnetic, resistive switching, and phase-change materials for their drains, respectively. Therefore, when the transistor gate is turned on, the resistance between the source and drain is different, resulting in different currents flowing through the source and drain. This difference in drain-source current determines the stored information state. For example, EFlash and FeFET use different dielectric materials connected to the transistor gates: thin-film floating gate material and ferroelectric material, respectively. Therefore, their threshold voltages Vt are different. Given a different gate voltage, the different threshold voltages Vt result in different resistances between the source and drain, leading to different currents flowing through the source and drain, thus determining the stored information state.

[0033] This application provides an electronic device. This electronic device can be, for example, a consumer electronics product, a home electronics product, an in-vehicle electronics product, a financial terminal product, or a communication electronics product. Consumer electronics products include mobile phones, tablets, laptops, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop monitors, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, and drones. Home electronics products include smart door locks, televisions, remote controls, refrigerators, and rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners). In-vehicle electronics products include in-vehicle navigation systems and in-vehicle high-density digital video discs (DVDs). Financial terminal products include automated teller machines (ATMs) and self-service terminals. Communication electronics products include servers, storage devices, radar, base stations, and other communication equipment.

[0034] Example of an electronic device, such as Figure 1 As shown, electronic device 1 includes components such as a memory 11, a processor 12, an input device 13, and an output device 14. Those skilled in the art will understand that... Figure 1 The architecture of the electronic device 1 shown does not constitute a limitation on the electronic device 1, which may include, for example... Figure 1 The components shown may have more or fewer components, or may be combined as follows: Figure 1 Some of the components shown, or those that can be used with, for example Figure 1 The component arrangements shown are different.

[0035] The memory 11 is used to store software programs and modules. The memory 11 mainly includes a program storage area and a data storage area. The program storage area can store and back up the operating system and application programs required for at least one function (such as sound playback function, image playback function, etc.). The data storage area can store data created according to the use of electronic device 1 (such as audio data, image data, telephone book, etc.).

[0036] Processor 12 is the control center of the electronic device 1. It connects various parts of the electronic device 1 via various interfaces and lines. By running or executing software programs and / or modules stored in memory 11, and by calling data stored in memory 11, it performs various functions and processes data of the electronic device 1, thereby providing overall monitoring of the electronic device 1. Optionally, processor 12 may include one or more processing units. For example, processor 12 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), etc. Different processing units can be independent devices or integrated into one or more processors. For example, processor 12 may integrate an application processor and a modem processor, where the application processor mainly handles the operating system, user interface, and applications, while the modem processor mainly handles wireless communication. It is understood that the modem processor may not be integrated into processor 12. The application processor may, for example, be a central processing unit (CPU).

[0037] Input device 13 is used to receive input numerical or character information and to generate key signal inputs related to user settings and function control of the electronic device. For example, input device 13 may include a touchscreen and other input devices. A touchscreen, also known as a touch panel, collects touch operations performed by the user on or near the touchscreen (such as operations performed by the user using a finger, stylus, or any suitable object or accessory on or near the touchscreen) and drives corresponding connected devices according to a pre-set program.

[0038] Output device 14 is used to output signals corresponding to the input of input device 13 and the data stored in memory 11. For example, output device 14 outputs audio signals or video signals.

[0039] Ferroelectric memories, as a new type of memory, have become one of the mainstream memories due to their non-volatile data storage characteristics.

[0040] Continue to refer to Figure 1 The memory 11 includes a controller and a memory array or memory circuitry. The controller is used to control the reading and writing of the memory array and memory circuitry.

[0041] The storage array consists of multiple arrays of storage cells, and the storage density of the storage cells 200 directly affects the storage density of the storage array.

[0042] The information stored in memory 11 is usually in binary units, that is, stored in memory in the form of "logic 0" or "logic 1". This digital logic information is mapped in physical devices, and the corresponding physical states are high or low voltage, high or low resistance, high or low charge, etc.

[0043] Based on whether the stored signal still exists after the external power supply to the chip is removed, the memory 11 can be divided into volatile memory and non-volatile memory.

[0044] Due to its unique physical characteristics, non-volatile memory retains the state of previously written information when the power is turned off, ensuring that the information is not lost after power is off. Furthermore, the information stored in the non-volatile memory can be read when the chip's power supply is restored.

[0045] Since the state of information retention is closely related to the physical characteristics of memory 11, a common feature of various non-volatile memories is that after the number of times information is written exceeds a certain value, due to factors such as the aging of memory devices, the physical and electrical states corresponding to the two digital information states represented by logic 0 and logic 1 become too similar and difficult to distinguish stably. This upper limit of the number of write operations is called the "upper limit of write operations" of the non-volatile memory, also known as "write endurance".

[0046] like Figure 2a As shown, the horizontal axis represents the number of write operations (cycles), and the vertical axis represents the drain-source current (Ids). When the measured value of the drain-source current (Ids) is greater than the reference current, the first physical state (state 0) is read; when the measured value of the drain-source current (Ids) is less than the reference current, the second physical state (state 1) is read (note that the definitions of 0 and 1 can be reversed, as they are arbitrarily defined). For example, the two physical states can also be interchanged: when the measured value of the drain-source current (Ids) is less than the reference current, the first physical state (state 0) is read; when the measured value of the drain-source current (Ids) is greater than the reference current, the first physical state (state 1) is read. When the number of memory write operations is approximately 10 to (10^16), the curves of the drain-source current (Ids) for the two different physical states lie on the reference current line (…). Figure 2aAs shown by the dashed line, when the number of memory write operations falls within this range, the drain-source current value corresponding to the first physical state (state 0) is consistently greater than the reference current value, while the drain-source current value corresponding to the second physical state (state 1) is consistently less than the reference current value. The two different physical states can be clearly distinguished by the reference current value. However, as the number of memory write operations increases, due to the aging of the memory device, the drain-source currents corresponding to the first physical state (state 0) and the second physical state (state 1) become increasingly similar. At this point, the number of write operations for the non-volatile memory gradually reaches its upper limit, and the difference between the drain-source currents (Ids) corresponding to the two physical states becomes too small to be reliably distinguished.

[0047] like Figure 2b As shown, the horizontal axis represents the number of write operations (cycles), and the vertical axis represents the drain-source current (Ids). When the measured value of the drain-source current (Ids) is greater than the reference current value, the first physical state (state 0) is read; when the measured value of the drain-source current (Ids) is less than the reference current value, the second physical state (state 1) is read. When the number of memory write operations is less than a specific value C0, the drain-source current value corresponding to the first physical state (state 0) is greater than the reference current value, and the drain-source current value corresponding to the second physical state (state 1) is less than the reference current value. The two different physical states can be clearly distinguished by the reference current value. However, as the number of memory write operations increases, the drain-source current values ​​corresponding to both the first physical state (state 0) and the second physical state (state 1) are greater than the reference current value. Therefore, the two physical states (state 0 and state 1) cannot be distinguished by the reference current value.

[0048] In summary, in both scenarios described above, to distinguish between the two different states of information stored in the memory, a reference current value needs to be selected first. Then, the drain-source current of the memory device is measured, and the relative magnitudes of the measured current and the reference current value are compared. When the measured drain-source current is greater than the reference current, it is presumed to be one of the information states; otherwise, it is presumed to be the other information state. Alternatively, a reference voltage value or any measurable physical quantity in the field of electricity can be selected as the reference physical value.

[0049] Through comparison, we can see that Figure 2a The characteristic curve of the drain-source current Ids as a function of the number of memory write operations is better than that of the characteristic curve of the drain-source current Ids as a function of the number of memory write operations. Figure 2b The characteristic curve of the drain-source current Ids changing with the number of memory write operations.

[0050] Therefore, in some embodiments, when fabricating non-volatile memory, a material conforming to [specific requirements] is preferentially selected. Figure 2aMemory media materials with characteristic curves.

[0051] However, when selecting or adjusting the properties of non-volatile memory media, multiple dimensions should be considered. Besides the relationship between drain-source current (Ids) and the number of write operations, factors such as read / write speed, power consumption, data retention time, and manufacturing complexity must also be taken into account. The desired characteristics for various applications often cannot be simultaneously met, and sometimes even conflict. Therefore, it is necessary to prioritize the most critical characteristics, sacrificing other characteristics to satisfy the primary application scenario.

[0052] Therefore, in certain specific scenarios, it is necessary to prioritize using the method that satisfies [the requirement]. Figure 2b Memory media materials with specific characteristics. However, such as Figure 2b As shown, only when the number of memory write operations is less than a specific value C0 can the drain-source current value corresponding to the first physical state (state 0) be greater than the reference current value, and the drain-source current value corresponding to the second physical state (state 1) be less than the reference current value, thus allowing the two different physical states to be distinguished by the reference current value. When the number of memory write operations exceeds the specific value C0, the two different physical states cannot be distinguished by the reference current value. How to increase the size of this specific value C0, how to raise the upper limit of the number of memory write operations, and how to extend the lifespan of memory devices have become hot research issues for those skilled in the art.

[0053] Based on this, this application proposes a non-volatile memory that can dynamically adjust the reference current value, which effectively increases the upper limit of the number of write operations of the non-volatile memory and enhances the reliability of the non-volatile memory device.

[0054] like Figure 3 As shown, with the increase in the number of write operations to the non-volatile memory, the drain-source current values ​​corresponding to the first physical state (state 0) and the second physical state (state 1) both increase. When the drain-source current value corresponding to the second physical state (state 1) approaches the reference current value of level 1, the reference current value jumps to a higher level (e.g., through the dynamic adjustment proposed in this application)... Figure 3 (The reference current value for position 2 is shown). At this time, for the same number of write operations to the memory, the drain-source current value corresponding to the second physical state state 1 is less than the reference current value for position 2, and the drain-source current value corresponding to the first physical state state 0 is greater than the reference current value for position 2. The drain-source current values ​​corresponding to the second physical state state 1 and the first physical state state 0 can still be distinguished by the reference current value for position 2.

[0055] And so on, such as Figure 3As shown, when the number of write operations to the memory increases indefinitely, the difference between the drain-source currents corresponding to the two different physical states becomes negligible and cannot be stably distinguished by any reference current value, thus reaching the upper limit of the number of write operations for the device.

[0056] Based on the on-chip dynamic adjustment of reference current provided in the embodiments of this application, as the number of write operations of the memory increases, the reference current value can be continuously changed and increased. Therefore, the upper limit of the number of write operations of the memory is effectively increased, and the service life of the memory is greatly extended.

[0057] like Figure 4 The diagram illustrates a memory circuit structure proposed in this application, comprising multiple word lines and multiple bit lines. The product of the number of word lines and the number of bit lines represents the memory capacity. The horizontal axis represents word lines (WL), for example, WL0, WL1, WL2, WL3...WLn are all word lines. Each word line (WL) corresponds to a memory address. The number of word lines represents the memory depth, i.e., how many memory addresses the memory can hold. The vertical axis represents bit lines, including bit lines for the main memory array, bit lines for the counting array, and bit lines for the select array. Each bit line intersects with a word line, and each word line and each bit line together define a memory bit cell. Multiple memory bit cells exist within the same memory address.

[0058] The main memory array accepts and stores externally written data. The bit lines BL of the main memory array include BL0, BL1, ..., BLn; typically, the number of bit lines allocated to the main memory array is an integer power of 2, for example, the main memory array can have 16, 32, ..., 128 bit lines.

[0059] When writing data to the memory, the data is written sequentially according to the memory address represented by the word line WL. Data can be written to all bit cells within the same memory address in the main memory array, or it can be written to a subset of bit cells within the same memory address in the main memory array.

[0060] The counting array is configured to count the number of write operations to the memory address corresponding to a single word line. Each time data is written to one or more memory bits within the memory address corresponding to a single word line, the counting array counts once. The bit lines CL of the counting array include CL0, CL1, ..., CLn; assuming 4 to 6 bit lines are allocated to the counting array, the maximum counts are 16, 32, and 64 respectively. Whenever the counting array reaches its maximum count, the information in the counting array is cleared, and counting restarts. A re-evaluation and adjustment of the reference current level is also required.

[0061] When the drain-source current Ids corresponding to both physical states increases with the accumulation of write operations, if the physical state with the smaller drain-source current Ids is set to 0, the counting array is first cleared to zero, and then the reference current value and the smaller drain-source current Ids value are compared to determine whether the reference current level needs to be readjusted. If it is found that the smaller drain-source current Ids value is also greater than the reference current value, the reference current level is readjusted. If the physical state with the smaller drain-source current Ids is set to 1, the reference current value and the smaller drain-source current Ids value are first compared to determine whether the reference current level needs to be readjusted, and then the counting array is cleared to zero.

[0062] When the drain-source current Ids corresponding to both physical states decreases with the accumulation of write operations, if the physical state with the smaller drain-source current Ids is set to 0, the reference current value is first compared with the smaller drain-source current Ids value to determine whether the reference current level needs to be readjusted, and then the counter array is cleared to zero. If the physical state with the smaller drain-source current Ids is set to 1, the counter array is first cleared to zero, and then the reference current value is compared with the smaller drain-source current Ids value to determine whether the reference current level needs to be readjusted.

[0063] The gear selection array is configured to store gear information for reference current. Each word line corresponds to a gear information for a reference current. The bit lines SL of the gear selection array include SL0, SL1...SLn. Assuming three bit lines are allocated to the gear selection array, it can store eight different gears. Each gear corresponds to a reference current value, and the correspondence between the gear selection array's gear information and the reference current value is stored in a gear lookup table. A portion of the memory's word lines are used to store the gear lookup table information.

[0064] like Figure 6The diagram shows the logic flow of the counting array and the gear selection array working together, where Iref is the reference current and σ is the current redundancy. At the start of the process, the counting array information is cleared, and the main memory array writes data. Each time data is written to the main memory array, the counting array counts once, until the count reaches its upper limit. When the count reaches its upper limit, the current information of the least significant bit line CL0 is read, and it is determined whether it is greater than the reference current Iref-σ. If the current information of the least significant bit line CL0 is greater than the reference current Iref-σ, the information in the gear selection array is incremented by 1, i.e., it jumps to a higher reference current gear, and the counting array information is cleared. If the current information of the least significant bit line CL0 is still less than Iref-σ, the information in the gear selection array remains unchanged, and the counting array information is cleared.

[0065] The number of bit lines allocated to different arrays of the memory can be flexibly allocated according to the specific use case, and the embodiments of this application do not limit it.

[0066] like Figure 4 As shown, it can also be seen that the same word line WL intersects with the bit line BL of the main memory array, the bit line CL of the counting array, and the bit line SL of the gear selection array. In other words, for the same memory address, there is the same information from the gear selection array and the counting array.

[0067] Since the information from the gear selection array can be used to index the corresponding reference current value in the gear lookup table, and the information from the counting array represents the number of write operations to the memory address corresponding to the word line WL, all bit cells in the main memory array within the same memory address are compared with the same reference current value, and all bit cells within the same memory address have the same number of write operations.

[0068] Similarly, different word lines (WL) correspond to different memory addresses, and the bit cells within different addresses have different write operation counts, which vary considerably. The reference current values ​​corresponding to the bit cells within different memory addresses are also different.

[0069] Before the chip is tested at the factory, the reference current information and current redundancy information corresponding to each range are written into the range lookup table based on the test results for subsequent lookup.

[0070] The memory also includes a sensitive amplifier SA, which is used to compare a reference current value with the current read from the main memory array to determine the stored information data.

[0071] First, select the memory address of the main memory array to be read, i.e., select word line WL, and read the information data in the main memory array. Then, find the bit line SL of the gear selection array that intersects with this word line. The gear information stored in the gear selection array is determined by the bit line SL. Based on this gear information, find the corresponding reference current value in the gear lookup table, and compare the reference current with the information data read from the main memory array. It should be noted that when the word line WL to be read is selected, the channel of that word line WL will be opened, while the channels of the other word lines WL will remain closed. The information data of all main memory array bit cells that intersect with this word line WL will be read.

[0072] like Figure 4 As shown, one end of the sensitive amplifier SA receives a reference current value (which can also be voltage information, then converted into current information through a resistor), and the other end receives information data read from the main memory array. For ease of description, this embodiment uses eight different levels of reference current values ​​as an example. Of course, in other embodiments, the number of reference current values ​​is not limited to eight, and can be any other integer number of levels.

[0073] like Figure 4 As shown, each of the multiple sensitive amplifiers SA is coupled to each of the multiple bit lines. These multiple bit lines include the bit line BL of the main memory array, the bit line CL of the counting array, and the bit line SL of the level selection array.

[0074] like Figure 5 As shown, the input terminals of the sensitive amplifiers SA corresponding to different arrays are different. The first input terminal of the sensitive amplifier SA corresponding to the gear selection array is coupled to the bit line SL of the gear selection array, and the second input terminal is coupled to the reference ground voltage terminal. Therefore, the information output by the sensitive amplifier SA is the information of the bit line SL of the gear selection array. For example, when there are 3 bit lines SL allocated to the gear selection array, 3 sensitive amplifiers SA are assigned to be coupled to the bit lines SL of the gear selection array. The first input terminals of the 3 sensitive amplifiers SA are coupled to the bit lines SL0, SL1, and SL2 of the gear selection array, respectively. The output terminals of the multiple sensitive amplifiers SA coupled to the bit lines SL of the gear selection array are all coupled to the bit selection terminal of the data selector MUX8. The bit lines SL of the gear selection array provide gear information to the data selector MUX8; the data input terminal of the data selector MUX8 is coupled to the gear lookup table, receiving information input from the gear lookup table. Therefore, based on the gear position information received by the bit selection terminal, the data selector MUX8 retrieves the reference current value corresponding to the gear position information from the gear position lookup table and uses it as the output terminal of the data selector MUX8.

[0075] The sensitive amplifier SA corresponding to the main memory array has its first input terminal coupled to the bit line BL of the main memory array to receive the information data read from the main memory array; the second input terminal of the sensitive amplifier SA is coupled to the output terminal of the data selector MUX8 to receive the reference current value retrieved by the data selector MUX8 from the gear lookup table, and finally compares the retrieved reference current value with the information data read from the main memory array.

[0076] In the above embodiment, both the bit line CL of the counting array and the bit line BL of the main storage array are coupled to the sensitive amplifier SA. The reference current value is compared with the information data read from the array through the sensitive amplifier SA. The two input terminals of the sensitive amplifier SA compare the magnitudes of the analog signals.

[0077] In other embodiments, such as Figure 7 As shown, one bit line CL0 of the counting array is coupled to a comparison readout circuit. The comparison readout circuit includes an analog-to-digital converter (ADC) and a comparator. First, the analog current value from the bit line CL0 of the counting array is converted into a digital signal by the ADC. Then, the output of the ADC is coupled to the first input of the comparator, and the second input of the comparator receives the reference current value information, and the two are compared. Compared with the above embodiment, the embodiment of this application replaces the sensitive comparator SA corresponding to the counting array with a combination of an ADC and a comparator. Since the sum of the circuit areas of the ADC and the comparator is still smaller than the circuit area of ​​the sensitive comparator SA, the design scheme of this application saves circuit area costs.

[0078] In other embodiments, the information data from all bit lines CL of the counting array can be read out, and then the average value of the information data from all bit lines CL can be calculated. For example, if the counting array is assigned 6 bit lines, then the average value of the information data is (CL0+CL1+CL2+CL3+CL4+CL5) / 6. The average value of all bit lines CL of the counting array is then compared with a reference current value to determine whether the reference current level needs to be adjusted.

[0079] In some embodiments, the main memory array, counting array, gear selection array, and gear lookup table unit can be a single, integrated memory array in chip manufacturing. In certain special application scenarios, to facilitate a more regular chip layout and easier metal interconnection, these four memory sections can also be independent arrays in chip manufacturing.

[0080] The design scheme proposed in this application not only avoids the drawbacks of parameter drift caused by aging of core materials, but also effectively increases the upper limit of the number of write operations in the memory. This improves the consistency of the entire memory bit cell, increases yield, and reduces bit error rate.

[0081] Furthermore, the reference current is dynamically adjusted internally within the memory, eliminating the need for external software operation. It also eliminates the need for external non-volatile memory and other on-chip non-volatile memory, saving on area costs. Additionally, it eliminates the need to store the number of memory write operations, reducing the capacity of the counting array and the level selection array.

[0082] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0083] Those skilled in the art will recognize that the devices and method steps described in connection with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0084] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the electronic devices and display devices described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0085] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0086] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0087] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A nonvolatile memory, comprising: include: A primary memory array for writing and storing data, the primary memory array comprising multiple different word lines and multiple different bit lines, the word lines and the bit lines intersecting; Each word line in the plurality of word lines corresponds to a memory address, and a single memory address includes a plurality of memory bit units. Each word line in the plurality of word lines and each bit line in the plurality of bit lines together determine one memory bit unit. The counting array is configured to count the number of write operations for a memory address corresponding to a single word line, wherein the counting array counts once each time data is written to one or more memory bit cells within the memory address corresponding to the single word line; The gear selection array is configured to store gear information of the reference current; each word line corresponds to a gear information of the reference current. The gear lookup table is configured to store the corresponding reference current information based on the gear selection array gear information.

2. The nonvolatile memory of claim 1, wherein, A portion of the word lines of the memory are used to store information about the gear lookup table.

3. The nonvolatile memory according to any one of claims 1 to 2, wherein, The reference current information corresponding to each gear in the gear selection array is written into the gear lookup table unit during chip factory testing.

4. The nonvolatile memory according to any one of claims 1 to 2, wherein, The gear lookup table also stores the reference current redundancy information.

5. The nonvolatile memory according to any one of claims 1 to 2, wherein, Within the main memory array, the same word line corresponds to the same reference current.

6. The nonvolatile memory according to any one of claims 1 to 2, wherein The memory also includes a sensitive amplifier for comparing the reference current value with the data read from the main memory array.

7. The nonvolatile memory of claim 6, wherein, One end of the sensitive amplifier is coupled to the reference current value, and the other end is coupled to the current value data read from the main memory array.

8. The nonvolatile memory according to any one of claims 1 to 2, wherein, The memory includes multiple sensitive amplifiers and multiple bit lines, each of the multiple sensitive amplifiers being coupled to each of the multiple bit lines.

9. A control method of a nonvolatile memory, characterized by, include: Write the required data to the main memory array; wherein the main memory array includes multiple different word lines and multiple different bit lines, the word lines and the bit lines intersect; each of the multiple word lines corresponds to a memory address, a single memory address includes multiple memory bit units, and each of the multiple word lines and each of the multiple bit lines jointly defines one memory bit unit; The counting array is used to count the number of times data is written to the memory address of a single word line. Each time data is written to one or more memory bit cells in the memory address corresponding to a single word line, the counting array counts once. Read the data of the selected word line, select the reference current range in the range selection array according to the word line, and find the corresponding reference current in the range lookup table according to the range. The gear selection array is used to store the gear information of the reference current; each word line corresponds to the gear information of the reference current; the gear lookup table is used to store the corresponding reference current information according to the gear information of the gear selection array.

10. An electronic device, comprising: include: The circuit board and the non-volatile memory according to any one of claims 1-8, wherein the circuit board and the non-volatile memory are coupled together.

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