A memory write control circuit, a write circuit and a memory
By setting up multiple write command channels and signal set modules in the write control circuit of the MRAM device, the problem that the width of the write enable signal cannot meet the DDR4 protocol is solved, and efficient write operation under the DDR4 protocol is realized.
CN117219135BActive Publication Date: 2026-07-21ZHEJIANG HIKSTOR TECHOGY CO LTD
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Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ZHEJIANG HIKSTOR TECHOGY CO LTD
- Filing Date
- 2022-06-02
- Publication Date
- 2026-07-21
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Figure CN117219135B_ABST
Abstract
The application provides a memory write control circuit, a write circuit and a memory. The memory write control circuit comprises a channel selector, a plurality of write command channels connected with the channel selector, and a signal collection module connected with the plurality of write command channels. The channel selector controls each write command channel in the plurality of write command channels to be sequentially opened and closed, so that the write command channel in the opened state receives a write command signal and an address signal corresponding to the write command signal. Each write command channel in the plurality of write command channels is used for generating a write enable signal corresponding to the write command signal in response to the received write command signal. The signal collection module is used for collecting and concurrently outputting the write enable signals generated by the plurality of write command channels. The application can meet the write speed requirement, does not reduce the width of the write enable signal, and has the advantages of simple implementation, wide application range and strong scalability.
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