Three-dimensional stacked chip and timing control method

Abstract

This application discloses a three-dimensional stacked chip and a timing control method. The three-dimensional stacked chip includes a memory chip, a logic chip, and a first timing control circuit. The logic chip and the memory chip are stacked and packaged. The target output terminal within the logic chip is connected to a memory array module within the memory chip via the first timing control circuit. The timing control circuit controls the transmission timing of multiple first target signals output from the target output terminal to the memory array module based on a received clock signal, thereby satisfying the interface timing conditions of the memory array module for the aforementioned multiple first target signals and ensuring the normal operation of the three-dimensional stacked chip.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a three-dimensional stacked chip and timing control method. Background Technology

[0002] Chip stacking technology removes the limitations of package pins for large-scale pin interconnects between designs using different processes, thus increasing bandwidth. Parallel DRAM (Dynamic Random Access Memory) chips and logic chips are connected using 3D technologies such as TSV (Through Silicon Via) before being packaged together. This allows the logic chip to access multiple DRAM banks in parallel, significantly increasing access efficiency. However, this DRAM differs from standard DRAM chips. The logic chip accesses the memory array directly, and the timing of the memory array's interface cannot meet the asynchronous timing requirements of the parallel DRAM memory array. For example, the timing of the address enable signal and the address signal must be matched, and similarly, the timing of the data signal and the data enable signal must also meet certain timing requirements. Summary of the Invention

[0003] This application provides a three-dimensional stacked chip and timing control method, which can effectively improve the technical problem that the timing requirements of the above-mentioned memory array cannot be met.

[0004] In a first aspect, embodiments of this application provide a three-dimensional stacked chip, comprising:

[0005] Logic chip;

[0006] The memory chip is stacked and packaged with the logic chip; and

[0007] A first timing control circuit is used to control the transmission timing of multiple first target signals output by the target output to the storage array module based on the received clock signal, so as to meet the interface timing conditions of the storage array module for the multiple first target signals.

[0008] Furthermore, the first timing control circuit includes:

[0009] A first sampling sub-circuit is disposed in the logic chip. The input terminal of the first sampling sub-circuit is connected to the target output terminal and is used to synchronously trigger multiple first target signals output from the target output terminal to be output from the logic chip under the control of the clock signal.

[0010] A second sampling sub-circuit is disposed on the memory chip. The input terminal of the second sampling sub-circuit is connected to the output terminal of the first sampling sub-circuit, and the output terminal is connected to the memory array module. It is used to synchronously trigger multiple first target signals output from the logic chip to be received by the memory array module under the control of the clock signal.

[0011] The three-dimensional stacked chip also includes a clock interface for providing the clock signal, and the clock terminals of the first sampling sub-circuit and the second sampling sub-circuit are both connected to the clock interface.

[0012] Furthermore, the first sampling sub-circuit includes: a plurality of first flip-flops configured in one-to-one correspondence with the multiple first target signals.

[0013] The input terminals of the plurality of first flip-flops are connected to the target output terminal, the clock terminals are all connected to the clock interface, and the output terminals are connected to the second sampling sub-circuit.

[0014] The plurality of first triggers are used to synchronously trigger the multiple first target signals output from the target output terminal to be output from the logic chip at the first sampling time point based on the clock signal.

[0015] Furthermore, the second sampling sub-circuit includes: a plurality of second flip-flops configured in a one-to-one correspondence with the plurality of first flip-flops.

[0016] The inputs of the plurality of second flip-flops are connected to the outputs of their respective first flip-flops, the clock terminals are all connected to the clock interface, and the output terminals are connected to the storage array module.

[0017] The plurality of second triggers are used to latch their respective received first target signals, and based on the clock signal, synchronously trigger the output of the latched first target signals to the storage array module at the second sampling time point, wherein the second sampling time point is later than the first sampling time point.

[0018] Furthermore, the arrival times of the multiple first target signals at the corresponding second triggers are all between the first sampling time point and the second sampling time point, and the effective duration of the multiple first target signals is greater than or equal to the time interval between the first sampling time point and the second sampling time point.

[0019] Furthermore, the time interval between the first sampling time point and the second sampling time point is one clock cycle of the clock signal.

[0020] Furthermore, the first timing control circuit further includes a delay sub-circuit, disposed in the memory chip.

[0021] The output of the second sampling sub-circuit is connected to the storage array module through the delay sub-circuit. The delay sub-circuit is used to adjust the relative time relationship of each first target signal output from the second sampling sub-circuit to the storage array module so as to meet the interface timing conditions.

[0022] Furthermore, the multiple first target signals include an address enable signal and an address signal, or the multiple first target signals include a write data enable signal and a write data signal.

[0023] Furthermore, the aforementioned three-dimensional stacked chip also includes: a second timing control circuit.

[0024] The target input terminal in the logic chip is connected to the storage array module in the storage chip through the second timing control circuit. The second timing control circuit is used to control the transmission timing of the multiple second target signals output by the storage array module to the target input terminal based on the clock signal, so as to meet the interface timing conditions of the logic chip for the multiple second target signals.

[0025] Secondly, embodiments of this application provide a timing control method applied to a three-dimensional stacked chip, wherein the three-dimensional stacked chip includes stacked logic chips and memory chips, the logic chip has a target output terminal, and the memory chip includes a memory array module, the method comprising:

[0026] Obtain the clock signal;

[0027] Based on the clock signal, the transmission timing of the multiple first target signals output by the target output terminal to the storage array module is controlled to meet the interface timing conditions of the storage array module for the multiple first target signals.

[0028] Further, the step of controlling the transmission timing of the multiple first target signals output from the target output terminal to the storage array module based on the clock signal includes:

[0029] Based on the clock signal, at the first sampling time point, the multiple first target signals output from the target output terminal are synchronously triggered to be output from the logic chip.

[0030] The multiple first target signals are latched respectively, and based on the clock signal, the latched first target signals are synchronously triggered to be output to the storage array module at the second sampling time point, where the second sampling time point is later than the first sampling time point.

[0031] Furthermore, the step of synchronously triggering the latching of each of the first target signals at the second sampling time point and outputting them to the storage array module includes:

[0032] The latched first target signal outputs are triggered synchronously at the second sampling time point;

[0033] According to the preset delay rules, the output first target signals are delayed respectively to adjust the relative time relationship of the first target signals arriving at the storage array module, so as to meet the interface timing conditions.

[0034] Furthermore, the logic chip also includes a target input terminal, and the method further includes:

[0035] Based on the clock signal, the transmission timing of the multiple second target signals output by the storage array module to the target input terminal is controlled to meet the interface timing conditions of the logic chip for the multiple second target signals.

[0036] In the three-dimensional stacked chip provided in this application embodiment, logic chips and memory chips are stacked and packaged. By adding a first timing control circuit between the target output terminal in the logic chip and the memory array module in the memory chip, the first timing control circuit is used to control the transmission timing of multiple first target signals output from the target output terminal to the memory array module based on the received clock signal, so as to meet the interface timing conditions of the memory array module for the aforementioned multiple first target signals. This can meet the timing requirements of the memory array for these first target signals with timing matching relationships, thereby ensuring the normal operation of the three-dimensional stacked chip, and is easy to implement, eliminating the need to design a dedicated physical interface hard core on the logic chip, which helps to reduce the design difficulty of the logic chip.

[0037] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, specific embodiments of this application are given below. Attached Figure Description

[0038] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0039] Figure 1 An exemplary conventional DRAM block diagram is shown;

[0040] Figure 2 This specification illustrates a packaging diagram of a three-dimensional stacked chip according to an embodiment. Figure 1 ;

[0041] Figure 3 This specification illustrates a schematic diagram of a two-layer chip structure as described in an embodiment. Figure 1 ;

[0042] Figure 4 This specification illustrates a data writing schematic diagram in one embodiment.

[0043] Figure 5 A schematic diagram of a three-layer chip structure according to an embodiment of this specification is shown;

[0044] Figure 6 This specification illustrates a schematic diagram of a two-layer chip structure as described in an embodiment. Figure 2 ;

[0045] Figure 7 A flowchart of a data processing method for a three-dimensional stacked chip according to an embodiment of this specification is shown;

[0046] Figure 8 This specification illustrates a packaging diagram of a three-dimensional stacked chip in an embodiment. Figure 2 ;

[0047] Figure 9 An exemplary timing diagram of the address signal and the address enable signal is shown;

[0048] Figure 10 A circuit diagram of the first timing control circuit in an embodiment of this specification is shown;

[0049] Figure 11 An exemplary transmission timing diagram of the address enable signal and address signal in an embodiment of this specification is shown;

[0050] Figure 12 A flowchart of the timing control method in an embodiment of this specification is shown. Detailed Implementation

[0051] Figure 1 This diagram illustrates an 8-bit data interface and a traditional DRAM block diagram with an internal 8x prefetch capability. The entire DRAM consists of 8 memory array modules (banks), numbered bank0 to bank7. The address and control lines of banks0 to bank7 are all connected to the same decoding and address resolution module located within the DRAM, and the data lines are all connected to the same parallel-to-serial conversion module located within the DRAM. Figure 1In the diagram, rwd0~rwd7 represent the data of bank0~bank7, illustrated in 64-bit format. Taking a write operation as an example, the decoding and address resolution module first receives the externally sent command and address information, including the bank address information. Decoding determines the bank targeted for this write operation, generating control signals and address information for that bank. Then, the parallel-to-serial conversion module receives the data signal dqs / dq<7:0> to be written, performs serial-to-parallel conversion, converting it into a 64-bit data signal rwd<63:0>, and sends it to the bank to complete the data write. In other words, only one bank can be read or written at a time.

[0052] Furthermore, due to packaging and hardware system limitations, the DRAM interface data width cannot be very large. This results in the internal memory array interface width being much larger than the DRAM interface width. Consequently, after parallel-to-serial conversion, the interface speed is much higher than the internal memory array's storage speed. For example, in the 8x prefetch structure described above, if the external interface data width is 8 bits, the internal memory array width is 64 bits. If the memory array speed is 200 Mbps, the interface speed needs to reach 1600 Mbps. Therefore, this is detrimental to improving DRAM data access bandwidth.

[0053] In view of this, the embodiments of this specification provide a three-dimensional stacked chip that eliminates the decoding and address resolution modules and serial-to-parallel conversion modules found in traditional DRAM. By setting N memory control modules at the logic wafer layer, each memory control module is directly connected to k memory array modules via a wafer-level interlayer interconnection structure before chip packaging. Here, k is an integer greater than or equal to 1 and less than M. This allows different memory control modules to control their respective connected memory array modules to perform data write or read operations. This eliminates the limitations of packaging and hardware system on the DRAM interface bit width, allowing direct output of the DRAM's memory array interface signals. This enables the logic wafer to directly read and write multiple memory array modules in parallel, effectively improving the DRAM's data access bandwidth and thus enhancing the chip's data processing speed.

[0054] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. It should be noted that "logic wafer layer" and "logic chip" described herein should be understood as having the same structure, and "memory wafer layer" and "memory chip" should also be understood as having the same structure. Small wafer pieces obtained after dicing a wafer are called dies, and dies are packaged to form chips.

[0055] Example 1

[0056] like Figure 2 As shown in the figure, this embodiment of the specification provides a three-dimensional stacked chip 100, which may be, for example, a System on Chip (SOC) chip. The three-dimensional stacked chip 100 may include a storage wafer layer 102 and a logic wafer layer 101 stacked on top of the storage wafer layer 102. It should be noted that the number of storage wafers and logic wafers in the three-dimensional stacked chip 100 shown in the accompanying drawings is only illustrative and not intended as a limitation. In specific implementations, the number can be set according to actual needs.

[0057] The storage wafer layer 102 includes one or more stacked storage wafers for expanding storage space. M storage array modules 121 are distributed within the storage wafer layer 102, where M is an integer greater than or equal to 2. In specific implementations, the number of storage wafer layers and the number of storage array modules 121 are set according to the actual application scenario's requirements for chip storage capacity. For example, each storage wafer may include 4, 8, or 16 storage array modules 121.

[0058] Correspondingly, N memory control modules 111 are provided in the logic wafer layer 101, where N is an integer greater than or equal to 2 and less than or equal to M. Each memory control module 111 is connected to k memory array modules 121 through a wafer-level interlayer interconnection structure 103, and is used to control the data write or read operations of its respective connected memory array modules 121. Here, k is an integer greater than or equal to 1 and less than M. Each memory array module 121 is connected to a memory control module 111, and different memory control modules 111 are connected to different memory array modules 121. In one specific embodiment, one memory control module 111 can be connected to one memory array module 121, that is, the memory control module 111 and the memory array module 121 are connected in a one-to-one correspondence; in another embodiment, one memory control module 111 can be connected to multiple memory array modules 121, for example, one memory control module 111 is connected to two memory array modules 121, and another memory control module 111 is connected to three memory array modules 121. During data read and write operations, multiple storage control modules 111 can simultaneously control the corresponding connected storage array modules 121 to perform data read and write operations. In this way, the logic wafer can read and write one of the storage array modules 121 connected to different storage control modules 111 in parallel. That is, it can achieve parallel read and write access to at least N storage array modules 121 in the storage wafer layer 102 without being limited by packaging and hardware system, effectively improving the data access bandwidth of DRAM, thereby helping to improve the data processing speed of the chip.

[0059] In specific implementation, the exact number of storage control modules 111 and the connected storage array modules 121 are determined based on the number of storage array modules 121 in the storage wafer layer 102 and the actual control logic. For example, k can be 1, and N equals M, meaning one storage control module 111 can control one storage array module 121. This allows the logic wafer to read and write all storage array modules 121 of the storage wafer in parallel, thus greatly increasing bandwidth. Again, taking a storage wafer speed of 200Mbps and a data interface width of 64 bits as an example... Figure 3 In the 8-bank example shown, the access bandwidth can reach 200Mbps × 64bit × 8banks = 100Gbps, which is 8 times that of the traditional solution. Alternatively, the M storage array modules 121 distributed in the storage wafer layer 102 can be divided into multiple groups, with at least one group containing multiple storage array modules 121. One storage control module 111 controls one group of storage array modules 121. In this case, k is the number of storage array modules 121 in the corresponding group, and N is equal to the number of groups.

[0060] Understandably, in a 3DIC (three-dimensional integrated circuit) chip, memory wafers (DRAM die) and logic wafers (logic die) can be connected together and packaged using wafer-level interconnection techniques such as hybrid bonding, RDL (redistribution layer), and TSV (through silicon via) technology to form a three-dimensional stacked chip 100.

[0061] Therefore, each memory control module 111 can be directly connected to the corresponding k memory array modules 121 through the wafer-level interlayer interconnection structure 103. This allows the DRAM interface bit width to be no longer limited by packaging and hardware system, and the interface signals of the memory array modules 121 can be directly output. The logic wafer can directly control multiple memory array modules 121 to read and write simultaneously, effectively improving the data access bandwidth of DRAM.

[0062] From a structural perspective, the interlayer interconnect structure 103 can be implemented using applicable wafer-level interconnect technologies, specifically determined based on the wiring requirements between the actual storage control module 111 and the storage array module 121, and is not limited here. For example, the interlayer interconnect structure 103 may include one or more combinations of hybrid bonding structures, wiring structures in the RDL layer, and through-silicon via structures.

[0063] From a functional perspective, the interlayer connection structure 103 serves as a signal transmission channel between the storage control module 111 and the storage array module 121, and is used to transmit the signals required for data writing or reading operations on the storage array module 121.

[0064] For example, the inter-layer interconnect structure 103 may include a data channel and a control channel. The data channel is used to transmit data signals for writing or reading, and its bit width can be determined based on the data bit width that the memory array module 121 can write or read at one time and the actual data bit width of the logic wafer. Figure 3 In this example, 64 bits are used. rwd0<63:0>~rwd7<63:0> represent the data signals of bank0 to bank7. In practice, the width can also be 128 or 256, etc.

[0065] The control channel is used to transmit control signals for writing or reading control data. For example, the control signals transmitted in the control channel may include command signals and address signals.

[0066] Command signals may include, but are not limited to: row operation enable signals, column operation enable signals, and write data control signals, the specifics of which can be determined according to actual needs. The row operation enable signal, also known as the bank row valid indicator, indicates that the row address can be captured for decoding. The column operation enable signal, also known as the bank column write / read address control signal, indicates that the column address can be captured for decoding. The write data control signal indicates that data should be written to the corresponding column.

[0067] Address signals can include row address signals and column address signals. The address bit width is determined according to the row and column structure of the DRAM.

[0068] It should be noted that, Figure 3 Other control and status signals in the DRAM represent control signals required for DRAM operation, such as powerdown control and bank_fail. For specific signal types and the structure of other control circuits, please refer to relevant DRAM technologies, which will not be detailed here.

[0069] In an alternative embodiment, the logic wafer layer 101 may also include a processing module 110. Each storage control module 111 is connected to the processing module 110. The processing module 110 is used to determine which storage array modules 121 in the storage wafer layer 102 will be read or written to, and sends data operation information to the storage control modules connected to the storage array modules to be operated. The data operation information may include commands and addresses; if the data operation is a write operation, it may also include the data to be written. Each storage control module 111 includes a decoding and parsing module. The decoding and parsing module decodes and analyzes the commands and addresses in the data operation information to perform data write or read operations on the storage array modules to be operated.

[0070] For example, processing module 110 can receive data write commands and write data, and determine the write address of the write data based on the space occupied by the write data and the storage space of storage array module 121, that is, determine the storage array module to be operated. In response to the write data occupying less than or equal to the storage space of storage array module 121, a storage array module 121 can be determined as the storage array module to be operated.

[0071] If the space occupied by the data to be written exceeds the storage space of the storage array module 121, the processing module 110 needs to determine multiple storage array modules 121 that match the occupied space as storage array modules to be operated. The specific number is determined based on the space occupied by the data to be written and the storage space of the storage array modules 121. For example, if the storage array modules to be operated include a first storage array module 121a and a second storage array module 121b, then the data to be written will be stored in the first storage array module 121a and the second storage array module 121b. The first storage array module 121a and the second storage array module 121b are controlled by different storage control modules 111. It should be noted that the first storage array module 121a and the second storage array module 121b can be located in the same layer of the storage wafer, or they can be located in different layers of the storage wafer.

[0072] For example, such as Figure 4 As shown, the storage control module 111 controlling the first storage array module 121a is the first storage control module 111a, and the storage control module 111 controlling the second storage array module 121b is the second storage control module 111b. The processing module 110 can send a first data write information to the first storage control module 111a and a second data write information to the second storage control module 111b, thereby storing the write data in the first storage array module 121a and the second storage array module 121b in parallel through the first storage control module 111a and the second storage control module 111b.

[0073] Accordingly, when reading data, the processing module 110 can send first data reading information to the first storage control module 111a and second data reading information to the second storage control module 111b according to the data reading address, so that data can be read from the first storage array module 121a and the second storage array module 121b in parallel through the first storage control module 111a and the second storage control module 111b.

[0074] For example, taking writing data as an example, in Figure 3In the example shown, it is assumed that the processing module 110 determines bank0 and bank1 as the storage array modules to be operated based on the space occupied by the written data and the storage space of the storage array module 121, and then uses bank0_ctrl and bank1_ctrl respectively to store a part of the written data in bank0 and the other part of the written data in bank1 in parallel. Specifically, processing module 110 sends a first data write information to bank0_ctrl and a second data write information to bank1_ctrl, respectively. This information includes a write command, a write address, and data information. The decoding and parsing module in bank0_ctrl decodes and analyzes the write command and write address in the first data write information. Then, bank0_ctrl sends bank activation information to bank0. After bank0 is activated, it sends the write command, write address, and data information to bank0 through the data channel and control channel, respectively, to complete the data writing to bank0. The decoding and parsing module in bank1_ctrl decodes and analyzes the write command and write address in the second data write information. Then, bank1_ctrl sends bank activation information to bank1. After bank1 is activated, it sends the write command, write address, and data information to bank1 through the data channel and control channel, respectively, to complete the data writing to bank1.

[0075] Furthermore, when reading the data written above, the processing module 110 can send a first data reading information to bank0_ctrl and a second data reading information to bank1_ctrl respectively, and read data from bank0 and bank1 in parallel through bank0_ctrl and bank1_ctrl.

[0076] In practice, depending on the architecture of the actual three-dimensional stacked chip 100 and the bandwidth requirements, the connection relationship between the storage control module 111 in the logic wafer layer 101 and the storage array module 121 in the storage wafer layer 102 can be configured in various ways. Several examples are listed below for illustration.

[0077] The first type involves a three-dimensional stacked chip 100, which is a two-layer wafer structure comprising a logic wafer and a memory wafer, where k=1. Each memory control module 111 in the logic wafer is directly connected to the data and control bus of a memory array module 121 in the memory wafer via a wafer-level inter-layer interconnection structure 103. The data and control buses of different memory array modules 121 are independent of each other. The data and control bus includes data signal lines and control signal lines. Data signal lines can be used to transmit data signals, such as rwd0<63:0>, and control signal lines include command signal lines and address signal lines, which can be used to transmit the aforementioned command and address signals. In this way, the M memory array modules 121 in the memory wafer can simultaneously perform read and write access.

[0078] For example, such as Figure 3 As shown, the three-dimensional stacked chip chip0 includes a logic die and a DRAM die stacked together. Assume the DRAM die includes eight banks, denoted as bank0 to bank7. Then, the logic die includes eight memory control modules 111, denoted as bank0_ctrl to bank7_ctrl. bank0_ctrl is connected to bank0 via an inter-layer connection structure 103, bank1_ctrl is connected to bank1 via the same structure, and so on, with bank7_ctrl connected to bank7 via the same structure.

[0079] The second type involves a storage wafer layer comprising multiple storage wafers, with M storage array modules 121 distributed across different storage wafers, k=1. Each storage control module 111 in the logic wafer is directly connected to the data and control buses of each storage array module 121 in the storage wafer layer via a wafer-level inter-layer interconnection structure 103. The data and control buses of different storage array modules 121 are independent of each other. This allows all storage array modules 121 in different storage wafers to perform read and write access simultaneously.

[0080] For example, such as Figure 5As shown, the three-dimensional stacked chip chip1 has a three-layer structure including one logic die and two DRAM dies, namely DRAM die0 and DRAM die1. DRAM die0 includes 8 banks, denoted as bank00 to bank07, and DRAM die1 also includes 8 banks, denoted as bank10 to bank17. Correspondingly, the logic die is provided with 16 memory control modules 111, denoted as bank0_ctrl to bank15_ctrl. Among them, bank0_ctrl to bank7_ctrl are connected one-to-one with bank00 to bank07 in DRAM die0 through inter-layer connection structure, and bank8_ctrl to bank15_ctrl are connected one-to-one with bank10 to bank17 in DRAM die1 through inter-layer connection structure 103 (not shown in the figure), so that banks00 to bank07 and banks10 to bank17 can be read and written simultaneously.

[0081] The third type involves k being an integer greater than or equal to 2 and less than M, where each storage control module 111 connects to k storage array modules 121 distributed across the same storage wafer. In this case, the storage wafer also includes control logic modules corresponding one-to-one with the storage control modules 111. The storage control modules 111 are connected to the control logic modules via a wafer-level inter-layer interconnection structure 103, and the control logic modules are directly connected to the data and control buses of the aforementioned k storage array modules 121. The control logic modules are used to: time-division control the k connected storage array modules 121 to perform data write or read operations based on the data write or read signals sent by the storage control module 111.

[0082] The specific control logic of the control logic module can be set according to actual needs. As one implementation, chip select control information can be set in the data write or read signals. The control logic module determines the memory array module 121 to be activated by recognizing this chip select control information. That is, the data write or read signals include chip select control information and write or read information. Specifically, the control logic module is used to: determine the memory array module 121 to be written to or read from among the k memory array modules 121 according to the chip select control information, and perform data write or read operations on the memory array module 121 according to the write or read information.

[0083] As another implementation, the k memory array modules 121 connected to the same control logic module can be divided into different address spaces. The memory array module 121 to be activated can be determined by distinguishing the address space corresponding to the address information in the data write or read signals. That is, the control logic module is specifically used to: determine the memory array module 121 to be written to or read from among the k memory array modules 121 according to the address space corresponding to the data write or read signals, and perform data write or read operations on the memory array module 121 according to the data write or read signals.

[0084] For example, such as Figure 6 As shown, the 3D stacked chip chip2 has a two-layer structure including a logic die and a DRAM die. Assume the DRAM die includes 8 banks and 4 control logic modules, i.e., k=2. The first control logic module 501, the second control logic module 502, the third control logic module 503, and the fourth control logic module 504 are connected to the four memory control modules in the logic die—bank01_ctrl, bank23_ctrl, bank45_ctrl, and bank67_ctrl—correspondingly through the wafer-level interlayer connection structure 103. The 8 banks are represented as bank0 to bank7. The first control logic module 501 is connected to bank0 and bank1, the second control logic module 502 is connected to bank2 and bank3, the third control logic module 503 is connected to bank4 and bank5, and the fourth control logic module 504 is connected to bank6 and bank7. In this way, each group of banks can be connected to the interface in the DRAM die for connection with the corresponding memory control module 111 via the corresponding control logic module in a time-division manner. The logic die can achieve parallel read and write operations to the four banks in the DRAM die.

[0085] The fourth type, where k is an integer greater than or equal to 2 and less than M, comprises k stacked storage wafers, and each storage control module 111 is connected to k storage array modules 121 distributed across the k storage wafers. In this case, a chip select channel is provided between the storage control module 111 and the k connected storage array modules 121 to select one of the storage array modules 121 for data writing or reading operations.

[0086] For example, the three-dimensional stacked chip 100 has a three-layer structure including one logic die and two DRAM dies, namely DRAM die0 and DRAM die1. DRAM die0 includes 8 banks, denoted as bank00 to bank07, and DRAM die1 also includes 8 banks, denoted as bank10 to bank17. Correspondingly, the logic die is provided with 8 memory control modules 111, denoted as bank0_ctrl to bank7_ctrl. Among them, bank0_ctrl is connected to bank00 in DRAM die0 and bank10 in DRAM die1 through inter-layer connection structure 103, and bank2_ctrl to bank7_ctrl are similar to bank0_ctrl.

[0087] Taking bank0_ctrl as an example, to achieve time-division control of bank00 and bank10, a chip select channel is set up between bank0_ctrl and the connected bank00 and bank10. The chip select channel activates different banks on different DRAM dies. For example, the command channel used to transmit row validity indication in the control channel between bank0_ctrl and bank00 and bank10 can be used as the chip select channel. Other control channels and data channels between bank0_ctrl and bank00 and bank10, besides this command channel, can be shared.

[0088] In addition, this specification also provides a data processing method for a three-dimensional stacked chip. The three-dimensional stacked chip includes a storage wafer layer and a logic wafer layer stacked on top of the storage wafer layer. The storage wafer layer includes M storage array modules 121, and the logic wafer layer has N corresponding storage control modules 111. Each storage control module 111 is connected to k storage array modules 121 through a wafer-level inter-layer interconnection structure 103, and is used to control its respective connected storage array modules 121 to perform data write or read operations. Here, M and N are both integers greater than or equal to 2, and N is less than or equal to M; k is an integer greater than or equal to 1 and less than M. For the specific structure of this three-dimensional stacked chip, please refer to the relevant description of the three-dimensional stacked chip 100 above, which will not be repeated here.

[0089] like Figure 7 As shown, the data processing method may include the following steps S701 and S702.

[0090] Step S701: Receive storage control signal;

[0091] Step S702: Based on the storage control signal, multiple storage control modules are used to perform data writing or reading operations on the storage array module connected to the storage control module in parallel.

[0092] The storage control signals are used to indicate the storage array module 121 to be operated on in this data access operation, as well as operation-related information such as commands, addresses, and data. There can be one or more storage array modules 121 to be operated on. When there are multiple storage array modules 121 to be operated on, multiple storage control modules 111 can be used to perform data write or read operations on the connected storage array modules 121 in parallel.

[0093] In one optional implementation, the storage control signal may include a data write command and write data. The write address of the write data can be determined based on the space occupied by the write data and the storage space of the storage array module 121, thereby identifying the storage array module 121 to be operated. Specifically, in response to the write data occupying a space greater than the storage space of the storage array module 121, the write data is stored in a first storage array module and a second storage array module, which are controlled by different storage control modules 111; or, the first storage array module and the second storage array module are located on different storage wafer layers and are controlled by different storage control modules 111. The specific process can be referred to the relevant description above, and will not be repeated here.

[0094] For example, regarding the first type of three-dimensional stacked chip structure mentioned above, using... Figure 3 Taking the illustrated exemplary structure as an example, assuming the storage array modules 121 to be operated are bank0 to bank7, data write or read operations on bank0 to bank7 can be completed in parallel through bank0_ctrl to bank7_ctrl. Taking the data write operation as an example, data operation information can be sent to bank0_ctrl to bank7_ctrl respectively. This information includes a write command, a write address, and data information. Then, the decoding and parsing module in bank0_ctrl decodes and analyzes the write command and write address in the data write information. After that, bank0_ctrl sends bank activation information to bank0. After bank0 is activated, the write command, write address, and data information are sent to bank0 through the data channel and control channel respectively to complete the data write to bank0. Similarly, bank1_ctrl to bank7_ctrl complete the data write to bank1 to bank7 respectively.

[0095] Regarding the second type of three-dimensional stacked chip structure mentioned above, Figure 5Taking the exemplary structure shown as an example, assuming that the storage array module 121 to be operated is: bank00~bank07 and bank10~bank17, the data writing or reading operations on bank00~bank07 and bank10~bank17 can be completed in parallel through bank0_ctrl~bank15_ctrl.

[0096] Regarding the third type of three-dimensional stacked chip structure mentioned above, Figure 6 Taking the exemplary structure shown as an example, assuming that the storage array modules 121 to be operated are: bank0, bank2, bank4 and bank6, bank0, bank2, bank4 and bank6 are activated by bank01_ctrl, bank23_ctrl, bank45_ctrl and bank67_ctrl and the control logic module, so as to complete the data writing or reading operations on bank0, bank2, bank4 and bank6 in parallel.

[0097] For the fourth type of three-dimensional stacked chip structure mentioned above, taking the three-layer structure of logic die, DRAM die0 and DRAM die1 as an example, assuming that the memory array module 121 to be operated is bank00 to bank07 in DRAM die0, then bank00 to bank07 on DRAM die0 can be activated through the chip select channel, thereby completing the data writing or reading operations on bank00 to bank07 in parallel through bank0_ctrl to bank7_ctrl.

[0098] Example 2

[0099] like Figure 8 As shown in the figure, this specification provides a three-dimensional stacked chip 200, including: a logic chip 201, a memory chip 202, and a first timing control circuit 230.

[0100] The memory chip 202 includes M memory array modules 121 (banks) for storing data. M is an integer greater than or equal to 2. The logic chip 201 and the memory chip 202 are stacked and packaged using chip stacking packaging technology. Chip stacking packaging technology is a technology for realizing three-dimensional heterogeneous integration of chips. Specifically, the current technology for realizing three-dimensional heterogeneous integration of logic chip 201 and memory chip 202 is mainly hybrid bonding technology. Specifically, the logic chip 201 can access multiple banks in the memory chip 202 in parallel through wafer-level interlayer connection structures 103, such as hybrid bonding structures and through-silicon via structures. The specific structure of the logic chip 201 can refer to the structure of the logic wafer layer 101 in the above embodiment 1, and the specific structure of the memory chip 202 can refer to the structure of the memory wafer layer 102 in the above embodiment 1.

[0101] The logic chip 201 has N memory control modules 111, where N is an integer greater than or equal to 2 and less than or equal to M. Each memory control module 111 is connected to k memory array modules 121 through a wafer-level interlayer interconnection structure 103, and is used to control the memory array modules 121 connected to it to perform data write or read operations. Here, k is an integer greater than or equal to 1 and less than M. During data read and write operations, multiple memory control modules 111 can simultaneously control the corresponding connected memory array modules 121 to perform data read and write operations. In this way, the logic chip 201 can read and write one of the memory array modules 121 connected to different memory control modules 111 in parallel, that is, it can realize parallel read and write access to at least N memory array modules 121 in the memory chip 202 without being limited by packaging and hardware system, effectively improving the data access bandwidth of DRAM, thereby improving the data processing speed of the chip.

[0102] For example, the three-dimensional stacked chip 200 includes a logic die and a DRAM die stacked together. Assume the DRAM die includes eight banks, designated bank0 to bank7. Then, the logic die correspondingly includes eight memory control modules 111, designated bank0_ctrl to bank7_ctrl. bank0_ctrl is connected to bank0 via a wafer-level interlayer interconnect structure 103, bank1_ctrl is connected to bank1 via the same structure, and so on, with bank7_ctrl connected to bank7 via the same structure. This allows the logic die to access all banks in parallel through the eight memory control modules 111. Alternatively, in another embodiment, the logic die may include fewer memory control modules 111 than the number of banks, for example, four memory control modules 111, designated bank0_ctrl to bank3_ctrl. bank0_ctrl is connected to bank0 and bank1 through wafer-level interlayer interconnection structure 103, bank1_ctrl is connected to bank2 and bank3 through wafer-level interlayer interconnection structure 103, and so on, bank3_ctrl is connected to bank6 and bank7 through wafer-level interlayer interconnection structure 103.

[0103] In this way, logic chip 201 can access multiple DRAM banks in memory chip 202 in parallel, greatly increasing access efficiency. However, since the DRAM at this point is different from standard DRAM chips, the memory control modules 111 in logic chip 201 access the banks directly, which is a direct access to the memory array. The access process involves the transmission of various signals required for reading and writing data, such as address enable signals, address signals, data enable signals, and data signals. Some of these signals need to meet certain timing relationships; for example, the address enable signal and the address signal need to be matched. Figure 9 As shown, the required setup time range for the address signal relative to the address enable signal is -100ps to 100ps; similarly, the data enable signal and the data signal must be matched to accurately complete the data read and write operations.

[0104] In this paper, the multiple signals with timing matching relationships mentioned above are referred to as multiple first target signals, and the port in the storage control module 111 that outputs the multiple first target signals is referred to as the target output terminal. It can be understood that each decoding and parsing module of the storage control module 111 is equipped with a signal generation circuit that generates the multiple first target signals, and the target output terminal is the output terminal of the corresponding signal generation circuit.

[0105] To meet the transmission timing requirements of the aforementioned multiple first target signals, for example, timing control logic can be added to the target output terminals of each storage control module 111 in the logic chip 201 to control the output time of the aforementioned multiple first target signals, thereby satisfying the interface timing conditions of the DRAM storage array for the aforementioned multiple first target signals. In this case, the target output terminals of each storage control module 111 in the logic chip 201 are connected to the aforementioned timing control logic, and the output terminals of the timing control logic are then directly connected to the storage array module 121 through a wafer-level interlayer interconnection structure.

[0106] Considering the high timing matching requirements of the storage array for the aforementioned multiple first target signals, such as the requirement that the establishment time of the address signal relative to the address enable signal be within the range of -100ps to 100ps, the design of the aforementioned timing control logic is quite difficult. Typically, a dedicated physical interface hard core needs to be designed on the logic chip 201 using a fully custom approach to meet this timing requirement. This brings additional overhead to the design of the logic chip 201, which mostly uses a semi-custom process, and also restricts the semi-custom layout and routing.

[0107] If the logic chip 201 contains multiple hard core PHYs to meet the timing requirements of the DRAM interface, the timing and functional verification between these hard cores and the logic chip 201 itself involves co-design verification of fully custom and semi-custom components, which is very labor-intensive and difficult. In addition, the presence of hard cores hinders the placement and routing of the logic chip 201, which increases the difficulty of back-end design.

[0108] Therefore, as Figure 8 As shown, a first timing control circuit 230 can be set in the three-dimensional stacked chip 200 to control the transmission timing of the multiple first target signals output from the target output terminal to the storage array module 121 based on the received clock signal, so as to meet the interface timing conditions of the storage array module 121 for the multiple first target signals. This can meet the timing requirements of the storage array for these first target signals with timing matching relationship, thereby ensuring the normal operation of the three-dimensional stacked chip, and is easy to implement, without the need to design a dedicated physical interface hard core on the logic chip 201, which helps to reduce the design difficulty of the logic chip 201.

[0109] Specifically, a first timing control circuit 230 can be added to each memory control module 111 in the logic chip 201 to control the timing of the signals output from the corresponding signal output port of the memory control module 111 reaching the corresponding bank. Compared to designing a dedicated physical interface hard core to strictly control the output time of these signals within an extremely short setup time range, this semi-custom process design helps to simplify the design process and reduce the difficulty of the logic chip 201, thereby accelerating the development progress of the logic chip 201.

[0110] Specifically, such as Figure 10 As shown, the target output terminal of each storage control module 111 within the logic chip 201 (e.g.) Figure 10 Both S1 and S2 shown are connected to the corresponding memory array module 121 within the memory chip 202 via the first timing control circuit 230. It should be noted that... Figure 10 For illustrative purposes only, a storage control module 111 and a storage array module 121 are shown. In actual applications, the specific number of storage control module 111, first timing control circuit 230 and storage array module 121 needs to be set according to the actual needs of the three-dimensional stacked chip.

[0111] The first timing control circuit 230 is used to control the transmission timing of the multiple first target signals output from the target output terminal to the storage array module 121 based on the received clock signal, so as to meet the interface timing conditions of the storage array for the multiple first target signals. These interface timing conditions are determined according to the timing requirements of the storage array in the actual application scenario. In this embodiment, the multiple first target signals have a timing matching relationship, such as signals that need to be synchronously output to the storage array module 121 in the logic chip 201.

[0112] For example, the aforementioned multiple first target signals include an address enable signal and an address signal. Correspondingly, the target output terminal includes the address enable output terminal of the address enable signal generation circuit within the logic chip 201, and the address output terminal of the address generation circuit. At this time, the correspondingly configured first timing control circuit 230 needs to control the transmission timing of the address enable signal output from the address enable output terminal and the address signal output from the address output terminal to the storage array module 121, so as to meet the timing requirements of the storage array for these two signals.

[0113] For example, the aforementioned multiple first target signals include a write data enable signal and a write data signal, i.e., the data signal to be written to the storage array module 121. Correspondingly, the target output terminal includes a write data enable output terminal of the write data enable generation circuit and a data output terminal of the data supply circuit. At this time, the correspondingly configured first timing control circuit 230 needs to control the transmission timing of the write data enable signal output from the write data enable output terminal and the write data signal output from the data output terminal to the storage array module 121, so as to meet the timing requirements of the storage array for these two signals.

[0114] Specifically, such as Figure 10 As shown, the first timing control circuit 230 may include a first sampling sub-circuit 231 and a second sampling sub-circuit 232. The first sampling sub-circuit 231 is disposed in the logic chip 201, and the second sampling sub-circuit 232 is disposed in the memory chip 202.

[0115] Furthermore, the aforementioned three-dimensional stacked chip also includes a clock interface for providing clock signals. The clock terminals of both the first sampling sub-circuit 231 and the second sampling sub-circuit 232 are connected to this clock interface, i.e., controlled by the same clock signal. The clock interface can be the output interface of the internal clock circuit of the logic chip 201 or an external clock interface; this embodiment does not impose any limitations on this.

[0116] The input terminal of the first sampling sub-circuit 231 is connected to the aforementioned target output terminal, and is used to synchronously trigger the multiple first target signals output from the target output terminal to be output from the logic chip 201 under the control of the aforementioned clock signal. The input terminal of the second sampling sub-circuit 232 is connected to the output terminal of the first sampling sub-circuit 231, and its output terminal is connected to the memory array module 121, and is used to synchronously trigger the multiple first target signals output from the logic chip 201 to be received by the memory array module 121 under the control of the aforementioned clock signal. In a specific implementation, the first sampling sub-circuit 231 and the second sampling sub-circuit 232 can be connected through the wafer-level interlayer interconnection structure 103.

[0117] In an optional implementation, the first sampling sub-circuit 231 may include a plurality of first flip-flops, each corresponding to one of the multiple first target signals. The inputs of these multiple first flip-flops are connected to the target outputs, i.e., to the outputs of their respective first target signals; their clock terminals are all connected to the clock interface; and their outputs are connected to the second sampling sub-circuit 232. These first flip-flops are used to synchronously trigger the multiple first target signals output from the target outputs at the first sampling time point, based on the same clock signal, to be output from the logic chip 201.

[0118] For example, if the target output terminal includes an address enable output terminal and an address output terminal, then the first sampling sub-circuit 231 includes a first flip-flop DFF0 and a first flip-flop DFF1. The input terminal of the first flip-flop DFF0 is connected to the address enable output terminal, and the input terminal of the first flip-flop DFF1 is connected to the address output terminal. In this way, the first flip-flop DFF0 and the first flip-flop DFF1 can synchronously trigger the address enable signal and the address signal to be output from the logic chip 201 to the memory chip 202 at the first sampling time point based on the same clock signal.

[0119] In one optional implementation, the second sampling sub-circuit 232 may include a plurality of second flip-flops, each corresponding to one of the plurality of first flip-flops. The inputs of the plurality of second flip-flops are connected to the outputs of their respective first flip-flops, their clock terminals are all connected to the aforementioned clock interface, and their outputs are connected to the storage array module 121. It should be noted that the clock terminals of the plurality of second flip-flops and the clock terminals of the plurality of first flip-flops are all connected to the same clock interface, receiving the same clock signal provided by that clock interface.

[0120] The aforementioned multiple second flip-flops are used to latch their respective received first target signals. Based on the same clock signal, the latched first target signals are synchronously triggered and output to the storage array module 121 at the second sampling time point. Since the signal needs to be output from the logic chip 201 before it can be latched in the storage chip 202, the second sampling time point should be later than the first sampling time point.

[0121] For example, in the above example, the first sampling sub-circuit 231 includes first flip-flops DFF0 and DFF1. Correspondingly, the second sampling sub-circuit 232 may include second flip-flops DFF2 and DFF3. The input terminal of the second flip-flop DFF2 is connected to the output terminal Q0 of the first flip-flop DFF0 to latch the received address enable signal. The input terminal of the second flip-flop DFF3 is connected to the output terminal Q1 of the first flip-flop DFF1 to latch the received address signal. In this way, the second flip-flop DFF2 and the second flip-flop DFF3 can synchronously trigger the address enable signal and the address signal at the second sampling time point based on the same clock signal, and are output to the memory array module 121 synchronously, that is, synchronously received by the memory array module 121. This makes the arrival time of the address enable signal and the address signal in the DRAM basically synchronized, converting the address enable port and the address port between the logic chip 201 and the DRAM into synchronous ports.

[0122] Furthermore, to ensure that all the aforementioned multiple first target signals can be sampled correctly by the clock, the arrival times of the aforementioned multiple first target signals at their respective second triggers are all between the first sampling time point and the second sampling time point, and the effective duration of the aforementioned multiple first target signals is greater than or equal to the time interval between the first sampling time point and the second sampling time point. This ensures that each first target signal can be correctly sampled at the second sampling time point.

[0123] In practice, the time interval between the first sampling time point and the second sampling time point can be set according to the needs of the actual application scenario. For example, this time interval can be set to one clock cycle of the aforementioned clock signal.

[0124] Understandably, compared to designing a dedicated physical interface hard core to control the signal output time of the aforementioned target output terminals within an extremely short setup time range, such as -100ps to 100ps, setting corresponding constraints on the relative clocks of these target output terminals, and controlling the first target signal of each channel to reach the flip-flop in DRAM between Ta and Tb, it is simple and easy to implement, effectively reducing the design requirements for the target output terminals in the logic chip 201.

[0125] For example, both the first and second flip-flops mentioned above can be D flip-flops. Figure 11An exemplary transmission timing diagram of the address enable signal and the address signal is shown. Figure 11 In the diagram, time Ta represents the first sampling time point, time Tb represents the second sampling time point, CLK represents the clock signal, Q0 represents the address enable signal output by the first flip-flop DFF0, Q1 represents the address signal output by the first flip-flop DFF1, Q2 represents the address enable latch signal output by the second flip-flop DFF2, and Q3 represents the address latch signal output by the second flip-flop DFF3.

[0126] Assume that the first flip-flops DFF0 and DFF1, and the second flip-flops DFF2 and DFF3, all use rising edge triggering. Figure 11 As shown, at time Ta, the clock signal CLK transitions high, triggering the Q0 port of the first flip-flop DFF0 to output the address enable signal received at its D port. This causes the second flip-flop DFF2 to latch the address enable signal. Simultaneously, it triggers the Q1 port of the first flip-flop DFF1 to output the address signal received at its D port, causing the second flip-flop DFF3 to latch the address signal. At time Tb, the clock signal CLK transitions from low to high, triggering the Q2 port of the second flip-flop DFF2 to output the latched address enable signal (address enable latch signal). Simultaneously, it triggers the Q3 port of the second flip-flop DFF3 to output the latched address signal (address latch signal), thus ensuring that the address enable signal and the address signal are received synchronously by the DRAM. It should be noted that, considering the time required for the flip-flops to respond from clock triggering, a certain interval is needed after clock triggering before the output port outputs the corresponding signal.

[0127] It is understood that the aforementioned second sampling sub-circuit 232 synchronously triggers the output of each first target signal. In an optional implementation, to better adapt to the sampling timing of the DRAM, such as... Figure 10 As shown, the first timing control circuit 230 may further include a delay sub-circuit 233, disposed in the memory chip 202, with the output of the second sampling sub-circuit 232 connected to the memory array module 121 via the delay sub-circuit 233. The delay sub-circuit 233 is used to adjust the relative time relationship between the first target signals output from the second sampling sub-circuit 232 and their arrival at the memory array module 121, in order to meet the aforementioned interface timing conditions. For example, an adjustable delay unit can be set for each first target signal, and the delay time of each delay unit can be adjusted according to a preset delay rule. The preset delay rule can be set according to the specific interface sampling timing requirements of the memory array.

[0128] Taking the aforementioned multiple first target signals, including address enable signal and address signal, as an example, a first delay unit and a second delay unit can be set respectively. The input terminal of the first delay unit is connected to the output terminal Q2 of the second flip-flop DFF2, and the input terminal of the second delay unit is connected to the output terminal Q3 of the second flip-flop DFF3. The output terminals of the first delay unit and the second delay unit are respectively connected to the corresponding signal receiving ports in the storage array module 121.

[0129] At this point, by configuring the delay times of the first delay unit and the second delay unit respectively, the relative time relationship between the address enable latch signal output by the second flip-flop DFF2 and the address latch signal output by the second flip-flop DFF3 arriving at the storage array module 121 can be controlled, thus satisfying the timing requirements of the storage array for the address enable signal and the address signal. For example, if the storage array requires the address signal to arrive before the address enable signal, with an interval of t, then the delay time of the first delay unit can be configured to be greater than the delay time of the second delay unit, with a delay time difference of t.

[0130] Alternatively, in other embodiments of this specification, the delay unit can be specifically set to delay the latch signal that needs to arrive later, which can meet the signal sampling timing requirements of the storage array. This embodiment does not limit the specific implementation of the delay sub-circuit 233.

[0131] The technical solution provided in this embodiment can effectively synchronize the signals output by the logic chip 201 to the DRAM by setting the first timing control circuit 230 and inputting a synchronous clock, thereby converting the interface between the logic chip 201 and the DRAM into a synchronous interface.

[0132] In the design of logic chip 201, only the output delay constraints of the signals output to the DRAM interface need to be set according to the DRAM interface path to achieve a semi-custom design process for logic chip 201. Furthermore, since memory chip 202 is a general-purpose design, while the corresponding logic chip 201 may have multiple forms, adding a second sampling sub-circuit 232 to the DRAM to achieve synchronous output of logic chip 201 simplifies the design process and reduces the difficulty of logic chip 201, thus accelerating its development progress.

[0133] Furthermore, in an optional embodiment, the aforementioned three-dimensional stacked chip further includes a second timing control circuit (not shown in the figure). The target input terminals of each storage control module 111 within the logic chip 201 are connected to the storage array module 121 within the storage chip 202 via the second timing control circuit. The clock terminal of the second timing control circuit is also connected to the aforementioned clock interface, i.e., it is controlled by the same clock signal as the first timing control circuit 230. The second timing control circuit is used to control the transmission timing of multiple second target signals output by the storage array module 121 to the target input terminals based on the clock signal, so as to satisfy the interface timing conditions of the logic chip 201 for the multiple second target signals. The multiple second target signals are multiple signals with timing matching relationships, for example, they may include a read data enable signal and a read data signal, i.e., the data signal read from the storage array module 121.

[0134] It should be noted that the specific principle of the second timing control circuit is similar to that of the first timing control circuit 230 mentioned above. For details, please refer to the relevant description of the first timing control circuit 230 mentioned above, which will not be repeated here.

[0135] In one alternative implementation, the target input terminal within the logic chip 201 has its own signal capture logic. In this case, compared to the first timing control circuit 230, the second timing control circuit does not need to set a delay sub-circuit to adjust the relative time relationship of each second target signal arriving at the target input terminal.

[0136] By setting a second timing control circuit and inputting a synchronous clock, the signal output from DRAM to logic chip 201 can be effectively synchronized, thereby converting the interface between logic chip 201 and DRAM into a synchronous interface.

[0137] In addition, the embodiments of this specification provide a timing control method that can be applied to... Figure 8 The corresponding embodiment provides a three-dimensional stacked chip 200. For example... Figure 12 As shown, the method includes the following steps:

[0138] Step S1201: Obtain the clock signal;

[0139] Step S1202: Based on the clock signal, control the transmission timing of the multiple first target signals output from the target output terminal in the control logic chip to the storage array module, so as to meet the interface timing conditions of the storage array module for the above-mentioned multiple first target signals.

[0140] It should be noted that the specific implementation process of steps S1201 and S1202 can be referred to the corresponding description in the chip structure embodiment above, and will not be repeated here.

[0141] In an optional implementation, step S1202 may include: synchronously triggering multiple first target signals output from the target output terminal to be output from the logic chip 201 at a first sampling time point based on a clock signal; latching the multiple first target signals respectively, and synchronously triggering the output of each latched first target signal to the storage array module 121 at a second sampling time point based on a clock signal, wherein the second sampling time point is later than the first sampling time point. Specific implementation details can be found in the relevant descriptions above and will not be repeated here.

[0142] In an optional implementation, the step of synchronously triggering the output of each of the first target signals latched at the second sampling time point to the storage array module 121 may include: synchronously triggering the output of each of the first target signals latched at the second sampling time point; and performing delay processing on each of the output first target signals according to a preset delay rule to adjust the relative time relationship of each of the first target signals arriving at the storage array module 121, so as to meet the interface timing conditions. Specific implementation processes can be referred to the relevant descriptions above, and will not be repeated here.

[0143] In an optional implementation, the timing control method further includes: controlling the transmission timing of the multiple second target signals output by the storage array module 121 to the target input terminal within the logic chip 201 based on the clock signal, so as to satisfy the interface timing conditions of the logic chip 201 for the multiple second target signals. Specific implementation details can be found in the above description and will not be repeated here.

[0144] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the method described above can be referred to the corresponding process in the aforementioned chip structure embodiments, and will not be repeated here.

[0145] In this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The term "a plurality of" means two or more, including two or more cases.

[0146] Although preferred embodiments have been described in this specification, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this specification.

[0147] Obviously, those skilled in the art can make various modifications and variations to this specification without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims and their equivalents, this specification is also intended to include such modifications and variations.

Claims

1. A three-dimensional stacked chip, characterized by, include: Logic chip; The memory chip is stacked and packaged with the logic chip; as well as The first timing control circuit connects the target output terminal in the logic chip to the storage array module in the storage chip. The first timing control circuit is used to control the transmission timing of multiple first target signals output by the target output terminal to the storage array module based on the received clock signal, so as to meet the interface timing conditions of the storage array module for the multiple first target signals. The first timing control circuit includes: A first sampling sub-circuit is disposed in the logic chip. The input terminal of the first sampling sub-circuit is connected to the target output terminal and is used to synchronously trigger multiple first target signals output from the target output terminal to be output from the logic chip under the control of the clock signal. A second sampling sub-circuit is disposed on the memory chip. The input terminal of the second sampling sub-circuit is connected to the output terminal of the first sampling sub-circuit, and the output terminal is connected to the memory array module. It is used to synchronously trigger multiple first target signals output from the logic chip to be received by the memory array module under the control of the clock signal. The three-dimensional stacked chip also includes a clock interface for providing the clock signal, and the clock terminals of the first sampling sub-circuit and the second sampling sub-circuit are both connected to the clock interface; The first sampling sub-circuit includes: a plurality of first flip-flops, each corresponding one-to-one with the multiple first target signals. The input terminals of the plurality of first flip-flops are connected to the target output terminal, the clock terminals are all connected to the clock interface, and the output terminals are connected to the second sampling sub-circuit. The plurality of first flip-flops are used to synchronously trigger the multiple first target signals output from the target output terminal to be output from the logic chip at the first sampling time point based on the clock signal; The second sampling sub-circuit includes: a plurality of second flip-flops configured in a one-to-one correspondence with the plurality of first flip-flops. The inputs of the plurality of second flip-flops are connected to the outputs of their respective first flip-flops, the clock terminals are all connected to the clock interface, and the output terminals are connected to the storage array module. The plurality of second triggers are used to latch their respective received first target signals, and based on the clock signal, synchronously trigger the output of the latched first target signals to the storage array module at the second sampling time point, wherein the second sampling time point is later than the first sampling time point.

2. The three-dimensional stacked chip of claim 1, wherein, The arrival times of the multiple first target signals at their respective second triggers are all between the first sampling time point and the second sampling time point, and the effective duration of the multiple first target signals is greater than or equal to the time interval between the first sampling time point and the second sampling time point.

3. The three-dimensional stacked chip of claim 2, wherein, The time interval between the first sampling time point and the second sampling time point is one clock cycle of the clock signal.

4. The three-dimensional stacked chip of claim 1, wherein, The first timing control circuit further includes a delay sub-circuit, disposed in the memory chip. The output of the second sampling sub-circuit is connected to the storage array module through the delay sub-circuit. The delay sub-circuit is used to adjust the relative time relationship of each first target signal output from the second sampling sub-circuit to the storage array module so as to meet the interface timing conditions.

5. The three-dimensional stacked chip of claim 1, wherein, The multiple first target signals include an address enable signal and an address signal, or, The multiple first target signals include a write data enable signal and a write data signal.

6. The three-dimensional stacked chip of claim 1, wherein, Also includes: Second timing control circuit, The target input terminal in the logic chip is connected to the storage array module in the storage chip through the second timing control circuit. The second timing control circuit is used to control the transmission timing of the multiple second target signals output by the storage array module to the target input terminal based on the clock signal, so as to meet the interface timing conditions of the logic chip for the multiple second target signals.

7. A method of timing control, characterized by, Applied to the three-dimensional stacked chip of claim 1, the three-dimensional stacked chip includes stacked and packaged logic chips and memory chips, the logic chip has a target output terminal, and the memory chip includes a memory array module, the method includes: Obtain the clock signal; Based on the clock signal, the transmission timing of the multiple first target signals output by the target output terminal to the storage array module is controlled to meet the interface timing conditions of the storage array module for the multiple first target signals.

8. The timing control method according to claim 7, wherein The step of controlling the transmission timing of multiple first target signals output from the target output terminal to the storage array module based on the clock signal includes: Based on the clock signal, at the first sampling time point, the multiple first target signals output from the target output terminal are synchronously triggered to be output from the logic chip. The multiple first target signals are latched respectively, and based on the clock signal, the latched first target signals are synchronously triggered to be output to the storage array module at the second sampling time point, where the second sampling time point is later than the first sampling time point.

9. The timing control method according to claim 8, wherein The output of each first target signal, which is synchronously triggered and latched at the second sampling time point, to the storage array module includes: The latched first target signal outputs are triggered synchronously at the second sampling time point; According to the preset delay rules, the output first target signals are delayed respectively to adjust the relative time relationship of the first target signals arriving at the storage array module, so as to meet the interface timing conditions.

10. The timing control method of claim 7, wherein, The logic chip also includes a target input terminal, and the method further includes: Based on the clock signal, the transmission timing of the multiple second target signals output by the storage array module to the target input terminal is controlled to meet the interface timing conditions of the logic chip for the multiple second target signals.

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