Semiconductor system for performing duty cycle adjustment operations

Abstract

A semiconductor system includes a first semiconductor device which outputs a clock and mode data, receives a strobe signal and outputs data, and adjusts a duty ratio of the strobe signal by comparing odd data and even data generated from the output data in synchronization with the strobe signal with the mode data, and a second semiconductor device which stores the mode data in synchronization with the clock, outputs the clock as the strobe signal by adjusting a duty ratio of the clock, and outputs the stored mode data as the output data.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Application No. 10-2022-0071072, filed on June 10, 2022, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to semiconductor systems, and more particularly to semiconductor systems for adjusting duty cycles. Background Technology

[0004] Recently, with the increasing operating speed of semiconductor systems, high-speed data transmission rates are often required between the semiconductor devices included in these systems. To meet the demands of high-speed data transmission rates or high bandwidth for serial input and output data between semiconductor devices, new technologies have been applied. For example, clock division schemes are used to achieve high-speed data input and output. When the clock is divided, multi-phase clocks with different phases are generated. By utilizing multi-phase clocks, data can be parallelized or serialized, enabling high-speed input and output of data. Summary of the Invention

[0005] In one embodiment, this disclosure may provide a semiconductor device comprising: a data comparison circuit configured to generate an odd comparison signal by comparing bits included in odd data generated from input data synchronously with an internal strobe signal and pattern data, and configured to generate an even comparison signal by comparing bits included in even data generated from input data synchronously with an internal strobe signal and pattern data; and a strobe signal duty cycle adjustment circuit configured to adjust the duty cycle of the internal strobe signal for strobe input data based on the odd comparison signal and the even comparison signal.

[0006] Furthermore, in one embodiment, this disclosure may provide a semiconductor system comprising: a first semiconductor device configured to output clock and mode data, configured to receive a strobe signal and output data, and configured to adjust the duty cycle of the strobe signal by comparing odd and even data generated synchronously from the output data with the mode data; and a second semiconductor device configured to store the mode data synchronously with a clock, configured to output a clock as a strobe signal by adjusting the duty cycle of the clock, and configured to output the stored mode data as output data. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating the structure of a semiconductor system according to an embodiment of the present disclosure.

[0008] Figure 2 It is shown Figure 1A block diagram showing the structure of the first semiconductor device included in the semiconductor system.

[0009] Figure 3 It is shown Figure 2 A block diagram showing the structure of the data comparison circuit included in the first semiconductor device.

[0010] Figure 4 It is shown Figure 2 The diagram shows a block diagram of the structure of the strobe signal duty cycle adjustment circuit included in the first semiconductor device.

[0011] Figure 5 It is shown Figure 4 The block diagram shown illustrates the structure of the code signal generation circuit included in the strobe signal duty cycle adjustment circuit.

[0012] Figure 6 It is shown Figure 5 The diagram shows the structure of the calibration control circuit included in the code signal generation circuit.

[0013] Figure 7 It is shown Figure 5 The diagram shows the structure of the duty cycle code signal generation circuit included in the code signal generation circuit.

[0014] Figure 8 It is shown Figure 4 The circuit diagram shown illustrates the structure of the internal gating signal generation circuit included in the gating signal duty cycle adjustment circuit.

[0015] Figure 9 This is a diagram illustrating the operation of an internal strobe signal generation circuit according to an embodiment of the present disclosure.

[0016] Figure 10 It is shown Figure 1 A block diagram showing the structure of the second semiconductor device included in the semiconductor system.

[0017] Figure 11 and Figure 12 This is a diagram used to describe a duty cycle adjustment operation according to an embodiment of the present disclosure.

[0018] Figure 13 This is a flowchart describing the duty cycle adjustment operation of a semiconductor system according to an embodiment of the present disclosure.

[0019] Figure 14 This shows the results based on what has already been applied for execution. Figures 1 to 13 A diagram illustrating the structure of an embodiment of an electronic system for a semiconductor system with duty cycle adjustment operation. Detailed Implementation

[0020] In the following description of embodiments, the term "preset" means that the value of a parameter is predetermined when it is used in a process or algorithm. According to one embodiment, the value of a parameter may be set at the start of the process or algorithm or during the execution of the process or algorithm.

[0021] Terms such as "first" and "second" used to distinguish components are not limited to any particular component. For example, the first component can be referred to as the second component, and vice versa.

[0022] When a component is said to be "coupled" or "connected" to another component, it should be understood that the components can be directly coupled or connected to each other or coupled or connected to each other through another component in between. On the other hand, when a component is said to be "directly coupled" or "directly connected" to another component, it should be understood that the components are directly coupled or connected to each other without any other component in between.

[0023] "Logic high" and "logic low" are used to describe the logic level of a signal. A signal with a "logic high" level is distinguished from a signal with a "logic low" level. For example, while a signal with a first voltage corresponds to a signal with a "logic high" level, a signal with a second voltage can correspond to a signal with a "logic low" level. According to one embodiment, a "logic high" level can be set to a voltage higher than a "logic low" level. According to one embodiment, the logic level of a signal can be set to different logic levels or opposite logic levels. For example, in some embodiments, a signal with a logic high level can be set to a logic low level, while in other embodiments, a signal with a logic low level can be set to a logic high level.

[0024] The teachings of this disclosure will be described in more detail below by way of examples. These examples are for illustrative purposes only, and the teachings of this disclosure are not limited to these examples.

[0025] Some embodiments of this disclosure relate to providing a semiconductor system in which, in each semiconductor device, an operation is performed to adjust the duty cycle of a gating signal for gating data.

[0026] According to one embodiment, by performing an operation to adjust the duty cycle of the gating signal for gating data in each semiconductor device, data errors can be prevented or reduced.

[0027] Furthermore, according to one embodiment, by gating data by performing an operation to adjust the duty cycle of the gating signal for the gating data in each semiconductor device, the effective window of the data can be guaranteed.

[0028] like Figure 1As shown, a semiconductor system 1 according to an embodiment of the present disclosure may include a first semiconductor device 10 and a second semiconductor device 20. The first semiconductor device 10 may include a data comparison circuit (DATA CMP) 140 and a strobe signal duty cycle adjustment circuit (DQS DUTY CTR) 150.

[0029] The first semiconductor device 10 may include a first control pin 11_1, a second control pin 11_2, a third control pin 11_3, and a fourth control pin 11_4. The second semiconductor device 20 may include a first device pin 13_1, a second device pin 13_2, a third device pin 13_3, and a fourth device pin 13_4. A first transmission line 12_1 may be connected between the first control pin 11_1 and the first device pin 13_1. A second transmission line 12_2 may be connected between the second control pin 11_2 and the second device pin 13_2. A third transmission line 12_3 may be connected between the third control pin 11_3 and the third device pin 13_3. A fourth transmission line 12_4 may be connected between the fourth control pin 11_4 and the fourth device pin 13_4. The first semiconductor device 10 may receive output data DOUT from the second semiconductor device 20 via the first transmission line 12_1. The first semiconductor device 10 may receive a strobe signal DQS from the second semiconductor device 20 via the second transmission line 12_2. The first semiconductor device 10 can output mode data PD to the second semiconductor device 20 via the third transmission line 12_3. The first semiconductor device 10 can output clock CLK to the second semiconductor device 20 via the fourth transmission line 12_4. After a write operation and / or a read operation begins, the mode data PD may include multiple bits with a preset combination of logic levels. After the mode data PD is stored in the second semiconductor device 20 after the write operation begins, output data DOUT can be generated from the stored mode data PD after the read operation begins. The output data DOUT may include multiple bits. The clock CLK and the strobe signal DQS can be set as signals triggered within a given interval to time the transmission of bits of the mode data PD and the output data DOUT.

[0030] Data comparison circuit 140 can compare odd data generated from output data DOUT synchronously with strobe signal DQS. Figure 2 OD_D<1:8> in the data and even data ( Figure 2 The data comparison circuit 140 compares the EV_D (1:8) with the pattern data PD. The data comparison circuit 140 can also compare the odd data (...) accordingly. Figure 2 OD_D<1:8> in the model data PD and even data ( Figure 2 The EV_D<1:8> in the model data PD generates an odd comparison signal. Figure 2OD CS) and even comparison signal ( Figure 2 (EVCS in the middle).

[0031] The strobe signal duty cycle adjustment circuit 150 can be based on an odd comparison signal ( Figure 2 ODCS in the even comparison signal ( Figure 2 The duty cycle of the strobe signal DQS is adjusted by the EVCS (in the context of the signal). Based on the odd comparison signal ( Figure 2 ODCS in the even comparison signal ( Figure 2 In the EVCS (internal strobe signal control circuit), the duty cycle adjustment circuit 150 can adjust the duty cycle of the internal strobe signal IDQS generated from the strobe signal DQS. The duty cycle can be set as the ratio of the intervals with logic high levels to the intervals with logic low levels included in the strobe signal DQS and the internal strobe signal IDQS.

[0032] The first semiconductor device 10 can receive a strobe signal DQS generated from clock CLK and output data DOUT generated from mode data PD. By comparing the odd data generated from the output data DOUT... Figure 2 OD_D<1:8> in the data and even data ( Figure 2 In the context of EV_D<1:8> and mode data PD, the first semiconductor device 10 can adjust the duty cycle of the strobe signal DQS. The first semiconductor device 10 can be implemented as a controller to control the operation of the second semiconductor device 20.

[0033] The second semiconductor device 20 can store mode data PD synchronously with clock CLK. The second semiconductor device 20 can output clock CLK as a strobe signal DQS by adjusting the duty cycle of clock CLK. The second semiconductor device 20 can output the stored mode data PD as output data DOUT. The second semiconductor device 20 can be implemented as a non-volatile memory device, retaining data even when its power supply is interrupted.

[0034] Figure 2 This is a block diagram illustrating the structure according to one embodiment of the first semiconductor device 10. (See diagram for example.) Figure 2 As shown, the first semiconductor device 10 may include a data delay circuit (DATA DELAY) 110, a strobe signal delay circuit (DQS DELAY) 120, a parallel conversion circuit (DSR) 130, a data comparison circuit (DATACMP) 140, and a strobe signal duty cycle adjustment circuit (DQS DUTYCTR) 150.

[0035] After the read operation begins, the data delay circuit 110 can generate the first to sixteenth input data IN_D<1:16> based on the first to sixteenth output data DOUT<1:16>. After the read operation begins, the data delay circuit 110 can generate the first to sixteenth input data IN_D<1:16> by delaying the first to sixteenth output data DOUT<1:16>. In different embodiments, the delay amount of the data delay circuit 110 can be set differently. The first to sixteenth output data DOUT<1:16> and the first to sixteenth input data IN_D<1:16> can be set to serial data including multiple bits that are input sequentially.

[0036] After the read operation begins, the strobe delay circuit 120 can generate an input strobe signal IN_DQS based on the strobe signal DQS. The strobe delay circuit 120 can also generate the input strobe signal IN_DQS by delaying the strobe signal DQS after the read operation begins. In different embodiments, the delay amount of the strobe delay circuit 120 can be set differently. To time the transmission of bits included in the first to sixteenth output data DOUT<1:16> and the first to sixteenth input data IN_D<1:16>, the strobe signal DQS and the input strobe signal IN_DQS can be set as signals triggered within a given interval.

[0037] The delay amounts of the data delay circuit 110 and the strobe signal delay circuit 120 can be set in the same way.

[0038] Synchronized with the rising interval of the internal strobe signal IDQS, the parallel conversion circuit 130 can generate the first to eighth odd data OD_D<1:8> based on the bits included in the first to sixteenth input data IN_D<1:16>. Synchronized with the falling interval of the internal strobe signal IDQS, the parallel conversion circuit 130 can generate the first to eighth even data EV_D<1:8> based on the bits included in the first to sixteenth input data IN_D<1:16>. Synchronized with the rising interval of the internal strobe signal IDQS, the parallel conversion circuit 130 can generate the first to eighth odd data OD_D<1:8> by changing the odd-numbered bits IN_D<1,3,5,7,9,11,13,15> included in the serially input first to sixteenth input data IN_D<1:16> to parallel. Synchronized with the falling interval of the internal strobe signal IDQS, the parallel conversion circuit 130 can generate the first to eighth even data EV_D<1:8> by converting the even-numbered bits IN_D<2,4,6,8,10,12,14,16> included in the first to sixteenth serial input data IN_D<1:16> into parallel data. The parallel conversion circuit 130 can be implemented as a general deserializer.

[0039] By correspondingly comparing the first to eighth odd data OD_D<1:8> with the first to sixteenth mode data PD<1:16> and the first to eighth even data EV_D<1:8> with the first to sixteenth mode data PD<1:16>, the data comparison circuit 140 can generate an odd comparison signal ODCS and an even comparison signal EVCS. By comparing the odd-numbered bits PD<1,3,5,7,9,11,13,15> included in the first to eighth odd data OD_D<1:8> and the first to sixteenth mode data PD<1:16>, the data comparison circuit 140 can generate an odd comparison signal ODCS. When the odd-numbered bits PD<1,3,5,7,9,11,13,15> included in the first to eighth odd data OD_D<1:8> and the first to sixteenth mode data PD<1:16> have different logic level combinations, the data comparison circuit 140 can generate an enabled odd comparison signal ODCS. By comparing the even-numbered bits PD<2,4,6,8,10,12,14,16> included in the first to eighth even data EV_D<1:8> and the first to sixteenth mode data PD<1:16> respectively, the data comparison circuit 140 can generate an even comparison signal EVCS. When the even-numbered bits PD<2,4,6,8,10,12,14,16> included in the first to eighth even data EV_D<1:8> and the first to sixteenth mode data PD<1:16> have different logic level combinations, the data comparison circuit 140 can generate an enabled even comparison signal EVCS.

[0040] Based on the odd comparison signal ODCS and the even comparison signal EVCS, the strobe signal duty cycle adjustment circuit 150 can adjust the duty cycle of the internal strobe signal IDQS for strobing the first to sixteenth input data IN_D<1:16>. Based on the odd comparison signal ODCS and the even comparison signal EVCS, the strobe signal duty cycle adjustment circuit 150 can also adjust the duty cycle of the internal strobe signal IDQS for latching the first to sixteenth input data IN_D<1:16>. The strobe signal duty cycle adjustment circuit 150 can sequentially store the input odd comparison signal ODCS and even comparison signal EVCS, and can adjust the duty cycle of the internal strobe signal IDQS until the odd comparison signal ODCS and even comparison signal EVCS stored in the strobe signal duty cycle adjustment circuit 150 become identical. For example, when the odd comparison signal ODCS and the even comparison signal EVCS have the same logic level combination, they are identical.

[0041] Figure 3 This is a block diagram illustrating the structure of one embodiment of the data comparison circuit 140. (See diagram for example.) Figure 3As shown, the data comparison circuit 140 may include an odd comparison circuit (ODD CMP) 141 and an even comparison circuit (EVEN CMP) 142.

[0042] By comparing the odd-numbered bits PD<1,3,5,7,9,11,13,15> included in the first to eighth odd data OD_D<1:8> and the first to sixteenth mode data PD<1:16>, the odd comparison circuit 141 can generate an odd comparison signal ODCS. When the odd-numbered bits PD<1,3,5,7,9,11,13,15> included in the first to eighth odd data OD_D<1:8> and the first to sixteenth mode data PD<1:16> have different logic level combinations, the odd comparison circuit 141 can generate an enabled odd comparison signal ODCS. For example, if the logic level combination of the first to eighth odd data OD_D<1:8> (i.e., 11111111) does not match the odd-numbered bits PD<1,3,5,7,9,11,13,15> (i.e., 11111110), the odd comparison signal ODCS can be enabled. When the odd-numbered bits PD<1,3,5,7,9,11,13,15> included in the first to eighth odd data OD_D<1:8> and the first to sixteenth mode data PD<1:16> have the same logic level combination, the odd comparison circuit 141 can generate a disabled odd comparison signal ODCS. For example, if the logic level combination of the first to eighth odd data OD_D<1:8> (i.e., 11111111) matches the odd-numbered bits PD<1,3,5,7,9,11,13,15> (i.e., 11111111), the odd comparison signal ODCS can be disabled. In different embodiments, the logic level at which the odd comparison signal ODCS is enabled can be set to a logic high level or a logic low level.

[0043] Even comparison circuit 142 generates an even comparison signal EVCS by comparing the even-numbered bits PD<2,4,6,8,10,12,14,16> included in the first to eighth even data EV_D<1:8> and the first to sixteenth mode data PD<1:16>. Even comparison circuit 142 generates an enabled even comparison signal EVCS when the even-numbered bits PD<2,4,6,8,10,12,14,16> included in the first to eighth even data EV_D<1:8> and the first to sixteenth mode data PD<1:16> have different logic level combinations. For example, if the logic level combination of the first to eighth even data EV_D<1:8> (i.e., 11111111) does not match the even-numbered bits PD<2,4,6,8,10,12,14,16> (i.e., 011111110), the even comparison signal EVCS can be enabled. When the even-numbered bits PD<2,4,6,8,10,12,14,16> included in the first to eighth even data EV_D<1:8> and the first to sixteenth mode data PD<1:16> have the same logic level combination, the even comparison circuit 142 can generate an inhibited even comparison signal EVCS. For example, if the logic level combination of the first to eighth even data EV_D<1:8> (i.e., 11111111) matches the even-numbered bits PD<2,4,6,8,10,12,14,16> (i.e., 11111111), the even comparison signal EVCS can be inhibited. In different embodiments, the logic level at which the even comparison signal EVCS is enabled can be set to a logic high level or a logic low level.

[0044] Figure 4 This is a block diagram illustrating the structure of an embodiment of the duty cycle adjustment circuit 150 based on a strobe signal. Figure 4 As shown, the strobe signal duty cycle adjustment circuit 150 may include a code signal generation circuit (CODE GEN) 151 and an internal strobe signal generation circuit (IDQS GEN) 152.

[0045] Based on the odd comparison signal ODCS and the even comparison signal EVCS, the code signal generation circuit 151 can generate first to fourth duty cycle signals DC<1:4> for adjusting the slope of the rising or falling interval of the internal strobe signal IDQS. The code signal generation circuit 151 can sequentially store the odd comparison signal ODCS and the even comparison signal EVCS, and can change the logic level combination of the first to fourth duty cycle signals DC<1:4> until the sequentially stored odd comparison signal ODCS and even comparison signal EVCS become the same. The code signal generation circuit 151 can sequentially store the odd comparison signal ODCS and the even comparison signal EVCS, and when the sequentially stored odd comparison signal ODCS and even comparison signal EVCS become the same, it can generate first to fourth duty cycle signals DC<1:4> with a fixed logic level combination.

[0046] The internal strobe signal generation circuit 152 can generate an internal strobe signal IDQS by adjusting the slope of the rising or falling interval of the input strobe signal IN_DQS based on the first to fourth duty cycle signals DC<1:4>. When the logic level combination of the first to fourth duty cycle signals DC<1:4> changes, the internal strobe signal generation circuit 152 can generate the internal strobe signal IDQS by adjusting the slope of the rising or falling interval of the input strobe signal IN_DQS. When the logic level combination of the first to fourth duty cycle signals DC<1:4> is fixed, the internal strobe signal generation circuit 152 can generate the internal strobe signal IDQS because the slope of the rising or falling interval of the input strobe signal IN_DQS is fixed. When the first to fourth duty cycle signals DC<1:4> are fixed, it indicates that the previously input first to fourth duty cycle signals DC<1:4> have not been counted upwards or downwards.

[0047] Figure 5 This is a block diagram illustrating the structure of one embodiment of the code signal generation circuit 151. (See diagram for example.) Figure 5 As shown, the code signal generation circuit 151 may include a comparison information generation circuit 210, a calibration control circuit (CAL CTR) 220, and a duty cycle code signal generation circuit (DC GEN) 230.

[0048] The comparison information generation circuit 210 may include a first register (first REG) 211, a second register (second REG) 212, a third register (third REG) 213, and a fourth register (fourth REG) 214. The first register 211 can continuously receive and store the odd comparison signal ODCS. By continuously receiving the odd comparison signal ODCS, the first register 211 can generate first to Mth odd comparison information signals OD_OP<1:M>. The second register 212 can continuously receive and store the even comparison signal EVCS. By continuously receiving the even comparison signal EVCS, the second register 212 can generate first to Mth even comparison information signals EV_OP<1:M>. The third register 213 can store optimized first to Mth odd comparison information signals OD_OP<1:M> and can output optimized first to Mth odd comparison information signals OD_OP<1:M>. The fourth register 214 can store optimized first to Mth even comparison information signals EV_OP<1:M> and can output optimized first to Mth even comparison information signals EV_OP<1:M>. The optimized first to Mth odd comparison information signals OD_OP<1:M> are stored when the first to fourth duty cycle signals DC<1:4> are fixed. The non-optimized first to Mth odd comparison information signals OD_OP<1:M> are stored when the first to fourth duty cycle signals DC<1:4> are counted up or down. The optimized first to Mth even comparison information signals EV_OP<1:M> are stored when the first to fourth duty cycle signals DC<1:4> are fixed. The non-optimized first to Mth even comparison information signals EV_OP<1:M> are stored when the first to fourth duty cycle signals DC<1:4> are counted up or down.

[0049] By continuously receiving the odd comparison signal ODCS, the comparison information generation circuit 210 can generate the first to the Mth odd comparison information signals OD_OP<1:M>. By receiving the first odd comparison signal ODCS, the comparison information generation circuit 210 can generate the first odd comparison information signal OD_OP. <1> By receiving the Mth odd comparison signal ODCS, the comparison information generation circuit 210 can generate the Mth odd comparison information signal OD_OP. <m>The comparison information generation circuit 210 can store the first to the Mth odd comparison information signals OD_OP<1:M>. By continuously receiving even comparison signals EVCS, the comparison information generation circuit 210 can generate the first to the Mth even comparison information signals EV_OP<1:M>. By receiving the first even comparison signal EVCS, the comparison information generation circuit 210 can generate the first even comparison information signal EV_OP. <1> By receiving the Mth even comparison signal EVCS, the comparison information generation circuit 210 can generate the Mth even comparison information signal EV_OP. <m>The comparison information generation circuit 210 can store the first to Mth even comparison information signals EV_OP<1:M>. The number of bits M for each of the first to Mth odd comparison information signals OD_OP<1:M> and the first to Mth even comparison information signals EV_OP<1:M> can be set to a natural number.

[0050] By comparing the absolute values ​​of the first to Mth odd comparison information signals OD_OP<1:M> with the absolute values ​​of the first to Mth even comparison information signals EV_OP<1:M>, the calibration control circuit 220 can generate a calibration control signal CAL_CTR and a calibration fixation signal CAL_FIX. When the absolute value of the first to Mth odd comparison information signals OD_OP<1:M> is less than the absolute value of the first to Mth even comparison information signals EV_OP<1:M>, the calibration control circuit 220 can generate an enabled calibration control signal CAL_CTR. When the absolute value of the first to Mth odd comparison information signals OD_OP<1:M> is greater than the absolute value of the first to Mth even comparison information signals EV_OP<1:M>, the calibration control circuit 220 can generate a disabled calibration control signal CAL_CTR. When the absolute values ​​of the first to Mth odd comparison information signals OD_OP<1:M> are the same as the absolute values ​​of the first to Mth even comparison information signals EV_OP<1:M>, the calibration control circuit 220 can generate an enabled calibration fixed signal CAL_FIX. The absolute value can be represented by the value obtained by converting the binary number to a decimal number.

[0051] The duty cycle signal generation circuit 230 can generate first to fourth duty cycle signals DC<1:4> with varying logic level combinations based on the calibration control signal CAL_CTR. When the calibration control signal CAL_CTR is enabled, the duty cycle signal generation circuit 230 can generate first to fourth duty cycle signals DC<1:4> that are sequentially counted upwards. When the calibration control signal CAL_CTR is disabled, the duty cycle signal generation circuit 230 can generate first to fourth duty cycle signals DC<1:4> that are sequentially counted downwards. When the calibration fixation signal CAL_FIX is enabled, the duty cycle signal generation circuit 230 can generate first to fourth duty cycle signals DC<1:4> with fixed logic level combinations. When the absolute values ​​of the first to Mth odd comparison information signals OD_OP<1:M> and the absolute values ​​of the first to Mth even comparison information signals EV_OP<1:M> are different, the calibration control circuit 220 can generate the disabled calibration fixation signal CAL_FIX.

[0052] Figure 6 This is a block diagram illustrating the structure of one embodiment of the calibration control circuit 220. (See diagram for example.) Figure 6 As shown, the calibration control circuit 220 may include an information comparison circuit (INF CMP) 221 and a calibration control signal generation circuit (CAL GEN) 222.

[0053] By comparing the absolute values ​​of the first to Mth odd comparison information signals OD_OP<1:M> with the absolute values ​​of the first to Mth even comparison information signals EV_OP<1:M>, the information comparison circuit 221 can generate a calibration comparison signal OP_CP and an optimization signal OPT. When the absolute value of the first to Mth odd comparison information signals OD_OP<1:M> is less than the absolute value of the first to Mth even comparison information signals EV_OP<1:M>, the information comparison circuit 221 can generate an enabled calibration comparison signal OP_CP. When the absolute value of the first to Mth odd comparison information signals OD_OP<1:M> is greater than the absolute value of the first to Mth even comparison information signals EV_OP<1:M>, the information comparison circuit 221 can generate a disabled calibration comparison signal OP_CP. When the absolute values ​​of the first to Mth odd comparison information signals OD_OP<1:M> are the same as the absolute values ​​of the first to Mth even comparison information signals EV_OP<1:M>, the information comparison circuit 221 can generate an enabled optimization signal OPT. When the absolute values ​​of the first to Mth odd comparison information signals OD_OP<1:M> are different from the absolute values ​​of the first to Mth even comparison information signals EV_OP<1:M>, the information comparison circuit 221 can generate an disabled optimization signal OPT.

[0054] Based on the calibration comparison signal OP_CP and the optimization signal OPT, the calibration control signal generation circuit 222 can generate the calibration control signal CAL_CTR and the calibration fixation signal CAL_FIX. When the calibration comparison signal OP_CP is enabled, the calibration control signal generation circuit 222 can generate the enabled calibration control signal CAL_CTR. When the calibration comparison signal OP_CP is disabled, the calibration control signal generation circuit 222 can generate the disabled calibration control signal CAL_CTR. When the optimization signal OPT is enabled, the calibration control signal generation circuit 222 can generate the enabled calibration fixation signal CAL_FIX. When the optimization signal OPT is disabled, the calibration control signal generation circuit 222 can generate the disabled calibration fixation signal CAL_FIX.

[0055] Figure 7 This is a block diagram illustrating the structure of one embodiment of the duty cycle signal generation circuit 230. (See diagram for example.) Figure 7 As shown, the duty cycle code signal generation circuit 230 may include a control signal generation circuit 231 and a code control circuit (CODE CTR) 232.

[0056] Based on the calibration control signal CAL_CTR, the control signal generation circuit 231 can generate the addition control signal AD_CTR and the subtraction control signal SB_CTR. When the calibration control signal CAL_CTR is enabled, the control signal generation circuit 231 can generate the enabled addition control signal AD_CTR. When the calibration control signal CAL_CTR is disabled, the control signal generation circuit 231 can generate the enabled subtraction control signal SB_CTR.

[0057] Based on the addition control signal AD_CTR and the subtraction control signal SB_CTR, the code control circuit 232 can generate first to fourth duty cycle signals DC<1:4> with adjusted logic level combinations. When the addition control signal AD_CTR is enabled, the code control circuit 232 can generate first to fourth duty cycle signals DC<1:4> that are sequentially counted upwards. When the subtraction control signal SB_CTR is enabled, the code control circuit 232 can generate first to fourth duty cycle signals DC<1:4> that are sequentially counted downwards. Based on the calibration fixed signal CAL_FIX, the code control circuit 232 can generate first to fourth duty cycle signals DC<1:4>. When the calibration fixed signal CAL_FIX is enabled, the code control circuit 232 can generate first to fourth duty cycle signals DC<1:4> with fixed logic level combinations. When the first to fourth duty cycle signals DC<1:4> are fixed, it indicates that the previously generated first to fourth duty cycle signals DC<1:4> have not been counted upwards or downwards.

[0058] Figure 8 This is a block diagram illustrating the structure of one embodiment of the internal gating signal generation circuit 152. (See diagram for example.) Figure 8 As shown, the internal strobe signal generation circuit 152 may include an inverting circuit 310 and an internal strobe signal driving circuit 320. The internal strobe signal driving circuit 320 may include a first driver 321, a first transfer strobe signal generation circuit 322, a second transfer strobe signal generation circuit 323, and a second driver 324.

[0059] The inverter circuit 310 can be implemented as an inverter 311. By inverting the first to fourth duty cycle signals DC<1:4>, the inverter circuit 310 can generate the first to fourth inverted duty cycle signals DCB<1:4>. The inverter circuit 310 is implemented as a single inverter, but it can be implemented as four inverters that invert the first to fourth duty cycle signals DC<1:4>.

[0060] Based on the logic level of the input strobe signal IN_DQS, the first driver 321 can drive the first node nd31. When the level of the input strobe signal IN_DQS is logic low, the first driver 321 can drive the first node nd31 to logic low. When the level of the input strobe signal IN_DQS is logic high, the first driver 321 can drive the first node nd31 to logic high.

[0061] The first pass gating signal generation circuit 322 can be implemented as a first PMOS transistor 322_1 and a second PMOS transistor 322_2 connected in series between the power supply voltage VDD and the second node nd32, and a first NMOS transistor 322_3 and a second NMOS transistor 322_4 connected in series between the second node nd32 and the ground voltage VSS.

[0062] The first pass strobe signal generation circuit 322 may have a drive power adjusted based on the logic level combination of the first to fourth duty cycle signals DC<1:4>, and when the level of the first node nd31 is logic low, by driving the second node nd32 to the level of the power supply voltage VDD with the adjusted drive power, a first pass strobe signal TDQS1 with a logic high level can be generated. The first pass strobe signal generation circuit 322 may have a drive power adjusted based on the logic level combination of the first to fourth duty cycle signals DC<1:4>, and when the level of the first node nd31 is logic high, by driving the second node nd32 to the level of the ground voltage VSS with the adjusted drive power, a first pass strobe signal TDQS1 with a logic low level can be generated.

[0063] The first PMOS transistor 322_1 is implemented as a single PMOS transistor, but four PMOS transistors receiving the first to fourth duty cycle signals DC<1:4> can be connected in parallel and implemented to form the first PMOS transistor 322_1. As the number of logic low levels among the bits included in the first to fourth duty cycle signals DC<1:4> increases, the drive power of the first PMOS transistor 322_1 can increase. The second NMOS transistor 322_4 is implemented as a single NMOS transistor, but four NMOS transistors receiving the first to fourth duty cycle signals DC<1:4> can be connected in parallel and implemented to form the second NMOS transistor 322_4. As the number of logic high levels among the bits included in the first to fourth duty cycle signals DC<1:4> increases, the drive power of the second NMOS transistor 322_4 can increase.

[0064] The second pass gating signal generation circuit 323 can be implemented as a third PMOS transistor 323_1 and a fourth PMOS transistor 323_2 connected in series between the power supply voltage VDD and the third node nd33, and a third NMOS transistor 323_3 and a fourth NMOS transistor 323_4 connected in series between the third node nd33 and the ground voltage VSS.

[0065] The second pass strobe signal generation circuit 323 may have a drive power adjusted based on the logic level combination of the first to fourth inverted duty code signals DCB<1:4>, and when the level of the second node nd32 is logic low, by driving the third node nd33 to the level of the power supply voltage VDD with the adjusted drive power, a second pass strobe signal TDQS2 with a logic high level can be generated. The second pass strobe signal generation circuit 323 may have a drive power adjusted based on the logic level combination of the first to fourth inverted duty code signals DCB<1:4>, and when the level of the second node nd32 is logic high, by driving the third node nd33 to the level of the ground voltage VSS with the adjusted drive power, a second pass strobe signal TDQS2 with a logic low level can be generated.

[0066] The third PMOS transistor 323_1 is implemented as a single PMOS transistor, but the four PMOS transistors receiving the first to fourth inverted duty cycle signals DCB<1:4> can be connected in parallel and implemented to form the third PMOS transistor 323_1. As the number of logic low levels among the bits included in the first to fourth inverted duty cycle signals DCB<1:4> increases, the drive power of the third PMOS transistor 323_1 can be increased. The fourth NMOS transistor 323_4 is implemented as a single NMOS transistor, but the four NMOS transistors receiving the first to fourth inverted duty cycle signals DCB<1:4> can be connected in parallel and implemented to form the fourth NMOS transistor 323_4. As the number of logic high levels among the bits included in the first to fourth inverted duty cycle signals DCB<1:4> increases, the drive power of the fourth NMOS transistor 323_4 can be increased.

[0067] Based on the logic level of the second pass strobe signal TDQS2, the second driver 324 can drive the internal strobe signal IDQS. When the level of the second pass strobe signal TDQS2 is logic low, the second driver 324 can drive the internal strobe signal IDQS to logic low. When the level of the second pass strobe signal TDQS2 is logic high, the second driver 324 can drive the internal strobe signal IDQS to logic high.

[0068] refer to Figure 9 The operation of adjusting the duty cycle of the internal strobe signal IDQS by the internal strobe signal generation circuit 152 according to an embodiment of the present disclosure is described below.

[0069] Before the description, the input strobe signal IN_DQS can be input as interval A, which is 45% of the set interval TD, having a logic high level, and interval A', which is 55% of the set interval TD. That is, the interval with a logic high level is shorter than the interval with a logic low level.

[0070] First, the first to fourth duty cycle signals DC<1:4> are fixed ( Figure 9 The case of the solid line in the middle is described as follows.

[0071] The first driver 321 can drive the first node nd31 to a logic high level when the level of the input strobe signal IN_DQS is logic high, and can drive the first node nd31 to a logic low level when the level of the input strobe signal IN_DQS is logic low.

[0072] The first pass strobe signal generation circuit 322 may have a fixed drive power based on a fixed combination of logic levels of the first to fourth duty code signals DC<1:4>, and when the level of the first node nd31 is logic high, the first pass strobe signal TDQS1 with a logic low level can be generated by driving the second node nd32 to the level of the ground voltage VSS with the help of the fixed drive power.

[0073] The first pass strobe signal generation circuit 322 may have a fixed drive power based on a fixed combination of logic levels of the first to fourth duty code signals DC<1:4>, and when the level of the first node nd31 is logic low, the first pass strobe signal TDQS1 with a logic high level can be generated by driving the second node nd32 to the level of the power supply voltage VDD with the help of the fixed drive power.

[0074] The second pass strobe signal generation circuit 323 may have a fixed drive power based on the logic level combination of the first to fourth inverted duty code signals DCB<1:4> which are inverted from the fixed first to fourth duty code signals DC<1:4>, and when the level of the second node nd32 is logic low, the third node nd33 can be driven to the level of the power supply voltage VDD by means of the fixed drive power to generate a second pass strobe signal TDQS2 with a logic high level.

[0075] The second pass strobe signal generation circuit 323 may have a fixed drive power based on the logic level combination of the first to fourth inverted duty code signals DCB<1:4> which are inverted from the fixed first to fourth duty code signals DC<1:4>, and when the level of the second node nd32 is logic high, the third node nd33 can be driven to the level of the ground voltage VSS by means of the fixed drive power to generate the second pass strobe signal TDQS2 with a logic low level.

[0076] When the level of the second pass strobe signal TDQS2 is logic high, the second driver 324 can drive the internal strobe signal IDQS to logic high. When the level of the second pass strobe signal TDQS2 is logic low, the second driver 324 can drive the internal strobe signal IDQS to logic low.

[0077] That is, the interval B where the level of the internal strobe signal IDQS is logic high can be made the same as the interval where the level of the input strobe signal IN_DQS is logic high (i.e., B = A).

[0078] Count upwards for the first to fourth duty cycle signals DC<1:4>. Figure 9 The case of the dashed line in the image is described as follows.

[0079] The first driver 321 can drive the first node nd31 to a logic high level when the level of the input strobe signal IN_DQS is logic high, and can drive the first node nd31 to a logic low level when the level of the input strobe signal IN_DQS is logic low.

[0080] The first pass strobe signal generation circuit 322 can have increased drive power based on the logic level combination of the first to fourth duty code signals DC<1:4> that have been counted upwards, and when the level of the first node nd31 is logic high, the second node nd32 can be driven to the level of the ground voltage VSS by means of the increased drive power to generate a first pass strobe signal TDQS1 with a logic low level. At this time, the falling interval of the second node nd32 decreases rapidly ( Figure 9 (rapid decline in the middle).

[0081] The first pass strobe signal generation circuit 322 can have reduced drive power based on the logic level combination of the first to fourth duty code signals DC<1:4> that have been counted upwards, and when the level of the first node nd31 is logic low, the first pass strobe signal TDQS1 with a logic high level can be generated by driving the second node nd32 to the level of the power supply voltage VDD with the help of the reduced drive power. At this time, the rising interval of the second node nd32 rises slowly ( Figure 9 (A slow rise in the middle).

[0082] The second pass strobe signal generation circuit 323 can have increased drive power based on the logic level combination of the first to fourth inverted duty code signals DCB<1:4>, which are inverted from the first to fourth duty code signals DC<1:4> that have been counted upwards. When the level of the second node nd32 is logic low, the third node nd33 can be driven to the level of the power supply voltage VDD by the increased drive power to generate a second pass strobe signal TDQS2 with a logic high level. At this time, the rising interval of the third node nd33 rises rapidly (…). Figure 9 (rapid rise in the middle).

[0083] The second pass strobe signal generation circuit 323 can have reduced drive power based on the logic level combination of the first to fourth inverted duty code signals DCB<1:4>, which are inverted from the first to fourth duty code signals DC<1:4> that have been counted upwards. When the level of the second node nd32 is logic high, the third node nd33 can be driven to the level of the ground voltage VSS by means of the reduced drive power to generate a second pass strobe signal TDQS2 with a logic low level. At this time, the falling interval of the third node nd33 slowly decreases (…). Figure 9 (a slow decline in the middle).

[0084] When the level of the second pass strobe signal TDQS2 is logic high, the second driver 324 can drive the internal strobe signal IDQS to logic high. At this time, the rising range of the internal strobe signal IDQS rises rapidly ( Figure 9 (Rapid rise in the middle). When the level of the second pass strobe signal TDQS2 is logic low, the second driver 324 can drive the internal strobe signal IDQS to logic low. At this time, the falling range of the internal strobe signal IDQS slowly decreases ( Figure 9 (a slow decline in the middle).

[0085] That is, as the rising interval of the internal strobe signal IDQS rises rapidly and its falling interval falls slowly, the interval C of the internal strobe signal IDQS being at a logic high level further increases or has a longer duration than the interval A of the input strobe signal IN_DQS being at a logic high level (i.e., C>A).

[0086] Figure 10 This is a block diagram illustrating the structure of one embodiment of the second semiconductor device 20. (See diagram for example.) Figure 10 As shown, the second semiconductor device 20 may include a clock buffer (CLK BUF) 410, a clock delay circuit (CLK DELAY) 420, a clock duty cycle adjustment circuit (CLK DUTY CTR) 430, a core circuit (CORE) 440, a serial converter circuit (SR) 450, a data driver (DATA DRV) 460, and a strobe signal driver (DQS DRV) 470.

[0087] Clock buffer 410 can generate input clock IN_CLK by receiving clock CLK. Clock buffer 410 can generate input clock IN_CLK by buffering clock CLK.

[0088] The clock delay circuit 420 can generate a delayed clock DCLK based on the input clock IN_CLK. The clock delay circuit 420 can generate the delayed clock DCLK by delaying the input clock IN_CLK. In different embodiments, the delay amount of the clock delay circuit 420 can be set differently.

[0089] The clock duty cycle adjustment circuit 430 can generate the internal clock ICLK by adjusting the duty cycle of the delayed clock DCLK, which has been modified by the clock buffer 410 and the clock delay circuit 420. The clock duty cycle adjustment circuit 430 can be implemented as a common duty cycle corrector (DCC) for similarly adjusting the logic high and low levels of the delayed clock DCLK.

[0090] After a write operation begins, the core circuit 440 can store the first to sixteenth mode data PD<1:16>. When the write signal WT for performing the write operation is enabled, the core circuit 440 can store the first to sixteenth mode data PD<1:16>. After a read operation begins, the core circuit 440 can output the stored first to sixteenth mode data PD<1:16> as the first to sixteenth internal data ID<1:16>. When the read signal RD for performing the read operation is enabled, the core circuit 440 can output the stored first to sixteenth mode data PD<1:16> as the first to sixteenth internal data ID<1:16>. The core circuit 440 can be implemented as a general memory circuit including multiple memory cells.

[0091] The serial conversion circuit 450 can generate first to sixteenth serial data SD<1:16> based on the first to sixteenth internal data IDs<1:16> in sync with the internal clock ICLK. By performing serial conversion on the parallel-input first to sixteenth internal data IDs<1:16> in sync with the rising and falling intervals of the internal clock ICLK, the serial conversion circuit 450 can generate first to sixteenth serial data SD<1:16>. The serial conversion circuit 450 can be implemented as a general-purpose serializer.

[0092] Data driver 460 can generate first to sixteenth output data DOUT<1:16> based on first to sixteenth serial data SD<1:16>. Data driver 460 can output first to sixteenth output data DOUT<1:16> by driving the first to sixteenth output data DOUT<1:16> with logic levels based on the first to sixteenth serial data SD<1:16>.

[0093] Based on the internal clock ICLK, the strobe driver 470 can generate a strobe signal DQS. By driving the strobe signal DQS with a logic level based on the internal clock ICLK, the strobe driver 470 can output the strobe signal DQS.

[0094] refer to Figure 11 The duty cycle adjustment operation based on the logic level combination of the first to fourth duty code signals DC<1:4> according to an embodiment of the present disclosure is described below.

[0095] The first to fourth duty cycle signals DC<1:4> can be implemented as four bits, and the duty cycle can be adjusted with a total of 16 levels. For example, if all four duty cycle signals DC<1:4> are counted down and all their bits are at logic low, the duty cycle can be adjusted to -8Δ. If all four duty cycle signals DC<1:4> are counted up and all their bits are at logic high, the duty cycle can be adjusted to +7Δ.

[0096] When the first to fourth duty cycle signals DC<1:4> count upwards once, the duty cycle can increase by +1Δ. When the first to fourth duty cycle signals DC<1:4> count downwards once, the duty cycle can decrease by -1Δ.

[0097] In different embodiments, the duty cycle can be adjusted in various ways in proportion to the number of bits in the duty cycle code signal during the duty cycle adjustment operation.

[0098] refer to Figure 12 The operation of strobing the first to sixteenth input data IN_D<1:16> synchronously with the rising interval of the internal strobe signal IDQS is described as follows.

[0099] First, if the duty cycles of the internal strobe signal IDQS are the same, then when the first to sixteenth input data IN_D<1:16> are selected synchronously with the rising interval of the internal strobe signal IDQS, the interval where the level of the internal strobe signal IDQS is generated as a logic high level becomes the effective window VW1 of the data. That is, if the duty cycles of the internal strobe signal IDQS are the same, the effective window VW1 of the data can be optimized.

[0100] Next, if the duty cycles of the internal strobe signal IDQS are different and the internal strobe signal IDQS drops rapidly from logic high to logic low, then when the first to sixteenth input data IN_D<1:16> are selected synchronously with the rising interval of the internal strobe signal IDQS, the interval during which the level of the internal strobe signal IDQS is generated as logic high is reduced, thus reducing the effective window of the corresponding data (i.e., VW2). In other words, if the duty cycles of the internal strobe signal IDQS are different, the effective window of the data is reduced.

[0101] Next, if the duty cycles of the internal strobe signal IDQS are different and IDQS slowly rises to a logic high level, when the first to sixteenth input data IN_D<1:16> are selected synchronously with the rising interval of the internal strobe signal IDQS, the interval during which the internal strobe signal IDQS is generated as a logic high level decreases, thus reducing the effective window of the corresponding data (i.e., VW3). In other words, if the duty cycles of the internal strobe signal IDQS are different, the effective window of the data decreases.

[0102] That is, if the duty cycle of the internal strobe signal IDQS is different, the duty cycle of the internal strobe signal IDQS needs to be adjusted because the effective window of the data is reduced and thus data errors occur.

[0103] According to an embodiment of the present disclosure, such a semiconductor system 1 can prevent or reduce data errors by performing an operation to adjust the duty cycle of the gating signal for gating data in each semiconductor device. By gating data in a manner that performs an operation to adjust the duty cycle of the gating signal for gating data in each semiconductor device, the semiconductor system 1 according to an embodiment of the present disclosure can guarantee a valid window for data.

[0104] refer to Figure 13 The duty cycle adjustment operation of a semiconductor system 1 according to an embodiment of the present disclosure is described below.

[0105] The duty cycle adjustment operation may include the duty cycle adjustment operation entry step S11, the duty code signal setting step S12, the reading and comparison step S13, the comparison information generation step S14, the duty cycle detection step S15, the comparison information comparison step S16, the up counting step S17, the down counting step S18, and the duty cycle adjustment operation completion step S19.

[0106] The duty cycle adjustment operation entry step S11 can be set as the step of entering the operation of adjusting the duty cycle of the strobe signal DQS.

[0107] The duty cycle signal setting step S12 can be configured to set the logic level combination of the first to fourth duty cycle signals DC<1:4> to 8 (i.e., the initial value). The initial value 8 of the first to fourth duty cycle signals DC<1:4> can be set to "0111". The initial value "0111" of the first to fourth duty cycle signals DC<1:4> can represent the first duty cycle signal DC<1:4>. <1> The level is logic high "1", the second duty cycle signal DC. <2> The level is logic high "1", the third duty cycle signal DC. <3> The level is logic high "1" and the fourth duty cycle signal DC <4> The level is the logic low level "0".

[0108] The reading and comparison step S13 can be configured to operate as follows: output the first to sixteenth output data DOUT<1:16> and the strobe signal DQS through the second semiconductor device 20; and compare the first to eighth odd data OD_D<1:8> and the first to eighth even data EV_D<1:8> generated from the first to sixteenth output data DOUT<1:16> with the first to sixteenth mode data PD<1:16> through the first semiconductor device 10.

[0109] The comparison information generation step S14 can be configured to include the following steps: generating the first to Mth odd comparison information signals OD_OP<1:M> from the odd comparison signals ODCS generated by comparing the first to eighth odd data OD_D<1:8> with the first to sixteenth pattern data PD<1:16>; and generating the first to Mth even comparison information signals EV_OP<1:M> from the even comparison signals EVCS generated by comparing the first to eighth even data EV_D<1:8> with the first to sixteenth pattern data PD<1:16>.

[0110] The duty cycle detection step S15 can be configured to detect the difference between the first to Mth odd comparison information signals OD_OP<1:M> and the first to Mth even comparison information signals EV_OP<1:M>. In the duty cycle detection step S15, if there is a difference (no) between the first to Mth odd comparison information signals OD_OP<1:M> and the first to Mth even comparison information signals EV_OP<1:M>, the duty cycle adjustment operation can proceed to the comparison information comparison step S16. In the duty cycle detection step S15, if there is no difference (yes) between the first to Mth odd comparison information signals OD_OP<1:M> and the first to Mth even comparison information signals EV_OP<1:M>, the duty cycle adjustment operation can proceed to the duty cycle adjustment operation completion step S19.

[0111] The comparison information comparison step S16 can be set to proceed to the up counting step S17 or the down counting step S18 based on the comparison result between the first to the Mth odd comparison information signals OD_OP<1:M> and the first to the Mth even comparison information signals EV_OP<1:M>.

[0112] The upward counting step S17 can be configured as follows: when the absolute value of the first to Mth odd comparison information signals OD_OP<1:M> is less than the absolute value of the first to Mth even comparison information signals EV_OP<1:M> in the comparison information comparison step S16 (yes), the first to fourth duty cycle signals DC<1:4> are counted upwards. In the upward counting step S17, the first to fourth duty cycle signals DC<1:4> can be counted upwards from the initial value "0111", therefore the first to fourth duty cycle signals DC<1:4> can be generated as "1000". The first to fourth duty cycle signals DC<1:4> "1000" can represent the first duty cycle signal DC<1:4>. <1> The level is logic low "0" and the second duty cycle signal DC. <2> The level is logic low "0" and the third duty cycle signal DC. <3> The level is logic low "0" and the fourth duty cycle signal DC <4> The level is logic high "1". When the up-counting step S17 terminates, the duty cycle adjustment operation can re-enter the read and compare step S13.

[0113] The down-counting step S18 can be configured as follows: when the absolute value of the first to Mth odd comparison information signals OD_OP<1:M> is greater than the absolute value of the first to Mth even comparison information signals EV_OP<1:M> (no) in the comparison information comparison step S16, the first to fourth duty cycle signals DC<1:4> are counted down. In the down-counting step S18, the first to fourth duty cycle signals DC<1:4> can be counted down from the initial value "0111", therefore the first to fourth duty cycle signals DC<1:4> can be generated as "0110". The first to fourth duty cycle signals DC<1:4> "0110" can represent the first duty cycle signal DC<1:4>. <1> The level is logic low "0" and the second duty cycle signal DC. <2> The level is logic high "1" and the third duty cycle signal DC. <3> The level is logic high "1" and the fourth duty cycle signal DC <4> The level is logic low "0". When the down-counting step S18 terminates, the duty cycle adjustment operation can re-enter the read and compare step S13.

[0114] The duty cycle adjustment operation completion step S19 can be set to the following operation: when the first to the Mth odd comparison information signals OD_OP<1:M> and the first to the Mth even comparison information signals EV_OP<1:M> have the same logic level combination (yes), the first to the fourth duty code signals DC<1:4> are fixed.

[0115] According to an embodiment of the present disclosure, such a semiconductor system 1 can prevent or reduce data errors by performing an operation to adjust the duty cycle of the gating signal for gating data in each semiconductor device. By gating data in a manner that performs an operation to adjust the duty cycle of the gating signal for gating data in each semiconductor device, the semiconductor system 1 according to an embodiment of the present disclosure can guarantee a valid window for data.

[0116] Figure 14 This is a block diagram illustrating the structure of an embodiment of an electronic system 1000 according to an embodiment of the present disclosure. (See diagram for details.) Figure 14 As shown, the electronic system 1000 may include a host 1100 and a semiconductor system 1200.

[0117] The host 1100 and the semiconductor system 1200 can send interactive signals using an interface protocol. The interface protocol used between the host 1100 and the semiconductor system 1200 may include Multimedia Card (MMC), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Peripheral Component Interconnect Fast (PCI-E), Advanced Technology Accessories (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), and Universal Serial Bus (USB), etc.

[0118] Semiconductor system 1200 may include controller 1300 and semiconductor devices 1400 (K:1). Controller 1300 can prevent data errors by receiving data and a gating signal from semiconductor devices 1400 (K:1) and performing an operation to adjust the duty cycle of the gating signal for the gating data in each semiconductor device. By gating data in a manner that adjusts the duty cycle of the gating signal for the gating data in each semiconductor device, controller 1300 can guarantee a valid data window. In one embodiment, each semiconductor device 1400 (K:1) can prevent or reduce data errors by receiving data and a clock from controller 1300 and performing an operation to adjust the duty cycle of the clock for the gating data in each semiconductor device. In one embodiment, by gating data in a manner that adjusts the duty cycle of the gating signal for the gating data in each semiconductor device, each semiconductor device 1400 (K:1) can guarantee a valid data window.

[0119] Controller 1300 can be implemented as Figure 1 The first semiconductor device 10 is shown. Each semiconductor device 1400 (K:1) can be implemented as Figure 1 The second semiconductor device 20 is shown. In some embodiments, the semiconductor device 20 may be implemented as one of dynamic random access memory (DRAM), phase change random access memory (PRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), and ferroelectric random access memory (FRAM).< / m> < / m>

Claims

1. A semiconductor device, comprising: A data comparison circuit generates an odd comparison signal by comparing odd data generated from input data synchronously with bits included in pattern data, and generates an even comparison signal by comparing even data generated from input data synchronously with bits included in pattern data. as well as A strobe signal duty cycle adjustment circuit adjusts the duty cycle of the internal strobe signal for latching the input data based on the odd comparison signal and the even comparison signal.

2. The semiconductor device according to claim 1, wherein: The odd data is generated from the bits included in the input data that are synchronized with the rising interval of the internal strobe signal. The even data is generated from the bits included in the input data that are input in a falling interval synchronized with the internal strobe signal.

3. The semiconductor device according to claim 1, wherein, After the read operation begins, the pattern data is generated as a preset combination of logic levels.

4. The semiconductor device according to claim 1, wherein, The data comparison circuit includes: An odd comparison circuit generates the odd comparison signal by comparing the odd data with bits of odd numbers included in the pattern data; and An even comparison circuit generates the even comparison signal by comparing the even data with the even number bits included in the pattern data.

5. The semiconductor device according to claim 1, wherein, The strobe signal duty cycle adjustment circuit adjusts the duty cycle based on the odd comparison signal and the even comparison signal by adjusting the slope of one of the rising and falling intervals of the internal strobe signal.

6. The semiconductor device according to claim 1, wherein, The duty cycle adjustment circuit adjusts the strobe signal duty cycle by adjusting the slope of one of the rising and falling intervals of the internal strobe signal until the odd comparison signal and the even comparison signal become the same as each other.

7. The semiconductor device according to claim 1, wherein, The gating signal duty cycle adjustment circuit includes: A code signal generation circuit, which generates a duty cycle code signal based on the odd comparison signal and the even comparison signal to adjust the slope of one of the rising and falling intervals of the internal strobe signal; and An internal gating signal generation circuit generates the internal gating signal by adjusting the slope of one of the rising and falling intervals of the input gating signal based on the duty cycle signal.

8. The semiconductor device according to claim 7, wherein, The code signal generation circuit includes: A comparison information generation circuit generates an odd comparison information signal by continuously receiving the odd comparison signal, and generates an even comparison information signal by continuously receiving the even comparison signal; A calibration control circuit generates a calibration control signal and a calibration fixation signal by comparing the absolute values ​​of the odd comparison information signals and the absolute values ​​of the even comparison information signals; and A duty cycle signal generation circuit generates a duty cycle signal comprising a combination of changed logic levels based on the calibration control signal, and generates a duty cycle signal comprising a combination of fixed logic levels based on the calibration fixation signal.

9. The semiconductor device according to claim 8, wherein, The comparison information generation circuit stores the odd comparison information signal and the even comparison information signal when they are the same.

10. The semiconductor device according to claim 8, wherein, The calibration control circuit includes: An information comparison circuit generates a calibration comparison signal and an optimization signal by comparing the absolute values ​​of the odd comparison information signals and the absolute values ​​of the even comparison information signals; and A calibration control signal generation circuit generates the calibration control signal based on the calibration comparison signal, and generates the calibration fixation signal based on the optimization signal.

11. The semiconductor device according to claim 8, wherein, The duty cycle signal generation circuit includes: A control signal generation circuit that generates an addition control signal when the calibration control signal is enabled, and generates a subtraction control signal when the calibration control signal is disabled; and The code control circuit generates the duty cycle signal that counts sequentially upwards when the addition control signal is enabled and counts sequentially downwards when the subtraction control signal is disabled, and generates the duty cycle signal including a fixed combination of logic levels when the calibration fixation signal is enabled.

12. The semiconductor device according to claim 7, wherein, The internal gating signal generation circuit includes: A first driver drives a first node based on the logic level of the input strobe signal; A first pass gating signal generation circuit generates a first pass gating signal by driving a second node based on the logic level of the first node, and has a drive power for driving the second node adjusted based on the logic level combination of the duty code signal. A second pass gating signal generation circuit generates a second pass gating signal by driving a third node based on the logic level of the second node, and has a drive power for driving the third node adjusted based on a combination of logic levels of an inverted duty cycle signal; and The second driver generates the internal strobe signal based on the logic level of the second pass strobe signal.

13. A semiconductor system, comprising: A first semiconductor device outputs clock and mode data, receives a strobe signal and outputs data, and adjusts the duty cycle of the strobe signal by comparing odd and even data generated from the output data synchronously with the mode data. as well as A second semiconductor device stores the mode data synchronously with the clock, outputs the clock as the strobe signal by adjusting the duty cycle of the clock, and outputs the stored mode data as the output data.

14. The semiconductor system of claim 13, wherein: The first semiconductor device is implemented as a controller, which controls the operation of the second semiconductor device, and The second semiconductor device is implemented as a non-volatile memory device.

15. The semiconductor system of claim 13, wherein: The odd data is generated from the bits included in the output data that are synchronized with the rising interval of the internal strobe signal generated by adjusting the duty cycle of the strobe signal and are input bits. The even data is generated from the bits included in the output data that are synchronized with the falling interval of the internal strobe signal generated by adjusting the duty cycle of the strobe signal and are input bits.

16. The semiconductor system of claim 13, wherein, The first semiconductor device adjusts the duty cycle of the strobe signal by comparing the mode data generated as a preset logic level combination after the start of the write operation with the odd data and the even data generated from the output data after the start of the read operation.

17. The semiconductor system of claim 13, wherein, The first semiconductor device includes: A data delay circuit that generates input data by delaying the output data after the read operation begins; A strobe delay circuit generates an input strobe signal by delaying the strobe signal after the start of the read operation; A parallel conversion circuit that generates odd data based on bits included in the input data in sync with the rising interval of the internal gating signal, and generates even data based on bits included in the input data in sync with the falling interval of the internal gating signal. A data comparison circuit generates an odd comparison signal and an even comparison signal by comparing the odd data with the pattern data and the even data with the pattern data, respectively; and A gating signal duty cycle adjustment circuit adjusts the duty cycle of the internal gating signal based on the odd comparison signal and the even comparison signal for gating the input data.

18. The semiconductor system of claim 17, wherein, The data comparison circuit includes: An odd comparison circuit generates the odd comparison signal by comparing the odd data with bits of odd numbers included in the pattern data; and An even comparison circuit generates the even comparison signal by comparing the even data with the even number bits included in the pattern data.

19. The semiconductor system of claim 17, wherein, The strobe signal duty cycle adjustment circuit adjusts the duty cycle based on the odd comparison signal and the even comparison signal by adjusting the slope of one of the rising and falling intervals of the internal strobe signal.

20. The semiconductor system of claim 17, wherein, The gating signal duty cycle adjustment circuit includes: A code signal generation circuit that generates a duty cycle code signal based on the odd comparison signal and the even comparison signal to adjust the slope of one of the rising and falling intervals of the internal strobe signal; and An internal strobe signal generation circuit generates the internal strobe signal by adjusting the slope of one of the rising and falling intervals of the input strobe signal based on the duty cycle signal.

21. The semiconductor system of claim 20, wherein, The code signal generation circuit includes: A comparison information generation circuit generates an odd comparison information signal by continuously receiving the odd comparison signal, and generates an even comparison information signal by continuously receiving the even comparison signal; A calibration control circuit generates a calibration control signal and a calibration fixation signal by comparing the absolute values ​​of the odd comparison information signals and the absolute values ​​of the even comparison information signals; and A duty cycle signal generation circuit generates a duty cycle signal comprising a combination of changed logic levels based on the calibration control signal, and generates a duty cycle signal comprising a combination of fixed logic levels based on the calibration fixation signal.

22. The semiconductor system of claim 21, wherein, The comparison information generation circuit stores the odd comparison information signal and the even comparison information signal when they are the same.

23. The semiconductor system of claim 21, wherein, The calibration control circuit includes: An information comparison circuit generates a calibration comparison signal and an optimization signal by comparing the absolute values ​​of the odd comparison information signals and the absolute values ​​of the even comparison information signals; and A calibration control signal generation circuit generates the calibration control signal based on the calibration comparison signal, and generates the calibration fixation signal based on the optimization signal.

24. The semiconductor system of claim 21, wherein, The duty cycle signal generation circuit includes: A control signal generation circuit that generates an addition control signal when the calibration control signal is enabled, and generates a subtraction control signal when the calibration control signal is disabled; and The code control circuit generates the duty cycle signal that counts sequentially upwards when the addition control signal is enabled and counts sequentially downwards when the subtraction control signal is disabled, and generates the duty cycle signal including a fixed combination of logic levels when the calibration fixation signal is enabled.

25. The semiconductor system of claim 20, wherein, The internal gating signal generation circuit includes: A first driver drives a first node based on the logic level of the input strobe signal; A first pass gating signal generation circuit generates a first pass gating signal by driving a second node based on the logic level of the first node, and has a drive power for driving the second node adjusted based on the logic level combination of the duty code signal. A second pass gating signal generation circuit generates a second pass gating signal by driving a third node based on the logic level of the second node, and has a drive power for driving the third node adjusted based on a combination of logic levels of an inverted duty cycle signal; and The second driver generates the internal strobe signal based on the logic level of the second pass strobe signal.

26. The semiconductor system of claim 13, wherein, The second semiconductor device includes: A clock buffer that generates an input clock by receiving the clock; A clock delay circuit that generates a delayed clock by delaying the input clock; A clock duty cycle adjustment circuit generates an internal clock by adjusting the duty cycle of the delayed clock; The core circuit stores the pattern data after the write operation begins, and outputs the stored pattern data as internal data after the read operation begins. A serial conversion circuit that generates serial data based on the internal data in sync with the internal clock. A data driver that receives the serial data and outputs the received serial data as the output data; and A strobe driver that receives the internal clock and outputs the received internal clock as the strobe signal.

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