Method for improving hard mask layer peeling in polysilicon gate layer etching

Abstract

The application provides a method for improving peeling of a hard mask layer in polysilicon gate layer etching, which comprises the following steps: providing a substrate, wherein the substrate comprises a storage area and a peripheral logic area, and gate oxide layers are formed on the storage area and the peripheral logic area; forming, on the gate oxide layer of the storage area structure, a floating gate, an inter-electrode dielectric layer, a control gate and a first hard mask layer in sequence from bottom to top; forming, on the storage area, a first side wall structure, a second side wall structure, a tunneling oxide layer, a select gate, a select gate oxide layer and a second hard mask layer; forming a polysilicon gate layer on the storage area and the peripheral logic area; patterning the polysilicon gate layer by using photolithography and etching to form a gate structure on the peripheral logic area; forming a side wall material layer on the storage area and the peripheral logic area, forming a protection layer on the side wall material layer, and forming a second photoresist layer on the protection layer. The application can solve the problem of peeling of the hard mask layer after the polysilicon gate layer etching caused by the cell step difference.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for improving the removal of hard mask layers during the etching of polysilicon gate layers. Background Technology

[0002] In embedded flash memory processes at both the 90nm and 55nm technology nodes, the hard mask for the polysilicon gate layer is made of oxide and can be removed with HF after etching.

[0003] In the 40nm embedded flash memory process, the polysilicon gate layer hard mask is APF (Advanced Thin Film) + Darc (Dielectric Anti-Reflection Coating). After etching, Darc peeling will occur on the cell sidewalls for the following reasons: Etching the polysilicon gate layer requires defining the APF size using nitrogen-free Darc, which defines the polysilicon gate layer size.

[0004] Referring to the embedded flash memory processes of the 90nm and 55nm technology nodes, after the cell etching and SiN hard mask removal, the polysilicon gate layer etching results in a large step difference in the cell region. After the APF and Darc are formed, sidewalls will be formed on both sides of the cell. The etching of the polysilicon gate layer is anisotropic. The APF and Darc on the gate structure surface can be removed, but the APF and Darc on the sidewalls will remain. After the ashing process, the APF is removed, and the Darc is peeled off and retained.

[0005] To address the aforementioned issues, a novel method is needed to improve the removal of the hard mask layer during polysilicon gate layer etching. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method to improve the hard mask layer peeling during polysilicon gate layer etching. This method addresses the problem that in the prior art, after cell etching and SiN hard mask removal, the cell region has a large step difference. After the formation of APF and Darc, sidewalls are formed on both sides of the cell. Since the polysilicon gate layer is etched anisotropically, the APF and Darc on the gate structure surface can be removed, but the APF and Darc on the sidewalls remain. After the ashing process, the APF is removed, but the Darc peels off and is retained.

[0007] To achieve the above and other related objectives, the present invention provides a method for improving hard mask layer peeling during polysilicon gate layer etching, comprising: Step 1: Provide a substrate, the substrate comprising a memory region and a peripheral logic region, a gate oxide layer is formed on both the memory region and the peripheral logic region, and a floating gate, an inter-electrode dielectric layer, a control gate, and a first hard mask layer are formed on the gate oxide layer of the memory region structure in a sequence from bottom to top; A first sidewall structure, a second sidewall structure, a tunneling oxide layer, a selection gate, a selection gate oxide layer, and a second hard mask layer are formed on the storage area. The first sidewall structure is located within the first hard mask layer. The second sidewall structure is located within the control gate and the inter-electrode dielectric layer and covers a portion of the sidewall of the first sidewall structure. The tunneling oxide layer is located within the floating gate and the gate oxide layer and covers the remaining sidewalls of the second sidewall structure and the first sidewall structure. The tunneling oxide layer is U-shaped. The selection gate fills the U-shaped space formed inside the tunneling oxide layer. The selection gate oxide layer covers the surface of the selection gate. The top edge of the first hard mask layer is flush with the top edge of the selection gate oxide layer. The second hard mask layer is located on the selection gate oxide layer and the first hard mask layer. Step 2: Form a polysilicon gate layer on the memory region and the peripheral logic region; Step 3: Pattern the polysilicon gate layer using photolithography and etching to form a gate structure located on the peripheral logic region; Step 4: Form a sidewall material layer on the storage area and the peripheral logic area, form a protective layer on the sidewall material layer, form a second photoresist layer on the protective layer, use photolithography to open the second photoresist layer on the storage area, etch the protective layer, sidewall material layer and polysilicon gate layer located on the storage area, and then remove the second photoresist layer. Step 5: Remove the first and second hard mask layers on the storage area using an etching process with a high selectivity ratio relative to the protective layer using the first and second hard mask layers; Step 6: Remove the protective layer to form a third photoresist layer covering the storage area and the peripheral logic area. Photolithography is used to open the third photoresist layer on the storage area. Then, the control gate, the inter-electrode dielectric layer, and the floating gate outside the two sides of the first sidewall are etched away, and the third photoresist layer is removed. Step 7: Etch back the sidewall material layer to form a sidewall located on the sidewall of the gate structure.

[0008] Preferably, the substrate in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate.

[0009] Preferably, the material of the first sidewall structure in step one is silicon dioxide.

[0010] Preferably, the material of the second sidewall structure in step one is silicon dioxide.

[0011] Preferably, the material of the inter-electrode dielectric layer in step one is an ONO layer, which is composed of a first oxide layer, a nitride layer, and a second oxide layer stacked sequentially from bottom to top.

[0012] Preferably, the material of the first hard mask layer in step one is silicon nitride.

[0013] Preferably, step one, which involves forming the first sidewall structure, the second sidewall structure, the tunneling oxide layer, the select gate, and the select gate oxide layer in the storage region, comprises: etching a first hard mask layer in the storage region to form a first trench; forming a first sidewall structure in the first trench, the first sidewall structure covering the sidewall of the first trench; etching the control gate and the inter-electrode dielectric layer on the bottom wall of the first trench to form a second trench; forming a second sidewall structure in the second trench, the second sidewall structure covering a portion of the sidewall of the second trench; etching the floating gate and the gate oxide layer on the bottom wall of the second trench to form a third trench; forming a tunneling oxide layer, the tunneling oxide layer covering the bottom wall and sidewall of the third trench; forming a select gate, the select gate filling the third trench; and forming a select gate oxide layer, the select gate oxide layer covering the select gate.

[0014] Preferably, the etching method described in step one is dry etching.

[0015] Preferably, the method for patterning the polysilicon gate layer using photolithography and etching in step three includes: sequentially forming an APF layer, a dielectric antireflective coating, and a first photoresist layer on the polysilicon gate layer; photolithography opens the first photoresist layer to expose the dielectric antireflective coating underneath it; etching the exposed dielectric antireflective coating and the APF layer underneath it, with the patterned APF layer defining the etching area of ​​the polysilicon gate layer on the peripheral logic region; using the etched APF layer as a mask to etch the polysilicon gate layer underneath it; and removing the remaining APF layer.

[0016] Preferably, the etching method described in step three is dry etching.

[0017] Preferably, the material of the sidewall material layer in step four is silicon nitride.

[0018] Preferably, the material of the protective layer in step four is silicon dioxide.

[0019] Preferably, the etching method described in step four is dry etching.

[0020] Preferably, in step four, after etching the protective layer, sidewall material layer, and polysilicon gate layer located on the memory region, the sidewall material layer is retained on the sidewall of the stacked structure on the memory region; the retained sidewall material layer is removed in the etching process in step five.

[0021] Preferably, the etching process in step five is wet etching.

[0022] Preferably, the protective layer is removed in step six using a wet etching method.

[0023] Preferably, the etching method described in step six is ​​dry etching.

[0024] Preferably, the etching method described in step seven is dry etching.

[0025] As described above, the method for improving hard mask layer peeling during polysilicon gate layer etching of the present invention has the following beneficial effects: This invention moves the cell structure formation to the sidewall material layer deposition, which can eliminate the cell region step difference during polysilicon gate layer etching and solve the problem of hard mask layer peeling off after polysilicon gate layer etching caused by cell step difference. Attached Figure Description

[0026] Figure 1 The diagram shown is a schematic representation of the process flow of the present invention. Figure 2 This is a schematic diagram of the initial structure of the storage area and peripheral logic area of ​​the present invention. Figure 3 The diagram shown illustrates the gate structure formed in the peripheral logic region according to the present invention. Figure 4 The diagram shown illustrates the formation of the sidewall material layer according to the present invention. Figure 5 The diagram shown illustrates the formation of the protective layer according to the present invention. Figure 6 The diagram shown is a schematic diagram of the photolithography opening of the second photoresist layer according to the present invention. Figure 7 This is a schematic diagram showing the area where the second photoresist layer is etched open according to the present invention. Figure 8 The diagram shown illustrates the removal of the first and second hard mask layers according to the present invention. Figure 9 The diagram shown illustrates the removal of the protective layer according to the present invention. Figure 10 The diagram shown is a schematic diagram of the photolithography opening of the third photoresist layer according to the present invention. Figure 11 The diagram shown illustrates the formation of the cell structure according to the present invention. Figure 12 The diagram shown is a schematic representation of the sidewalls forming the gate structure of the peripheral logic region according to the present invention. Detailed Implementation

[0027] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0028] Please see Figure 1 The present invention provides a method for improving hard mask layer peeling during polysilicon gate layer etching, comprising: Step 1: Provide a substrate 100, which includes a memory region and a peripheral logic region. A gate oxide layer 110 is formed on both the memory region and the peripheral logic region. A floating gate 102, an inter-electrode dielectric layer 103, a control gate 104, and a first hard mask layer 101 are formed on the gate oxide layer 110 of the memory region structure, which are stacked sequentially from bottom to top. A first sidewall structure 109, a second sidewall structure 107, a tunneling oxide layer 105, a selection gate 106, a selection gate oxide layer 108, and a second hard mask layer are formed on the storage area. The first sidewall structure 109 is located within the first hard mask layer 101. The second sidewall structure 107 is located within the control gate 104 and the inter-electrode dielectric layer 103 and covers a portion of the sidewall of the first sidewall structure 109. The tunneling oxide layer 105 is located within the floating gate 102 and the gate oxide layer 110 and covers the remaining sidewalls of the second sidewall structure 107 and the first sidewall structure 109. The tunneling oxide layer 105 is U-shaped. The selection gate 106 fills the U-shaped space formed inside the tunneling oxide layer 105. The selection gate oxide layer 108 covers the surface of the selection gate 106. The top end of the first hard mask layer 101 is flush with the top end of the selection gate oxide layer 108. The second hard mask layer is located on the selection gate oxide layer 108 and the first hard mask layer 101. In embodiments of the present invention, the substrate 100 in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer located beneath a thin semiconductor layer serving as the active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor typically comprise the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed-orientation substrates.

[0029] In an embodiment of the present invention, the material of the first sidewall structure 109 in step one is silicon dioxide.

[0030] In an embodiment of the present invention, the material of the second sidewall structure 107 in step one is silicon dioxide.

[0031] In an embodiment of the present invention, the material of the inter-electrode dielectric layer 103 in step one is an ONO layer, which is composed of a first oxide layer, a nitride layer, and a second oxide layer stacked sequentially from bottom to top.

[0032] In an embodiment of the present invention, the material of the first hard mask layer 101 in step one is silicon nitride.

[0033] In an embodiment of the present invention, step one, forming a first sidewall structure 109, a second sidewall structure 107, a tunneling oxide layer 105, a selection gate 106, and a selection gate oxide layer 108 in the storage region, includes: etching a first hard mask layer 101 in the storage region to form a first trench; forming a first sidewall structure 109 in the first trench, the first sidewall structure 109 covering the sidewall of the first trench; etching a control gate 104 and an inter-electrode dielectric layer 103 on the bottom wall of the first trench to form a second trench; forming a second sidewall structure 107 in the second trench, the second sidewall structure 107 covering a portion of the sidewall of the second trench; etching a floating gate 102 and a gate oxide layer 110 on the bottom wall of the second trench to form a third trench; forming a tunneling oxide layer 105, the tunneling oxide layer 105 covering the bottom wall and sidewall of the third trench; forming a selection gate 106, the selection gate 106 filling the third trench; and forming a selection gate oxide layer 108, the selection gate oxide layer 108 covering the selection gate 106.

[0034] In the embodiments of the present invention, the etching method in step one is dry etching.

[0035] Step Two, please refer to Figure 2A polysilicon gate layer 111 is formed on the memory region and the peripheral logic region; Step 3: Pattern the polysilicon gate layer 111 using photolithography and etching to form the gate structure 114 located on the peripheral logic region, forming a structure as shown in the figure. Figure 3 The structure shown; In an embodiment of the present invention, please refer to Figure 2 The method for patterning the polysilicon gate layer 111 using photolithography and etching in step three includes: sequentially forming an APF layer 112, a dielectric antireflective coating 113, and a first photoresist layer (not shown in the figure) on the polysilicon gate layer 111; photolithography opens the first photoresist layer to expose the dielectric antireflective coating 113 underneath it; etching the exposed dielectric antireflective coating 113 and the APF layer 112 underneath it, the patterned APF layer 112 is used to define the etching area of ​​the polysilicon gate layer 111 on the peripheral logic region; using the etched APF layer 112 as a mask, etching the polysilicon gate layer 111 underneath it, the dielectric antireflective coating 113 and the first photoresist layer are usually removed during etching; removing the remaining APF layer 112, usually by using an ashing process and wet cleaning.

[0036] In an embodiment of the present invention, the etching method in step three is dry etching.

[0037] Step 4: Form a sidewall material layer 115 on the memory area and the peripheral logic area. The sidewall material layer 115 is used to form sidewalls on the sidewalls of the gate structure 114 during subsequent etch-back, forming as shown in the figure. Figure 4 The structure shown has a protective layer 116 formed on the sidewall material layer 115, forming a structure as shown. Figure 5 The structure shown includes a protective layer 116 for protecting the sidewall material layer 115 on the logic region. A second photoresist layer 117 is formed on the protective layer 116. Photolithography is used to open the second photoresist layer 117 on the memory region, forming a structure as shown. Figure 6 The structure shown involves etching the protective layer 116, sidewall material layer 115, and polysilicon gate layer 111 located on the memory region, followed by removing the second photoresist layer 117. The sidewall material layer 115 on the sidewalls of the stacked structure on the memory region is retained, forming a structure as shown. Figure 7 The structure shown; In an embodiment of the present invention, the material of the sidewall material layer 115 in step four is silicon nitride.

[0038] In an embodiment of the present invention, the material of the protective layer 116 in step four is silicon dioxide.

[0039] In an embodiment of the present invention, the etching method in step four is dry etching, and the sidewall material layer 115 on the sidewall of the stacked structure located on the storage area can protect the sidewall of the stacked structure.

[0040] Step 5: Using an etching process with a high selectivity ratio relative to the protective layer 116, the first and second hard mask layers on the storage area are removed. Simultaneously, the sidewall material layer 115 on the sidewalls of the stacked structure on the storage area is also removed, forming a layer as shown in the image. Figure 8 The structure shown; In an embodiment of the present invention, the etching process in step five is wet etching.

[0041] Step 6: Remove protective layer 116 to form a structure like... Figure 9 The structure shown forms a third photoresist layer 118 covering the memory region and the peripheral logic region. Photolithography opens the third photoresist layer 118 on the memory region, forming a structure as shown. Figure 10 The mechanism shown is then etched away, removing the control gate 104, inter-electrode dielectric layer 103, and floating gate 102 on both sides of the first sidewall to form a cell structure. The third photoresist layer 118 is then removed to form a structure as shown. Figure 11 The structure shown can eliminate the cell structure formation after the sidewall material layer 115 is deposited, thus eliminating the cell step difference during the etching of the polysilicon gate layer 111. This can solve the problem of the hard mask layer peeling off after the polysilicon gate layer 111 is etched due to the cell step difference. In an embodiment of the present invention, the protective layer 116 is removed in step six using a wet etching method.

[0042] In an embodiment of the present invention, the etching method in step six is ​​dry etching.

[0043] Step 7: Etch back the sidewall material layer 115 to form a sidewall 119 located on the sidewall of the gate structure 114, forming as shown in the figure. Figure 12 The structure shown.

[0044] In an embodiment of the present invention, the etching method in step seven is dry etching.

[0045] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0046] In summary, by shifting the cell structure formation to the sidewall material layer deposition stage, this invention eliminates the step difference in the cell region during polysilicon gate layer etching, thus resolving the problem of hard mask layer peeling off after polysilicon gate layer etching caused by cell step difference. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0047] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for improving hard mask layer peeling during polysilicon gate layer etching, characterized in that, At least including: Step 1: Provide a substrate, the substrate comprising a memory region and a peripheral logic region, a gate oxide layer is formed on both the memory region and the peripheral logic region, and a floating gate, an inter-electrode dielectric layer, a control gate, and a first hard mask layer are formed on the gate oxide layer of the memory region structure in a sequence from bottom to top; A first sidewall structure, a second sidewall structure, a tunneling oxide layer, a selection gate, a selection gate oxide layer, and a second hard mask layer are formed on the storage area. The first sidewall structure is located within the first hard mask layer. The second sidewall structure is located within the control gate and the inter-electrode dielectric layer and covers a portion of the sidewall of the first sidewall structure. The tunneling oxide layer is located within the floating gate and the gate oxide layer and covers the remaining sidewalls of the second sidewall structure and the first sidewall structure. The tunneling oxide layer is U-shaped. The selection gate fills the U-shaped space formed inside the tunneling oxide layer. The selection gate oxide layer covers the surface of the selection gate. The top edge of the first hard mask layer is flush with the top edge of the selection gate oxide layer. The second hard mask layer is located on the selection gate oxide layer and the first hard mask layer. Step 2: Form a polysilicon gate layer on the memory region and the peripheral logic region; Step 3: Pattern the polysilicon gate layer using photolithography and etching to form a gate structure located on the peripheral logic region; Step 4: Form a sidewall material layer on the storage area and the peripheral logic area, form a protective layer on the sidewall material layer, form a second photoresist layer on the protective layer, use photolithography to open the second photoresist layer on the storage area, etch the protective layer, sidewall material layer and polysilicon gate layer located on the storage area, and then remove the second photoresist layer. Step 5: Remove the first and second hard mask layers on the storage area using an etching process with a high selectivity ratio relative to the protective layer using the first and second hard mask layers; Step 6: Remove the protective layer to form a third photoresist layer covering the storage area and the peripheral logic area. Photolithography is used to open the third photoresist layer on the storage area. Then, the control gate, the inter-electrode dielectric layer, and the floating gate outside the two sides of the first sidewall are etched away, and the third photoresist layer is removed. Step 7: Etch back the sidewall material layer to form a sidewall located on the sidewall of the gate structure.

2. The method for improving hard mask layer peeling during polysilicon gate layer etching according to claim 1, characterized in that: The substrate in step one includes a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate.

3. The method for improving hard mask layer peeling during polysilicon gate layer etching according to claim 1, characterized in that: The material of the first sidewall structure in step one is silicon dioxide.

4. The method for improving hard mask layer peeling during polysilicon gate layer etching according to claim 1, characterized in that: The material of the second sidewall structure in step one is silicon dioxide.

5. The method for improving hard mask layer peeling during polysilicon gate layer etching according to claim 1, characterized in that: The material of the inter-electrode dielectric layer in step one is an ONO layer, which is composed of a first oxide layer, a nitride layer, and a second oxide layer stacked sequentially from bottom to top.

6. The method for improving hard mask layer peeling during polysilicon gate layer etching according to claim 1, characterized in that: The material of the first hard mask layer in step one is silicon nitride.

7. The method for improving hard mask layer peeling during polysilicon gate layer etching according to claim 1, characterized in that: Step one, which involves forming the first sidewall structure, the second sidewall structure, the tunneling oxide layer, the select gate, and the select gate oxide layer in the storage region, includes: etching a first hard mask layer in the storage region to form a first trench; forming a first sidewall structure in the first trench, the first sidewall structure covering the sidewall of the first trench; etching the control gate and the inter-electrode dielectric layer on the bottom wall of the first trench to form a second trench; forming a second sidewall structure in the second trench, the second sidewall structure covering a portion of the sidewall of the second trench; etching the floating gate and the gate oxide layer on the bottom wall of the second trench to form a third trench; forming a tunneling oxide layer, the tunneling oxide layer covering the bottom wall and sidewall of the third trench; forming a select gate, the select gate filling the third trench; and forming a select gate oxide layer, the select gate oxide layer covering the select gate.

8. The method for improving hard mask layer peeling during polysilicon gate layer etching according to claim 1, characterized in that: The etching methods described in step one are all dry etching.

9. The method for improving hard mask layer peeling during polysilicon gate layer etching according to claim 1, characterized in that: Step three involves patterning the polysilicon gate layer using photolithography and etching, including: sequentially forming an APF layer, a dielectric antireflective coating, and a first photoresist layer on the polysilicon gate layer; photolithography to open the first photoresist layer to expose the dielectric antireflective coating underneath; etching the exposed dielectric antireflective coating and the APF layer underneath, with the patterned APF layer defining the etching area of ​​the polysilicon gate layer on the peripheral logic region; using the etched APF layer as a mask to etch the polysilicon gate layer underneath; and removing the remaining APF layer.

10. The method for improving hard mask layer peeling during polysilicon gate layer etching according to claim 9, characterized in that: The etching method described in step three is dry etching.

11. The method for improving hard mask layer peeling during polysilicon gate layer etching according to claim 1, characterized in that: The sidewall material layer in step four is made of silicon nitride.

12. The method for improving hard mask layer peeling during polysilicon gate layer etching according to claim 1, characterized in that: The protective layer in step four is made of silicon dioxide.

13. The method for improving hard mask layer peeling during polysilicon gate layer etching according to claim 1, characterized in that: The etching method described in step four is dry etching.

14. The method for improving hard mask layer peeling during polysilicon gate layer etching according to claim 1, characterized in that: In step four, after etching the protective layer, sidewall material layer, and polysilicon gate layer located on the memory region, the sidewall material layer is retained on the sidewall of the stacked structure on the memory region; the retained sidewall material layer is removed in the etching process in step five.

15. The method for improving hard mask layer peeling during polysilicon gate layer etching according to claim 1, characterized in that: The etching process described in step five is wet etching.

16. The method for improving hard mask layer peeling during polysilicon gate layer etching according to claim 1, characterized in that: In step six, the protective layer is removed using a wet etching method.

17. The method for improving hard mask layer peeling during polysilicon gate layer etching according to claim 1, characterized in that: The etching method described in step six is ​​dry etching.

18. The method for improving hard mask layer peeling during polysilicon gate layer etching according to claim 1, characterized in that: The etching method described in step seven is dry etching.

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