A semiconductor structure and its formation method

Abstract

This disclosure provides a semiconductor structure and a method for forming the same. The method includes: providing a stacked structure formed on a substrate surface having an array region and a peripheral region; sequentially forming a buffer layer and a mask layer on the stacked structure; wherein the mask layer located in the array region has a first pattern; sequentially etching the buffer layer and the stacked structure through the mask layer to transfer the first pattern into the stacked structure; and etching away the mask layer until the buffer layer on the surface of the peripheral region is exposed to form the semiconductor structure. In this disclosure, the buffer layer can act as an etching stop layer when removing the mask layer, which can improve the step difference between the array region and the peripheral region caused by the etching load effect, avoid damage to the stacked structure and mask layer residue, and improve the fabrication yield of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and to, but is not limited to, a semiconductor structure and a method for forming the same. Background Technology

[0002] Currently, in order to improve the capacitance of capacitors in semiconductor structures, capacitors often have a very high aspect ratio. Therefore, in order to form capacitors with high height through dry etching, a mask layer with a high aspect ratio has become a necessary requirement.

[0003] However, removing a high aspect ratio mask layer after it has been used to form a high aspect ratio capacitor becomes extremely difficult. For example, when using a dry etching process to remove the mask layer, the existing capacitor structure (cell container profiler) is often preserved. This can easily lead to residues of the mask layer or its oxides, as well as damage to the material on top of the capacitor, affecting the deposition of the electrode material underneath and reducing the yield of the resulting semiconductor structure. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same.

[0005] In a first aspect, embodiments of this disclosure provide a method for forming a semiconductor structure, including:

[0006] A stacked structure is provided, the stacked structure being formed on a substrate surface having an array region and a peripheral region;

[0007] A buffer layer and a mask layer are sequentially formed on the stacked structure; wherein the mask layer located in the array region has a first pattern;

[0008] The first pattern is transferred to the stacked structure by sequentially etching the buffer layer and the stacked structure through the mask layer;

[0009] The mask layer is etched away until the buffer layer on the surface of the peripheral region is exposed to form the semiconductor structure.

[0010] In some embodiments, the thickness of the buffer layer is 99–152 nanometers.

[0011] In some embodiments, during the process of sequentially etching the buffer layer and the stacked structure through the mask layer, the etching selectivity of the buffer layer relative to the mask layer is greater than or equal to 8.

[0012] In some embodiments, during the etching process to remove the mask layer until the buffer layer on the surface of the peripheral region is exposed, the etch selectivity of the mask layer relative to the buffer layer is greater than or equal to 5.

[0013] In some embodiments, the stacked structure includes a first support layer, a first sacrificial layer, a second support layer, a second sacrificial layer, and a third support layer stacked sequentially from bottom to top; the buffer layer and the stacked structure are sequentially etched through the mask layer to transfer the first pattern into the stacked structure, including:

[0014] The first pattern is transferred to the buffer layer and part of the stacked structure by sequentially etching the buffer layer, the third support layer, the second sacrificial layer, the second support layer, and a portion of the first sacrificial layer through the mask layer.

[0015] In some embodiments, the mask layer located in the peripheral region has a second pattern;

[0016] The pattern density of the first pattern is greater than that of the second pattern.

[0017] In some embodiments, the first pattern includes a capacitor hole pattern; the substrate includes at least a contact structure corresponding to the capacitor hole pattern;

[0018] After etching away the mask layer until the buffer layer on the surface of the peripheral region is exposed, the method for forming the semiconductor structure further includes:

[0019] The remaining first sacrificial layer and first support layer are etched until the contact structure is exposed to form a plurality of capacitor holes and etch pillars located between two adjacent capacitor holes in the stacked structure, wherein the etch selectivity ratio between the buffer layer and the first sacrificial layer is greater than or equal to 1.

[0020] In some embodiments, the method further includes removing the buffer layer while forming the plurality of capacitor holes.

[0021] In some embodiments, the method further includes:

[0022] A first electrode layer is formed on the inner wall of the capacitor hole and on the surface of the etched pillar;

[0023] The second sacrificial layer and the first sacrificial layer in the etching column are removed sequentially;

[0024] A dielectric layer and a second electrode layer are sequentially deposited on the surface of the first electrode layer to form a capacitor structure.

[0025] In some embodiments, the sequential removal of the second sacrificial layer in the etching pillar and the first sacrificial layer in the etching pillar includes:

[0026] A sealing mask layer is formed on the surface of a capacitor hole having the first electrode layer and an etch post having the first electrode layer; wherein the sealing mask layer exposes a portion of the first electrode layer;

[0027] By etching away part of the first electrode layer through the sealing mask layer, part of the third support layer is exposed;

[0028] A first opening is formed in the exposed third support layer;

[0029] The second sacrificial layer is removed through the first opening, exposing a portion of the second support layer;

[0030] A second opening is formed in the exposed second support layer; the first sacrificial layer is removed through the second opening.

[0031] In some embodiments, the method further includes: depositing electrode material within the capacitor aperture to form a first electrode layer; wherein the electrode material fills the capacitor aperture;

[0032] A dielectric layer and a second electrode layer are sequentially deposited on the surface of the first electrode layer to form a capacitor structure.

[0033] In some embodiments, the substrate further includes an insulating layer for isolating the contact structure;

[0034] Wherein, the etching selectivity ratio of the first support layer relative to the insulating layer is greater than or equal to 10.

[0035] In a second aspect, embodiments of this disclosure provide a semiconductor structure, which is formed by the above-described semiconductor structure formation method, and the semiconductor structure includes at least: a substrate and a capacitor structure;

[0036] The substrate includes a contact structure;

[0037] The capacitor structure is located on the surface of the substrate and is in contact with the contact structure.

[0038] In some embodiments, the capacitor structure includes at least a first support layer; the substrate further includes an insulating layer for isolating the contact structure;

[0039] Wherein, the etching selectivity ratio of the first support layer relative to the insulating layer is greater than or equal to 10.

[0040] In some embodiments, the semiconductor structure further includes: a transistor; the transistor includes a gate, a source, and a drain; the substrate further includes word lines and bit lines;

[0041] The gate is connected to the word line, the drain or the source is connected to the bit line, and the source or the drain is connected to the contact structure.

[0042] The semiconductor structure and its formation method provided in this disclosure improve the step difference caused by etching load on the mask layer between the array region and the peripheral region by adding a buffer layer between the stacked structure and the mask layer. This avoids damage to the stacked structure and mask layer residue, reduces oxide residue around the array region, facilitates subsequent process steps, and improves the semiconductor structure fabrication yield. Furthermore, this disclosure also avoids the loss of bottom support material during cleaning, forming a curved profile, thus preventing short circuits in subsequently formed capacitors and improving the semiconductor structure yield. Additionally, the semiconductor structure formation method provided in this disclosure can form capacitors with high height, high aspect ratio, and large capacitance. Attached Figure Description

[0043] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0044] Figure 1 A schematic flowchart illustrating a method for forming a semiconductor structure according to an embodiment of this disclosure;

[0045] Figures 2a-2n This is a schematic diagram of the formation process of forming a semiconductor structure provided in an embodiment of the present disclosure;

[0046] Figure 3 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0047] Figure 4 This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure;

[0048] The annotations in the attached figures are explained as follows:

[0049] 10—Substrate; 101—Contact structure; 102—Insulating layer; 11—Stacked structure; 115—First support layer; 114—First sacrificial layer; 114a—Remaining first sacrificial layer; 113—Second support layer; 112—Second sacrificial layer; 111—Third support layer; 12—Buffer layer; 13—Mask layer; 13a—Initial mask layer; 131—Mask layer of peripheral region B; 132—Mask layer of array region A; 14—First photoresist layer; 15—Etching hole; 16—Etching pillar; 17—Capacitor hole; 171—First electrode layer; 172—Dielectric layer; 173—Second electrode layer; 174—Conductive material; 18—Sealing mask layer; 18a—Initial sealing mask layer; 19—Second photoresist layer; 30 / 40—Semiconductor structure. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the specific technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings of the embodiments of this disclosure. The following embodiments are used to illustrate this disclosure, but are not intended to limit the scope of this disclosure.

[0051] Based on the problems existing in related technologies, this disclosure provides a semiconductor structure and its formation method, which improves the penetration and / or residue defects in the semiconductor structure fabrication process. By adding a buffer layer between the stacked structure and the mask layer, the step difference caused by etching load on the mask layer in the array region and the peripheral region is improved, avoiding damage to the stacked structure and mask layer residue, reducing the problem of oxide residue around the array region, facilitating subsequent process steps, and improving the semiconductor structure fabrication yield. Furthermore, the semiconductor structure formation method provided in this disclosure can etch and form capacitor structures with high height (e.g., height greater than 1000 nm) and high aspect ratio (e.g., aspect ratio greater than 20:1, such as reaching 35:1 or 38:1). In other words, the semiconductor structure formation method provided in this disclosure can form capacitors with high height, high aspect ratio, and large capacitance.

[0052] Figure 1 This is a schematic flowchart of a method for forming a semiconductor structure according to an embodiment of the present disclosure, as shown below. Figure 1 As shown, the method for forming a semiconductor structure includes the following steps:

[0053] Step S101: Provide a stacked structure, which is formed on the surface of a substrate having an array region and a peripheral region.

[0054] In this embodiment, the substrate has an array region and a peripheral region, and a stacked structure is located on the surface of the substrate. For example, a capacitor structure can be formed in the stacked structure of the array region. The stacked structure includes a support layer and a sacrificial layer stacked alternately from bottom to top. The support layer has a higher hardness than the sacrificial layer, and the support layer has a higher etching selectivity than the sacrificial layer. The support layer is used to support the ultimately formed capacitor structure.

[0055] In this embodiment of the disclosure, the capacitor structure can be a columnar capacitor structure or a cup-shaped capacitor structure.

[0056] In this embodiment of the disclosure, the support layer may be a silicon nitride layer or a silicon carbide nitride layer. The sacrificial layer may be a silicon oxide layer, a phosphoro silicate glass (PSG) layer, or a borophospho silicate glass (BPSG) layer.

[0057] In this embodiment of the disclosure, both the sacrificial layer and the support layer can be formed by any suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, or coating process.

[0058] Step S102: A buffer layer and a mask layer are sequentially formed on the stacked structure; wherein the mask layer located in the array region has a first pattern.

[0059] In this embodiment, the buffer layer can be an oxide layer, such as silicon oxide or aluminum oxide, and the thickness of the buffer layer is between 99 nanometers (nm) and 152 nm, for example, 100 nm, 120 nm, 140 nm, or 150 nm. The mask layer can be a polycrystalline silicon layer, silicon nitride, silicon carbide, or silicon oxynitride. Both the buffer layer and the mask layer can be formed by any suitable deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, coating process, or thin film process.

[0060] In this embodiment, the mask layer located in the array region has a first pattern, such as a capacitor hole pattern, so that a capacitor structure can be formed in the array region. When forming a capacitor structure with a high aspect ratio, a high-thickness mask layer is required. In this embodiment, between the array region with the first pattern and the peripheral region without a pattern, a buffer layer can absorb the etching load problem of the mask layer during the etching process, improve the step difference (height difference) problem between the array region and the peripheral region, avoid the above defects and improve the yield.

[0061] In other embodiments, the mask layer located in the peripheral region may also have a second pattern, and the pattern density of the first pattern is greater than that of the second pattern, so as to form corresponding semiconductor devices in the array region and the peripheral region respectively. Under the fabrication method provided in the embodiments of this disclosure, the problem of heavier etching load during the removal of the mask layer in the peripheral region due to the pattern density of the first pattern being greater than that of the second pattern can be reduced.

[0062] Step S103: The buffer layer and the stacked structure are sequentially etched through the mask layer to transfer the first pattern into the stacked structure.

[0063] In this embodiment of the disclosure, a dry etching process can be used to etch the stacked structure, such as plasma etching, reactive ion etching, or ion milling. The gas used for dry etching can be one or a combination of trifluoromethane (CHF3), carbon tetrafluoride (CF4), difluoromethane (CH2F2), hydrogen bromide (HBr), chlorine (Cl2), or sulfur hexafluoride (SF6).

[0064] In some embodiments, during the sequential etching of the buffer layer and the stacked structure through the mask layer, the etching selectivity of the buffer layer relative to the mask layer can be greater than or equal to 8, for example, 10, 15, or 20. Further, the etching selectivity of each layer in the stacked structure relative to the mask layer can be greater than or equal to 5, for example, 8, 10, 15, or 20. Within these ranges, the first pattern can be quickly transferred to the buffer layer and the stacked structure at a relatively low etching rate to the mask layer without damaging the buffer layer and the stacked structure. In some embodiments, the mask layer and the buffer layer can be etched using CF4 gas to achieve a high etching selectivity.

[0065] Step S104: Etch away the mask layer until the buffer layer on the surface of the peripheral area is exposed to form a semiconductor structure.

[0066] In some embodiments, during the etching process to remove the mask layer until the buffer layer on the surface of the peripheral region is exposed, the etching selectivity ratio of the mask layer relative to the buffer layer is greater than or equal to 5, for example, 6, 7, 8, 9, 10, 15, 20, or 30. Therefore, when removing the mask layer, the buffer layer can be used as an etching stop layer. The buffer layer improves the step difference between the array region and the peripheral region, avoids damage to the stacked structure and mask layer residue, facilitates subsequent process steps, and improves the semiconductor structure fabrication yield. Furthermore, the semiconductor structure formation method provided in this disclosure can etch and form capacitor structures with high height (e.g., height greater than 1000 nm) and high aspect ratio (e.g., aspect ratio greater than 20:1). In other words, the semiconductor structure formation method provided in this disclosure can form capacitors with high height, high aspect ratio, and large capacitance. In some embodiments, for example, the mask layer and buffer layer can be etched using Cl2 and HBr to achieve a high etching selectivity ratio.

[0067] Figures 2a-2n This is a schematic diagram of the formation process of a semiconductor structure provided in an embodiment of this disclosure. Please refer to the following. Figures 2a-2n The method for forming a semiconductor structure provided in the embodiments of this disclosure will be described in further detail.

[0068] First, you can refer to Figure 2a Step S101 is performed to provide a stacked structure 11, which is formed on the surface of a substrate 10 having an array region A and a peripheral region B.

[0069] like Figure 2a As shown in this embodiment, the stacked structure 11 is formed on the surface of a substrate 10 having an array region A and a peripheral region B. The substrate 10 includes at least a substrate and other device structures, such as word lines, bit lines, or transistors. The substrate may be a silicon substrate, a silicon-on-insulator substrate, etc. The substrate may also include other semiconductor elements or semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or include other semiconductor alloys, such as gallium arsenide phosphide (GaAsP), indium aluminum arsenide (AlInAs), gallium aluminum arsenide (AlGaAs), indium gallium arsenide (GaInAs), indium gallium phosphide (GaInP), and / or indium gallium arsenide phosphide (GaInAsP) or combinations thereof.

[0070] like Figure 2aAs shown in the embodiments of this disclosure, the stacked structure 11 includes, for example, a first support layer 115, a first sacrificial layer 114, a second support layer 113, a second sacrificial layer 112, and a third support layer 111 stacked sequentially from bottom to top. In this embodiment, based on the viewpoint of increasing the capacitor's height to increase its capacitance, the thickness of the first support layer 115 can be 10nm to 20nm, and the thickness of the first sacrificial layer 114 is at least greater than 80nm, and further, for example, less than 800nm. For example, the thickness of the first sacrificial layer 114 is, for example, 80nm, 100nm, 150nm, 200nm, 300nm, or 500nm.

[0071] In this embodiment of the disclosure, a capacitor structure is formed by a stacked structure 11. Please continue to see... Figure 2a The substrate 10 also includes a contact structure 101 and an insulating layer 102 that isolates adjacent contact structures 101. The contact structure 101 is used for electrical connection with the formed capacitor structure.

[0072] In this embodiment, the first support layer 115 has a high etching selectivity relative to the insulating layer 102. For example, the etching selectivity of the first support layer 115 relative to the insulating layer 102 is greater than or equal to 10. In this way, when etching the stacked structure 11 to form a capacitor structure, damage to the insulating layer 102 can be prevented during the etching of the first support layer 115, thus preventing the formation of holes in the insulating layer 102. This also prevents over-etching and the formation of holes in the insulating layer 102, thereby avoiding the problem of uneven filling of electrode material when filling the capacitor hole 17, and improving the fabrication yield of the semiconductor structure.

[0073] In some embodiments, the insulating layer 102 may be made of SiNCH and / or silicon carbonitride (SiCN). In other embodiments, the insulating layer 102 may also be made of silicon nitride.

[0074] Next, you can refer to Figure 2b and 2c Step S102 is executed, in which a buffer layer 12 and a mask layer 13 are sequentially formed on the stacked structure 11; wherein the mask layer 13 located in the array region A has a first pattern C.

[0075] In some embodiments, the buffer layer 12 may be formed by the following steps: depositing a buffer material on the surface of the stacked structure 11 to form the buffer layer 12.

[0076] In this embodiment of the present disclosure, a buffer material can be deposited using any deposition method to form a buffer layer 12. The material of the buffer layer 12 is different from that of the mask layer 13. The material of the buffer layer 12 can be, for example, an oxide, such as silicon oxide, aluminum oxide, or other suitable materials.

[0077] like Figure 2b and 2c As shown, a buffer layer 12 and a mask layer 13 with a first pattern C are sequentially deposited on the stacked structure 11. In this embodiment of the present disclosure, the mask layer 13 with the first pattern C is located in the array region A to form a corresponding device structure in the array region A. The mask layer 13 with the first pattern C can be formed by the following steps: an initial mask layer 13a and a first photoresist layer 14 with the first pattern C are sequentially formed on the surface of the buffer layer 12; the initial mask layer 13a is etched through the first photoresist layer 14 to transfer the first pattern C into the initial mask layer 13a, thereby forming the mask layer 13 with the first pattern C.

[0078] In this embodiment of the disclosure, the first pattern C may be a capacitor hole pattern, and the capacitor hole pattern corresponds to the contact structure 101.

[0079] Next, you can refer to Figure 2d In step S103, the buffer layer 12 and the stacked structure 11 are etched sequentially through the mask layer 13 to transfer the first pattern C into the stacked structure 11.

[0080] In this embodiment of the present disclosure, the buffer layer 12 and the stacked structure 11 are sequentially etched through the mask layer 13 to transfer the first pattern C into the stacked structure 11. This includes: sequentially etching the buffer layer 12, the third support layer 111, the second sacrificial layer 112, the second support layer 113, and a partial thickness of the first sacrificial layer 114 through the mask layer 13 to transfer the first pattern C into the buffer layer 12 and a portion of the stacked structure 11, forming a pattern as shown in the figure. Figure 2d The multiple etched holes 15 shown.

[0081] In this embodiment of the disclosure, the thickness of the remaining first sacrificial layer 114a is between 80 nm and 120 nm.

[0082] In this embodiment of the disclosure, during the process of etching the stacked structure 11 by dry etching process to form the etched hole 15, etching residues, such as polymers, will be generated on the inner wall of the etched hole 15. Therefore, the method for forming a semiconductor structure further includes removing the etching residues generated during the formation of the plurality of etched holes 15.

[0083] In this embodiment of the disclosure, etching residues generated during the formation of the plurality of etched holes 15 can be removed by strong acid cleaning.

[0084] In related technologies, during capacitor via cleaning, the support material at the bottom of the via is easily lost, forming a bow-shaped profile. This is because during dry etching to form the via, residue deposition and etching are competing mechanisms. As etching progresses, the residue deposited near the top of the via becomes thicker, while there is almost no residue deposited at the bottom. Therefore, during prolonged cleaning of the via with strong acid, the lack of protection from the bottom support layer easily leads to the loss of the bottom support material, resulting in a bow-shaped profile. This bow-shaped profile reduces the adhesion between the electrode material and the inner wall of the via, making electrode material deposition difficult and even causing electrode material to detach. In subsequent wet etching processes, the acid will seep through the detached electrode material and the lost support material into the peripheral area. If a second pattern exists in the peripheral area, the acid will penetrate into the second pattern, thereby damaging the device structure formed by the second pattern in the peripheral area. Furthermore, the bow-shaped profile can cause short circuits in subsequently formed capacitors, thus reducing the yield of semiconductor structure fabrication.

[0085] Based on the above problems, in this embodiment of the disclosure, multiple etched holes 15 are formed by etching the stacked structure 11 and stopping at the first sacrificial layer 114. Thus, when cleaning the etched holes 15, a slightly weaker acid solution can be used for a shorter cleaning time. Furthermore, the first sacrificial layer 114, which is not etched during the cleaning process, can protect the first support layer 115, preventing material loss and thus avoiding the formation of a curved profile. In this way, on the one hand, the adhesion between the electrode material and the inner wall of the capacitor hole is strong during electrode material deposition, preventing electrode material detachment and thus avoiding acid seepage that could damage peripheral devices due to electrode material detachment; on the other hand, it prevents short circuits in subsequently formed capacitors, improving the yield of the semiconductor structure.

[0086] Next, you can refer to Figure 2e Step S104 is executed to etch and remove the mask layer 13 until the buffer layer 12 on the surface of the peripheral region B is exposed to form a semiconductor structure.

[0087] In this embodiment of the disclosure, since the array region has a first pattern C, when forming a high aspect ratio array region device structure, during the etching of the buffer layer 12 and the stacked structure 11 through the thick mask layer 13, due to the etching load effect, the mask layer 13 will exhibit conditions such as... Figure 2d The step difference h is shown. Similarly, when the outer region has a second pattern, the pattern density in array region A is greater than the pattern density of the first pattern in outer region B, and there will also be step differences of different degrees.

[0088] refer to Figure 2dIn this embodiment of the present disclosure, during, for example, dry etching to remove the mask layer 13, the surface of the mask layer 13 is damaged due to high energy and long etching time, and the etching load problem causes a step difference h between the mask layer 132 of the array region A and the mask layer 131 of the peripheral region B. Furthermore, the mask layer 132 of the array region A is lower than the mask layer 131 of the peripheral region B. Therefore, the mask layer 132 of the array region A will be removed first, exposing the buffer layer 12 in the array region A. At this point, etching needs to continue until the mask layer 131 of the peripheral region B is completely removed, exposing the buffer layer 12 on the surface of the peripheral region B. In some embodiments of the present disclosure, for example, the etching selectivity ratio of the mask layer 13 to the buffer layer 12 can be controlled to be greater than or equal to 5, so that the buffer layer 12 can act as an etching stop layer when removing the mask layer 13. When continuing to remove the mask layer 131 of the peripheral region B, the buffer layer 12 of the array region A will not be damaged or will be minimally damaged (i.e., ...). Figure 2e As shown, there is no step difference on the buffer layer 12. In other words, the buffer layer 12 can absorb the step difference generated between the array region A and the peripheral region B, avoid damage to the stacked structure 11 and the residue of the mask layer 13, facilitate subsequent process steps, and improve the fabrication yield of the semiconductor structure.

[0089] In this embodiment of the disclosure, a dry etching technique can be used to remove the mask layer 13. The gas used in the dry etching technique can be one or a combination of trifluoromethane, carbon tetrafluoride, difluoromethane, hydrogen bromide, chlorine, or sulfur hexafluoride.

[0090] In some embodiments, please refer to Figure 2f After removing the mask layer 13, the method for forming the semiconductor structure further includes: continuing to etch the remaining first sacrificial layer 114a and first support layer 115 along the etch hole until the contact structure 101 is exposed, so as to form a plurality of capacitor holes 17 and etch pillars 16 located between two adjacent capacitor holes 17 in the stacked structure 11.

[0091] like Figure 2f As shown, for example, the remaining first sacrificial layer 114a and first support layer 115 can be etched by CxHyFz, such as CH3F or CH2F2 gas, to expose the contact structure 101, forming a plurality of capacitor holes 17 and a plurality of etching pillars 16 located between the plurality of capacitor holes 17, wherein the etching selectivity ratio of the buffer layer 12 to the first sacrificial layer 13 is greater than or equal to 1.

[0092] In some embodiments, the buffer layer 12 is removed while forming a plurality of capacitor holes 17.

[0093] In this embodiment of the present disclosure, the etching selectivity ratio between the buffer layer 12 and the first sacrificial layer 114 is greater than or equal to 1, for example, they can be the same. In this case, when the remaining first sacrificial layer 114a is removed, the buffer layer 12 will also be removed at the same time, without the need for additional processes.

[0094] In this embodiment of the present disclosure, the buffer layer 12 can not only improve the step difference between the array region and the peripheral region, but also provide protection for the third support layer 111 in the stacked structure 11 during the etching of the remaining first sacrificial layer 114a and first support layer 115. The thickness of the buffer layer 12 in this embodiment of the present disclosure is, for example, between 99nm and 152nm, such as 100nm, 120nm, 140nm, or 150nm.

[0095] In some embodiments, the method for forming a semiconductor structure further includes cleaning a plurality of capacitor holes 17. Although the capacitor holes 17 formed at this time are relatively deep and have exposed the first support layer 115, since the etching residues generated in the plurality of etching holes 15 have been cleaned during the formation of the etching holes 15, the etching residues in the capacitor holes 17 are now minimal. Only a short cleaning with a weak acid is required for the capacitor holes 17, so the first support layer 115 will not be damaged during the cleaning process, thereby avoiding the formation of a curved profile. Thus, on the one hand, the adhesion between the electrode material and the inner wall of the capacitor hole is strong when the electrode material is deposited, and the phenomenon of electrode material detachment will not occur. Therefore, the phenomenon of acid seepage due to electrode material detachment damaging the peripheral circuit will not occur. On the other hand, it will not cause short circuits in the capacitors formed subsequently, thus improving the yield of the semiconductor structure.

[0096] In some embodiments, please refer to Figure 2g~2n The method for forming a semiconductor structure also includes the following steps:

[0097] A first electrode layer 171 is formed on the inner wall of the capacitor hole 17 and the surface of the etched pillar 16.

[0098] The second sacrificial layer 112 and the first sacrificial layer 114 in the etching pillar 16 are removed sequentially.

[0099] A dielectric layer 172 and a second electrode layer 173 are sequentially deposited on the surface of the first electrode layer 171 to form a capacitor structure.

[0100] The first electrode layer 171, the dielectric layer 172, and the second electrode layer 173 can be formed using any suitable deposition process. The materials of the first electrode layer 171 and the second electrode layer 173 can include metals or metal compounds, such as gold (Au), silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), tungsten (W), titanium (Ti), platinum (Pt), palladium (Pd), tin (Sn), lead (Pb), zinc (Zn), indium (In), cadmium (Cd), chromium (Cr), or molybdenum (Mo), titanium nitride (TiN), aluminum (Al), or tungsten silicide (WSix). The material of the dielectric layer 172 can include high-k dielectric materials, such as lanthanum oxide (La₂O₃), aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), hafnium oxynitride (HfON), or hafnium silicate (HfSiO₂). x One or any combination of zirconium oxide (ZrO2) or zirconium oxide (ZrO2).

[0101] like Figure 2g As shown, a first electrode layer 171 is formed on the inner wall of the capacitor hole 17 and the surface of the etched pillar 16.

[0102] In some embodiments, removing the first sacrificial layer 114 and the second sacrificial layer 112 in array region A, and the stacked structure 11 in peripheral region B, may include, for example, the following steps:

[0103] A sealing mask layer 18 is formed on the surface of the capacitor hole 17 having a first electrode layer 171 and the etching post 16 having a first electrode layer 171; wherein the sealing mask layer 18 exposes a portion of the first electrode layer 171.

[0104] By using the sealing mask layer 18, a portion of the first electrode layer 171 is etched away, exposing a portion of the third support layer 111.

[0105] A first opening is formed in the exposed third support layer 111.

[0106] The second sacrificial layer 112 is removed through the first opening, exposing part of the second support layer 113.

[0107] A second opening is formed in the exposed second support layer 113.

[0108] The first sacrificial layer 114 is removed through the second opening.

[0109] In this embodiment of the present disclosure, the sealing mask layer 18 can be formed by the following steps: First, an initial sealing mask layer 18a and a second photoresist layer 19 are formed on the surfaces of the capacitor hole 17 having a first electrode layer 171 and the etching post 16 having the first electrode layer 171, wherein the second photoresist layer 19 has a specific pattern D, the specific pattern D exposing a portion of the first electrode layer 171 in the array region A and the first electrode layer on the surface of the peripheral region B; Second, the initial sealing mask layer 18a is etched through the second photoresist layer 19 to transfer the specific pattern D into the initial sealing mask layer 18a, thereby forming the sealing mask layer 18.

[0110] like Figures 2h-2k As shown, an initial sealing mask layer 18a and a second photoresist layer 19 with a specific pattern D are formed on the surfaces of the capacitor hole 17 with the first electrode layer 171 and the etching pillar 16 with the first electrode layer 171. The initial sealing mask layer 18a is etched through the second photoresist layer 19 to transfer the specific pattern D into the initial sealing mask layer 18a, forming the sealing mask layer 18. Through the sealing mask layer 18, a portion of the first electrode layer 171 in the array region A and the first electrode layer on the surface of the peripheral region B are etched away, exposing the first electrode layer. The stacked structure of the third support layer 111 and the peripheral region B is partially exposed. A first opening (not shown in the figure) is formed in the exposed third support layer 111 in the array region A using a dry etching process. Through the first opening, a second sacrificial layer 112 is removed using a wet etching process, exposing a portion of the second support layer 113. A second opening (not shown in the figure) is formed in the exposed second support layer 113 using a dry etching process. Through the second opening, a first sacrificial layer 114 is removed using a wet etching process, forming a structure as shown in the figure. Figure 2j The structure shown includes a dielectric layer 172 and a second electrode layer 173 sequentially formed on the surface of the first electrode layer 171 in array region A.

[0111] It should be noted that when removing the second sacrificial layer 112 and the first sacrificial layer 114 in array region A, the third support layer 111, the second sacrificial layer 112, the second support layer 113, and the first sacrificial layer 114 in the outer region B are also removed simultaneously, leaving only the first support layer 115 in the outer region B. Figure 2j and 2k (The outer area is not shown).

[0112] In some embodiments, after forming the second electrode layer 173, the method for forming the semiconductor structure further includes depositing a conductive material 174 in the gaps between the second electrode layers 173. In this embodiment, the conductive material 174 may be polycrystalline silicon or any other suitable conductive material, such as germanium-silicon or doped polycrystalline silicon.

[0113] like Figure 2lAs shown, conductive material 174 is deposited in the gaps between the second electrode layers 173.

[0114] In related technologies, during the process of opening the first electrode layer 171 and the first support layer 115 at the top of the etched pillar 16 to form the first opening, the first electrode layer 171 in contact with the first support layer 115 is simultaneously removed, resulting in a reduction in the effective area between the electrodes and thus a decrease in the final capacitance. In this embodiment, by directly forming a sealing mask layer 18 on the surface of the capacitor hole 17 with the first electrode layer 171 and the etched pillar 16 with the first electrode layer 171, the first electrode layer 171 is removed through the sealing mask layer 18 to form the first opening without damaging the first electrode layer 171 in contact with the first support layer 115. Therefore, the final capacitor structure is highly uniform, and the effective area between the electrodes is larger than that in related technologies. Thus, the capacitor structure formed in this embodiment has a higher capacitance.

[0115] In other embodiments, please refer to Figure 2m and 2n Other methods for forming semiconductor structures include:

[0116] Electrode material is deposited within the capacitor aperture to form a first electrode layer 171; wherein the electrode material fills the capacitor aperture.

[0117] A dielectric layer 172 and a second electrode layer 173 are sequentially deposited on the surface of the first electrode layer 171 to form a capacitor structure.

[0118] like Figure 2m and 2n As shown, electrode material is deposited within capacitor aperture 17 to form a first electrode layer 171, wherein the electrode material fills capacitor aperture 17. A first opening (not shown) is formed in the exposed third support layer 111, through which a second sacrificial layer 112 is removed, exposing a portion of the second support layer 113. A second opening (not shown) is formed in the exposed second support layer 113, through which the first sacrificial layer 114 is removed. A dielectric layer 172 and a second electrode layer 173 are sequentially formed on the surface of the first electrode layer 171, ultimately forming a capacitor structure, wherein the second electrode layer 173 fills the gaps between the dielectric layers 172.

[0119] It should be noted that, Figure 2m and 2n Only array region A is shown; the surrounding region is not shown.

[0120] The semiconductor structure formation method provided in this disclosure, on the one hand, adds a buffer layer 12 between the stacked structure 11 and the mask layer to improve the step difference between the array region and the peripheral region, avoids damage to the stacked structure 11 and residue of the mask layer 13, facilitates subsequent process steps, and improves the semiconductor structure fabrication yield. On the other hand, in this disclosure, the stacked structure 11 is first partially etched (without exposing the bottom support structure), then the etched structure is cleaned, and finally the remaining stacked structure 11 is etched again. This avoids the loss of bottom support material during the cleaning process, forming a curved profile, which prevents short circuits in the subsequently formed capacitors and improves the semiconductor structure yield. In addition, the semiconductor structure formation method provided in this disclosure can etch and form capacitor structures with high height (e.g., height greater than 1000 nanometers) and high aspect ratio (e.g., aspect ratio greater than 20:1). That is, the semiconductor structure formation method provided in this disclosure can form capacitors with high height, high aspect ratio, and large capacitance.

[0121] This disclosure also provides a semiconductor structure, which is formed using the semiconductor structure formation method described in the above embodiments. Figure 3 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure. The semiconductor structure 30 includes at least a substrate 10 and a capacitor structure. The substrate 10 includes a contact structure 101 and an insulating layer 102 that isolates adjacent contact structures 101. The capacitor structure includes a first electrode layer 171, a dielectric layer 172, and a second electrode layer 173. The gap between adjacent second electrode layers 173 is filled with a conductive material 174. The capacitor structure is located on the surface of the substrate 10 and is in contact with the contact structure 101.

[0122] In some embodiments, the capacitor structure further includes a first support layer 115, a second support layer 113, and a third support layer 111; wherein the etching selectivity of the first support layer 115 relative to the insulating layer 102 is greater than or equal to 10.

[0123] In this embodiment, since the first support layer 115 has a higher etching selectivity than the insulating layer 102, meaning that the first support layer 115 is easier to etch and remove than the insulating layer 102, the first support layer 115 will not be over-etched when etching the first support layer 115 to form a capacitor structure, thus preventing damage to the insulating layer 102 material and improving the semiconductor structure fabrication yield.

[0124] In some embodiments, the semiconductor structure also includes other functional structures, such as transistors (not shown in the figure); the transistor includes a gate, a source, and a drain; the substrate 10 also includes word lines and bit lines (not shown in the figure); wherein the gate is connected to the word lines, the drain or source is connected to the bit lines, and the source or drain is connected to the contact structure 101.

[0125] In this embodiment, the gate includes a gate dielectric layer, a gate metal layer, and a gate insulating layer. The gate dielectric layer can be a high-k dielectric material, such as one or any combination of lanthanum oxide, aluminum oxide, hafnium oxide, hafnium oxynitride, hafnium silicate, or zirconium oxide. The gate metal layer can be one or a combination of polysilicon, metals (e.g., tungsten, copper, aluminum, titanium, tantalum), metal alloys, metal silicides, titanium nitride, and other conductive materials.

[0126] In this embodiment of the disclosure, the bit line may be made of conductive material, such as one or a combination of polysilicon, metal silicide, conductive metal nitride (e.g., titanium nitride, tantalum nitride, tungsten nitride, etc.) and metal (e.g., tungsten, titanium, tantalum, etc.).

[0127] The semiconductor structure provided in this disclosure is similar to the semiconductor structure formation method in the above embodiments. For technical features not disclosed in detail in this disclosure, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0128] The semiconductor structure provided in this disclosure includes at least a capacitor structure. Since the capacitor structure in this disclosure has a high height (e.g., greater than 1000 nm) and is uniform, and has a large depth-to-width ratio (e.g., greater than 20:1), the effective area between the electrodes of the capacitor structure is large, and the capacitance of the capacitor structure is high. This disclosure can provide a semiconductor structure with a high-capacity capacitor structure.

[0129] This disclosure also provides another semiconductor structure, which is formed by the semiconductor structure formation method described in the above embodiments. Figure 4 This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure. The semiconductor structure 40 includes at least: a substrate 10 and a capacitor structure; wherein, the substrate 10 includes a contact structure 101 and an insulating layer 102 that isolates adjacent contact structures 101; the capacitor structure includes a first electrode layer 171, a dielectric layer 172 and a second electrode layer 173, and the capacitor structure is located on the surface of the substrate 10 and is in contact with the contact structure 101.

[0130] Please continue reading Figure 4In the capacitor structure, the first electrode layer 171 is in contact with the contact structure 101, the first support layer 115, the second support layer 113 and the third support layer 111 respectively, and the top surface of the first electrode layer 171 is flush with the top surface of the third support layer 111. The dielectric layer 172 is located on the surface of the first electrode layer 171 and the second electrode layer 173 is located on the surface of the dielectric layer 172.

[0131] In some embodiments, the capacitor structure includes at least a first support layer 115; wherein the etching selectivity of the first support layer 115 relative to the insulating layer 102 is greater than or equal to 10.

[0132] In this embodiment, since the first support layer 115 has a higher etching selectivity than the insulating layer 102, meaning that the first support layer 115 is easier to etch and remove than the insulating layer 102, the first support layer 115 will not be over-etched when etching the first support layer 115 to form a capacitor structure, thus preventing damage to the insulating layer 102 material and improving the semiconductor structure fabrication yield.

[0133] In some embodiments, the semiconductor structure further includes other functional structures, such as transistors; the transistors include a gate, a source, and a drain; the substrate further includes a substrate, word lines, and bit lines; wherein the gate is connected to the word lines, the drain or source is connected to the bit lines, and the source or drain is connected to the contact structure 101.

[0134] The semiconductor structure provided in this disclosure is similar to the semiconductor structure formation method in the above embodiments. For technical features not disclosed in detail in this disclosure, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0135] The semiconductor structure provided in this disclosure includes at least a capacitor structure. Since the capacitor structure in this disclosure has a high height (e.g., greater than 1000 nm) and a large depth-to-width ratio (e.g., greater than or equal to 20:1), the effective area between the electrodes of the capacitor structure is large, and the capacitance of the capacitor structure is high. This disclosure can provide a semiconductor structure with a high-capacity capacitor structure.

[0136] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the various components shown or discussed are coupled to each other or directly coupled.

[0137] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0138] The above are merely some embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, include: A stacked structure is provided, the stacked structure being formed on a substrate surface having an array region and a peripheral region; A buffer layer and a mask layer are sequentially formed on the stacked structure; wherein the mask layer located in the array region has a first pattern; The first pattern is transferred to the stacked structure by sequentially etching the buffer layer and the stacked structure through the mask layer; The mask layer is etched away until the buffer layer on the surface of the peripheral region is exposed to form the semiconductor structure.

2. The method according to claim 1, characterized in that, The thickness of the buffer layer is 99–152 nanometers.

3. The method according to claim 1, characterized in that, During the process of sequentially etching the buffer layer and the stacked structure through the mask layer, the etching selectivity of the buffer layer relative to the mask layer is greater than or equal to 8.

4. The method according to any one of claims 1 to 3, characterized in that, During the etching process to remove the mask layer until the buffer layer on the surface of the peripheral region is exposed, the etch selectivity of the mask layer relative to the buffer layer is greater than or equal to 5.

5. The method according to claim 4, characterized in that, The stacked structure includes a first support layer, a first sacrificial layer, a second support layer, a second sacrificial layer, and a third support layer stacked sequentially from bottom to top; The first pattern is transferred into the stacked structure by sequentially etching the buffer layer and the stacked structure through the mask layer, including: The first pattern is transferred to the buffer layer and part of the stacked structure by sequentially etching the buffer layer, the third support layer, the second sacrificial layer, the second support layer, and a portion of the first sacrificial layer through the mask layer.

6. The method according to any one of claims 1 to 3, characterized in that, The mask layer located in the peripheral region has a second pattern; The pattern density of the first pattern is greater than that of the second pattern.

7. The method according to claim 5, characterized in that, The first pattern includes a capacitor hole pattern; the substrate includes at least a contact structure corresponding to the capacitor hole pattern; After etching away the mask layer until the buffer layer on the surface of the peripheral region is exposed, the method for forming the semiconductor structure further includes: The remaining first sacrificial layer and first support layer are etched until the contact structure is exposed to form a plurality of capacitor holes and etch pillars located between two adjacent capacitor holes in the stacked structure, wherein the etch selectivity of the buffer layer relative to the first sacrificial layer is greater than or equal to 1.

8. The method according to claim 7, characterized in that, The method further includes: While forming the plurality of capacitor holes, the buffer layer is removed.

9. The method according to claim 7, characterized in that, The method further includes: A first electrode layer is formed on the inner wall of the capacitor hole and on the surface of the etched pillar; The second sacrificial layer and the first sacrificial layer in the etching column are removed sequentially; A dielectric layer and a second electrode layer are sequentially deposited on the surface of the first electrode layer to form a capacitor structure.

10. The method according to claim 9, characterized in that, The sequential removal of the second sacrificial layer and the first sacrificial layer in the etching pillar includes: A sealing mask layer is formed on the surface of a capacitor hole having the first electrode layer and an etch post having the first electrode layer; wherein the sealing mask layer exposes a portion of the first electrode layer; By etching away part of the first electrode layer through the sealing mask layer, part of the third support layer is exposed; A first opening is formed in the exposed third support layer; The second sacrificial layer is removed through the first opening, exposing a portion of the second support layer; A second opening is formed in the exposed second support layer; The first sacrificial layer is removed through the second opening.

11. The method according to claim 7, characterized in that, The method further includes: An electrode material is deposited within the capacitor aperture to form a first electrode layer; wherein the electrode material fills the capacitor aperture. A dielectric layer and a second electrode layer are sequentially deposited on the surface of the first electrode layer to form a capacitor structure.

12. The method according to any one of claims 7 to 11, characterized in that, The substrate also includes an insulating layer for isolating the contact structure; Wherein, the etching selectivity ratio of the first support layer relative to the insulating layer is greater than or equal to 10.

13. A semiconductor structure, characterized in that, The semiconductor structure is formed by the semiconductor structure forming method according to any one of claims 1 to 12, and the semiconductor structure includes at least: a substrate and a capacitor structure; The substrate includes a contact structure; The capacitor structure is located on the surface of the substrate and is in contact with the contact structure.

14. The semiconductor structure according to claim 13, characterized in that, The capacitor structure includes at least a first support layer; the substrate also includes an insulating layer for isolating the contact structure. Wherein, the etching selectivity ratio of the first support layer relative to the insulating layer is greater than or equal to 10.

15. The semiconductor structure according to claim 13 or 14, characterized in that, The semiconductor structure further includes: a transistor; the transistor includes a gate, a source, and a drain; the substrate further includes word lines and bit lines; The gate is connected to the word line, the drain or the source is connected to the bit line, and the source or the drain is connected to the contact structure.

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