Methods for fabricating semiconductor structures and memory

Abstract

This disclosure provides a method for fabricating a semiconductor structure and a memory, relating to the field of semiconductor technology, and addresses the problem of poor integration in semiconductor structures. The semiconductor structure includes multiple rows of memory groups, each row comprising multiple memories spaced apart along the row direction. In any two adjacent rows of memory groups, the memories in one row are staggered with those in the other. This allows for efficient use of the space between adjacent memories, increasing the number of memories per unit area and improving the integration of the semiconductor structure. Furthermore, this embodiment integrates two memory cell arrays together, sharing a single bitline structure. This reduces the memory size and further enhances the integration of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor structure technology, and more particularly to a method for fabricating a semiconductor structure and a memory. Background Technology

[0002] Dynamic random access memory (DRAM) is a semiconductor memory that allows for high-speed, random writing and reading of data, and is widely used in data storage devices. DRAM consists of multiple repeating memory cells, each typically including a capacitor and a transistor. The capacitor stores data, and the transistor controls the reading of the data from the capacitor.

[0003] To increase the storage capacity of semiconductor structures, semiconductor structures have evolved from two-dimensional to three-dimensional, meaning that the storage cells in three-dimensional semiconductor structures are arranged in three dimensions. However, the aforementioned storage cells still suffer from a lack of compactness in their arrangement, reducing the integration density of the semiconductor structure. Summary of the Invention

[0004] In view of the above problems, this disclosure provides a method for fabricating a semiconductor structure and a memory, which is used to improve the integration of the semiconductor structure.

[0005] According to some embodiments, a first aspect of the present disclosure provides a semiconductor structure comprising: multiple rows of memory groups, each row of the memory group comprising a plurality of memories spaced apart along the row direction, and in any two adjacent rows of memory groups, the memories in one row of the memory group are misaligned with the memories in the other row of the memory group.

[0006] Each of the memories includes two memory cell arrays and a bit line structure, wherein the two memory cell arrays are located on opposite sides of the bit line structure in the row direction;

[0007] The bit line structure extends along a first direction and is electrically connected to transistors in two memory cell arrays. One end of the bit line structure protrudes from the memory cell array and is a stepped surface. The protruding portion of the bit line structure is located between adjacent memories in the adjacent memory group. The first direction is perpendicular to the row direction and lies in the same horizontal plane.

[0008] In some embodiments, each row of the memory group includes a first sub-memory group and a second sub-memory group, the first sub-memory group and the second sub-memory group being spaced apart along the first direction, and the first sub-memory group and the second sub-memory group being symmetrically arranged with respect to the row direction.

[0009] In some embodiments, the storage cell array includes a plurality of storage cell layers, which are spaced apart along a second direction. In any two adjacent storage cell layers, the projection of one storage cell layer onto the other storage cell layer coincides with the projection of the other storage cell layer. The second direction, the first direction, and the row direction are perpendicular to each other.

[0010] Each of the memory cell layers includes a plurality of memory cells spaced apart along the first direction, and each memory cell includes a transistor and a capacitor connected to the transistor.

[0011] In some embodiments, there are multiple capacitors, which are spaced apart along a row direction, and one electrode layer of each capacitor is interconnected.

[0012] In some embodiments, the bit line structure includes a plurality of bit lines spaced apart along the second direction, one bit line connecting all the transistors of the memory cells in the memory cell layer located on the same layer, and the connection end between the transistor and the bit line and the connection end between the transistor and the capacitor are not the same end;

[0013] Along the first direction, each bit line has a first surface and a second surface disposed opposite to each other; one of the first surface and the second surface of all bit lines is aligned, and the other forms a step from top to bottom along the second direction.

[0014] In some embodiments, all bit lines except the topmost bit line include a first segment and a second segment connected in sequence, wherein the width of the second segment is smaller than the width of the first segment.

[0015] At least a portion of the second segment is located between adjacent memories in the adjacent memory group.

[0016] In some embodiments, the memory further includes a word line structure comprising a plurality of word lines spaced apart along a first direction, each word line extending along a second direction for connecting the gates of all the memory cells in the same second direction.

[0017] In some embodiments, a first data line, a second data line, and a third data line are also included;

[0018] The first data line is connected to the bit line structure;

[0019] The second data line is connected to the word line, and the third data line is connected to the capacitor of the memory.

[0020] According to some embodiments, a second aspect of this disclosure provides a method for fabricating a memory in a semiconductor structure provided in the first aspect, comprising the following steps:

[0021] A substrate is provided, the substrate having a first region, a second region and a third region, the first region and the third region being symmetrically disposed on both sides of the second region;

[0022] Storage cell arrays are formed in the first region and the third region, respectively;

[0023] A bit line structure is formed in the second region, and the bit line structure is electrically connected to the transistors in the two memory cell arrays respectively. One end of the bit line structure protrudes from the memory cell array and is a stepped surface.

[0024] In some embodiments, the first region includes a first sub-region and a second sub-region that are interconnected, the first sub-region being used to form a transistor and the second sub-region being used to form a capacitor;

[0025] The steps of forming a memory cell array in the first region and the third region respectively include:

[0026] Multiple stacked structures are formed in the first region and the third region at intervals along a first direction, and a first trench is formed between adjacent stacked structures; and a stacked structure is formed in the second region; wherein each stacked structure includes multiple sacrificial layers and active layers that are alternately stacked, and the film layers of the stacked structure are the same as the film layers of the stacked structure.

[0027] Remove a portion of the sacrificial layer located in the first region and the third region to form a second trench communicating with the first trench;

[0028] A support structure is formed in the first trench and the second trench, the support structure being used to support any adjacent active layers;

[0029] Remove the remaining sacrificial layer and form a first dielectric layer in the region where the remaining sacrificial layer is located;

[0030] A portion of the first dielectric layer and a portion of the second dielectric layer located in the first sub-region are removed to form a filling region, which exposes a portion of the active layer for forming the channel region of a transistor.

[0031] A gate oxide layer and word lines are formed within the filled region, wherein the word lines and gate oxide layer surrounding the active layer constitute a transistor together with the active layer;

[0032] A capacitor is formed in the second sub-region, and the capacitor is connected to a transistor.

[0033] In some embodiments, after the step of forming a multi-column stacked structure spaced apart along a first direction on the first region and the third region, and before the step of removing a portion of the sacrificial layer located in the first region and the third region, the method further includes:

[0034] A second dielectric layer is formed within the first trench, the second dielectric layer extending outside the first trench and covering the top surface of the multiple stacked structures.

[0035] In some embodiments, the capacitor includes a first electrode layer, a dielectric layer, and a second electrode layer, wherein the first electrode layer, the dielectric layer, and the second electrode layer are sequentially surrounded on an active layer located in a second sub-region.

[0036] In some embodiments, a capacitor is formed in the second sub-region after the step of connecting the capacitor to the transistor.

[0037] An interconnect layer is formed, which fills the space between any adjacent capacitors and is connected to the second electrode layer of each capacitor;

[0038] An insulating layer is formed on the second region and the first sub-region, the top surface of the insulating layer being flush with the top surface of the interconnect layer.

[0039] In some embodiments, the step of forming a bit line structure in the second region includes:

[0040] A portion of the stacked structure is removed to form a groove within the stacked structure. The bottom of the groove is the top surface of the lowest active layer, and one sidewall of the groove is a stepped surface. The active layer retained on the second region constitutes a bitline structure.

[0041] In some embodiments, after the step of forming a bit line structure in the second region, the method further includes:

[0042] A third dielectric layer is formed, which fills the groove and covers the insulating layer and the interconnect layer;

[0043] The third dielectric layer is graphically represented to form a plurality of filling holes within the third dielectric layer, wherein the bottom of the filling hole located in the first sub-region is the top surface of the word line, the bottom of the filling hole located in the second sub-region is the top surface of the interconnect layer, and the bottom of the filling hole located in the second region are each of the step surfaces;

[0044] Conductive material is deposited within the filling holes to form a first data line, a second data line, and a third data line, respectively.

[0045] In the semiconductor structure and memory fabrication method provided in this disclosure, in any two adjacent rows of memory groups, the memory in one row of memory group is staggered with the memory in the other row of memory group, and the protruding part of the bit line structure is located between adjacent memories in the adjacent memory group. In this way, the space between adjacent memories can be reasonably utilized, the number of memories per unit area can be increased, and the integration density of the semiconductor structure can be improved.

[0046] Furthermore, this embodiment integrates two memory cell arrays together, and the two memory cell arrays share a single bit line structure. This reduces the size of the memory and improves the integration density of the semiconductor structure.

[0047] In addition to the technical problems solved by the embodiments of this disclosure, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the semiconductor structure and memory fabrication methods provided by the embodiments of this disclosure, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific embodiments. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 A schematic diagram of the semiconductor structure provided in the embodiments of this disclosure. Figure 1 ;

[0050] Figure 2 for Figure 1 Enlarged schematic diagram of region F in the middle;

[0051] Figure 3 A schematic diagram of the semiconductor structure provided in the embodiments of this disclosure. Figure 2 ;

[0052] Figure 4 for Figure 3 Enlarged schematic diagram of region H in the middle;

[0053] Figure 5 A schematic diagram of the memory structure provided in the embodiments of this disclosure;

[0054] Figure 6 A partial structural schematic diagram of the memory provided in an embodiment of this disclosure;

[0055] Figure 7 A partial perspective view of the memory provided in an embodiment of this disclosure;

[0056] Figure 8 A process flow diagram of the method for fabricating the memory provided in the embodiments of this disclosure;

[0057] Figure 9 Cross-sectional views in the AA, BB, CC, DD and EE directions after the initial stacked structure is formed in the method for fabricating the memory provided in the embodiments of this disclosure;

[0058] Figure 10 Cross-sectional views in the AA, BB, CC, DD and EE directions after the formation of the first mask layer in the method for fabricating the memory provided in the embodiments of this disclosure;

[0059] Figure 11 Cross-sectional views in the AA, BB, CC, DD and EE directions after the first trench is formed in the method for fabricating the memory provided in the embodiments of this disclosure;

[0060] Figure 12 Cross-sectional views in the AA, BB, CC, DD and EE directions after the formation of the second dielectric layer in the method for fabricating the memory provided in the embodiments of this disclosure;

[0061] Figure 13 Cross-sectional views in the AA, BB, CC, DD and EE directions after the second trench is formed in the method for fabricating the memory provided in the embodiments of this disclosure;

[0062] Figure 14 Cross-sectional views in the AA, BB, CC, DD and EE directions after the support structure is formed in the method for fabricating the memory provided in the embodiments of this disclosure;

[0063] Figure 15 Cross-sectional views in the AA, BB, CC, DD and EE directions after the formation of the first dielectric layer in the method for fabricating the memory provided in the embodiments of this disclosure;

[0064] Figure 16 Cross-sectional views in the AA, BB, CC, DD and EE directions after the filling region is formed in the method for fabricating the memory provided in the embodiments of this disclosure;

[0065] Figure 17 Cross-sectional views in the AA, BB, CC, DD and EE directions after the gate oxide layer and word lines are formed in the method for fabricating the memory provided in the embodiments of this disclosure;

[0066] Figure 18Cross-sectional views in the AA, BB, CC, DD and EE directions after removing a portion of the first dielectric layer and the second dielectric layer in the method for fabricating the memory provided in the embodiments of this disclosure;

[0067] Figure 19 Cross-sectional views in the AA, BB, CC, DD and EE directions after the capacitor is formed in the method for fabricating the memory provided in the embodiments of this disclosure;

[0068] Figure 20 Cross-sectional views in the AA, BB, CC, DD and EE directions after the formation of the first photoresist layer in the method for fabricating the memory provided in the embodiments of this disclosure;

[0069] Figure 21 Cross-sectional views in the AA, BB, CC, DD and EE directions after forming the bit line structure in the method for fabricating the memory provided in the embodiments of this disclosure;

[0070] Figure 22 Cross-sectional views in the AA, BB, CC, DD and EE directions after the formation of the third dielectric layer in the method for fabricating the memory provided in the embodiments of this disclosure;

[0071] Figure 23 Cross-sectional views in the AA, BB, CC, DD and EE directions after forming a filling hole in the method for fabricating a memory provided in the embodiments of this disclosure;

[0072] Figure 24 Cross-sectional views in the AA, BB, CC, DD and EE directions after the formation of the first data line, the second data line and the third data line in the method for fabricating the memory provided in the embodiments of this disclosure.

[0073] Figure label:

[0074] 1000: Memory group; 100: Memory; 110: Memory cell array; 111: Memory cell; 1111: Transistor; 1112: Capacitor; 120: Bit line structure; 121: Bit line; 121a: First segment; 121b: Second segment; 130: Gap; 140: Word line; 150: First data line; 160: Second data line; 170: Third data line; 180: First photoresist layer; 181: First aperture; 190: Third dielectric layer; 191: Fill hole;

[0075] 10: Substrate; 21: Initial active layer; 22: First initial sacrificial layer; 23: Initial stack-up structure; 24: First trench; 25: Sacrificial layer; 26: Active layer; 27: Second trench; 30: Stack-up structure; 40: Second dielectric layer; 50: Support structure; 60: First dielectric layer; 70: Fill region; 80: Gate oxide layer; 90: Interconnect layer; 91: Insulating layer. Detailed Implementation

[0076] As described in the background art, the three-dimensional semiconductor structure in the related art has the defect of low integration. The inventors have found that the reason for this problem is that when the memory is arranged in a regular rectangular array, in order to avoid interference between adjacent bit line structures, the distance between any adjacent memory is usually increased, which reduces the integration of the semiconductor structure.

[0077] To address the aforementioned technical problems, this application provides a method for fabricating a semiconductor structure and a memory. In any two adjacent rows of memory groups, the memory in one row of memory group is staggered with the memory in the other row of memory group. The protruding part of the bit line structure is located between adjacent memories in the adjacent memory group. In this way, the space between adjacent memories can be reasonably utilized, the number of memories per unit area can be increased, and the integration density of the semiconductor structure can be improved.

[0078] Furthermore, this embodiment integrates two memory cell arrays together, and the two memory cell arrays share a single bit line structure. This reduces the size of the memory and improves the integration density of the semiconductor structure.

[0079] To make the above-mentioned objects, features, and advantages of the embodiments of this disclosure more apparent and understandable, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0080] This embodiment does not limit the semiconductor structure. The following description will take dynamic random access memory (DRAM) as an example, but this embodiment is not limited to this. Other semiconductor structures are also possible in this embodiment.

[0081] Please refer to the attached document. Figure 1 To be continued Figure 7 This disclosure provides a semiconductor structure including a multi-row memory group 1000, wherein each row of the memory group 1000 includes an appendix. Figure 1 The component within the dashed box.

[0082] Please refer to the attached document. Figure 2 Each row of memory groups 1000 includes multiple memory units 100, which are spaced apart along the row direction, such that there is a gap 130 between adjacent memory units 100. The row direction can be referenced in the appendix. Figure 1 The X direction in the equation.

[0083] It should be noted that in the same row of memory group 1000, the gap 130 between adjacent memory 100 can be equal or unequal, and this embodiment does not make a specific limitation here.

[0084] In any two adjacent rows of memory groups 1000, the memory 100 in one row of memory group 1000 is misaligned with the memory 100 in the other row of memory group 1000.

[0085] With attachment Figure 1 Taking the semiconductor structure shown as an example, the semiconductor structure includes four rows of memory groups 1000. For ease of description, we can refer to the top row as the first row or along the Y direction, and the bottom row as the fourth row.

[0086] As can be seen from the above, in this embodiment, the memory groups 1000 in odd-numbered rows and even-numbered rows are staggered, so that the memory groups 1000 in odd-numbered rows are aligned in the column direction, and the memory groups 1000 in even-numbered rows are aligned in the column direction. This makes the arrangement of the memory groups 1000 more compact, thereby allowing more memory groups 1000 to be placed per unit area, increasing the density of memory groups 1000 in the semiconductor structure, and thus improving the integration of the semiconductor structure. It is understood that the column direction can be... Figure 1 in the Y direction.

[0087] Each memory 100 includes two memory cell arrays 110 and a bit line structure 120. In the row direction X, the two memory cell arrays 110 are located on opposite sides of the bit line structure 120. In other words, in the row direction X, the memory cell arrays 110, the bit line structure 120 and the memory cell arrays 110 are arranged in sequence.

[0088] The bitline structure 120 extends along a first direction, which is perpendicular to the row direction and lies in the same horizontal plane. For example, the first direction can be understood as the column direction.

[0089] Bit line structure 120 is electrically connected to transistors in two memory cell arrays 110 to write data into or read data from memory cell arrays 110 via bit line structure 120.

[0090] One end of the bit line structure 120 protrudes from the memory cell array 110, and this end has a stepped surface to facilitate the connection of subsequent data lines to the bit line structure 120. The protruding portion of the bit line structure 120 is located between adjacent memory cells 100 in the adjacent memory group 1000. (See attached image) Figure 1 Taking the orientation as an example, the protruding portion of the bit line structure 120 of the first memory 100 in the second memory group 1000 is located in the gap 130 between the first memory 100 and the second memory 100 in the first memory group 1000.

[0091] In the semiconductor structure of this embodiment, in any two adjacent rows of memory groups 1000, the memory 100 in one row of memory group 1000 is staggered with the memory 100 in the other row of memory group 1000. The protruding part of the bit line structure 120 is located between adjacent memory 100 in the adjacent memory group. In this way, the space between adjacent memory 100 can be reasonably utilized, the number of memory 100 per unit area can be increased, and the integration density of the semiconductor structure can be improved.

[0092] In addition, this embodiment integrates two memory cell arrays 110 together, and the two memory cell arrays 110 share a bit line structure 120. In this way, the size of the memory 100 can be reduced, which is beneficial to improving the integration of the semiconductor structure.

[0093] In some embodiments, please refer to the appendix. Figure 3 and attached Figure 4 Each row of memory group 1000 includes a first sub-memory group 1000a and a second sub-memory group 1000b. The first sub-memory group 1000a and the second sub-memory group 1000b are spaced apart along a first direction and are symmetrically arranged with respect to the row direction.

[0094] For ease of understanding, the first sub-memory group 1000a is an appendix. Figure 3 The component within the first dashed box, and the second sub-memory group 1000b are attached. Figure 3 The component within the second dashed box.

[0095] The first sub-memory group 1000a and the second sub-memory group 1000b are arranged at intervals along the first direction Y, and the first sub-memory group 1000a and the second sub-memory group 1000b are arranged symmetrically with respect to the row direction X. That is, the protruding part of the bit line structure 120 of the first sub-memory group 1000a is in the opposite direction to the protruding part of the bit line structure 120 of the second row memory 100b.

[0096] With attachment Figure 3Taking the orientation as an example, the protruding portion of the bit line structure 120 in the first sub-memory group 1000a of the second row memory group 1000 is located in the gap between adjacent memories 100 in the first row memory group 1000, and the protruding portion of the bit line structure 120 in the second sub-memory group 1000b of the second row memory group 1000 is located in the gap between adjacent memories 100 in the third row memory group 1000. In this way, more memory groups 1000 can be set within a unit area to increase the integration density of the semiconductor structure.

[0097] In some embodiments, please refer to the appendix. Figure 5 and attached Figure 7 The storage cell array 110 includes multiple storage cell layers, which are spaced apart along a second direction. The second direction, the first direction, and the row direction are perpendicular to each other; that is, the second direction is the adjacent direction. Figure 7 The Z direction within. It's important to understand that the storage unit layer can be understood as attached... Figure 5 The structure in.

[0098] In any two adjacent storage cell layers, the projection of one storage cell layer onto the other storage cell layer coincides with the projection of the other storage cell layer. That is, multiple storage cell layers are aligned in a direction perpendicular to the paper to facilitate the setting of subsequent word line structures.

[0099] Each memory cell layer includes a plurality of memory cells 111 spaced apart along a first direction. Each memory cell 111 includes a transistor 1111 and a capacitor 1112 connected to the transistor 1111, such that the extension direction of each memory cell is horizontal. In this way, multiple stacked memory cell layers can be formed in the same equivalent area, thereby increasing the storage capacity of the memory and thus improving the storage capacity of the semiconductor structure.

[0100] Among them, transistor 1111 can be a gate all-around field-effect transistor (GAA), which can include a source, a drain, and a gate located between the source and the drain. The gate can be used to control the current flow between the source and the drain.

[0101] Capacitor 1112 can be connected to one of the source and drain of transistor 1111. For example, capacitor 1112 can be connected to the source of transistor 1111, and correspondingly, bit line structure 120 can be connected to the drain of transistor 1111.

[0102] In one possible implementation, there are multiple capacitors 1112, which are spaced apart along the row direction, and adjacent capacitors 1112 are connected by a support member. This increases the storage capacity of a single memory module, thereby improving the storage capacity of the semiconductor structure.

[0103] Multiple capacitors 1112 have their electrode layers interconnected, allowing them to be connected in parallel. This makes the capacitance of the semiconductor structure equal to the sum of the capacitances of all the capacitor structures, and the total current after the capacitor structures are connected in parallel equal to the sum of the currents of each individual capacitor structure. This increases the storage capacity of the semiconductor structure and improves its performance.

[0104] In some embodiments, continue to refer to the appendix. Figure 7 The bit line structure 120 includes multiple bit lines 121 spaced apart along a second direction. Each bit line 121 connects to the transistors 1111 of all memory cells 111 in the same memory cell layer. The number of bit lines 121 corresponds one-to-one with the number of memory cell layers; that is, each bit line 121 connects to a memory cell layer on the same horizontal plane. For example, one bit line 121 is used to connect the memory cell layers of the first layer in two memory cell arrays 110.

[0105] The connection point between the transistor and bit line 121 is not the same as the connection point between the transistor and capacitor 1112. For example, if bit line 121 is connected to the source of the transistor, then capacitor 1112 is connected to the drain of the transistor; or, for another example, if bit line 121 is connected to the drain of the transistor, then capacitor 1112 is connected to the source of the transistor.

[0106] Along the first direction, each bit line 121 has a first surface and a second surface disposed opposite to each other; with attachment Figure 6 and attached Figure 7 Taking the orientation shown as an example, the first surface can be the rear surface of the bit line 121, and the second surface can be the front surface of the bit line 121.

[0107] One of the first and second surfaces of bit line 121 is aligned, while the other is stepped down along a second direction. In one example, the first surfaces of all bit lines 121 are aligned, while the second surfaces of all bit lines 121 are not aligned, and the length of the bit lines increases sequentially from top to bottom, resulting in a stepped second surface on all bit lines 121. In another example, the first surfaces of all bit lines 121 are not aligned, while the second surfaces of all bit lines 121 are aligned, resulting in a stepped first surface on all bit lines 121. This facilitates the fabrication of data lines connected to each bit line and also increases the spacing between these bit lines, preventing interference of transmitted signals. Furthermore, it can reduce the parasitic capacitance between the bit lines of the upper and lower layers, improving the performance of the semiconductor structure.

[0108] The width of bit line 121 can be equal everywhere or unequal. For example, continue to refer to the appendix. Figure 7All bit lines 121 except the topmost bit line include a first segment 121a and a second segment 121b connected in sequence. The width of the second segment 121b is smaller than the width of the first segment 121a.

[0109] With attachment Figure 7 Taking the orientation shown as an example, there are four bit lines 121. From top to bottom, the width of the first bit line 121 is the same everywhere. The widths of the second bit line 121, the third bit line 121, and the fourth bit line 121 are not equal. Each bit line 121 includes a first segment 121a and a second segment 121b. The width of the second segment 121b is smaller than the width of the first segment 121a. At least a portion of the second segment 121b is located between adjacent memory 100s in the adjacent memory group 1000.

[0110] This embodiment reduces the width of the second bit line 121, the third bit line 121, and the fourth bit line 121. If the gap 130 between adjacent memory 100 in the same row can be further reduced, space can be better utilized, thus enabling more memory to be placed in a unit area and improving the integration of the semiconductor structure.

[0111] In addition, the width of the first segment 121a can be the same as the width of the first bit line 121, thereby ensuring that a bit line structure of uniform width is formed in the same manufacturing process.

[0112] In some embodiments, continue to refer to the appendix. Figure 7 The memory 100 also includes a word line structure, which includes a plurality of word lines 140 spaced apart along a first direction. Each word line 140 extends along a second direction and is used to connect the gates of all memory cells 111 in the same second direction.

[0113] A voltage is applied to the gate of the memory cell 111 through word line 140 to control the on / off state of the source and drain of the memory cell 111.

[0114] In some embodiments, please continue to refer to the appendix. Figure 7 The memory 100 includes a first data line 150, a second data line 160, and a third data line 170. The first data line 150 is connected to the bit line structure 120, the second data line 160 is connected to the word line 140, and provides electrical signals to the word line 140 through the second data line 160. The third data line 170 is connected to the capacitor of the memory 100 so that the capacitor of the memory 100 is grounded.

[0115] There are multiple first data lines 150 and multiple second data lines 160. The number of first data lines 150 corresponds one-to-one with the number of bit lines 121, that is, one first data line 150 is connected to one bit line 121, and the connection position of each first data line 150 and each bit line 121 is located on the step surface formed by adjacent bit lines 121.

[0116] With attachment Figure 7 Taking the orientation shown as an example, the first data line 150 is connected to the upper surface of the first bit line 121, the second data line 150 is connected to the second bit line 121, and the connection position is at the step formed by the first bit line 121 and the second bit line 121, and so on, the third data line 150 is connected to the third bit line 121, and the connection position is at the step formed by the second bit line 121 and the third bit line 121, and the fourth data line 150 is connected to the fourth bit line 121, and the connection position is at the step formed by the third bit line 121 and the fourth bit line 121.

[0117] This facilitates the connection between each first data line 150 and each bit line 121, thereby facilitating the fabrication of each first data line 150.

[0118] The number of second data lines 160 is set to correspond one-to-one with the number of word lines 140, that is, one second data line 160 is connected to one word line 140 to achieve independent control of word line 140.

[0119] Please refer to the attached document. Figure 8 This disclosure also provides a method for fabricating a memory, used to fabricate the memory described in the above embodiments. Schematic diagrams of the memory cell array and bit line structure can be found in the appendix. Figure 6 and attached Figure 7 To facilitate a detailed description of each process step in the memory fabrication process and to simplify the accompanying drawings, the following descriptions will all use the figures provided. Figure 6 The cross-sectional views at different locations are illustrated. Specifically, the cross-section at AA is parallel to the extension direction of the bit line structure 120 and is located in the second region L2; the cross-section at BB is parallel to the extension direction of the bit line structure 120 and is located in the adjacent first sub-region L11; the cross-section at CC is parallel to the extension direction of the bit line structure 120 and is located on the capacitor 1112 in the second sub-region L12; the cross-section at DD is parallel to the extension direction of the bit line structure 120 and is located between adjacent capacitors 1112 in the second sub-region L12; and the cross-section at EE is perpendicular to the extension direction of the bit line structure 120 and is located on the active layer.

[0120] The preparation method mainly includes the following steps:

[0121] Step S100: Provide a substrate having a first region, a second region and a third region, wherein the first region and the third region are symmetrically arranged on both sides of the second region.

[0122] Please refer to the attached document. Figure 6 and attached Figure 9 The substrate 10 provides support for the membrane layer thereon. The substrate 10 includes a first region, a second region, and a third region; the first region and the third region are symmetrically arranged on both sides of the second region, that is, the first region, the second region, and the third region are connected sequentially.

[0123] To facilitate a clearer explanation of the first, second, and third regions, it is advisable to include the appendix. Figure 5 The L1 region is defined as the first region, and the attached region is... Figure 5 L2 is defined as the second region, and the attached Figure 5 L3 is defined as the third region.

[0124] In this embodiment, the substrate 10 can be a semiconductor substrate. For example, the substrate 10 can be a silicon substrate, germanium substrate, silicon carbide (SiC) substrate, silicon germanide (SiGe) substrate, germanium on insulator (GOI) substrate, or silicon on insulator (SOI) substrate, etc.

[0125] Step S200: Form a storage cell array in the first region and the third region respectively.

[0126] Step S300: A bit line structure is formed in the second region. The bit line structure is electrically connected to the transistors in the two memory cell arrays respectively. One end of the bit line structure protrudes from the memory cell array and is a stepped surface.

[0127] In this embodiment, two memory cell arrays share a single bit line structure. Compared with related technologies where a memory cell array and a bit line structure constitute a memory, this approach can reduce the size of the memory and improve the integration density of the semiconductor structure.

[0128] In some embodiments, to further refine the placement of transistors and capacitors in the memory cell array, the first region and the third region can be divided into interconnected first sub-regions and second sub-regions. The first sub-region is denoted as L11, and the second sub-region is denoted as L12. Their distribution is further detailed in the appendix. Figure 6 The steps of forming the memory cell array in the first region and the third region respectively include:

[0129] Please refer to the attached document. Figure 10Step S210: Multiple stacked structures spaced apart along a first direction are formed on the first and third regions, with a first trench formed between adjacent stacked structures; and a layered structure is formed in the second region; wherein each stacked structure includes multiple alternately stacked sacrificial layers and active layers, and the film layers of the layered structure are the same as those of the stacked structure, as shown in the attached figure. Figure 10 As shown.

[0130] For example, please refer to the appendix. Figure 9 An initial stacked structure 23 is formed on the substrate 10. The initial stacked structure 23 includes stacked and alternately arranged initial active layers 21 and first initial sacrificial layers 22. That is, multiple initial active layers 21 and multiple first initial sacrificial layers 22 are formed on the substrate 10. The multiple initial active layers 21 and multiple first initial sacrificial layers 22 are stacked sequentially and alternately arranged in a direction perpendicular to the substrate 10, and the first initial sacrificial layers 22 are disposed on the substrate 10. The number of initial active layers 21 and first initial sacrificial layers 22 can be set according to actual needs.

[0131] It should be noted that the appendix Figure 9 Structure and appendices of cross-sectional views at other locations Figure 9 The cross-sectional view along the AA direction has the same structure. To simplify the diagram and make it easier to view, cross-sectional views in other locations are not shown.

[0132] In some possible implementations, the initial active layer 21 and the first initial sacrificial layer 22 can be formed by a deposition process, which may include chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0133] In some other possible implementations, the first initial sacrificial layer 22 is formed by epitaxy (EPI), thus avoiding the problem of lattice mismatch between the first initial sacrificial layer 22 and the initial active layer 21. The material of the first initial sacrificial layer 22 includes silicon germanide, which gives the first initial sacrificial layer 22 and the initial active layer 21 a large etching selectivity ratio, so that subsequent processes can selectively remove the sacrificial layer and reduce the etching of the initial active layer.

[0134] In addition, the first initial sacrificial layer 22 also provides a certain support for the initial active layer 21, ensuring the normal progress of the semiconductor structure fabrication process.

[0135] Subsequently, a first mask layer 11 with a mask pattern is formed on the initial active layer 21, wherein the mask pattern is located on the first region and the third region.

[0136] Next, please refer to the appendix. Figure 11 Using the first mask layer 11 as a mask, a portion of the initial stacked structure 23 located in the first region and the third region is removed to form a plurality of first trenches 24 in the first region and the third region. The plurality of first trenches 24 divide the initial stacked structure located in the first region and the third region into multiple stacked structures 20; at the same time, the initial stacked structure 23 retained in the second region constitutes the stacked structure 30.

[0137] Each column of stacked structures 20 includes multiple alternately stacked sacrificial layers 25 and active layers 26. The film layers of the stacked structure 30 are the same as those of the stacked structure 20, and will not be described in detail here. The material of the sacrificial layer 25 includes, but is not limited to, silicon oxide.

[0138] In this embodiment, the first mask layer 11 can be a single film layer or a stacked structure. When the first mask layer 11 is a stacked structure, the accuracy of the mask pattern on the first mask layer 11 during the transfer process can be increased, thereby increasing the yield of the memory.

[0139] Step S220: Remove a portion of the sacrificial layer located in the first and third regions to form a second trench communicating with the first trench, the structure of which is shown in the attached figure. Figure 13 .

[0140] Please refer to the attached document. Figure 12 A second dielectric layer 40 is deposited within the first trench 24 and extends beyond the first trench 24, covering the multi-row stacked structure 20 and the stacked structure 30.

[0141] For example, a second dielectric layer 40 is formed within the first trench 24 using processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The thickness direction of the second dielectric layer 40 is the same as the depth direction of the first trench 24, both being perpendicular to the substrate 10.

[0142] In this embodiment, the material of the second dielectric layer 40 includes, but is not limited to, silicon oxide.

[0143] Next, please refer to the appendix. Figure 13A second mask layer (not shown in the figure) with a mask pattern can be formed on the second dielectric layer 40. Using the second mask layer as a mask, a portion of the sacrificial layer 25 and the second dielectric layer 40 are removed to expose a portion of the first trench 24 and the second trench 27 communicating with the first trench 24.

[0144] Step S230: Form a support structure in the exposed first and second trenches, the support structure being used to support any adjacent active layers.

[0145] Please refer to the attached document. Figure 14 An insulating material is deposited in the exposed first trench 24 and second trench 27 using a deposition process to form a support structure 50. The support structure 50 is used to support any adjacent active layer 26. That is, the support structure 50 can support adjacent active layers 26 on a horizontal plane or on a plane perpendicular to the substrate 10.

[0146] Step S240: Remove the remaining sacrificial layer and form a first dielectric layer in the region where the remaining sacrificial layer is located, the structure of which is shown in the attached figure. Figure 15 As shown.

[0147] A first dielectric layer 60 can be deposited in the area where the remaining sacrificial layer is located using a deposition process. The material of the first dielectric layer 60 includes, but is not limited to, silicon nitride.

[0148] Step S250: Remove a portion of the first dielectric layer and a portion of the second dielectric layer located in the first sub-region to form a filled region, which exposes a portion of the active layer, which is used to form the channel region of the transistor.

[0149] For example, please refer to the appendix. Figure 16 Etching gas or etching solution can be used to remove part of the first dielectric layer 60 and the second dielectric layer 40 in the first sub-region to form a filling region 70. The filling region 70 is used to expose the channel region of the active layer 26 so as to facilitate the subsequent formation of the gate oxide layer and word line around the channel region.

[0150] Step S260: A gate oxide layer and word lines are formed in the filled region, wherein the word lines and gate oxide layer surrounding the active layer constitute a transistor with the active layer.

[0151] Please refer to the attached document. Figure 17 A gate oxide layer 80 and word lines 140 are sequentially formed around the active layer 26 located within the filled region 70 using a deposition process. The gate oxide layer 80 has a high dielectric constant.

[0152] Step S270: A capacitor is formed in the second sub-region, and the capacitor is connected to the transistor.

[0153] Please refer to the attached document. Figure 18Using etching gas or etching solution, a portion of the second dielectric layer 40 and a portion of the first dielectric layer 60 located in the second sub-region are removed to expose a portion of the surface of the active layer located in the second sub-region.

[0154] Next, please refer to the appendix. Figure 19 A capacitor 1112 is formed on the active layer exposed in the second sub-region using a deposition process. The capacitor includes a first electrode layer 1112a, a dielectric layer 1112b, and a second electrode layer. The first electrode layer 1112a, the dielectric layer 1112b, and the second electrode layer 1112c are sequentially surrounded on the active layer 26 located in the second sub-region.

[0155] Next, please refer to the appendix. Figure 19 An interconnect layer 90 is formed, which fills the spaces between any adjacent capacitors and is connected to the second electrode layer 1112c of each capacitor 1112, so as to connect multiple capacitors 1112 in parallel. The interconnect layer 90 is made of polycrystalline silicon, but is not limited to this.

[0156] Please refer to the attached document. Figure 20 An insulating layer 91 is formed on the second region and the first sub-region. The top surface of the insulating layer 91 is flush with the top surface of the interconnecting layer 90. The insulating layer 91 serves as an isolation and protection layer.

[0157] In some embodiments, forming a bit line structure in the second region includes:

[0158] Please refer to the attached document. Figure 21 Part of the stacked structure is removed to form a groove within the stacked structure. The bottom of the groove is the top surface of the lowest active layer, and one sidewall of the groove is a stepped surface. The active layer retained on the second region constitutes a bit line structure.

[0159] For example, please continue to refer to Figure 20 and Figure 21 A first photoresist layer 180 with a first opening 181 is formed on the insulating layer 91 and the interconnect layer 90. The portion of the film layer exposed within the first opening is removed, and a first groove is formed in the second region. The bottom of the first groove is the top surface of the bottom active layer 26, which serves as the first bit line 121. The first opening 181 exposes only the film layer within the second region.

[0160] It should be noted that the appendix Figure 21 and attached Figure 20 Only the cross-sectional view in the AA direction is different; the annotations for the cross-sectional views in the other directions can be found in the appendix. Figure 20 .

[0161] Then, the first photoresist layer is removed, and a second photoresist layer (not shown in the figure) is re-formed for the second opening, with the sidewall of the second opening overlapping the sidewall of the first groove.

[0162] Subsequently, an etching solution or etching gas is used to remove a portion of the film layer exposed in the second opening, forming a second groove in the second region. The bottom of the second groove is the top surface of the active layer retained in the penultimate layer, thus forming a second bit line 121.

[0163] According to the above process steps, multiple position lines 121 are formed in the second region, and the multiple position lines 121 form a stepped surface from bottom to top.

[0164] Please refer to the attached document. Figure 22 A third dielectric layer 190 is formed, which fills the groove and covers the insulating layer 91 and the interconnect layer 90.

[0165] Please refer to the attached document. Figure 23 The third dielectric layer 190 is graphically represented to form a plurality of filling holes 191 within the third dielectric layer 190. The bottom of the filling hole 191 located in the first sub-region is the top surface of the word line 140, the bottom of the filling hole 191 located in the second sub-region is the top surface of the interconnect layer 90, and the bottom of the filling hole 191 located in the second region are the respective step surfaces.

[0166] Please refer to the attached document. Figure 24 Conductive material is deposited in the filled holes to form the first data line 150, the second data line 160 and the third data line (not shown in the figure).

[0167] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0168] In the description of this specification, references to terms such as “one embodiment,” “some embodiments,” “illustrative embodiment,” “example,” “specific example,” or “some examples” refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of this disclosure.

[0169] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0170] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A semiconductor structure, characterized by, It includes multiple rows of memory groups, each row of which includes multiple memories spaced apart along the row direction, and in any two adjacent rows of memory groups, the memories in one row of memory groups are staggered with the memories in the other row of memory groups. Each of the memories includes two memory cell arrays and a bit line structure, wherein the two memory cell arrays are located on opposite sides of the bit line structure in the row direction; The bit line structure extends along a first direction and is electrically connected to transistors in two memory cell arrays. One end of the bit line structure protrudes from the memory cell array and is a stepped surface. The protruding portion of the bit line structure is located between adjacent memories in the adjacent memory group. The first direction is perpendicular to the row direction and lies in the same horizontal plane.

2. The semiconductor structure of claim 1, wherein, Each row of the memory group includes a first sub-memory group and a second sub-memory group, which are spaced apart along the first direction and are symmetrically arranged with respect to the row direction.

3. The semiconductor structure according to claim 1 or 2, characterized in that, The storage cell array includes multiple storage cell layers, which are spaced apart along a second direction. In any two adjacent storage cell layers, the projection of one storage cell layer onto the other storage cell layer coincides with the projection of the other storage cell layer. The second direction, the first direction, and the row direction are perpendicular to each other. Each of the memory cell layers includes a plurality of memory cells spaced apart along the first direction, and each memory cell includes a transistor and a capacitor connected to the transistor.

4. The semiconductor structure according to claim 3, characterized in that, The capacitors are multiple, and the multiple capacitors are spaced apart along the row direction, and one electrode layer of the multiple capacitors is connected to each other.

5. The semiconductor structure according to claim 4, characterized in that, The bit line structure includes multiple bit lines spaced apart along the second direction. One bit line connects the transistors of all the memory cells in the memory cell layer located on the same layer. The connection end between the transistor and the bit line and the connection end between the transistor and the capacitor are not the same end. Along the first direction, each bit line has a first surface and a second surface disposed opposite to each other; one of the first surface and the second surface of all bit lines is aligned, and the other forms a step from top to bottom along the second direction.

6. The semiconductor structure according to claim 5, characterized in that, All of the bit lines except the topmost bit line include a first segment and a second segment connected in sequence, wherein the width of the second segment is smaller than the width of the first segment. At least a portion of the second segment is located between adjacent memories in the adjacent memory group.

7. The semiconductor structure according to claim 6, characterized in that, The memory also includes a word line structure, which includes multiple word lines spaced apart along a first direction, each word line extending along a second direction for connecting the gates of all the memory cells in the same second direction.

8. The semiconductor structure according to claim 7, characterized in that, It also includes a first data line, a second data line, and a third data line; The first data line is connected to the bit line structure; The second data line is connected to the word line, and the third data line is connected to the capacitor of the memory.

9. A method for fabricating a memory, characterized in that, The method for preparing a memory in the semiconductor structure according to any one of claims 1-8 comprises the following steps: A substrate is provided, the substrate having a first region, a second region and a third region, the first region and the third region being symmetrically disposed on both sides of the second region; Storage cell arrays are formed in the first region and the third region, respectively; A bit line structure is formed in the second region, and the bit line structure is electrically connected to the transistors in the two memory cell arrays respectively. One end of the bit line structure protrudes from the memory cell array and is a stepped surface.

10. The method for fabricating a memory according to claim 9, characterized in that, The first region includes a first sub-region and a second sub-region that are interconnected, the first sub-region being used to form a transistor and the second sub-region being used to form a capacitor; The steps of forming a memory cell array in the first region and the third region respectively include: Multiple stacked structures are formed in the first region and the third region at intervals along a first direction, and a first trench is formed between adjacent stacked structures; and a stacked structure is formed in the second region; wherein each stacked structure includes multiple sacrificial layers and active layers that are alternately stacked, and the film layers of the stacked structure are the same as the film layers of the stacked structure. Remove a portion of the sacrificial layer located in the first region and the third region to form a second trench communicating with the first trench; A support structure is formed in the first trench and the second trench, the support structure being used to support any adjacent active layers; Remove the remaining sacrificial layer and form a first dielectric layer in the region where the remaining sacrificial layer is located; A portion of the first dielectric layer and a portion of the second dielectric layer located in the first sub-region are removed to form a filling region, which exposes a portion of the active layer for forming the channel region of a transistor. A gate oxide layer and word lines are formed within the filled region, wherein the word lines and gate oxide layer surrounding the active layer constitute a transistor together with the active layer; A capacitor is formed in the second sub-region, and the capacitor is connected to a transistor.

11. The method for fabricating a memory according to claim 10, characterized in that, After the step of forming a multi-column stacked structure spaced apart along a first direction on the first region and the third region, and before the step of removing a portion of the sacrificial layer located in the first region and the third region, the method further includes: A second dielectric layer is formed within the first trench, the second dielectric layer extending outside the first trench and covering the top surface of the multiple stacked structures.

12. The method for fabricating a memory according to claim 10, characterized in that, The capacitor includes a first electrode layer, a dielectric layer, and a second electrode layer, wherein the first electrode layer, the dielectric layer, and the second electrode layer are sequentially surrounded on an active layer located in a second sub-region.

13. The method for fabricating a memory according to any one of claims 10-12, characterized in that, Following the step of forming a capacitor in the second sub-region and connecting the capacitor to a transistor... An interconnect layer is formed, which fills the space between any adjacent capacitors and is connected to the second electrode layer of each capacitor; An insulating layer is formed on the second region and the first sub-region, the top surface of the insulating layer being flush with the top surface of the interconnect layer.

14. The method for fabricating a memory according to claim 13, characterized in that, The step of forming a bit line structure in the second region includes: A portion of the stacked structure is removed to form a groove within the stacked structure. The bottom of the groove is the top surface of the lowest active layer, and one sidewall of the groove is a stepped surface. The active layer retained on the second region constitutes a bitline structure.

15. The method for fabricating a memory according to claim 14, characterized in that, After the step of forming a bit line structure in the second region, the method further includes: A third dielectric layer is formed, which fills the groove and covers the insulating layer and the interconnect layer; The third dielectric layer is graphically represented to form a plurality of filling holes within the third dielectric layer, wherein the bottom of the filling hole located in the first sub-region is the top surface of the word line, the bottom of the filling hole located in the second sub-region is the top surface of the interconnect layer, and the bottom of the filling hole located in the second region are each of the step surfaces; Conductive material is deposited within the filling holes to form a first data line, a second data line, and a third data line, respectively.

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