A semiconductor structure and its formation method

Abstract

This disclosure provides a semiconductor structure and a method for forming the same, wherein the semiconductor structure includes: a first semiconductor layer and a second semiconductor layer bonded together; the first semiconductor layer includes a first rewiring; the first rewiring has a first projected length on the bonding surface between the first semiconductor layer and the second semiconductor layer; the second semiconductor layer includes a second rewiring; the second rewiring has a second projected length on the bonding surface, and the first projected length and the second projected length are not equal; the first rewiring and the second rewiring are electrically connected.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and to, but is not limited to, a semiconductor structure and a method for forming the same. Background Technology

[0002] In current three-dimensional semiconductor structure technology, wafers are typically stacked together using contact holes. However, during the etching of contact holes, misalignment can easily occur, leading to misalignment of the electrical connection points between the two wafers and preventing effective electrical connection between them. In addition, when connecting two wafers through contact holes, the small distance between the contact holes results in a large parasitic capacitance, which can easily cause delay in the resistor-capacitance circuit (RC). Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same.

[0004] In a first aspect, embodiments of this disclosure provide a semiconductor structure, including: a first semiconductor layer and a second semiconductor layer bonded together;

[0005] The first semiconductor layer includes a first overlay; wherein the first overlay has a first projected length on the bonding surface between the first semiconductor layer and the second semiconductor layer;

[0006] The second semiconductor layer includes a second overlay; wherein the second overlay has a second projected length on the bonding surface, and the first projected length is not equal to the second projected length;

[0007] The first layer of wiring is electrically connected to the second layer of wiring.

[0008] In some embodiments, the first semiconductor layer includes a plurality of first overwires, and the second semiconductor layer includes a plurality of second overwires; the projected lengths of any two adjacent first overwires on the bonding surface are not equal; or, the projected lengths of any two adjacent second overwires on the bonding surface are not equal.

[0009] In some embodiments, the plurality of first wirings are electrically connected to the plurality of second wirings in a one-to-one correspondence, and the projected length of each first wiring on the bonding surface is equal to the sum of the projected lengths of the corresponding second wiring on the bonding surface.

[0010] In some embodiments, a plurality of the first wirings are arranged cyclically according to a preset arrangement;

[0011] The preset arrangement includes: the first projection length increasing sequentially, the first projection length decreasing sequentially, the first projection length increasing first and then decreasing, and the first projection length decreasing first and then increasing.

[0012] In some embodiments, as the first projection length of the plurality of first overwires on the bonding surface decreases sequentially, the second projection length of the second overwire corresponding to each of the first overwires on the bonding surface increases sequentially.

[0013] In some embodiments, as the first projection length of the plurality of first overwires on the bonding surface increases sequentially, the second projection length of the second overwire corresponding to each of the first overwires on the bonding surface decreases sequentially.

[0014] In some embodiments, when the first projection length of the plurality of first overwires on the bonding surface first increases and then decreases, the second projection length of the second overwire corresponding to each of the first overwires on the bonding surface first decreases and then increases.

[0015] In some embodiments, when the first projection length of the plurality of first overwires on the bonding surface first decreases and then increases, the second projection length of the second overwire corresponding to each of the first overwires on the bonding surface first increases and then decreases.

[0016] In some embodiments, the first semiconductor layer further includes a first metal pad connected to the first rewiring; the second semiconductor layer further includes a second metal pad connected to the second rewiring.

[0017] The first layer of wiring and the corresponding second layer of wiring are electrically connected through the first metal pad and the second metal pad.

[0018] In some embodiments, the first metal pad is bonded to the corresponding second metal pad to form a bonding pad; the plurality of bonding pads are arranged in a stepped manner in the bonding surface.

[0019] In some embodiments, the first semiconductor layer includes a memory array; the memory array includes a plurality of word lines and a plurality of bit lines;

[0020] Each word line is electrically connected to a corresponding first overlay, and each bit line is electrically connected to a corresponding first overlay.

[0021] In some embodiments, the second semiconductor layer includes peripheral circuitry; the second redistribution is electrically connected to the peripheral circuitry.

[0022] In some embodiments, each word line is electrically connected to the peripheral circuit via a first overlay and a corresponding second overlay, and each bit line is electrically connected to the peripheral circuit via a first overlay and a corresponding second overlay.

[0023] In some embodiments, the first semiconductor layer includes a first dielectric layer, and the first redistribution is located in the first dielectric layer; the second semiconductor layer includes a second dielectric layer, and the second redistribution is located in the second dielectric layer; the semiconductor structure further includes a barrier layer;

[0024] The barrier layer is located between the first rewiring and the first dielectric layer, between the second rewiring and the second dielectric layer, between the bonding pad and the first dielectric layer, and between the bonding pad and the second dielectric layer.

[0025] In a second aspect, embodiments of this disclosure provide a method for forming a semiconductor structure, including:

[0026] Provide a first semiconductor layer and a second semiconductor layer;

[0027] A first overlay is formed in the first semiconductor layer; wherein the first overlay has a first projected length on the bonding surface between the first semiconductor layer and the second semiconductor layer;

[0028] A second overlay is formed in the second semiconductor layer; wherein the second overlay has a second projected length on the bonding surface, and the first projected length is not equal to the second projected length;

[0029] The first semiconductor layer and the second semiconductor layer are bonded to electrically connect the first overwire and the second overwire.

[0030] In some embodiments, the first rewiring is formed by the following steps:

[0031] A first dielectric layer is formed on the substrate surface of the first semiconductor layer;

[0032] The first dielectric layer is etched to form the first etched groove;

[0033] The first etched groove is filled with metal material to form the first rewiring.

[0034] In some embodiments, the second rewiring is formed by the following steps:

[0035] A second dielectric layer is formed on the substrate surface of the second semiconductor layer;

[0036] The second dielectric layer is etched to form a second etched groove;

[0037] The second etched groove is filled with metal material to form the second rewiring.

[0038] In some embodiments, the method further includes: forming a first metal pad electrically connected to the first rewiring, and forming a second metal pad electrically connected to the second rewiring.

[0039] In some embodiments, bonding the first semiconductor layer and the second semiconductor layer to electrically connect the first redistribution and the second redistribution includes:

[0040] The first surface of the first semiconductor layer exposing the first metal pad and the second surface of the second semiconductor layer exposing the second metal pad are subjected to surface activation treatment;

[0041] The first surface and the second surface are adhered together, and each of the first metal pads is aligned face to face with one of the second metal pads;

[0042] The first semiconductor layer and the second semiconductor layer are annealed.

[0043] The semiconductor structure and its formation method provided in this disclosure include: a first semiconductor layer and a second semiconductor layer bonded together; the first semiconductor layer includes a first redistribution; the first redistribution has a first projected length on the bonding surface between the first and second semiconductor layers; the second semiconductor layer includes a second redistribution; the second redistribution has a second projected length on the bonding surface, and the first projected length and the second projected length are not equal; the first redistribution and the second redistribution are electrically connected. In this disclosure, the semiconductor layers are electrically connected by bonding. Because the metal pads used for bonding have a large area, the problem of non-connection caused by small and misaligned electrical connection points between the two semiconductor layers can be avoided, thus improving the semiconductor fabrication yield. In addition, by setting different projected lengths of the redistribution in the two semiconductor layers, the spacing between the metal pads is increased, thereby reducing parasitic capacitance and improving the performance of the semiconductor structure. Attached Figure Description

[0044] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0045] Figure 1a This is a schematic diagram of the semiconductor structure provided in the embodiments of this disclosure;

[0046] Figure 1b A schematic projection of multiple bonding pads on the bonding surfaces of the first and second semiconductor layers provided in an embodiment of this disclosure;

[0047] Figures 2a to 2d A schematic projection of the first and second overlays on the bonding surface of the first and second semiconductor layers, as provided in an embodiment of this disclosure.

[0048] Figure 3 This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure;

[0049] Figure 4 A schematic flowchart illustrating a method for forming a semiconductor structure according to an embodiment of this disclosure;

[0050] Figures 5a-5l A schematic diagram illustrating the formation process of a semiconductor structure provided in this embodiment of the disclosure;

[0051] The annotations in the attached figures are explained as follows:

[0052] 10—Bonding surface; 11—First semiconductor layer; 111 / 111a / 111b / 111c / 111d / 111e—First redistribution; 12—Second semiconductor layer; 121 / 121a / 121b / 121c / 121d / 121e—Second redistribution; 1111—First wiring; 1112—Second wiring; 1113—Third wiring; 1211—Fourth wiring; 1212—Fifth wiring; 1213—Sixth wiring; 112—First dielectric layer; 122—Second dielectric layer; 1121—First initial dielectric layer; 1122—Second initial dielectric layer; 1123—Third initial dielectric layer; 1124—Fourth initial dielectric layer; 1221—Fifth initial dielectric layer; 1222—Sixth initial dielectric layer Dielectric layer; 1223—Seventh initial dielectric layer; 1224—Eighth initial dielectric layer; 13 / 13a / 13b / 13c / 13d / 13e / 13f / 13g / 13h / 13i / 13j—Bonding pads; 131—First metal pad; 132—Second metal pad; 14—Memory array; 141—Word line; 142—Capacitor; 143—Support structure; 15—Peripheral circuit; 151—Active region; 16—Barrier layer; 161—First barrier layer; 162—Second barrier layer; 163—Third barrier layer; 164—Fourth barrier layer; 165—Fifth barrier layer; 166—Sixth barrier layer; 167—Seventh barrier layer; 168—Eighth barrier layer; 17—Substrate; 100 / 200—Semiconductor structure. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the specific technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings of the embodiments of this disclosure. The following embodiments are used to illustrate this disclosure, but are not intended to limit the scope of this disclosure.

[0054] Based on the problems existing in related technologies, this disclosure provides a semiconductor structure and a method for forming the same. The semiconductor structure and method for forming the same provided in this disclosure will be further described in detail below with reference to the accompanying drawings.

[0055] Figure 1a This is a schematic diagram of the semiconductor structure provided in the embodiments of this disclosure, such as... Figure 1a As shown, the semiconductor structure 100 includes: a first semiconductor layer 11 and a second semiconductor layer 12 bonded together; the first semiconductor layer 11 includes a first redistribution 111; the first redistribution 111 has a first projected length d1 on the bonding surface 10 between the first semiconductor layer 11 and the second semiconductor layer 12; the second semiconductor layer 12 includes a second redistribution 121; the second redistribution 121 has a second projected length d2 on the bonding surface 10, and the first projected length d1 and the second projected length d2 are not equal; the first redistribution 111 and the second redistribution 121 are electrically connected.

[0056] In this embodiment of the disclosure, the first semiconductor layer 11 and the second semiconductor layer 12 can be a wafer or a chip obtained after wafer dicing. The bonding method of the first semiconductor layer 11 and the second semiconductor layer 12 can include direct bonding, thermo-press bonding, plasma-activated bonding, or bonding agent bonding, etc.

[0057] In this embodiment of the present disclosure, the first semiconductor layer 11 further includes a first dielectric layer 112, and the first redistribution 111 is located in the first dielectric layer 112; the second semiconductor layer 12 further includes a second dielectric layer 122, and the second redistribution 121 is located in the second dielectric layer 122. The first redistribution 111 and the second redistribution 121 can be composed of any conductive metal material, such as copper, aluminum, copper-aluminum alloy, or tungsten; the materials of the first dielectric layer 112 and the second dielectric layer 122 can be oxides, such as silicon oxide.

[0058] Please continue to refer to this. Figure 1a The first semiconductor layer 11 further includes a first metal pad 131 connected to the first rewiring 111; the second semiconductor layer 12 further includes a second metal pad 132 connected to the second rewiring 121; the first rewiring 111 and the corresponding second rewiring 121 are electrically connected through the first metal pad 131 and the second metal pad 132.

[0059] In this embodiment of the present disclosure, the first metal pad 131 is bonded to the corresponding second metal pad 132 to form a bonding pad 13; the multiple bonding pads 13 are arranged in a stepped manner on the bonding surface 10 of the first semiconductor layer 11 and the second semiconductor layer 12.

[0060] Figure 1b This is a schematic projection of multiple bonding pads on the bonding surfaces of the first and second semiconductor layers provided in an embodiment of this disclosure, as shown in the figure. Figure 1b As shown in the embodiments of this disclosure, bonding pads 13a, 13b, 13c, 13d, and 13e are distributed in a stepped manner on the bonding surfaces of the first semiconductor layer 11 and the second semiconductor layer 12; bonding pads 13f, 13g, 13h, 13i, and 13j are also distributed in a stepped manner on the bonding surfaces of the first semiconductor layer 11 and the second semiconductor layer 12.

[0061] In this embodiment of the present disclosure, the bonding pads are distributed in a stepped manner on the bonding surfaces of the first semiconductor layer 11 and the second semiconductor layer 12, including at least one of the following: the distances of the bonding pads 13a, 13b, 13c, 13d, and 13e to the memory array increase sequentially, decrease sequentially, increase first and then decrease, and decrease first and then increase.

[0062] In this embodiment, the semiconductor layers are electrically connected by bonding. Since the metal pads used for bonding have a large area, the problem of electrical connection failure caused by small and misaligned electrical connection points between the two semiconductor layers can be avoided, thus improving the semiconductor fabrication yield. In addition, in this embodiment, the spacing between the bonding pads is increased by setting different projection lengths of the redistribution lines in the two semiconductor layers, thereby reducing parasitic capacitance and improving the performance of the semiconductor structure.

[0063] In some embodiments, a plurality of first wiring 111 are electrically connected to a plurality of second wiring 121 in a one-to-one correspondence, and the projected length of each first wiring 111 on the bonding surface 10 is equal to the sum of the projected lengths of the corresponding second wiring 121 on the bonding surface 10.

[0064] In this embodiment of the present disclosure, a plurality of first rewiring 111 are arranged cyclically according to a preset arrangement; wherein, the preset arrangement includes at least one of the following: the first projection length increases sequentially, the first projection length decreases sequentially, the first projection length increases first and then decreases, and the first projection length decreases first and then increases.

[0065] Figures 2a to 2d This is a schematic projection of the first and second overlays provided in the embodiments of this disclosure on the bonding surface of the first and second semiconductor layers. The following is a combined view... Figures 2a to 2d The arrangement of the first and second wiring on the bonding surface in the embodiments of this disclosure will be described in detail.

[0066] In some embodiments, when the first projected length of the plurality of first overwires 111 on the bonding surface 10 first decreases and then increases, the second projected length of the second overwire 121 corresponding to each first overwire 111 on the bonding surface 10 first increases and then decreases. For example... Figure 2a As shown, the first rewiring 111a, 111b, 111c, 111d and 111e are electrically connected to the second rewiring 121a, 121b, 121c, 121d and 121e respectively. When the first projection length of the first rewiring 111a, 111c and 111d on the bonding surface 10 first decreases (i.e. d1a>d1c) and then increases (i.e. d1c<d1d), the second projection length of the second rewiring 121a, 121c and 121d corresponding to the first rewiring on the bonding surface 10 first increases (i.e. d2a<d2c) and then decreases (i.e. d2c>d2d). In this embodiment of the disclosure, the sum of the projected lengths (d1a+d2a) of the first super-wire 111a and the second super-wire 121a on the bonding surface 10 is equal to the sum of the projected lengths (d1c+d2c) of the first super-wire 111c and the second super-wire 121c on the bonding surface 10.

[0067] In some embodiments, as the first projected lengths of the plurality of first overwires 111 on the bonding surface 10 decrease sequentially, the second projected lengths of the second overwires 121 corresponding to each first overwire 111 on the bonding surface 10 increase sequentially. For example... Figure 2b As shown, the first multiplexing wires 111a, 111b, 111c, 111d, and 111e are electrically connected to the second multiplexing wires 121a, 121b, 121c, 121d, and 121e in a one-to-one correspondence. When the first projection lengths of the first multiplexing wires 111a, 111c, and 111e on the bonding surface 10 decrease sequentially (i.e., d1a > d1c > d1e), the second projection lengths of the second multiplexing wires 121a, 121c, and 121e corresponding to each first multiplexing wire on the bonding surface 10 increase sequentially (i.e., d2a < d2c < d2e). In this embodiment, the sum of the projection lengths of the first multiplexing wire 111a and the second multiplexing wire 121a on the bonding surface 10 (d1a + d2a) is equal to the sum of the projection lengths of the first multiplexing wire 111e and the second multiplexing wire 121e on the bonding surface 10 (d1e + d2e).

[0068] In some embodiments, as the first projected lengths of the plurality of first overwires 111 on the bonding surface 10 increase sequentially, the second projected lengths of the second overwires 121 corresponding to each first overwire 111 on the bonding surface 10 decrease sequentially. For example... Figure 2cAs shown, the first wirings 111a, 111b, 111c, 111d and 111e are electrically connected to the second wirings 121a, 121b, 121c, 121d and 121e in a one-to-one correspondence. When the first projection length of the first wirings 111a, 111c and 111e on the bonding surface 10 increases sequentially (i.e. d1a < d1c < d1e), the second projection length of the second wirings 121a, 121c and 121e corresponding to each first wiring on the bonding surface 10 decreases sequentially (i.e. d2a > d2c > d2e).

[0069] In some embodiments, when the first projected lengths of the plurality of first overwires 111 on the bonding surface 10 first increase and then decrease, the second projected lengths of the second overwires 121 corresponding to each first overwire 111 on the bonding surface 10 first decrease and then increase. For example... Figure 2d As shown, the first wirings 111a, 111b, 111c, 111d and 111e are electrically connected to the second wirings 121a, 121b, 121c, 121d and 121e in a one-to-one correspondence. When the first projection length of the first wirings 111a, 111c and 111d on the bonding surface 10 first increases (i.e. d1a < d1c) and then decreases (i.e. d1c > d1d), the second projection length of the second wirings 121a, 121c and 121d corresponding to each first wiring 111 on the bonding surface 10 first decreases (i.e. d2a > d2c) and then increases (i.e. d2c < d2d).

[0070] In some embodiments, please refer to Figures 2a to 2d The first semiconductor layer 11 includes a plurality of first redundancy lines 111, wherein the projected lengths of any two adjacent first redundancy lines 111 on the bonding surface 10 are not equal. For example, the first semiconductor layer 11 includes first redundancy lines 111a, 111b, 111c, 111d, and 111e; the projected lengths of first redundancy lines 111a and 111b on the bonding surface 10 are not equal, or the projected lengths of first redundancy lines 111c and 111d on the bonding surface 10 are not equal. In this embodiment of the present disclosure, when the projected lengths of any two adjacent first redundancy lines 111 on the bonding surface 10 are not equal, the projected lengths of the second redundancy lines 121 corresponding to any two adjacent first redundancy lines 111 on the bonding surface 10 may be equal or unequal. For example, the projection lengths of the first wiring 111a and the first wiring 111b on the bonding surface 10 are not equal, while the projection lengths of the second wiring 121a and the second wiring 121b on the bonding surface 10 are equal (not shown).

[0071] In some embodiments, please refer to Figures 2a to 2dThe second semiconductor layer 12 includes a plurality of second overwires 121, wherein the projected lengths of any two adjacent second overwires 121 on the bonding surface 10 are not equal. For example, the second semiconductor layer 12 includes second overwires 121a, 121b, 121c, 121d, and 121e; the projected lengths of second overwires 121a and 121b on the bonding surface 10 are not equal, or the projected lengths of second overwires 121c and 121d on the bonding surface 10 are not equal. In this embodiment of the present disclosure, when the projected lengths of any two adjacent second overwires 121 on the bonding surface 10 are not equal, the projected lengths of the first overwire 111 corresponding to any two adjacent second overwires 121 on the bonding surface 10 may be equal or unequal. For example, the projection lengths of the second wiring 121a and the second wiring 121b on the bonding surface 10 are not equal, while the projection lengths of the first wiring 111a and the first wiring 111b on the bonding surface 10 are equal (not shown).

[0072] Figure 3 This is a schematic diagram of another semiconductor structure provided in an embodiment of this disclosure. (See attached diagram.) Figure 3 As shown, the semiconductor structure 200 provided in this embodiment includes: a first semiconductor layer 11 and a second semiconductor layer 12 bonded together; the first semiconductor layer 11 includes a first redistribution 111; the first redistribution 111 has a first projected length d1 on the bonding surface 10 of the first semiconductor layer 11 and the second semiconductor layer 12; the second semiconductor layer 12 includes a second redistribution 121; the second redistribution 121 has a second projected length d2 on the bonding surface 10, and the first projected length d1 and the second projected length d2 are not equal; the first redistribution 111 and the second redistribution 121 are electrically connected.

[0073] In this embodiment of the present disclosure, the first semiconductor layer 11 includes a first dielectric layer 112, and the first redistribution 111 is located in the first dielectric layer 112; the second semiconductor layer 12 includes a second dielectric layer 122, and the second redistribution 121 is located in the second dielectric layer 122.

[0074] Please continue to refer to this. Figure 3 The first semiconductor layer 11 further includes a first metal pad 131 connected to the first rewiring 111; the second semiconductor layer 12 further includes a second metal pad 132 connected to the second rewiring 121; the first rewiring 111 and the corresponding second rewiring 121 are electrically connected through the first metal pad 131 and the second metal pad 132.

[0075] Please continue to refer to this. Figure 3 The first semiconductor layer 11 also includes a memory array 14; the memory array 14 includes multiple word lines (i.e., a full-ring gate structure) 141 and multiple bit lines ( Figure 3(not shown in the image); wherein each word line 141 is electrically connected to a corresponding first overlay 111, and each bit line is electrically connected to a corresponding first overlay 111.

[0076] In some embodiments, the memory array 14 included in the first semiconductor layer 11 is a three-dimensional semiconductor structure. For example, the memory array 14 may include a plurality of stepped word lines extending in a direction parallel to the substrate surface and perpendicular to the substrate surface, for example, the word lines having a progressively decreasing length from bottom to top in the direction perpendicular to the substrate surface, and the memory array 14 may also include bit lines extending in the direction perpendicular to the substrate surface. Alternatively, the memory array 14 may include a plurality of stepped bit lines extending in a direction parallel to the substrate surface and perpendicular to the substrate surface, for example, the bit lines having a progressively decreasing length from bottom to top in the direction perpendicular to the substrate surface, and the memory array 14 may also include word lines extending in the direction perpendicular to the substrate surface. Figure 1b As shown, for example, bonding pads 13a, 13b, 13c, 13d, and 13e are used to connect bit lines of the memory array in the first semiconductor layer that extend in a direction perpendicular to the substrate surface, and bonding pads 13f, 13g, 13h, 13i, and 13j are used to connect word lines of the memory array in the first semiconductor layer that extend in a direction parallel to the substrate surface.

[0077] In some embodiments, the memory array 14 further includes a plurality of transistors, a plurality of capacitors 142, and a support structure 143 for supporting the plurality of transistors and the plurality of capacitors 142.

[0078] In this embodiment of the disclosure, the bit line may be made of conductive material, such as one or a combination of polysilicon, metal silicide, conductive metal nitride (e.g., titanium nitride, tantalum nitride, tungsten nitride, etc.) and metal (e.g., tungsten, titanium, tantalum, etc.).

[0079] In some embodiments, the second semiconductor layer 12 includes peripheral circuitry 15; the second redistribution wiring 121 is electrically connected to the peripheral circuitry 15.

[0080] In some embodiments, the peripheral circuitry 15 may include a sensing amplifier located in an active region 151 within the peripheral circuitry. The sensing amplifier senses the voltage difference between a bit line and a complementary bit line, and amplifies this voltage difference to a recognizable logic level, enabling the logic unit outside the memory device to correctly interpret the data. This, in turn, controls the memory unit to store data in the corresponding capacitor and / or read data from the corresponding capacitor. Please continue to refer to... Figure 3 The second wiring 121 is connected to the active area 151.

[0081] In other embodiments, the peripheral circuitry 15 may also include a row decoder, a column decoder, an input / output controller, or a multiplexer.

[0082] In some embodiments, please refer to Figure 3 Each word line 141 is electrically connected to the peripheral circuit 15 through a first overlay 111 and a corresponding second overlay 121, and each bit line ( Figure 3 (Not shown) is electrically connected to the external circuit 15 via a first overlay 111 and a corresponding second overlay 121.

[0083] It should be noted that in this embodiment, the character lines have a stepped structure.

[0084] In some embodiments, please refer to Figure 3 The semiconductor structure 200 further includes a barrier layer 16; the barrier layer 16 is located between the first redistribution 111 and the first dielectric layer 112, between the second redistribution 121 and the second dielectric layer 122, between the bonding pad 13 and the first dielectric layer 112, and between the bonding pad 13 and the second dielectric layer 122.

[0085] In this embodiment of the disclosure, the material of the barrier layer 16 may be titanium nitride, tantalum nitride, cobalt nitride, nickel nitride, or tungsten nitride. In this embodiment of the disclosure, the material of the barrier layer 16 is titanium nitride. Titanium nitride has good barrier properties and adhesion properties, and can effectively block the diffusion of the first and second wiring materials.

[0086] In this embodiment of the disclosure, the semiconductor layers are electrically connected by bonding. Since the metal pads used for bonding have a large area, the problem of electrical connection failure caused by small and misaligned electrical connection points between two semiconductor layers can be avoided, thereby improving the semiconductor fabrication yield.

[0087] This disclosure also provides a method for forming a semiconductor structure. Figure 4 This is a schematic flowchart of a method for forming a semiconductor structure according to an embodiment of the present disclosure, as shown below. Figure 4 As shown, the method for forming a semiconductor structure includes:

[0088] Step S401: Provide a first semiconductor layer and a second semiconductor layer.

[0089] Step S402: Form a first overlay in the first semiconductor layer; wherein the first overlay has a first projected length on the bonding surface between the first semiconductor layer and the second semiconductor layer.

[0090] Step S403: Form a second wiring in the second semiconductor layer; wherein the second wiring has a second projected length on the bonding surface, and the first projected length is not equal to the second projected length.

[0091] Step S404: Bond the first semiconductor layer and the second semiconductor layer to electrically connect the first overlay and the second overlay.

[0092] Figures 5a-5l This is a schematic diagram of the semiconductor structure formation process provided in the embodiments of this disclosure. Please refer to the following. Figures 5a-5l The schematic diagram of the semiconductor structure formation process provided in the embodiments of this disclosure is described in further detail.

[0093] First, you can refer to Figure 5a and 5b Step S401 is executed, providing a first semiconductor layer 11 and a second semiconductor layer 12. The first semiconductor layer 11 includes a substrate 17 and a memory array 14 located on the surface of the substrate 17, and the second semiconductor layer 12 includes the substrate 17 and a peripheral circuit 15 located on the surface of the substrate 17.

[0094] In this embodiment of the disclosure, the substrate 17 may be a silicon substrate, a silicon-on-insulator substrate, or the like. The substrate may also include other semiconductor elements or semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or other semiconductor alloys, such as gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP) or combinations thereof.

[0095] Next, you can refer to 5c to Figure 5e Step S402 is executed to form a first redistribution 111 in the first semiconductor layer 11; wherein the first redistribution 111 has a first projection length d1 on the bonding surface 10 between the first semiconductor layer 11 and the second semiconductor layer 12.

[0096] In some embodiments, the first redistribution 111 can be formed by the following steps: forming a first dielectric layer 112 on the surface of the substrate 17 of the first semiconductor layer 11; etching the first dielectric layer 112 to form a first etched groove; filling the first etched groove with a metal material to form the first redistribution 111.

[0097] First, refer to Figure 5c A first initial dielectric layer 1121 is formed on the surface of the substrate 17 of the first semiconductor layer 11, and the first initial dielectric layer 1121 is etched to form a first groove. Figure 5c(Not shown in the image), a first recess exposes word lines or bit lines in the memory array 14. The inner wall of the first recess is filled with a barrier material to form a first barrier layer 161. The surface of the first barrier layer 161 is filled with a metallic material to form a first wiring 1111. The first wiring 1111 fills the first recess; next, refer to... Figure 5d A second initial dielectric layer 1122 is formed on the surface of the first initial dielectric layer 1121, and the second initial dielectric layer 1122 is etched to form a second groove. Figure 5d (Not shown in the image), the second groove exposes the first wiring 1111, the inner wall of the second groove is filled with a blocking material to form a second blocking layer 162, the surface of the second blocking layer 162 is filled with a metallic material to form a second wiring 1112, and the second wiring 1112 fills the second groove; finally, refer to Figure 5e A third initial dielectric layer 1123 is formed on the surface of the second initial dielectric layer 1122, and the third initial dielectric layer 1123 is etched to form a third groove. Figure 5e (Not shown in the image), the third groove exposes the second wiring 1112. The inner wall of the third groove is filled with a blocking material to form a third blocking layer 163. The surface of the third blocking layer 163 is filled with a metal material to form a third wiring 1113. The third wiring 1113 fills the third groove. The first initial dielectric layer 1121, the second initial dielectric layer 1122, and the third initial dielectric layer 1123 constitute the first dielectric layer 112; the first wiring 1111, the second wiring 1112, and the third wiring 1113 constitute the first rewiring 111.

[0098] In some embodiments, reference may be made to Figure 5f The method for forming a semiconductor structure further includes forming a first metal pad 131 electrically connected to the first redistribution 111.

[0099] like Figure 5f As shown, a fourth initial dielectric layer 1124 is formed on the surface of the third initial dielectric layer 1123, and the fourth initial dielectric layer 1124 is etched to form a first metal pad groove. Figure 5f (Not shown in the image), the first metal pad groove exposes the third wiring 1113, and the opening size of the first metal pad groove is larger than the opening size of the third groove. The inner wall of the first metal pad groove is filled with a blocking material to form a fourth blocking layer 164. The surface of the fourth blocking layer 164 is filled with metal material to form a first metal pad 131, wherein the top surface of the first metal pad 131 is flush with the top surface of the fourth initial dielectric layer 1124.

[0100] In this embodiment of the disclosure, the blocking material can be titanium, tungsten, tantalum, or platinum metal alloy, such as tantalum nitride; the metal material can be copper, aluminum, copper-aluminum alloy, or tungsten.

[0101] Next, you can refer to 5G to Figure 5iStep S403 is executed to form a second redistribution 121 in the second semiconductor layer 12; wherein the second redistribution 121 has a second projection length d2 on the bonding surface, and the first projection length d1 and the second projection length d2 are not equal.

[0102] In some embodiments, the second rewiring 121 is formed by the following steps: forming a second dielectric layer 122 on the surface of the substrate 17 of the second semiconductor layer; etching the second dielectric layer 122 to form a second etched groove; filling the second etched groove with a metal material to form the second rewiring 121.

[0103] First, refer to Figure 5g A fifth initial dielectric layer 1221 is formed on the surface of the substrate 17 of the second semiconductor layer 12, and the fifth initial dielectric layer 1221 is etched to form a fourth groove. Figure 5g (Not shown in the image), the fourth groove exposes the active area in the peripheral circuit 15. A blocking material is filled into the inner wall of the fourth groove to form a fifth blocking layer 165. Metal material is filled into the surface of the fifth blocking layer 165 to form a fourth wiring 1211, which fills the fourth groove. Next, refer to... Figure 5h A sixth initial dielectric layer 1222 is formed on the surface of the fifth initial dielectric layer 1221, and the sixth initial dielectric layer 1222 is etched to form a fifth groove. Figure 5h (Not shown in the image), the fifth groove exposes the fourth wiring 1211. A blocking material is filled into the inner wall of the fifth groove to form a sixth blocking layer 166. Metal material is filled into the surface of the sixth blocking layer 166 to form the fifth wiring 1212. The fifth wiring 1212 fills the fifth groove. Finally, refer to... Figure 5i A seventh initial dielectric layer 1223 is formed on the surface of the sixth initial dielectric layer 1222, and the surface of the seventh initial dielectric layer 1223 is etched to form a sixth groove. Figure 5i (Not shown in the image), the sixth groove exposes the fifth wiring 1212. A blocking material is filled into the inner wall of the sixth groove to form a seventh blocking layer 167. Metal material is filled into the surface of the sixth wiring 1213 to form the sixth wiring 1213, which fills the sixth groove. The fifth initial dielectric layer 1221, the sixth initial dielectric layer 1222, and the seventh initial dielectric layer 1223 constitute the second dielectric layer 122; the fourth wiring 1211, the fifth wiring 1212, and the sixth wiring 1213 constitute the second rewiring 121.

[0104] In this embodiment of the disclosure, the blocking material may be titanium, tungsten, tantalum, or platinum metal alloy, such as tantalum nitride; the metal material may be copper, aluminum, copper-aluminum alloy, or tungsten.

[0105] In some embodiments, reference Figure 5jThe method for forming a semiconductor structure further includes forming a second metal pad 132 that is electrically connected to the second redistribution 121.

[0106] like Figure 5j As shown, an eighth initial dielectric layer 1224 is formed on the surface of the seventh initial dielectric layer 1223, and the eighth initial dielectric layer 1224 is etched to form a second metal pad groove. Figure 5j (Not shown in the image), the second metal pad groove exposes the sixth wiring 1213, and the opening size of the second metal pad groove is larger than the opening size of the sixth groove. The inner wall of the second metal pad groove is filled with a barrier material to form an eighth barrier layer 168. The surface of the eighth barrier layer 168 is filled with a metal material to form a second metal pad 132, wherein the top surface of the second metal pad 132 is flush with the top surface of the eighth initial dielectric layer 1224.

[0107] Please continue to refer to this. Figures 5c to 5j In this embodiment of the present disclosure, the first barrier layer 161, the second barrier layer 162, the third barrier layer 163, the fourth barrier layer 164, the fifth barrier layer 165, the sixth barrier layer 166, the seventh barrier layer 167, and the eighth barrier layer 168 constitute the barrier layer 16.

[0108] In this embodiment, the first metal pad 131 and the second metal pad 132 can be made of any conductive metal material, such as copper, aluminum, copper-aluminum alloy, or tungsten. The first metal pad 131 and the second metal pad 132 are used to electrically connect the first rewiring 111 and the second rewiring 121. In some embodiments, to reduce the possibility of short circuits between adjacent metal pads, an insulating material can be filled between adjacent metal pads.

[0109] Next, you can refer to Figure 5k and Figure 5l Step S404 is executed to bond the first semiconductor layer 11 and the second semiconductor layer 12 to electrically connect the first rewiring 111 and the second rewiring 121.

[0110] In some embodiments, bonding the first semiconductor layer 11 and the second semiconductor layer 12 to electrically connect the first redistribution 111 and the second redistribution 121 includes:

[0111] The first surface of the first semiconductor layer 11 exposing the first metal pad 131 and the second surface of the second semiconductor layer 12 exposing the second metal pad 132 are subjected to surface activation treatment.

[0112] In this embodiment of the disclosure, the purpose of the activation process is to clean the surfaces of the first semiconductor layer 11 and the second semiconductor layer 12, and remove metal oxides, chemical substances, particles, or other impurities from the surfaces of the first semiconductor layer 11 and the second semiconductor layer 12.

[0113] In this embodiment of the present disclosure, the first surface and the second surface are bonded together, and each first metal pad 131 is aligned face to face with a second metal pad 132; the first semiconductor layer 11 and the second semiconductor layer 12 are annealed.

[0114] In this embodiment of the disclosure, defects in the first semiconductor layer and the second semiconductor layer are reduced by annealing the first semiconductor layer and the second semiconductor layer.

[0115] In this embodiment of the disclosure, reference is made to Figure 5k and 5l The first redistribution 111 has a first projected length d1 on the bonding surface 10 between the first semiconductor layer 11 and the second semiconductor layer 12. The second redistribution 121 has a second projected length d2 on the bonding surface 10 between the first semiconductor layer 11 and the second semiconductor layer 12. The first projected length d1 and the second projected length d2 are not equal; for example, the first projected length d1 is greater than the second projected length d2 (e.g., ...). Figure 5k As shown), or, the first projection length d1 is less than the second projection length d2 (as shown). Figure 5l (As shown).

[0116] The semiconductor structure formation method provided in this disclosure involves forming a first metal pad on the surface of a first semiconductor and a second metal pad on the surface of a second semiconductor. The first and second semiconductor layers are bonded together using the first and second metal pads. Because the first and second metal pads have relatively large areas, the problem of misalignment at small electrical connection points between the two semiconductor layers, leading to a failure to make electrical connections, can be avoided, thus improving the semiconductor fabrication yield. Furthermore, this disclosure method increases the spacing between the metal pads by forming first and second rewiring lines with different projected lengths, thereby reducing the parasitic capacitance of the formed semiconductor structure and improving its performance.

[0117] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. Furthermore, the various components shown or discussed may be coupled or directly coupled to each other.

[0118] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0119] The above descriptions are merely some embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: A first semiconductor layer and a second semiconductor layer bonded together; The first semiconductor layer includes a plurality of first rewiring connections; wherein the first rewiring connections have a first projected length on the bonding surface between the first semiconductor layer and the second semiconductor layer; The second semiconductor layer includes a plurality of second overwires; wherein the second overwires have a second projected length on the bonding surface, and the first projected length is not equal to the second projected length; The plurality of first-level wirings are electrically connected to the plurality of second-level wirings in a one-to-one correspondence, and the projected length of each first-level wiring on the bonding surface is equal to the sum of the projected lengths of the corresponding second-level wiring on the bonding surface. The projected lengths of any two adjacent first overlays on the bonding surface are not equal; or, the projected lengths of any two adjacent second overlays on the bonding surface are not equal.

2. The semiconductor structure according to claim 1, characterized in that, Multiple first-level wirings are arranged cyclically according to a preset arrangement; The preset arrangement includes: the first projection length increasing sequentially, the first projection length decreasing sequentially, the first projection length increasing first and then decreasing, and the first projection length decreasing first and then increasing.

3. The semiconductor structure according to claim 2, characterized in that, As the first projection length of the plurality of first overwires on the bonding surface decreases sequentially, the second projection length of the second overwire corresponding to each of the first overwires on the bonding surface increases sequentially.

4. The semiconductor structure according to claim 2, characterized in that, As the first projection length of multiple first overlays on the bonding surface increases sequentially, the second projection length of the second overlay corresponding to each first overlay on the bonding surface decreases sequentially.

5. The semiconductor structure according to claim 2, characterized in that, When the first projection length of multiple first overlays on the bonding surface first increases and then decreases, the second projection length of the second overlay corresponding to each first overlay on the bonding surface first decreases and then increases.

6. The semiconductor structure according to claim 2, characterized in that, When the first projection length of multiple first overlays on the bonding surface first decreases and then increases, the second projection length of the second overlay corresponding to each first overlay on the bonding surface first increases and then decreases.

7. The semiconductor structure according to any one of claims 1 to 6, characterized in that, The first semiconductor layer further includes a first metal pad connected to the first rewiring; the second semiconductor layer further includes a second metal pad connected to the second rewiring. The first layer of wiring and the corresponding second layer of wiring are electrically connected through the first metal pad and the second metal pad.

8. The semiconductor structure according to claim 7, characterized in that, The first metal pad is bonded to the corresponding second metal pad to form a bonding pad; the plurality of bonding pads are arranged in a stepped manner in the bonding surface.

9. The semiconductor structure according to claim 8, characterized in that, The first semiconductor layer includes a memory array; the memory array includes multiple word lines and multiple bit lines; Each word line is electrically connected to a corresponding first overlay, and each bit line is electrically connected to a corresponding first overlay.

10. The semiconductor structure according to claim 9, characterized in that, The second semiconductor layer includes peripheral circuitry; the second redistribution wiring is electrically connected to the peripheral circuitry.

11. The semiconductor structure according to claim 10, characterized in that, Each word line is electrically connected to the peripheral circuit via a first overlay and a corresponding second overlay, and each bit line is electrically connected to the peripheral circuit via a first overlay and a corresponding second overlay.

12. The semiconductor structure according to claim 11, characterized in that, The first semiconductor layer includes a first dielectric layer, and the first redistribution is located in the first dielectric layer; The second semiconductor layer includes a second dielectric layer, and the second redistribution is located in the second dielectric layer; The semiconductor structure further includes: a barrier layer; The barrier layer is located between the first rewiring and the first dielectric layer, between the second rewiring and the second dielectric layer, between the bonding pad and the first dielectric layer, and between the bonding pad and the second dielectric layer.

13. A method for forming a semiconductor structure, characterized in that, include: Provide a first semiconductor layer and a second semiconductor layer; Multiple first overlay wirings are formed in the first semiconductor layer; wherein, the first overlay wirings have a first projected length on the bonding surface between the first semiconductor layer and the second semiconductor layer; Multiple second-level wirings are formed in the second semiconductor layer; wherein the second-level wirings have a second projected length on the bonding surface, and the first projected length is not equal to the second projected length; The first semiconductor layer and the second semiconductor layer are bonded to electrically connect the plurality of first superwires and the plurality of second superwires in a one-to-one correspondence, and the sum of the projected length of each first superwire on the bonding surface and the projected length of the corresponding second superwire on the bonding surface is equal; Wherein, the projected lengths of any two adjacent first overlays on the bonding surface are not equal; or, the projected lengths of any two adjacent second overlays on the bonding surface are not equal.

14. The method according to claim 13, characterized in that, The first layer of wiring is formed through the following steps: A first dielectric layer is formed on the substrate surface of the first semiconductor layer; The first dielectric layer is etched to form the first etched groove; The first etched groove is filled with metal material to form the first rewiring.

15. The method according to claim 13, characterized in that, The second rewiring is formed through the following steps: A second dielectric layer is formed on the substrate surface of the second semiconductor layer; The second dielectric layer is etched to form a second etched groove; The second etched groove is filled with metal material to form the second rewiring.

16. The method according to any one of claims 13 to 15, characterized in that, The method further includes: forming a first metal pad electrically connected to the first rewiring, and forming a second metal pad electrically connected to the second rewiring.

17. The method according to claim 16, characterized in that, The bonding of the first semiconductor layer and the second semiconductor layer to electrically connect the first redistribution and the second redistribution includes: The first surface of the first semiconductor layer exposing the first metal pad and the second surface of the second semiconductor layer exposing the second metal pad are subjected to surface activation treatment; The first surface and the second surface are adhered together, and each of the first metal pads is aligned face to face with one of the second metal pads; The first semiconductor layer and the second semiconductor layer are annealed.

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