Semiconductor structure and its fabrication method

Abstract

This disclosure provides a semiconductor structure and its fabrication method, relating to the field of semiconductor technology, to solve the technical problem of high contact resistance between bit lines and bit line contacts. The semiconductor structure includes: a substrate, on which a first stacked structure is disposed, the first stacked structure including a memory cell array; multiple word lines disposed within the first stacked structure and electrically connected to the memory cell array, with a first direction perpendicular to the substrate; multiple bit lines disposed beside the first stacked structure and electrically connected to the memory cell array; a step formed at one end of each bit line away from the memory cell array, each bit line including a first core layer and a first conductive layer covering the first core layer; and multiple bit line plugs, each bit line plug corresponding to and contacting the first conductive layer of a bit line. By adjusting the materials of the bit line plugs and the first conductive layer, the contact resistance between the bit line plugs and the first conductive layer can be reduced, thereby reducing the contact resistance between the bit line plugs and the bit lines.

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