A gate-commutated thyristor chip and a thyristor

Abstract

The application belongs to the technical field of semiconductor devices, and particularly relates to a gate-commutated thyristor chip and a thyristor, which comprises a cathode metal layer, gate metal layers located on both sides of the cathode metal layer, an anode metal layer opposite to the cathode metal layer, and a semiconductor substrate formed between the cathode metal layer and the anode metal layer; the semiconductor substrate comprises a five-layer structure or a six-layer structure, and each structure layer has a different conductive type, a P base region is divided into zones to form a "concave" main junction, the junction depth and concentration of the P base region below the cathode comb are improved, and the current gain alpha of the corresponding equivalent npn transistor in this part is reduced 21 The gate-commutated thyristor chip and the thyristor can simultaneously reduce on-state loss and off-state loss. The application is particularly suitable for reverse blocking GCT, can reduce the wafer thickness, and realize a good compromise between blocking, on-state and off-state.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a gate-commutated thyristor chip and thyristor. Background Technology

[0002] IGCT (Integrated Gate Commutated Thyristor), as a fully controllable power semiconductor device, has broad application prospects in the power grid field due to its large power capacity, low on-state loss, and robustness in short-circuit failure modes. As a core component of power devices, the IGCT chip, also known as a GCT, has loss characteristics that are closely related to the energy transfer efficiency of the power device.

[0003] The main vertical structure of existing trench-type GCT chips includes PNPN four regions, such as Figure 1 As shown. Based on the degree of doping, it can be further subdivided into P... + 、N′、N - P, P + N + The six zones correspond to P respectively. + Anode emission region, N′ buffer layer, N - base region, P base region, P + short base region and N + The emitter region (also known as the cathode comb). There are three PN junctions inside the chip: J1 (anode transparent junction), J2 (blocking voltage main junction), and J3 (gate cathode junction) from the anode to the cathode. The cathode and gate are connected by a trench forming a step. Viewed laterally from the GCT chip, the cathode combs are arranged in sector arcs or evenly around the circumference of a wafer. For GCT dies of different diameters, the cathode combs are generally arranged radially in 2 to 16 loops.

[0004] For grooved GCTs, such as Figure 1 As shown, its trench structure can, on the one hand, form gaps for gate-cathode isolation; on the other hand, the trench depth can control the current gain α2 of the npn equivalent transistor and the current gain α1 of the pnp equivalent transistor contained in the GCT chip, thereby optimizing the loss characteristics and turn-off capability of the GCT chip. Furthermore, for existing HPT (high power technology) type GCT structures, such as... Figure 2As shown, with a fixed waveform height, improving turn-off capability requires increasing the junction depth of the main junction to reduce the current gain α2 of the npn equivalent transistor below the cathode comb. This leads to an increase in the wafer thickness of the GCT single crystal, resulting in increased turn-off and on-state losses, especially for GCT reverse-resistance type devices. On the other hand, existing HPT technology only utilizes the lateral electric field to quickly extract hole carriers in the region below the cathode comb, but this improves the cathode electron emission efficiency in that region, thus having limited effect on improving the turn-off current capability of the GCT. In summary, existing HPT GCT loss control always presents a design contradiction between turn-on and turn-off losses, and the improvement in turn-off capability is limited. Therefore, a wave-shaped GCT chip structure scheme is proposed to improve turn-off capability while simultaneously reducing turn-on and turn-off losses. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a gate commutated thyristor chip and thyristor that improves turn-off capability while reducing turn-on loss and turn-off loss.

[0006] The present invention provides a gate-commutated thyristor chip, comprising: a cathode metal layer, a gate metal layer located on both sides of the cathode metal layer, an anode metal layer opposite to the cathode metal layer, and a semiconductor substrate formed between the cathode metal layer and the anode metal layer; The semiconductor substrate includes a five-layer or six-layer structure, and each structural region has a different conductivity type. The five-layer structure includes: N in contact with the cathode metal layer. + Emitter region, AND gate metal layer and N + P in contact with the launch area + Short base region, and P + P-base region in contact with short base region, N-base region in contact with P-base region - base region, and N - P in base region contact + Anode emission region; the P + The anode emission region is in contact with the anode metal layer; The six-layer structure includes: N in contact with the cathode metal layer. + Emitter region, AND gate metal layer and N + P in contact with the launch area + Short base region, and P + P-base region in contact with short base region, N-base region in contact with P-base region - base region, and N - The N′ buffer layer or P-type anode emitter region in contact with the base region, and the P-type anode emitter region in contact with the N′ buffer layer or P-type anode emitter region. + Anode emission region; the P + The anode emission region is in contact with the anode metal layer; The P-base region has a protruding structure, and the N-base region has a protruding structure. - The base region has a recessed structure, and the protruding structure is embedded within the recessed structure.

[0007] Optionally, the N + The launch region is partially embedded with P + Within the short base region, the embedding depth is 0-30 μm.

[0008] Optionally, the N + The doping concentration of the emitter region is 1E16cm. -3 -1E22cm -3 The diffusion depth is 5μm-40μm.

[0009] Optionally, the P + The doping concentration of the short base region is 1E15cm. -3 -5E18cm -3 The diffusion depth is approximately 20μm-80μm.

[0010] Optionally, the doping concentration of the P-based region is 1E13cm. -3 -2E16cm -3 The diffusion depth is 60μm-200μm.

[0011] Optionally, the doping concentration of the P-type anode emitter region is 1E13cm. -3 -2E16cm -3 The diffusion depth is 60μm-200μm.

[0012] Optionally, the doping concentration of the N′ buffer layer is 1E12cm. -3 -1E17cm -3 The diffusion depth is typically 10μm-100μm.

[0013] Optionally, the P + The doping concentration of the anode emitter region is 1E15cm. -3 -5E18cm -3 The diffusion depth is 0.5μm-80μm.

[0014] A thyristor, comprising the gate-commutated thyristor chip.

[0015] Optionally, the thyristor includes the gate-commutated thyristor chip and the fast recovery diode chip, wherein the gate-commutated thyristor chip and the fast recovery diode chip are connected in anti-parallel through an NPN isolation structure to form the thyristor.

[0016] The beneficial effect of this invention is that the gate-commutated thyristor chip provided by this invention has a "concave" shaped corrugated main junction designed in the P-base region, which increases the junction depth and concentration of the P-base region below the cathode comb, thereby reducing the current gain α of the corresponding equivalent npn transistor. 21 On the one hand, the efficiency of electron emission from the cathode during turn-off is improved; on the other hand, the lateral electric field below hinders the accumulation of charge carriers in the P-base region below the cathode comb, thereby increasing the turn-off current. Reducing the junction depth and concentration of the P-base region below the gate increases the current gain α of the corresponding equivalent npn transistor. 22 This design enhances the carrier modulation effect of the npn transistor beneath the gate metal layer (occupying more than 60% of the chip area) during on-state operation to reduce on-state voltage drop. Simulation design verification shows that, compared to trench-type GCTs, it can simultaneously reduce on-state and off-state losses under the same current conditions; it is particularly suitable for reverse-resistance GCTs, allowing for reduced chip thickness and achieving a better trade-off design between blocking, on-state, and off-state. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of an existing trench-type GCT chip; Figure 2 This is a schematic diagram of the structure of an existing HPT-type GCT chip; Figure 3 A schematic diagram of the reverse-resistance GCT chip provided in an embodiment of the present invention. Figure 1 ; Figure 4 A schematic diagram of the planar reverse-resistance GCT chip provided in an embodiment of the present invention. Figure 2 ; Figure 5 This is a schematic diagram of the planar asymmetric GCT chip provided in an embodiment of the present invention; Figure 6 A schematic diagram of the structure of the asymmetric GCT chip provided in the embodiments of the present invention. Figure 1 ; Figure 7 A schematic diagram of the structure of the asymmetric GCT chip provided in the embodiments of the present invention. Figure 2 ; Figure 8 This is a schematic diagram of the structure of the reverse-conductive GCT chip provided in an embodiment of the present invention.

[0018] In the diagram: 1, N + Launch area; 2, P + 3. Short base region; 4. P base region; 5. N base region - 5. Base region; 6. P-type anode emitter region; +7. Anode Emitter; 8. N′ Buffer Layer; 9. Cathode Metal Layer; 10. Anode Metal Layer; 11. Gate Metal Layer; 12. J1 Junction; 13. J2 Junction; 14. FRD-P + Anode emitter region; 15. P-anode region; 16. N-anode region + Cathode emission region; 17, N - Isolation base area. Detailed Implementation

[0019] like Figure 3-8 As shown, this embodiment of the invention provides a gate-commutated thyristor chip, including: a cathode metal layer 8, a gate metal layer 10 located on both sides of the cathode metal layer 8, an anode metal layer 9 opposite to the cathode metal layer 8, and a semiconductor substrate formed between the cathode metal layer 8 and the anode metal layer 9; the semiconductor substrate includes a five-layer region structure or a six-layer region structure, and each layer structure region has a different conductivity type. The five-layer structure includes: N in contact with the cathode metal layer 8 + Emitter region 1, gate metal layer 10 and N + P that is in contact with launch zone 1 + Short base region 2, and P + P-base region 3 in contact with short base region 2, N-base region 3 in contact with short base region 2 - Base region 4, and N - P in base region 4 contact + Anode emission region 6; P + Anode emission region 6 is in contact with anode metal layer 9; The six-layer structure includes: N in contact with the cathode metal layer 8 + Emitter region 1, gate metal layer 10 and N + P that is in contact with launch zone 1 + Short base region 2, and P + P-base region 3 in contact with short base region 2, N-base region 3 in contact with short base region 2 - Base region 4, and N - The N′ buffer layer 7 or P-type anode emission region 5 in contact with the base region 4, and the P-type anode emission region 5 in contact with the N′ buffer layer 7 or P-type anode emission region 5 + Anode emission region 6; P + Anode emission region 6 is in contact with anode metal layer 9; The P-base region 3 has a convex structure, N - Base region 4 has a concave structure, and the convex structure is embedded in the concave structure, so the cross-section of the J2 junction 12 formed is concave.

[0020] Compared with the prior art, the gate-commutated thyristor chip provided by the present invention designs the P-base region 3 into a concave corrugated main junction, increasing the junction depth and concentration of the P-base region 3 below the cathode comb, thereby reducing the current gain α of the corresponding equivalent npn transistor. 21 On the one hand, the efficiency of electron emission from the cathode during turn-off is improved, and on the other hand, the lateral electric field below hinders the accumulation of charge carriers in the P-base region 3 below the cathode comb, thereby increasing the turn-off current. Reducing the junction depth and concentration of the P-base region 3 below the gate increases the current gain α of the corresponding equivalent npn transistor. 22 This design enhances the carrier modulation effect of the npn transistor beneath the gate metal layer 10 (occupying more than 60% of the chip area) during on-state operation to reduce on-state voltage drop. Simulation design verification shows that, compared to trench-type GCTs, it can simultaneously reduce on-state and off-state losses under the same current conditions; it is particularly suitable for reverse-resistance GCTs, allowing for reduced chip thickness and achieving a better trade-off design between blocking, on-state, and off-state.

[0021] Compared to a standard GCT of the same level, the wavy GCT proposed in this invention shows a more than 20% improvement in turn-off capability in simulations. Under the same on-state loss design structure, its loss is reduced by more than 10%. Therefore, it can effectively improve turn-off capability while conveniently balancing the turn-off and on-state losses of the designed device.

[0022] Example 1 This invention is applied to reverse-resistance gate-commutated thyristors, such as... Figure 3 and Figure 4 As shown; The reverse-resistance GCT chip structure, from top to bottom, consists of N... + Launch Area 1, P + Short base region 2, P base region 3, N - Base region 4, P-type anode emitter region 5 and P + Anode emitter region 6; reverse-resistance type GCT chip P + Short base region 2 and N + Launch area 1 is located on the same side, P + Short base region 2 and N + The emitter area 1 is located on the same side, and the height difference (groove depth) between the two is 0-30μm. When the height difference is 0, it is a planar reverse-resistance type GCT chip. This reverse-resistance GCT chip has four working states: blocking, triggering (on), on, and off, and the working process is as follows: Blocking state: when the anode-cathode gap (P + Anode emission region 6-N + Emitter region 1) Apply a positive voltage V DC The device is in a forward blocking state, and the blocking voltage is mainly determined by the reverse-biased J2 junction (P-base region 3-N). - The PN junction formed in the base region bears the load. When the anode-cathode (P...+ Anode emission region 6-N + Emitter region 1) Apply reverse voltage -V DC The device is in reverse blocking state, and the blocking voltage is mainly caused by the reverse-biased J1 junction 11(N - The base region - P-type anode emitter region 5 forms the PN junction. However, when GCT is blocked, the device gate-cathode J3 junction 13 (N) must be blocked. + Launch Zone 1 and P + Apply a reverse bias voltage (or short-circuit) of -20V to the PN junction formed by the short base region 2 to avoid a significant reduction in the device's breakdown voltage due to the forward bias injection effect of the J3 junction 13.

[0023] Triggering (Turn-On) Process: Before triggering, the device is in a blocking state, i.e., junctions J2 12 and J3 13 are in a reverse-biased blocking state. A forward bias voltage is applied to the gate-cathode (junction J3 13) of the chip, and the gate forward pulse current amplitude (I) is... GT When the current amplification factor (di / dt) of the two equivalent transistors is sufficiently large, electrons will be uniformly injected into junction 13 of the J3 transistor and eventually diffused away from the anode. Similarly, holes will be uniformly injected into junction 11 of the PNP transistor and eventually diffused away from the cathode. When the sum of the current amplification factors of the two equivalent transistors is greater than 1 (i.e., α...),... PNP +α NPN When >1), the GCT is turned on and held, which macroscopically manifests as the GCT changing from a high-resistance state to a low-resistance state.

[0024] On-state state: After the GCT is turned on, it enters the conduction state and exhibits thyristor characteristics. Due to the "lock-up" effect, the GCT can still maintain forward conduction even if the gate current is removed. At the same time, due to the conductance modulation effect generated by the bipolar carriers in the N-base and P-base regions, the GCT has the advantages of low on-state voltage drop and strong current carrying capacity.

[0025] Turn-off process: A -20V bias voltage is applied to the gate-cathode of the GCT during conduction, causing junction J3 (13) to turn off. Before the voltage at junction J2 (12) rises, the cathode current switches entirely to the gate (i.e., hard turn-off), and the GCT enters the open-base PNP transistor operating mode. At this time, excess electron carriers in the N-base region diffuse through the anode J1 and are pumped away, while excess hole carriers in the P-base region are pumped away through the gate, allowing the anode current of the GCT to be reliably turned off in a very short time. Simultaneously, junction J2 (12) regains its blocking capability. Macroscopically, this manifests as the GCT switch changing from a low-resistance state to a high-resistance state.

[0026] N + The doping concentration of emitter region 1 is 1E16cm. -3 -1E22cm -3 The diffusion depth is 5μm-40μm; P +The doping concentration of short base region 2 is 1E15cm. -3 -5E18cm -3 The diffusion depth is approximately 20μm-80μm; among them, such as Figure 4 As shown, P in the reverse-resistance GCT chip structure + The short base region 2 is divided into two parts located in N. + P1 directly below launch area 1 + Short base region and located at P1 + P2 on both sides of the short base region + Short base region; introduction of P1 + The design of the short base region is based on N + Launch Area 1, P1 + Short base region and N - The equivalent NPN transistor formed in the base region (its equivalent current gain α) NPN1 The main chip's turn-on function is introduced, thus solving the problem of freely adjustable turn-on characteristics and conduction losses; P2 is introduced. + The design of the short base region is based on N + Launch Area 1, P2 + Short base region and N - The equivalent NPN transistor formed in the base region (its equivalent current gain α) NPN2 This technology, which is the main chip for shutdown function, solves the problem of freely adjustable GCT shutdown capability and shutdown loss.

[0027] The doping concentration of P-based region 3 is 1E13cm. -3 -2E16cm -3 The diffusion depth is 60μm-200μm, depending on the trade-off design between blocking voltage and on-state loss. The shape of the J2 junction 12 in the P-base region 3 can be rectangular, trapezoidal, conical, or multi-step, etc. Its shape design determines the lateral electric field strength, electric field distribution, and NPN transistor current gain α. NPN2 The specific size depends on the trade-off design between turn-off capability and on-state loss characteristics. During IGCT turn-off, on the one hand, the lateral electric field of the J2 junction is used to rapidly extract hole carriers from the region below the cathode comb; on the other hand, the shape design of the J2 junction controls the flow of N... + Launch Area 1, P2 + Short base region and N - The equivalent NPN transistor current gain α formed in the base region NPN2 By reducing the cathode electron emission efficiency, the carrier concentration below the cathode comb is reduced, thus avoiding turn-off re-trigger failure, thereby improving the chip's turn-off capability and controlling the device's turn-off loss.

[0028] N - The doping concentration and width of base region 4 depend on the blocking voltage design; The doping concentration of the P-type anode emitter region 5 is 1E13cm. -3 -2E16cm -3 The diffusion depth is 60μm-200μm, depending on the trade-off design between blocking voltage and on-state loss. P + The doping concentration of anode emitter region 6 is 1E15cm. -3 -5E18cm -3 The diffusion depth ranges from 0.5 μm to 80 μm, and the diffusion depth depends on the trade-off design of the device's on-state loss. The P + The short base region 2 is typically led out through a gate metal layer 10 formed by stacking one or more regions; The N + The emitter region 1 is typically led out through a gate metal layer 10 composed of one or more regions stacked together; The P + The anode emitter region 6 is typically led out through a gate metal layer 10 formed by stacking one or more regions.

[0029] Example 2 This invention is applied to asymmetric gate-commutated thyristors, such as... Figures 5-7 As shown; The asymmetric GCT chip (hereinafter referred to as GCT chip) structure, from top to bottom, consists of N+ emitter region 1, P+ short base region 2, P base region 3, and N... - Base region 4 (or containing N′ buffer layer 7) and P + Anode emitter region 6; This asymmetric GCT chip has four operating states: blocking, triggering (on), on, and off. The operating process is as follows: Blocking state: when the anode-cathode gap (P) + Anode emission region 6-N + Emitter region 1) Apply a positive voltage V DC The device is in a forward blocking state, and the blocking voltage is mainly determined by the reverse-biased J2 junction (P-base region 3-N). - The PN junction formed in the base region can withstand this. However, when GCT is blocked, the gate-cathode J3 junction (N) of the device must be blocked. + Launch Zone 1 and P + Apply a reverse bias voltage (or short-circuit) of -20V to the PN junction formed by the short base region 2 to avoid a significant reduction in the device's breakdown voltage due to the forward bias injection effect of the J3 junction.

[0030] Triggering (Turn-On) Process: Before triggering, the device is in a blocking state, i.e., junctions J2 12 and J3 13 are in a reverse-biased blocking state. A forward bias voltage is applied to the gate-cathode (junction J3 13) of the chip, and the gate forward pulse current amplitude (I) is... GTWhen the current amplification factor (di / dt) of the two equivalent transistors is sufficiently large, electrons will be uniformly injected into junction 13 of the J3 transistor and eventually diffused away from the anode. Similarly, holes will be uniformly injected into junction 11 of the PNP transistor and eventually diffused away from the cathode. When the sum of the current amplification factors of the two equivalent transistors is greater than 1 (i.e., α...),... PNP +α NPN When >1), the GCT is turned on and held, which macroscopically manifests as the GCT changing from a high-resistance state to a low-resistance state.

[0031] On-state state: After the GCT is turned on, it enters the conduction state and exhibits thyristor characteristics. Due to the "lock-up" effect, the GCT can still maintain forward conduction even if the gate current is removed. At the same time, due to the conductance modulation effect generated by the bipolar carriers in the N-base and P-base regions, the GCT has the advantages of low on-state voltage drop and strong current carrying capacity.

[0032] Turn-off process: A -20V bias voltage is applied to the gate-cathode of the GCT during conduction, causing junction J3 13 to turn off. Before the voltage at junction J2 12 rises, the cathode current is completely switched to the gate (i.e., hard turn-off), and the GCT enters the open-base PNP transistor operating mode. At this time, excess electron carriers in the N-base region diffuse through the transparent anode junction J1 11 (N′ buffer layer 7 and P...). + The PN junction formed by the anode emitter region 6 is removed, while the excess hole carriers in the P-base region are extracted and discharged through the gate, enabling the anode current of the GCT to be reliably turned off in a very short time. At the same time, the J2 junction 12 recovers its blocking capability. Macroscopically, this is manifested as the GCT switch changing from a low-resistance state to a high-resistance state.

[0033] The P+ short base region 2 and N+ emitter region 1 of the GCT chip are located on the same side, and the height difference (groove depth) between them is 0-30μm. When the height difference is 0, it is a planar asymmetric GCT chip. N + The doping concentration of emitter region 1 is 1E16cm. -3 -1E22cm -3 The diffusion depth is 5μm-40μm; P + The doping concentration of short base region 2 is 1E15cm. -3 -5E18cm -3 The diffusion depth is approximately 20μm-80μm; The doping concentration of P-based region 3 is 1E13cm. -3 -2E16cm -3 The diffusion depth is 60μm-200μm, depending on the trade-off design between blocking voltage and on-state loss. The shape of the J2 junction 12 in the P-base region 3 can be rectangular, trapezoidal, conical, or multi-step, etc. Its shape design determines the lateral electric field strength, electric field distribution, and NPN transistor current gain α.NPN2 The specific size depends on the trade-off design between turn-off capability and on-state loss characteristics; when the IGCT is turned off, on the one hand, the lateral electric field of the J2 junction is used to quickly extract hole carriers from the region below the cathode comb; on the other hand, the shape design of the J2 junction is used to control the flow of N... + Launch Area 1, P2 + Short base region and N - The equivalent NPN transistor current gain α formed in the base region NPN2 By reducing the cathode electron emission efficiency, the carrier concentration below the cathode comb is reduced, thus avoiding turn-off re-trigger failure, thereby improving the chip's turn-off capability and controlling the device's turn-off loss.

[0034] N - The doping concentration and width of base region 4 depend on the blocking voltage design; N′ buffer layer 7, with a doping concentration of 1E12cm⁻¹ -3 -1E17cm -3 Its diffusion depth is 10μm-100μm, and its design depends on the device voltage level.

[0035] P + Anode emitter region 6 has a doping concentration of 1E15cm⁻¹. -3 -5E18cm -3 The diffusion depth is 0.5μm-20μm, and the diffusion depth depends on the trade-off design between turn-off loss and on-state loss characteristics.

[0036] The P + The short base region 2 is typically led out through one or more stacked gate metal layers 10.

[0037] The N + The emitter layer is typically led out through one or more stacked gate metal layers 10.

[0038] The P + The anode emitter region 6 is typically led out through one or more stacked gate metal layers 10.

[0039] Example 3 When this invention is applied to a reverse-conducting gate-commutated thyristor, the GCT structure and the FRD structure are connected in anti-parallel through an NPN isolation structure to form a structure as shown in the figure. Figure 8 The structure shown indicates that FRD is a fast recovery diode. This reverse-conducting GCT chip has five operating states: blocking, triggering (on), on, off, and reverse recovery. The operating process is as follows: Blocking state: when the anode-cathode gap (P + Anode emission region 6 / N + Cathode emission region 16-N + Launch Area 1 / P+ A positive voltage V is applied to the anode emitter region 14) DC The device is in a forward blocking state, and the blocking voltage is mainly due to the reverse-biased J2 junction 12() P base region 3-N - Base region 4, P-anode region 15-N - The PN junction formed in base region 4 is subjected to this. However, when GCT is blocked, the gate-cathode J3 junction 13 (N) must be blocked. + Launch Zone 1 and P + Apply a reverse bias voltage (or short-circuit) of -20V to the PN junction formed by the short base region 2 to avoid a significant reduction in the device's breakdown voltage due to the forward bias injection effect of the J3 junction 13.

[0040] Triggering (Turn-On) Process: Before triggering, the device is in a blocking state, i.e., junctions J2 12 and J3 13 are in a reverse-biased blocking state. A forward bias voltage is applied to the gate-cathode (junction J3 13) of the chip, and the gate forward pulse current amplitude (I) is... GT When the current amplification factor (di / dt) of the two equivalent transistors is sufficiently large, electrons will be uniformly injected into junction 13 of the J3 transistor and eventually diffused away from the anode. Similarly, holes will be uniformly injected into junction 11 of the PNP transistor and eventually diffused away from the cathode. When the sum of the current amplification factors of the two equivalent transistors is greater than 1 (i.e., α...),... PNP +α NPN When >1), the GCT is turned on and held, which macroscopically manifests as the GCT changing from a high-resistance state to a low-resistance state.

[0041] On-state state: After the GCT is turned on, it enters the conduction state and exhibits thyristor characteristics. Due to the "lock-up" effect, the GCT can still maintain forward conduction even if the gate current is removed. At the same time, due to the conductance modulation effect generated by the bipolar carriers in the N-base and P-base regions, the GCT has the advantages of low on-state voltage drop and strong current carrying capacity.

[0042] Turn-off process: A -20V bias voltage is applied to the gate-cathode of the conducting GCT to turn off junction J3 13. Before the voltage of junction J2 12 rises, the cathode current is completely switched to the gate (i.e., hard turn-off), and the GCT enters the open-base PNP transistor operating mode, while the FRD is in the blocking state. At this time, the excess electron carriers in the N-base region diffuse through the transparent anode junction J1 11 (N′ buffer layer 7 and P...). + The PN junction formed by the anode emitter region 6 is removed, while the excess hole carriers in the P-base region are extracted and discharged through the gate, enabling the anode current of the GCT to be reliably turned off in a very short time. At the same time, the J2 junction 12 recovers its blocking capability. Macroscopically, this is manifested as the GCT switch changing from a low-resistance state to a high-resistance state.

[0043] Reverse recovery state: After the GCT chip FRD structure is fully reverse-biased and turned on, the N-base region 4 is filled with a large number of free carriers due to the "conductance modulation" phenomenon. When the anode-cathode space of the FRD structure (P... + Anode emission region 6 / N + Cathode emission region 16-N + Launch Area 1 / P + A positive voltage V is applied to the anode emitter region 14) DC At this point, it is necessary to quickly extract carriers from the N-base region to form a sufficiently wide depletion layer to withstand the voltage, while holes are pulled by the electric field to the "anode" (P) in the FRD structure. + Anode emission region 14 / N + (Emitting region 1) Electrons are swept out in the opposite direction by the electric field into the "cathode" (N) of the FRD structure. + Cathode emission region 16 / P + Anode emitter region 6), thus generating a reverse current and quickly reaching I. RR Subsequently, the carriers in the bulk center are depleted through recombination centers, and the IRR slowly recovers to 0. Macroscopically, this manifests as the switch in the GCT changing from a low-resistance state to a high-resistance state.

[0044] The GCT chip structure, from top to bottom, consists of N... + Launch Area 1, P + Short base region 2, P base region 3, N - Base region 4 (or containing N′ buffer layer 7) and P + Anode emission region 6; the FRD chip structure from top to bottom is FRD-P + Anode emission region 14, P anode region 15, N - Base region 4 (or containing N′ buffer layer 7), N + Cathode emission region 16; wherein the GCT chip and the FRD chip are connected by N - Isolation base region 17, via the P of the GCT chip + Short base region 2 / P base region 3, N-base region and FRD-P + The anode emitter region / P anode region 15 is laterally formed into an NPN transistor structure for isolation, such as Figure 8 As shown in the dashed box.

[0045] Among them, the P of the GCT chip + Short base region 2 and N + The emitter area 1 is located on the same side, and the height difference (groove depth) between the two is 0-30μm. When the height difference is 0, it is a planar asymmetric GCT chip. GCT chip N + Emitter region 1 doping concentration is 1E16cm -3 -1E22cm -3 The diffusion depth is 5μm-40μm; N in the FRD structure of the GCT chip + The doping concentration of cathode emitter region 16 is 1E16cm. -3 -1E22cm -3 The diffusion depth is 5μm-60μm; GCT chip P + The doping concentration of short base region 2 is 1E15cm. -3 -5E18cm -3 The diffusion depth is approximately 20μm-80μm; In the FRD structure of the GCT chip, P + The doping concentration of anode emitter region 14 is 1E15cm. -3 -5E18cm -3 The diffusion depth is approximately 20μm-80μm; The doping concentration of the P-base region 3 of the GCT chip and the P-anode region 15 of the FRD chip is 1E13cm. -3 -2E16cm -3 The diffusion depth is 60μm-200μm, depending on the trade-off design between blocking voltage and on-state loss. The doping concentration of the P-anode region 15 in the FRD structure of the GCT chip is 1E13cm. -3 -2E16cm -3 The diffusion depth is 60μm-200μm, depending on the trade-off between the blocking voltage and the reverse soft recovery characteristics. The shape of the J2 junction 12 in the P-base region 3 of the GCT chip can be rectangular, trapezoidal, conical, or multi-step, depending on the trade-off design between turn-off capability and on-state loss characteristics. Its shape design determines the lateral electric field strength, electric field distribution, and NPN transistor current gain α. NPN2 The specific size depends on the trade-off design between turn-off capability and on-state loss characteristics; when the IGCT is turned off, on the one hand, the lateral electric field of the J2 junction is used to quickly extract hole carriers from the region below the cathode comb; on the other hand, the shape design of the J2 junction is used to control the flow of N... + Launch Area 1, P2 + Short base region and N - The equivalent NPN transistor current gain α formed in the base region NPN2 By reducing the cathode electron emission efficiency, the carrier concentration below the cathode comb is reduced, thus avoiding turn-off re-trigger failure, thereby improving the chip's turn-off capability and controlling the device's turn-off loss.

[0046] N of GCT chip and FRD chip - The doping concentration and width of base region 4 depend on the trade-off between blocking voltage and reverse recovery characteristics. N -The doping concentration of isolation base region 17 is the same as that of the N in the GCT chip and the FRD chip. - The base region 4 typically has a surface isolation width L of 5μm-60μm, depending on the isolation electrical characteristics design.

[0047] The N′ buffer layer 7 of the GCT chip and FRD chip has a doping concentration of 1E12cm⁻¹. -3 -1E17cm -3 Its diffusion depth is 10μm-100μm, and its design depends on the device voltage level.

[0048] GCT chip P + Anode emitter region 6 has a doping concentration of 1E15cm⁻¹. -3 -5E18cm -3 The diffusion depth is 0.5μm-20μm, and the diffusion depth depends on the trade-off design between turn-off loss and on-state loss characteristics. The P + The short base region 2 is typically led out through one or more stacked gate metal layers 10.

[0049] The N + The emitter region 1 is typically led out through one or more stacked gate metal layers 10.

[0050] The P + The anode emitter region 6 is typically led out through one or more stacked gate metal layers 10.

[0051] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of protection of this application is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of one or more embodiments of this application as described above, which are not provided in detail for the sake of brevity.

[0052] One or more embodiments in this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of this application. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments in this application should be included within the protection scope of this application.

Claims

1. A gate-commutated thyristor chip, characterized in that, include: The cathode metal layer (8), the gate metal layer (10) located on both sides of the cathode metal layer (8), the anode metal layer (9) opposite to the cathode metal layer (8), and the semiconductor substrate formed between the cathode metal layer (8) and the anode metal layer (9); The semiconductor substrate comprises a six-layer region structure, and each region has a different conductivity type. The six-layer structure includes: N in contact with the cathode metal layer (8) + The emitter region (1), the gate metal layer (10), and the N + P in contact with the launch area (1) + Short base region (2), and P + The P-base region (3) in contact with the short base region (2), and the N-base region in contact with the P-base region (3) - Base region (4), and N - The base region (4) is in contact with the N′ buffer layer (7) or the P-type anode emission region (5), and the P-type anode emission region (5) is in contact with the N′ buffer layer (7) or the P-type anode emission region (5). + Anode emission region (6); the P + The anode emission region (6) is in contact with the anode metal layer (9); The P-base region (3) has a protruding structure, and the N-base region (3) has a protruding structure. - The base region (4) has a recessed structure, the protruding structure is embedded in the recessed structure, and the bottom of the recessed structure is located below the cathode metal layer (8).

2. The gate-commutated thyristor chip according to claim 1, characterized in that, The N + The launch region (1) is partially embedded with P + Within the short base region (2), the embedding depth is 0-30 μm.

3. The gate-commutated thyristor chip according to claim 1, characterized in that, The N + The doping concentration of the emitter region (1) is 1E16cm. -3 -1E22cm -3 The diffusion depth is 5μm-40μm.

4. The gate-commutated thyristor chip according to claim 1, characterized in that, The P + The doping concentration of the short base region (2) is 1E15cm. -3 -5E18cm -3 The diffusion depth is 20μm-80μm.

5. The gate-commutated thyristor chip according to claim 1, characterized in that, The doping concentration of the P-base region (3) is 1E13cm. -3 -2E16cm -3 Its diffusion depth is 60μm-200μm.

6. The gate-commutated thyristor chip according to claim 1, characterized in that, The doping concentration of the P-type anode emitter region (5) is 1E13cm. -3 -2E16cm -3 The diffusion depth is 60μm-200μm.

7. The gate-commutated thyristor chip according to claim 1, characterized in that, The doping concentration of the N′ buffer layer (7) is 1E12cm. -3 -1E17cm -3 The diffusion depth is 10μm-100μm.

8. The gate-commutated thyristor chip according to claim 1, characterized in that, The P + The doping concentration of the anode emitter region (6) is 1E15cm. -3 -5E18cm -3 The diffusion depth is 0.5μm-80μm.

9. A thyristor, characterized in that, Includes the gate-commutated thyristor chip as described in any one of claims 1-8.

10. The thyristor according to claim 9, characterized in that, It includes the gate-commutated thyristor chip and the fast recovery diode chip, which are connected in anti-parallel through an NPN isolation structure to form a thyristor.

Images