Charge pump circuit related to overvoltage

Abstract

A charge pump circuit is provided, comprising: a first charge pump having an input terminal for receiving a supply voltage and configured to boost the received supply voltage to provide a first charge pump voltage at an output terminal of the first charge pump; a second charge pump having an input terminal coupled to the output terminal of the first charge pump to receive the first charge pump voltage and configured to boost the received first charge pump voltage to provide a second charge pump voltage at an output terminal of the second charge pump; and a voltage drop sensing arrangement configured to detect a drop in the first charge pump voltage and to deactivate a second transistor of a bypass cell associated with a disabled charge pump stage when the drop in the first charge pump voltage is detected.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Italian patent application No. 102022000012356, filed with the Italian Intellectual Property Office on June 10, 2022, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The various embodiments generally relate to the field of electronics, and more specifically, to charge pump circuits. Background Technology

[0004] A charge pump is an electronic circuit configured to convert an input DC power supply voltage into an output DC voltage that is higher than the input power supply voltage (e.g., several times the input power supply voltage) by using a capacitor as an energy storage element, so as to be used as a DC-DC voltage boost converter.

[0005] Typically, charge pumps are used in circuit systems that require an operating voltage that is higher (in absolute terms) than the power supply voltage of the circuit system itself.

[0006] For example, electronic non-volatile memory devices such as EEPROM (Electrically Erasable Programmable Read-Only Memory), especially flash memory devices, require one or more charge pumps to operate correctly.

[0007] US 8,339,185 discloses a multi-stage charge pump configured to dynamically select the number of active stages. This is accomplished by a master charge pump section having multiple stages and a slave charge pump section designed identically to the master section, wherein the number of active stages in the master charge pump section is settable. The master section drives an external load, while the slave section drives an adjustable internal load. The adjustable internal load is set by control logic by comparing the operations of the two sections. The control logic then operates the slave section with a different number of active stages than the master section to determine whether the master section is using the optimal number of active stages. The control logic can then change the number of active stages accordingly.

[0008] US 10,033,271 discloses a multi-stage charge pump comprising first, second, and third charge pump stages connected in series. Each of the first, second, and third charge pump stages includes a first type of charge pump circuit that amplifies the input signal of its respective charge pump circuit by up to a given amount. The multi-stage charge pump also includes a level shifter that oscillates a level clock signal between the voltage of the output signal of the third charge pump stage and one of an offset voltage and ground. The multi-stage charge pump further includes a second type of charge pump circuit that amplifies the voltage of the output of the third charge pump stage by up to another amount and provides an output, the other amount being set by the level shifter. Moreover, the multi-stage charge pump includes a third type of charge pump circuit.

[0009] US 8,659,860 discloses a power converter including transient voltage protection circuitry connected between the input of the power converter and the power stage of the power converter. The transient voltage protection circuitry provides a low-resistance connection from the input of the power converter to the power stage of the power converter when the input voltage is below a predetermined threshold voltage, but blocks the input voltage from the power stage when the input voltage is equal to or greater than the predetermined threshold voltage. The power converter may be a boost power converter used in a vehicle to provide power from the vehicle's main power bus to vehicle subsystems, such as an anti-lock braking system. Summary of the Invention

[0010] In an embodiment, the charge pump circuit includes a first charge pump and a second charge pump. The first charge pump may include an input terminal configured to receive a power supply voltage and boost the received power supply voltage to provide a first charge pump voltage at the output terminal of the first charge pump. The second charge pump may include an input terminal coupled to the output terminal of the first charge pump to receive the first charge pump voltage and boost the received first charge pump voltage to provide a second charge pump voltage at the output terminal of the second charge pump. The second charge pump includes a sequence of charge pump stages connected in series between the input and output terminals of the second charge pump. Each charge pump stage may be selectively enabled to boost the input stage voltage at the stage input terminal to a voltage corresponding to the power supply voltage, to provide a corresponding output stage voltage at the stage output terminal when the charge pump stage is enabled. Each charge pump stage may be selectively disabled to bring its corresponding stage output terminal into a high-impedance state and associate it with a corresponding bypass unit including a first transistor configured to electrically connect the stage output terminal to the output terminal of the first charge pump when the charge pump stage is disabled. The bypass unit further includes a second transistor connected in parallel to the first transistor and may be activated when the charge pump stage is disabled. The charge pump circuit further includes a voltage drop sensing device configured to detect a drop in the first charge pump voltage and, when a drop in the first charge pump voltage is detected, to disable a second transistor of a bypass unit associated with the disabled charge pump stage. Attached Figure Description

[0011] Referring to the accompanying drawings, certain features of the disclosed technology are illustrated in various embodiments.

[0012] Figure 1A A flash memory device including two charge pumps is shown.

[0013] Figure 1B A flash memory device including a charge pump circuit is shown, which includes two charge pumps, the input of which is connected to the output of the other charge pump.

[0014] Figure 2A and Figure 2B A charge pump circuit according to an embodiment is shown.

[0015] Figure 3A and Figure 3B A charge pump circuit according to an embodiment is shown.

[0016] Figure 3C It shows the relationship with Figure 3A and Figure 3B An example of the voltage evolution over time in a charge pump circuit of a related embodiment.

[0017] Figure 4A A charge pump circuit according to an embodiment is shown.

[0018] Figure 4B It shows the relationship with Figure 4A An example of the voltage evolution over time in a charge pump circuit of a related embodiment. Detailed Implementation

[0019] Charge pumps can manage voltages of considerable magnitude, such as several times the supply voltage. To achieve this, the circuitry of a typical charge pump is designed so that during normal operation, the voltage difference across its transistors is only a fraction of these large voltages.

[0020] However, in some cases, a sudden drop in voltage at some nodes of the charge pump can occur due to, for example, a sudden large current demand from the load. This can be dangerous because these sudden voltage drops can cause the charge pump transistors to experience voltage differences higher than the maximum voltage difference they are designed to withstand without causing breakdown. This can happen, for example, when one terminal of a transistor included in a stage of the charge pump experiences a large voltage drop, while another terminal of the same transistor remains at a higher voltage, for example, due to connection to the plate of a large boost capacitor that is still charging.

[0021] In view of the above, various embodiments can provide a charge pump circuit designed to effectively prevent or mitigate overvoltage problems.

[0022] According to various embodiments, the efficiency of the second charge pump can be improved without causing overvoltage problems due to a sudden and significant drop in the voltage of the first charge pump.

[0023] In fact, in the embodiments, the charge pump efficiency is advantageously improved by providing a second transistor in parallel with the first transistor in its bypass unit and arranging the second transistor to eliminate the voltage drop caused by the voltage threshold of the first transistor in each bypass unit. At the same time, potential overvoltage problems caused by a sudden and large drop in the voltage of the first charge pump, which may propagate through the second transistor at the input terminal of the charge pump stage, can be advantageously prevented or mitigated by the proper and selective deactivation of the second transistor.

[0024] According to an embodiment, in each bypass unit, the first transistor has a first on terminal connected to the output terminal of the first charge pump, a second on terminal connected to the stage output terminal of the corresponding charge pump stage, and a control terminal configured to be connected to the output terminal of the first charge pump.

[0025] According to an embodiment, in each bypass unit, the second transistor has a first conducting terminal connected to a first conducting terminal of the first transistor, a second conducting terminal connected to a second conducting terminal of the first transistor, and a control terminal configured to be connected to the output terminal of the second charge pump.

[0026] According to an embodiment, each bypass unit further includes a switch configured to cause a control terminal of the second transistor to: be connected to the output terminal of the second charge pump when the charge pump stage associated with the bypass unit is disabled, thereby activating the second transistor; and be connected to a reference terminal when the charge pump stage associated with the bypass unit is enabled, to deactivate the second transistor.

[0027] According to an embodiment, the voltage drop sensing device is configured to drive a switch of each bypass unit associated with a disabled charge pump stage when a drop in the first charge pump voltage is detected, so that the control terminal of the second transistor is also connected to the reference terminal.

[0028] According to an embodiment, the charge pump circuit further includes a charge pump control unit configured to selectively enable / disable a charge pump stage selected based on a desired value of a second charge pump voltage.

[0029] According to an embodiment, the charge pump control unit is configured to be a selected set of charge pump stages from a sequence of disabled charge pump stages.

[0030] According to an embodiment, the selected set of charge pump stages includes multiple charge pump stages, the number of which is based on an expected value of the second charge pump voltage.

[0031] According to an embodiment, the selected set of charge pump stages includes at least the first in a sequence of charge pump stages.

[0032] According to an embodiment, the first of the charge pump stages in the sequence has a stage input terminal configured to be connected to the output terminal of the first charge pump when the second charge pump is activated.

[0033] According to an embodiment, the selected set of charge pump stages includes multiple adjacent charge pump stages in a sequence of charge pump stages.

[0034] According to an embodiment, each charge pump stage includes a switch and at least one capacitor, which is periodically charged and discharged by the switch under the control of a corresponding control signal: oscillates with a clock signal when the charge pump stage is enabled; and is fixed at a constant value when the charge pump stage is disabled.

[0035] According to an embodiment, the charge pump circuit further includes a bypass unit, the bypass unit including a first transistor configured to electrically connect the output terminal of the first charge pump to the input terminal of the first in a sequence of charge pump stages.

[0036] According to an embodiment, the voltage drop sensing device is configured to detect a drop in the first charge pump output voltage when the first charge pump output voltage drops below a corresponding voltage threshold.

[0037] According to an embodiment, each bypass unit includes another switch configured to connect the control terminal of the first transistor to a first on terminal of the first transistor when the second charge pump is activated, and to a reference terminal to deactivate the first transistor when the second charge pump is deactivated.

[0038] According to an embodiment, each switch is configured to connect the control terminal of the second transistor to the reference terminal when the second charge pump is turned off.

[0039] Various embodiments relate to a non-volatile semiconductor memory device including a charge pump circuit.

[0040] Figure 1A A flash memory device, denoted throughout by reference numeral 100, is shown, comprising a first charge pump CP1 and a second charge pump CP2. The flash memory device 100 is powered by a power supply voltage Vdd, for example, generated by a battery (not shown).

[0041] The charge pump CP1 is configured to receive the power supply voltage Vdd of the flash memory device 100 at the input terminal and generate a corresponding charge pump output voltage Vp1 at the output terminal that is higher than the power supply voltage Vdd.

[0042] Similarly, charge pump CP2 is configured to receive the power supply voltage Vdd of flash memory device 100 at the input terminal and generate a corresponding charge pump output voltage Vp2 at the output terminal that is higher than the power supply voltage Vdd.

[0043] The charge pump CP2 is configured to generate a charge pump voltage Vp2 that is higher than the charge pump output voltage Vp1.

[0044] Charge pump voltages Vp1 and Vp2 are used by the flash memory device 100 during operation and are selectively supplied according to the operation being performed by the flash memory device 100. Figure 1A The different loads identified by L1 and L2 are marked in the attached diagram.

[0045] For example, the charge pump voltage Vp1 can be used as a word line bias voltage to be supplied to the selected word line (not shown) of the flash memory device 100, while the charge pump voltage Vp2 (higher than the charge pump voltage Vp1) can be used to activate a word line switch (not shown) to provide the word line bias voltage to the selected word line. According to this example, the load L1 of charge pump CP1 (i.e., the selected word line) draws a relatively high current from charge pump CP1, while the load L2 of charge pump CP2 (i.e., the selected word line switch) draws a moderate current from charge pump CP2 (lower than the current drawn by charge pump CP1).

[0046] Charge pumps CP1 and CP2 each consist of a sequence of corresponding charge pump stages. Figure 1A (Not shown in the diagram), wherein each charge pump stage includes a switching element and at least one capacitor, which is periodically charged and discharged through the switching element under the control of a clock signal, specifically the clock signal ck1 for the charge pump stage of charge pump CP1 and the clock signal ck2 for the charge pump stage of charge pump CP2. The switching element of the charge pump stage is implemented by a low-voltage MOS transistor. "Low-voltage transistor" herein refers to a transistor manufactured in a manner capable of maintaining a voltage difference below, for example, a predetermined voltage based on the supply voltage Vdd (e.g., a voltage difference below 4 volts) between its terminal pairs. The term "predetermined" as used herein in relation to parameters such as predetermined voltages indicates that the value of the parameter is determined prior to the parameter used in the process or algorithm. In some embodiments, the value of the parameter is determined before the start of the process or algorithm. In other embodiments, the value of the parameter is determined during the process or algorithm but prior to its use in the process or algorithm.

[0047] Each charge pump stage is configured to boost the voltage received at its input terminal by approximately the amount of the supply voltage Vdd by utilizing charge transfer implemented by charging and discharging a capacitor under the control of switching elements via clock signals ck1 and ck2. Specifically, the switching elements of the general-purpose charge pump stage are configured to alternately connect the positive terminal of the charge pump stage capacitor to the input and output terminals of the same charge pump stage according to clock signal oscillation. Furthermore, the switching elements are also configured to connect the negative terminal of the charge pump stage capacitor to the supply voltage Vdd and the ground voltage GND according to clock signal oscillation.

[0048] Based on the reference voltage VREF and the charge pump output voltage Vp1, starting from the master clock signal ck of the flash memory device 100, the clock signal CK1 of the charge pump stage of the charge pump CP1 is generated by the corresponding charge pump control unit CTRL1. The charge pump control unit CTRL1 is configured to appropriately set the clock signal ck1 through a feedback loop according to the received value of the reference voltage Vref, thereby adjusting the value of the charge pump voltage Vp1.

[0049] Similarly, based on the reference voltage VREF and the charge pump output voltage Vp2, the clock signal CK2 of the charge pump stage of the charge pump CP2 is generated via the corresponding charge pump control unit CTRL2, starting from the master clock signal ck of the flash memory device 100. The charge pump control unit CTRL2 is configured to appropriately set the clock signal ck2 via a feedback loop according to the received value of the reference voltage Vref, thereby adjusting the value of the charge pump voltage Vp2.

[0050] Charge pump CP1 comprises N charge pump stages, and charge pump CP2 comprises N' charge pump stages. Since each charge pump stage is configured to boost the voltage received at its input terminal by approximately the value of the supply voltage Vdd, and since charge pump CP2 is configured to generate a charge pump voltage Vp2 that is higher than the charge pump output voltage Vp1, the number of charge pump stages N' of charge pump CP2 is typically greater than the number of charge pump stages N of charge pump CP1.

[0051] Figure 1B Another charge pump circuit is shown, in which the input of charge pump CP2 is connected to the output of charge pump CP1 to receive the charge pump voltage Vp1 (instead of the supply voltage Vdd) generated by charge pump CP1. Because... Figure 1B In the circuit, the input voltage to be boosted by charge pump CP2 (a sequence of charge pump stages) is already higher than the supply voltage Vdd, therefore... Figure 1A Compared to the quantity N', Figure 1B To produce the same charge pump voltage Vp2, the circuit's charge pump CP2 requires a reduced number of M charge pump stages.

[0052] exist Figure 1AIn the circuit, charge pump CP1 includes N charge pump stages to generate charge pump voltage Vp1 starting from the power supply voltage Vdd, and charge pump CP2 includes N' charge pump stages to generate charge pump voltage Vp2 starting from the power supply voltage Vdd. Figure 1A Compared to the circuit, in Figure 1B In the circuit, the same charge pump voltage Vp2 can be generated by a charge pump CP2 with M charge pump stages equal to N-N'.

[0053] Figures 2A to 2B A charge pump circuit according to an embodiment is shown, wherein: the input terminal of charge pump CP2 is connected to the output terminal of charge pump CP1 to receive the charge pump voltage Vp1 (e.g., ...). Figure 1B (as shown in the circuit diagram); and the charge pump stage of charge pump CP2 can be selectively activated / deactivated to optimize the charge pump current efficiency based on the actual value of the charge pump voltage Vp2 to be generated by charge pump CP2.

[0054] Specifically, the charge pump CP2 comprises a sequence of M charge pump stages STG(i) (i = 1 to M), each charge pump stage having an input terminal for receiving a corresponding voltage V(i-1) and an output terminal for providing the corresponding voltage V(i) generated by the charge pump stage STG(i) by boosting the voltage V(i-1) at its input terminal by approximately Vdd (when the charge pump stage STG(i) is enabled). In an embodiment, at least one of the sequence of M charge pump stages STG(i) (i = 1 to M) can be selected as the target charge pump stage. The input terminal of a general charge pump stage STG(i) in the sequence that is different from the first charge pump stage STG(1) is connected to the output terminal of the preceding charge pump stage STG(i-1) in the sequence, such that the voltage V(i-1) provided at the input terminal of the charge pump stage STG(i) is the voltage generated by the preceding charge pump stage STG(i-1). The input terminal of the first charge pump stage STG(1) is changed to be connected to the input terminal of charge pump CP2 (which is in turn connected to the output terminal of charge pump CP1), so that the voltage V(0) received by the first charge pump stage STG(1) corresponds to the charge pump voltage Vp1 generated by charge pump CP1. The output terminal of the last charge pump stage STG(M) corresponds to the output terminal of charge pump CP2, so that the charge pump voltage Vp2 generated by charge pump CP2 corresponds to the voltage V(M) generated by charge pump stage STG(M) and provided at its output terminal.

[0055] Each charge pump stage STG(i) has a clock terminal for receiving a clock signal ck2 from the charge pump control unit CTRL2. Additionally, each charge pump stage STG(i) has an enable terminal for receiving a corresponding enable signal en(i) from the charge pump control unit CTRL2. Each charge pump stage STG(i) can be selectively enabled / disabled based on the value adopted by the corresponding enable signal en(i).

[0056] When the enable signal en(i) is set to an enabled value (e.g., a logic value "1" corresponding to the power supply voltage Vdd), the charge pump stage STG(i) is enabled to boost the voltage V(i-1) received at its input terminal, thereby generating a voltage V(i) at its output terminal corresponding to approximately V(i-1) + Vdd.

[0057] When the enable signal en(i) is set to a disabled value (e.g., a logic value “0” corresponding to the ground voltage GND), the charge pump stage STG(i) is disabled and does not boost the voltage V(i-1) received at its input terminal, and its output terminal becomes a high-impedance state.

[0058] For example, the charge pump stage STG(i) can be configured such that the periodic charging / discharging of at least one capacitor of the charge pump stage STG(i) caused by the oscillation of the clock signal ck2 can be selectively enabled / disabled according to the value of the enable signal en(i).

[0059] For example, the charge pump stage STG(i) can be configured to use a control signal to control the periodic charging / discharging of the capacitor: when the enable signal en(i) is in the enabled value, the control signal oscillates following the received clock signal ck2; and when the enable signal en(i) is in the disabled value, the control signal is fixed at a constant value.

[0060] The enable signal en(i) can be generated by the charge pump control unit CTRL2 based on the enable digital CE provided to the charge pump control unit CTRL2.

[0061] According to an embodiment, the charge pump CP2 includes a corresponding bypass unit SU(i) for each charge pump stage STG(i). The bypass unit SU(i) is configured to selectively connect the output terminal of the corresponding charge pump stage STG(i) to the input terminal of the charge pump CP2 when the charge pump stage STG(i) is disabled. The bypass unit SU(i) is configured to disconnect the output terminal of the corresponding charge pump stage STG(i) from the input terminal of the charge pump CP2 when the charge pump stage STG(i) is enabled.

[0062] according to Figure 2BIn the illustrated embodiment, each bypass unit su(i) includes a high-voltage NMOS transistor SW1(i), which has: a first on (e.g., drain) terminal connected to the input terminal of a charge pump CP2 for receiving a charge pump voltage Vp1 generated by a charge pump CP1; a second on (e.g., source) terminal connected to the output terminal of a corresponding charge pump stage STG(i) that provides voltage V(i); and a gate (e.g., control) terminal that can be coupled to the first on terminal to introduce the transistor SW1(i) into a diode connection circuit.

[0063] "High voltage transistor" in this document refers to a transistor that is manufactured in a manner that enables a voltage difference (e.g., a voltage difference of more than 4 volts) to be maintained between its terminal pairs at a predetermined voltage, such as that according to the power supply voltage Vdd.

[0064] When the charge pump stage STG(i) is enabled, the diode-connected transistor SW1(i) of the corresponding bypass unit SU(i) is reverse biased because its second conducting terminal is at a voltage V(i) higher than the voltage Vp1 at its first conducting terminal. Therefore, the output terminal of the charge pump stage STG(i) is electrically disconnected from the input terminal of the charge pump CP2.

[0065] When the charge pump stage STG(i) is disabled, the diode-connected transistor SW1(i) of the corresponding bypass unit SU(i) is forward biased, and the output terminal of the charge pump stage STG(i) is electrically connected to the input terminal of the charge pump CP2. Therefore, the voltage V(i) at the output terminal of the charge pump stage STG(i) becomes Vp1-Vth1, where Vth1 is the threshold voltage of the transistor SW1(i).

[0066] According to the embodiment, a bypass unit SU(0) identical to other bypass units SU(i) (i>0) is also provided, which is configured to selectively connect the input terminal of charge pump CP2 (which is also the output terminal of charge pump CP1) to the input terminal of the first charge pump stage STG(1) of charge pump CP2.

[0067] According to an embodiment, the charge pump stage STG(i) of charge pump CP2 (via its respective enable signal en(i)) is selectively activated / deactivated based on the value (amplitude) of charge pump voltage Vp2 in the following manner.

[0068] The range of charge pump voltage Vp2 is defined as having a lower limit Vp2(l) that approximately corresponds to the lower limit Vp2(l) of charge pump voltage Vp1 and an upper limit Vp2(u) that is higher than the upper limit Vp1.

[0069] When the charge pump voltage Vp2 required by charge pump CP2 corresponds to the upper limit Vp2(u) of the charge pump voltage range, all enable signals en(i) are set to the enabled value, thereby enabling all charge pump stages STG(i). In this case, the diode-connected transistor SW1(i) of all bypass units SU(i) (i>0) is reverse biased, and the output terminal of charge pump stage STG(i) is disconnected from the input terminal of charge pump CP2. Conversely, the diode-connected transistor SW1(i) of bypass unit SU(i) (i=0) is forward biased, and the voltage V(0) at the input terminal of charge pump stage STG(1) is therefore equal to Vp1-Vth1.

[0070] When the charge pump voltage Vp2 required by charge pump CP2 is lower than the upper limit Vp2(u) of the charge pump voltage range, starting from the first charge pump stage STG(1), as the value of charge pump voltage Vp2 decreases towards the lower limit Vp2(l) of the charge pump voltage range, the sequence of charge pump stages STG(i) gradually advances to the last charge pump stage STG(M), and one or more charge pump stages STG(i) can be disabled. In this case, the diode-connected transistor SW1(i) of the bypass unit SU(i) corresponding to the disabled charge pump stage STG(i) is forward biased, thereby clamping the voltage V(i) at its output terminal at Vp1–Vth1.

[0071] The diode-connected transistor SW1(i) of the bypass unit SU(i) (i=0) is also forward biased, and therefore the voltage V(0) at the input terminal of the charge pump stage STG(1) is equal to Vp1-Vth1.

[0072] In this way, for a disabled charge pump stage, there is no difference between the voltage at the input terminal and the voltage at the output terminal; both are biased to Vp1-Vth1.

[0073] Typically, when the charge pump voltage Vp2 required by charge pump CP2 is between the lower limit Vp2(l) and the upper limit Vp2(u) of the charge pump voltage range: charge pump stages STG(i) (i = K to M) in the sequence of charge pump stages STG(i) are enabled; and charge pump stages STG(i) (i = 1 to K-1) in the sequence of charge pump stages STG(i) are disabled, and the voltage V(i) at its output terminal is clamped to Vp1-Vth1 by the bypass unit SU(i) (if If K = 1, then there are no disabled charge pump stages STG(i)), where K ranges from: a value equal to 1 when the value of the charge pump voltage Vp2 that charge pump CP2 needs to output corresponds to the upper limit Vp2(u) of the charge pump voltage range (enabling all charge pump stages STG(i)); to a value equal to M when the value of the charge pump voltage Vp2 that charge pump CP2 needs to output corresponds to the lower limit Vp2(l) of the charge pump voltage range (enabling only the last charge pump stage STG(M)).

[0074] Similar considerations apply to cases where the highest value of K (corresponding to the lower limit of the charge pump voltage range Vp2(l)) is lower than M (indicating that charge pump stage STG(i) greater than 1 is always enabled).

[0075] In this embodiment, the current efficiency of charge pump CP2 can be optimized by changing the number of enabled charge pump stages STG(i) according to the charge pump voltage Vp2, while clamping the voltage V(i) at the output terminal of the disabled charge pump stages STG(i).

[0076] When charge pump CP2 is turned off, the output terminals of charge pump stage STG(i) discharge during the so-called "charge pump CP2 discharge operation". If the diode-connected transistor SW1(i) of the bypass unit SU(i) corresponding to one or more charge pump stages STG(i) is forward biased, it means that the output terminals of the charge pump stage STG(i) are electrically connected to the input terminals of charge pump CP2, which in turn are connected to the output terminals of charge pump CP1. The discharge of the output terminals of these charge pump stages STG(i) will then cause the output terminals of charge pump CP1 to discharge across the forward biased transistor SW1(i). In other words, during the charge pump CP2 discharge operation, the voltage Vp1 at the output terminal of charge pump CP1 will decrease.

[0077] To avoid this drawback, according to an embodiment, the bypass unit SU(i) (i = 0, 1, ..., M) is configured to turn off the transistor SW1(i) during the discharge operation of the charge pump CP2, so as to disconnect the electrical connection between the input terminal of the charge pump CP2 (and therefore the output terminal of the charge pump CP1) and the output terminal of the charge pump stage STG(i).

[0078] Therefore, according to the embodiment, each bypass unit SU(i) includes a switch S1(i), which is controlled by a corresponding control signal SC1(i) ​​generated by the charge pump control unit CTRL2 and configured to selectively turn off the transistor SW1(i) during the discharge operation of the charge pump CP2.

[0079] The switch S1(i) has a first conducting terminal connected to the gate terminal of the transistor SW1(i), a second conducting terminal connected to the first conducting terminal (drain) of the transistor SW1(i), and a third conducting terminal connected to the terminal that provides the ground voltage GND.

[0080] The switch S1(i) is configured to electrically connect its first conducting terminal to its second conducting terminal when the control signal SC1(i) ​​is set to a first value indicating that the charge pump CP2 is operating normally (e.g., a logic value "1" corresponding to the power supply voltage Vdd); and to electrically connect its first conducting terminal to its third conducting terminal when the control signal SC1(i) ​​is set to a second value indicating that the charge pump CP2 is discharging (e.g., a logic value "0" corresponding to the ground voltage GND).

[0081] During normal operation of charge pump CP2, control signal SC1(i) ​​is set to a first value, causing switch S1(i) to connect the gate terminal of transistor SW1(i) to the first conducting terminal of transistor SW1(i), thereby allowing operation of transistor SW1(i) in the diode connection circuit described above.

[0082] In an embodiment, during the discharge operation of charge pump CP2, control signal SC1(i) ​​is set to a second value, causing transistor SW1(i) to be turned off, thereby advantageously avoiding undesirable discharge at the output terminals of charge pump CP1 across transistor SW1(i).

[0083] In the embodiments, due to including Figure 2B The circuit of switch S1(i) shown means that, during the discharge operation of charge pump CP2, the voltage Vp1 at the output terminal of charge pump CP1 is advantageously unaffected by the voltage drop of voltage V(i).

[0084] From the above description, it should be clear that for Figure 2A and Figure 2B In the embodiments of this disclosure described herein, the voltage at the input terminal of the first enable stage STG(i) of charge pump CP2 is always Vp1-Vth. In the embodiments, this voltage level is important and should be maximized because it is the base level used to generate the charge pump voltage VP2 output by charge pump CP2 by capacitor pumping in each stage STG(i).

[0085] In this embodiment, to improve the efficiency of charge pump CP2, the voltage at the input terminal of the first enable stage STG(i) of charge pump CP2 should be as close as possible to Vp1. Furthermore, if the transistor SW(i) in the bypass unit SU(i) is not a triple-well transistor, its threshold voltage Vth may be very high (~1V or above) due to the body effect of transistor SW(i), thus causing the voltage level at the input terminal of the first enable stage STG(i) of charge pump CP2 to be much lower than Vp1.

[0086] Therefore, in the embodiment, the level of the charge pump voltage Vp2 output by the charge pump CP2 may be lower than expected, and thus the number of charge pump stages STG(i) of the charge pump CP2 needs to be increased to match the maximum output voltage requirement of the charge pump CP2, thereby reducing the overall power efficiency of the charge pump.

[0087] This feature can be achieved through Figure 3A and Figure 3B Another embodiment described herein is used to avoid or at least mitigate this.

[0088] exist Figures 2A to 2B The voltage V(i) at the output terminal of the disabled charge pump stage STG(i) and the voltage V(0) at the input terminal of the charge pump stage STG(0) are changed to Vp1-Vth1 by the forward bias diode of the corresponding bypass unit SU(i) connected to the transistor SW1(i), and are related to... Figures 2A to 2B Compared to the charge pump circuit, in Figures 3A to 3B In the charge pump circuit, the voltage V(i) at the output terminal of the disabled charge pump stage STG(i) and the voltage V(0) at the input terminal of the charge pump stage STG(0) become Vp1. In this way, in the embodiment, the efficiency of charge pump CP2 can be improved by eliminating the voltage loss Vth1 of each charge pump stage STG(i).

[0089] Therefore, each bypass unit SU(i) is modified to include another transistor SW2(i), which has: a first conducting terminal (drain) connected to the first conducting terminal of transistor SW1(i); a second conducting terminal (source) connected to the second conducting terminal of transistor SW1(i); and a gate (e.g., control) terminal, which can be selectively connected to the output terminal of charge pump CP2 for receiving charge pump voltage Vp2 if charge pump stage STG(i) is disabled during normal operation of charge pump CP2; and connected to the terminal for providing ground voltage GND if charge pump stage STG(i) is enabled during normal operation of charge pump CP2 and during discharge operation of charge pump CP2.

[0090] For this purpose, each bypass unit SU(i) includes a switch S2(i) controlled by a respective control signal SC2(i) generated by the charge pump control unit CTRL2, and includes a first on terminal connected to the gate terminal of the transistor SW2(i), a second on terminal connected to the output terminal of the charge pump CP2 for receiving the charge pump voltage VP2, and a third on terminal connected to the terminal providing the ground voltage GND.

[0091] The switch S2(i) is configured to electrically connect its first conducting terminal to its second conducting terminal when the control signal SC2(i) is set to a first value (e.g., a logic value "1" corresponding to the power supply voltage Vdd); and to electrically connect its first conducting terminal to its third conducting terminal when the control signal SC2(i) is set to a second value (e.g., a logic value "0" corresponding to the ground voltage GND).

[0092] During normal operation of charge pump CP2, the control signal SC1(i) ​​of all bypass units (i) is set to the first value, such that each transistor SW1(i) is in diode configuration.

[0093] Furthermore, during normal operation of charge pump CP2, the control signal SC2(i) of each bypass unit corresponding to the activated charge pump stage STG(i) is set to a second value, causing the corresponding transistor SW2(i) to be turned off and the corresponding (diode-connected) transistor SW1(i) to be turned on and reverse-biased. In this way, the voltage V(i) at the output terminal of charge pump stage STG(i) is boosted by charge pump stage STG(i) to V(i-1) + Vdd (as shown in the image). Figures 2A to 2B (As shown).

[0094] Furthermore, during normal operation of charge pump CP2, the control signal SC2(i) of each bypass unit corresponding to the disabled charge pump stage STG(i) is set to its first value. Therefore, because during normal operation of charge pump CP2, the charge pump voltage Vp2 is higher than the charge pump voltage Vp1 plus the threshold voltage Vth2 of transistor SW2(i), the corresponding transistor SW2(i) is turned on. In this way, the voltage V(i) at the output terminal of charge pump stage STG(i) becomes Vp1 (instead of Vp1-Vth1, as...). Figures 2A to 2B (as shown in the circuit diagram), and transistor SW1(i) is turned off.

[0095] Furthermore, the control signal SC2(0) of the bypass unit SU1(0) is always on during the normal operation of the charge pump CP2, causing the voltage V1(0) at the input terminal of the charge pump stage STG1(1) to also become Vp1 (instead of Vp1-Vth1, as shown below). Figures 2A to 2B(as shown in the circuit diagram), and transistor SW1(0) is turned off.

[0096] Therefore, according to Figure 3A and Figure 3B In the disclosed embodiment, the voltage level at the input terminal of the first enabled charge pump stage STG(i) of charge pump CP2 is higher than that of the input stage STG(i). Figure 2A and Figure 2B In one of the related embodiments, the voltage level is Vp1 (instead of Vp1-Vth). Therefore, in the embodiment, since the charge pump CP2 can be designed to have the minimum number of stages required to meet the output value requirements, the charge pump CP2 can be optimized in terms of power efficiency.

[0097] During the discharge operation of charge pump CP2, the control signal SC1(i) ​​of all bypass units (i) is set to the second value, so that each transistor SW1(i) is in the off state.

[0098] In addition, during the discharge operation of charge pump CP2, the control signal SC2(i) of all bypass units (i) is also set to the second value, so that each transistor SW2(i) is in the off state.

[0099] In the embodiment, since all internal nodes of charge pump CP2 (i.e., the input and output terminals of its charge pump stage STG(i)) are disconnected from charge pump CP1 during charge pump CP2 discharge operation, charge pump CP2 can be discharged without affecting charge pump CP1 (i.e., charge pump CP1 can be discharged without discharging).

[0100] It should also be noted that the charge pump CP2 behaves differently in cases where the output suddenly drops due to a change in load L2. When this occurs (during normal operation of charge pump CP2), the output voltage Vp2 of charge pump CP2 may drop below the charge pump voltage Vp1 plus the threshold voltage Vth2 of transistor SW2(i). Therefore, transistor SW2(i) of the disabled charge pump stage STG(i) may turn off. However, the diode-connected transistor SW1(i) of the disabled charge pump stage STG(i) turns on and becomes forward biased. In this case, charge is supplied to the input terminal of the first enabled charge pump stage STG(i) of CP2. In this way, the voltage at the output terminal of the disabled charge pump stage STG(i) becomes Vp1 - Vth1.

[0101] Figures 3A to 3BThe charge pump circuit is affected by overvoltage problems. When the charge pump voltage Vp1 drops suddenly and significantly, for example due to a sudden large change in the load L1, the overvoltage problem may cause the first enabled charge pump stage STG(i) component in the sequence of charge pump stages STG(i) of charge pump CP2 to break down.

[0102] Specifically, by referring to the general case, where: charge pump stage STG(i) (i = 1 to K) in the sequence of charge pump stage STG(i) is disabled; and charge pump stage STG(i) (i = K+1 to M) in the sequence of charge pump stage STG(i) is enabled.

[0103] Figure 3C An example is shown illustrating the evolution of the voltage V(K) at the output terminal of the last disabled charge pump stage STG(K) and the voltage V(K+1) at the output terminal of the first enabled charge pump stage STG(K+1) over time before, during, and after the sudden drop in the charge pump voltage Vp1. Figure 3C In the diagram, the X-axis represents time in seconds, and the Y-axis represents voltage level.

[0104] If you have already referred Figure 3B As described, the control signals SC1(K) and SC2(K) of the bypass unit SU(K) of the disabled charge pump stage STG(K) are both set to the first value (logic "1"), causing the corresponding transistor SW2(K) to turn on because the charge pump voltage Vp2 is higher than the charge pump voltage Vp1 plus the threshold voltage Vth2 of the transistor SW2(K). In this way, the voltage V(K) at the output terminal of the charge pump stage STG(K) becomes Vp1, and the transistor SW1(K) turns off.

[0105] Furthermore, the control signal SC1(K+1) of the bypass unit SU(K+1) of the activated charge pump stage STG(K+1) is set to a first value (logic "1"), and the control signal SC2(K+1) of the bypass unit SU(K+1) is set to a second value (logic "0"), causing the corresponding transistor SW2(K+1) to turn off, and the corresponding (diode-connected) transistor SW1(K+1) to be in diode configuration. In this way, the voltage V(K+1) at the output terminal of the charge pump stage STG(K+1) is boosted to V(K) + Vdd by the charge pump stage STG(K).

[0106] At time t1 (see Figure 3CAt this point, the charge pump voltage Vp1 at the output terminal of charge pump CP1 suddenly drops. Since the output terminal of charge pump stage STG(K) is connected to the output terminal of charge pump CP1 through the (activated) transistor SW2(K) of bypass unit SU(K), the voltage V(K) at the output terminal of charge pump stage STG(K) drops along with the charge pump voltage Vp1.

[0107] Since the charge pump stage STG(K+1) is enabled, at time t1, the internal capacitors of the charge pump stage STG(K+1) are still being charged (charged to a value Vdd corresponding to a multiple of the voltage). Therefore, although the voltage V(K) at the output terminal of the disabled charge pump stage STG(K) decreases following the charge pump voltage Vp1, the voltage V(K+1) at the output terminal of the charge pump stage STG(K+1) does not decrease immediately because the capacitors of this stage require a certain amount of time to discharge. Therefore, the difference between the voltage V(K) at the input terminal of the charge pump stage STG(K+1) and the voltage V(K+1) at the output terminal of the charge pump stage STG(K+1) increases accordingly.

[0108] If the charge pump voltage VP1 drops too much (overvoltage condition), the voltage difference experienced by the transistor in the charge pump stage STG(K+1) may exceed the maximum voltage difference that the transistor can maintain, and the transistor may break down. The fact that the transistors in the charge pump stage STG(K+1) are low-voltage transistors exacerbates this defect, and therefore they are able to maintain a relatively low voltage difference.

[0109] It should be noted that although conventional charge pumps prevent overvoltage caused by voltage drops at the output terminals of their charge pump stage through corresponding protection diodes, these protection diodes cannot be used to prevent overvoltage caused by voltage drops at the input terminals of the charge pump stage (such as the voltage drop at the input terminal of the charge pump stage STG(K+1)) because these protection diodes limit the boost efficiency of the charge pump stage.

[0110] It is also important to emphasize that the overvoltage problem described above, caused by a voltage drop at the input terminal of the activated charge pump stage, can only occur when the charge pump stage is a charge pump that receives a voltage that may suddenly drop at its input terminal, such as charge pump CP2, whose input terminal receives the charge pump voltage Vp1 generated by charge pump CP1. Conventional charge pumps, which receive the power supply voltage Vdd at their input terminals, are not affected by this overvoltage problem.

[0111] According to an embodiment, the overvoltage problem caused by the drop in charge pump voltage Vp1 is overcome by temporarily shutting down the transistor SW2(i) of the bypass unit SU(i) of the disabled charge pump stage STG(i) (i = 0 to K) when a sufficiently large drop in charge pump voltage Vp1 is detected, thereby interrupting the direct electrical connection between the output terminal of the disabled charge pump stage STG(i) and the output terminal of the charge pump CP1.

[0112] In this way, the voltage V(K) at the output terminal of the last disabled charge pump stage STG(K) no longer changes to the charge pump voltage Vp1 due to transistor SW2(K). Therefore, transistors SW1(K) and SW2(K) of the bypass unit SU(K) of the last disabled charge pump stage STG(K) are suddenly turned off after the charge pump voltage Vp1 drops. Since charge pump CP2 is supplying current to load L2, the voltage V(i) at the output terminal of charge pump stage STG(i) (I = K to M) will decrease, meaning the voltage V(K) at the input terminal of the first enabled stage STG(K+1) of charge pump CP2 will be floating. Once the voltage V(K) drops below the level of Vp1-Vth, transistor SW1(K) turns on, thus starting to supply current to the first enabled charge pump stage STG(K+1). In this way, the voltage V(i) at the output terminal of the charge pump stage STG(i) (i = K to M) increases toward its steady level (i.e., the steady level used during normal operation of charge pump CP2 without significant disturbances). Based on the above description, it should be understood that during this transient period, charge pump CP1 also recovers from the drop in charge pump voltage Vp1 by readjusting the charge pump voltage Vp1 level back to its steady level.

[0113] Therefore, according to Figure 4A The embodiment shown provides a charge pump voltage drop sensing device 400, which is configured to detect when the charge pump voltage Vp1 at the output terminal of charge pump CP1 (and therefore the input terminal of charge pump CP2) drops to a voltage threshold Vp1TH (e.g., corresponding to 90% of the expected value of charge pump voltage Vp1).

[0114] exist Figure 4A In the illustrated embodiment, the charge pump voltage drop sensing device 400 includes a comparator 410 having: a non-inverting input terminal configured to receive a reference voltage Vref; an inverting input terminal connected to the center tap of a voltage divider 420 for receiving a voltage divider voltage Vdiv based on the charge pump voltage Vp1; and an output terminal for providing a corresponding detection signal PD to the charge pump control unit CTRL2.

[0115] exist Figure 4AIn the illustrated embodiment, the voltage divider 420 includes: a first resistor R1 connected between the terminal providing the ground voltage GND and the inverting input terminal of the comparator 410; and a second resistor R2 connected between the inverting input terminal of the comparator 410 and the output terminal of the charge pump CP1 for receiving the charge pump voltage Vp1.

[0116] According to the embodiment, the resistance values ​​of resistors R1 and R2 are set in such a way that when the charge pump voltage Vp1 is equal to the voltage threshold Vp1TH, the voltage divider voltage Vdiv is equal to Vref.

[0117] In this way, as long as the charge pump voltage Vp1 is higher than the voltage threshold Vp1TH, the detection signal PD remains at a low value. When the charge pump voltage Vp1 drops below the voltage threshold Vp1TH, the detection signal PD switches to a high value.

[0118] According to an embodiment, the charge pump control unit CTRL2 is configured to: when the detection signal PD is high, set the control signal SC2(i) of the bypass unit SU(i) corresponding to the disabled charge pump stage STG(i) (i = 1 to K) to a second value ("logo 0") to turn off the corresponding transistor SW2(i); and when the detection signal PD is low, set the control signal SC2(i) back to the first value ("logo 1") to turn on the corresponding transistor SW2(i) again.

[0119] In this way, in an embodiment, when a sufficiently large decrease in charge pump voltage Vp1 is detected, the direct electrical connection between the output terminal of the disabled charge pump stage STG(i) (i = 1 to K) and the output terminal of charge pump CP1 is prevented or weakened, thereby preventing or weakening the transistor of the first enabled charge pump stage STG(K+1) from experiencing a large voltage difference.

[0120] In particular, by reference Figure 4B An example scenario is shown, illustrating the period during a decrease in charge pump voltage Vp1 according to an embodiment. Figure 4A An example of how the signal and voltage at the circuit nodes of a charge pump circuit evolve over time. Figure 4B In the diagram, the X-axis represents time in seconds, and the Y-axis represents voltage levels.

[0121] As in Figure 3C As in the example considered, the charge pump stage STG(i) (i = 1 to K) of charge pump CP2 is disabled, while the subsequent charge pump stages STG(i) (i = K+1 to M) of charge pump CP2 with charge pump stages STG(i) (i = 1 to K) are enabled.

[0122] The initial configuration specifies that the control signals SC1(K) and SC2(K) of the bypass unit SU(K) of the last disabled charge pump stage STG(K) are both set to the first value (logic "1"), causing the corresponding transistor SW2(K) to turn on because the charge pump voltage Vp2 is higher than the charge pump voltage Vp1 plus the threshold voltage Vth2 of transistor SW2(K). In this way, the voltage V(K) at the output terminal of the charge pump stage STG(K) becomes Vp1, and transistor SW1(K) turns off. Furthermore, the control signal SC1(K+1) of the bypass unit SU(K+1) of the first enabled charge pump stage STG(K+1) is set to the first value (logic "1"), and the control signal SC2(K+1) of the bypass unit SU(K+1) is set to the second value (logic "0"), causing the corresponding transistor SW2(K+1) to turn off, and the corresponding (diode-connected) transistor SW1(K+1) to be in diode configuration. In this way, the voltage V(K+1) at the output terminal of the charge pump stage STG(K+1) is boosted to V(K)+Vdd through the charge pump stage STG(K).

[0123] In addition, the initial configuration specifies that the charge pump voltage Vp1 generated by the charge pump CP1 is higher than the voltage threshold Vp1TH, so the detection signal PD is low.

[0124] At time t1, the charge pump voltage Vp1 at the output terminal of charge pump CP1 suddenly drops. Since the output terminal of charge pump stage STG(K) is connected to the output terminal of charge pump CP1 through the (activated) transistor SW2(K) of bypass unit SU(K), the voltage V(K) at the output terminal of charge pump stage STG(K) follows the drop of charge pump voltage Vp1.

[0125] At time t2, the charge pump voltage Vp1 drops below the voltage threshold Vp1TH, so the detection signal PD switches from the second value to the first value. Therefore, the control signal SC2(i) of the bypass unit SU(i) corresponding to the disabled charge pump stage STG(i) (i = 1 to K) is switched to the second value to turn off the corresponding transistor SW2(i). In this way, the voltage V(i) at the output terminal of the charge pump stage STG(i) (i = 1 to K) no longer follows the charge pump voltage VP1, but instead floats in a high-impedance state. Specifically, starting from time t2, the output terminal of the last disabled charge pump stage STG(K) (which is also the input terminal of the first enabled charge pump stage STG(K+1)) becomes floating, and the voltage V(K) at the input terminal of the first enabled charge pump stage STG(K+1) no longer directly follows the decrease of the charge pump voltage VP1.

[0126] Since the charge pump stages STG(i) (i = K+1 to M) of charge pump CP2 are enabled and operate to deliver current to load L2, but the input terminal of the first enabled charge pump stage STG(K+1) is floating (i.e., not receiving new charge), the voltage V(K) will decrease following the charging requests of the subsequent charge pump stages STG(i) (i = K+1 to M). The voltage V(i+1) of each of the subsequent charge pump stages STG(i+1) (i = K to M-1) will decrease accordingly, approximately equal to V(i) + Vdd. For example, as... Figure 4B As shown, the voltage V(K+1) decreases as the voltage V(K) decreases, with a difference of approximately Vdd.

[0127] The voltage V(i) (i = K to M) continues to decrease until the voltage V(K) drops below Vp1 - Vth1 (where Vth1 is the threshold voltage of the transistor SW(K) of the bypass unit SU(K). Figure 4B In the example shown, this event occurs at time t3. At this time, transistor SW1(K) turns on, connecting the input terminal of the first enabled charge pump stage STG(K+1) to the output terminal of charge pump CP1 (transistor SW1(K) is diode-connected and forward-biased). In this case, once the charge pump voltage Vp1 begins to recover from its drop (at... Figure 4B In the example shown, the charge pump voltage Vp1 has already begun to recover from its decline before time t3, and the voltage V(K) begins to increase toward its steady value. Therefore, each of the voltages V(i+1) in the subsequent charge pump stages STG(i+1) (i = K to M-1) will correspondingly begin to increase, approximately equal to V(i) + Vdd.

[0128] When the charge pump voltage Vp1 exceeds the voltage threshold Vp1TH (at time t4), the detection signal PD switches from the first value back to the second value. Therefore, the control signal SC2(i) of the bypass unit SU(i) corresponding to the disabled charge pump stage STG(i) (i = 1 to K) is switched to the first value to turn on the corresponding transistor SW2(i). At this time, voltage V(K) begins to directly follow the rise of the charge pump voltage Vp1 until Vp1 stabilizes at its stable level, while other voltages V(i) (i = K+1 to M) increase towards their stable levels.

[0129] In this embodiment, since the transistor SW2(K) of the bypass unit SU(K) of the last disabled charge pump stage STG(K) is temporarily deactivated, the direct electrical connection between the output terminal of the disabled charge pump stage STG(i) and the output terminal of the charge pump CP1 is advantageously prevented or weakened as long as the charge pump voltage Vp1 experiences a significant drop. This prevents or weakens the transistors of the first enabled charge pump stage STG(K+1) from experiencing excessive voltage differences and avoids these transistors from being broken down.

[0130] Naturally, those skilled in the art can apply numerous logical and / or physical modifications and alterations to the above embodiments to meet local and specific requirements. More specifically, while various embodiments have been described with particular emphasis, it should be understood that various omissions, substitutions, and changes in form and detail, as well as in other embodiments, are possible. In particular, different embodiments may even be implemented without the specific details set forth in the foregoing detailed embodiments for providing a more thorough understanding thereof; instead, well-known features may have been omitted or simplified to avoid unnecessary detail from hindering the description. Furthermore, specific elements and / or method steps explicitly described in connection with any disclosed embodiment of the invention may be incorporated into other embodiments.

[0131] For example, although in the above embodiment, the bypass unit SU(i) is provided with a switch S1(i) configured to selectively turn off the transistor SW1(i) during the discharge operation of the charge pump CP2 in order to avoid an undesirable drop in the charge pump voltage Vp1 caused by the discharge of the internal node of the charge pump CP2 during the discharge operation of the charge pump CP2, the concept can also be applied without providing the switch S1(i).

Claims

1. A charge pump circuit, comprising: A first charge pump includes an input terminal for receiving a power supply voltage, and the first charge pump boosts the received power supply voltage to provide a first charge pump voltage at the output terminal of the first charge pump. as well as A second charge pump includes an input terminal connected to the output terminal of the first charge pump and receiving the voltage from the first charge pump. The second charge pump boosts the received first charge pump voltage to provide a second charge pump voltage at its output terminal. The second charge pump includes a sequence of charge pump stages connected in series between the input and output terminals of the second charge pump. Each charge pump stage is selectively activated to boost the input stage voltage at the stage input terminal to a voltage corresponding to the power supply voltage, so as to provide a corresponding output stage voltage at the stage output terminal when the charge pump stage is activated. Each charge pump stage is selectively disabled to make its corresponding stage output terminal a high-impedance state and associated with a corresponding bypass unit including a first transistor, which electrically connects the stage output terminal to the output terminal of the first charge pump when the charge pump stage is disabled. The bypass unit further includes a second transistor connected in parallel to the first transistor and activated when the charge pump stage is disabled. The charge pump circuit further includes a voltage drop sensing device that detects a drop in the first charge pump voltage and, when a drop in the first charge pump voltage is detected, disables a second transistor of a bypass unit associated with the disabled charge pump stage.

2. The charge pump circuit according to claim 1, wherein, In each bypass unit: The first transistor has a first conducting terminal connected to the output terminal of the first charge pump, a second conducting terminal connected to the stage output terminal of the corresponding charge pump stage, and a control terminal connected to the output terminal of the first charge pump. The second transistor has a first conducting terminal connected to a first conducting terminal of the first transistor, a second conducting terminal connected to a second conducting terminal of the first transistor, and a control terminal connected to the output terminal of the second charge pump.

3. The charge pump circuit according to claim 2, wherein, Each bypass unit further includes a switch that, when the charge pump stage associated with the bypass unit is disabled, connects the control terminal of the second transistor to the output terminal of the second charge pump to activate the second transistor, or when the charge pump stage associated with the bypass unit is enabled, connects the control terminal of the second transistor to a reference terminal to deactivate the second transistor.

4. The charge pump circuit according to claim 3, wherein, When a drop in the voltage of the first charge pump is detected, the voltage drop sensing device drives the switch of each bypass unit associated with the disabled charge pump stage to connect the control terminal of the second transistor to the reference terminal.

5. The charge pump circuit according to claim 3, wherein, When the second charge pump is turned off, the switch of each bypass unit connects the control terminal of the second transistor to the reference terminal.

6. The charge pump circuit of claim 1, further comprising a charge pump control unit that selectively enables or disables a target charge pump stage selected based on a predetermined value of the second charge pump voltage in a sequence of charge pump stages.

7. The charge pump circuit according to claim 6, wherein, The charge pump control unit disables the target charge pump stage, and the number of the target charge pump stages is determined based on the predetermined value.

8. The charge pump circuit according to claim 7, wherein, The target charge pump stage includes at least the first in a sequence of charge pump stages, the first in the sequence of charge pump stages including a stage input terminal, which is connected to the output terminal of the first charge pump when the second charge pump is activated.

9. The charge pump circuit according to claim 1, wherein, Each charge pump stage includes a switch and at least one capacitor, which is periodically charged and discharged through the switch under the control of a corresponding control signal, which oscillates with a clock signal when the charge pump stage is enabled and is fixed to a constant value when the charge pump stage is disabled.

10. The charge pump circuit of claim 8, further comprising a bypass unit, the bypass unit including a first transistor that electrically connects the output terminal of the first charge pump to the input terminal of the first in the sequence of charge pump stages.

11. The charge pump circuit according to claim 1, wherein, When the voltage of the first charge pump drops below a corresponding voltage threshold, the voltage drop sensing device detects the drop in the voltage of the first charge pump.

12. The charge pump circuit according to claim 2, wherein, Each bypass unit includes a switch that connects the control terminal of the first transistor to a first on terminal of the first transistor when the second charge pump is activated, or connects the control terminal of the first transistor to a reference terminal to deactivate the first transistor when the second charge pump is turned off.

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