Low-jitter all-digital phase-locked loop for SDH equipment from clock and design method

Abstract

A low-jitter all-digital phase-locked loop applied to an SDH device from a clock, comprising: a first pulse generator for adjusting the pulse width of a reference clock signal to be consistent with a crystal oscillator signal, and outputting a reference clock pulse signal; a filter phase detector for comparing the reference clock pulse signal with a feedback clock pulse signal, detecting a phase difference and performing a preset process to convert the phase difference signal into an output leading or lag control signal; a fractional frequency digital controlled oscillator for adjusting the output frequency according to the leading or lag control signal, reducing the phase difference between the adjusted reference clock signal and the feedback clock pulse signal, and outputting a first output signal and a second output signal; a second pulse generator for adjusting the pulse width of the second output signal to be consistent with the crystal oscillator signal, and outputting a second output clock pulse signal; and a frequency divider for dividing the second output clock pulse signal to output the feedback clock pulse signal to the filter phase detector.

Description

Technical Field

[0001] This application relates to the field of digital integrated circuit design, specifically to a low-jitter all-digital phase-locked loop and design method for clock feeds in SDH equipment. Background Technology

[0002] Modern communication systems require a high-precision and unified clock reference, a need that has spurred the development of time synchronization systems. Synchronous Digital Hierarchy (SDH) proposes a complete set of hierarchical standard digital transmission structures, forming a synchronous network. SDH is a high-speed, high-capacity optical fiber transmission technology. Its purpose is to standardize optical paths, enabling different products to communicate with each other on the same optical path, thereby improving network flexibility and interoperability. This technology is widely used in the field of optical communication and can support various digital transmission services, such as voice, data, and video.

[0003] SDH equipment slave clocks (SECs) provide SDH equipment with a system clock conforming to the ITU-T (International Telecommunication Union Telecommunication Standardization Sector) G.813 standard, and can also provide three levels of clock signals to external systems. This design allows SDH equipment to adapt to different environments and achieve flexible networking. The All-Digital Phase-Locked Loop (ADPLL) is the core of the SEC, functionally multiplying the input reference source signal to a clock signal that is phase-locked to it at output. The performance of this output signal directly determines whether the system can operate normally; therefore, the design of the ADPLL must especially meet the requirement of low jitter. Summary of the Invention

[0004] This application provides a low-jitter, all-digital phase-locked loop and its design method for use as a clock source in SDH equipment, which can provide high-performance clock sources for SDH equipment.

[0005] In a first aspect, embodiments of this application provide a low-jitter all-digital phase-locked loop (PLL) applied to the clock of an SDH device, comprising:

[0006] The first pulse generator is used to adjust the pulse width of the reference clock signal to match the crystal oscillator signal and output the reference clock pulse signal.

[0007] A filtered phase detector is used to compare the phase of the reference clock pulse signal and the feedback clock pulse signal, detect the phase difference, and perform preset processing to convert the phase difference signal into an output leading or lagging control signal.

[0008] A fractional frequency divider type numerically controlled oscillator is used to reduce the phase difference between the reference clock pulse signal and the feedback clock pulse signal by adjusting the output frequency according to the leading or lagging control signal, and output a first output signal and a second output signal.

[0009] The second pulse generator is used to adjust the pulse width of the second output signal to match the crystal oscillator signal and output the second output clock pulse signal.

[0010] A frequency divider is used to divide the second output clock pulse signal and output a feedback clock pulse signal to the filtered phase detector.

[0011] In some embodiments, the first pulse generator is configured to:

[0012] Obtain the crystal oscillator signal period;

[0013] The pulse width of the reference clock signal is adjusted to be the same as the period of the crystal oscillator signal to generate the reference clock pulse signal;

[0014] Output a reference clock pulse signal to a filtered phase detector.

[0015] In some embodiments, the filtered phase detector is used for:

[0016] Receive reference clock pulse signal;

[0017] Obtain the number of crystal pulses between the falling edge of the reference clock pulse signal and the rising edge of the feedback clock pulse signal;

[0018] The number of crystal oscillator pulses is compared with the number of crystal oscillator pulses within half a cycle of the reference clock pulse signal;

[0019] When the number of crystal oscillator pulses is greater than or equal to the number of crystal oscillator pulses in half a cycle of the reference clock pulse signal, an advance control signal is output.

[0020] When the number of crystal oscillator pulses is less than the number of crystal oscillator pulses in half a cycle of the reference clock pulse signal, a hysteresis control signal is output.

[0021] The lead control signal or the lag control signal is output to the fractional frequency division type numerically controlled oscillator.

[0022] In some embodiments, the fractional frequency-division digitally controlled oscillator is used for:

[0023] Receive leading or lagging control signals;

[0024] When the received signal is a lead control signal, the counter in the fractional frequency divider CNC oscillator decreases, the output signal frequency decreases, the phase difference between the feedback clock pulse signal and the reference clock pulse signal decreases, and the first output signal and the second output signal are output.

[0025] When the received signal is a hysteresis control signal, the counter in the fractional frequency divider CNC oscillator increases its count value, increases the output signal frequency, decreases the phase difference between the feedback clock pulse signal and the reference clock pulse signal, and outputs the first output signal and the second output signal.

[0026] The second output signal is output to the second pulse generator.

[0027] In some embodiments, the second pulse generator is used to:

[0028] Receive the second output signal to obtain the crystal oscillator signal period;

[0029] The pulse width of the second output signal is adjusted to be the same as the period of the crystal oscillator signal to generate the second output clock pulse signal;

[0030] Output the second output clock pulse signal to the frequency divider.

[0031] In some embodiments, the frequency divider is used for:

[0032] Receive the second output clock pulse signal;

[0033] Set the feedback clock pulse signal to low level at the rising edge of the crystal oscillator signal;

[0034] When the rising edge count of the second output clock pulse signal reaches a preset value, a high level is retained as a feedback clock pulse signal;

[0035] The feedback clock pulse signal is output to the filtered phase detector.

[0036] Secondly, embodiments of this application provide a low-jitter all-digital phase-locked loop design method for SDH equipment slave clocks, including:

[0037] The pulse width of the reference clock pulse signal is adjusted to match the crystal oscillator signal by the first pulse generator, and the reference clock pulse signal is output to the filter phase detector.

[0038] The reference clock pulse signal and the feedback clock pulse signal are compared by a filtered phase detector. The phase difference is detected and preset processing is performed to convert the phase difference signal into an output leading or lagging control signal. The output leading or lagging control signal is then output to a fractional frequency division numerically controlled oscillator.

[0039] By using a fractional frequency divider type numerically controlled oscillator, the output frequency is adjusted according to the leading or lagging control signal to reduce the phase difference between the reference clock pulse signal and the feedback clock pulse signal, and a first output signal and a second output signal are output. The second output signal is then output to the second pulse generator.

[0040] The second pulse generator is used to adjust the pulse width of the second output signal to match the crystal oscillator signal, and outputs the second output clock pulse signal to the frequency divider.

[0041] The second output clock pulse signal is divided by a frequency divider to output a feedback clock pulse signal. The feedback clock pulse signal is then output to a filtered phase detector, which detects the phase difference. When the loop reaches a stable state, the output signal locks with the reference signal.

[0042] In some embodiments, adjusting the pulse width of the reference clock pulse signal to match the crystal oscillator signal via a first pulse generator and outputting the reference clock pulse signal to a filtered phase detector includes:

[0043] Obtain the crystal oscillator signal period;

[0044] Adjust the pulse width of the reference clock signal to be the same as the period of the crystal oscillator signal;

[0045] Output a reference clock pulse signal to a filtered phase detector.

[0046] In some embodiments, the step of comparing the phase of the reference clock pulse signal and the feedback clock pulse signal using a filtered phase detector, detecting the phase difference, performing preset processing to convert the phase difference signal into an output leading or lagging control signal, and outputting the output leading or lagging control signal to a fractional-frequency-division numerically controlled oscillator includes:

[0047] Receive reference clock pulse signal;

[0048] Obtain the number of crystal pulses between the falling edge of the reference clock pulse signal and the rising edge of the feedback clock pulse signal;

[0049] The number of crystal oscillator pulses is compared with the number of crystal oscillator pulses within half a cycle of the reference clock pulse signal;

[0050] When the number of crystal oscillator pulses is greater than or equal to the number of crystal oscillator pulses in half a cycle of the reference clock pulse signal, an advance control signal is output.

[0051] When the number of crystal oscillator pulses is less than the number of crystal oscillator pulses in half a cycle of the reference clock pulse signal, a hysteresis control signal is output.

[0052] The lead control signal or the lag control signal is output to the fractional frequency division type numerically controlled oscillator.

[0053] In some embodiments, the step of adjusting the output frequency of a fractional-frequency-division digitally controlled oscillator according to the leading or lagging control signal to reduce the phase difference between the adjusted reference clock signal and the feedback clock pulse signal, and outputting a first output signal and a second output signal, and outputting the second output signal to a second pulse generator, includes:

[0054] Receive leading or lagging control signals;

[0055] When the received signal is a lead control signal, the counter in the fractional frequency divider CNC oscillator decreases, the output signal frequency decreases, the phase difference between the feedback clock pulse signal and the reference clock pulse signal decreases, and the first output signal and the second output signal are output.

[0056] When the received signal is a hysteresis control signal, the counter in the fractional frequency divider CNC oscillator increases its count value, increases the output signal frequency, decreases the phase difference between the feedback clock pulse signal and the reference clock pulse signal, and outputs the first output signal and the second output signal.

[0057] The second output signal is output to the second pulse generator.

[0058] This application utilizes a low-jitter, fully digital phase-locked loop (PLL) for slave clocks in SDH equipment, comprising: a first pulse generator for adjusting the pulse width of a reference clock signal to match the crystal oscillator signal, outputting a reference clock pulse signal; a filtered phase detector for comparing the phase of the reference clock pulse signal with a feedback clock pulse signal, detecting the phase difference, and performing preset processing to convert the phase difference signal into a leading or lagging control signal; a fractional-frequency-controlled oscillator for reducing the phase difference between the reference clock pulse signal and the feedback clock pulse signal by adjusting the output frequency according to the leading or lagging control signal, and outputting a first output signal and a second output signal; a second pulse generator for adjusting the pulse width of the second output signal to match the crystal oscillator signal, outputting a second output clock pulse signal; and a frequency divider for dividing the second output clock pulse signal and outputting a feedback clock pulse signal to the filtered phase detector. This results in an output clock signal jitter significantly lower than the standard specified in ITU-T G.813 for slave clock modules in SDH equipment, exhibiting low jitter and a high harmonic rejection ratio. This application also has the advantages of being fully integrated, low power consumption, simple structure, and suitable for multi-channel interface circuits. Attached Figure Description

[0059] Figure 1 This is a schematic diagram of a low-jitter all-digital phase-locked loop (PLL) applied to the clock of an SDH device, as described in this application.

[0060] Figure 2 This is a schematic diagram of the architecture of the low-jitter all-digital phase-locked loop in this application;

[0061] Figure 3 This is a schematic diagram illustrating the application of the filtered phase detector in this application;

[0062] Figure 4 This is a schematic diagram of the phase detection timing of the low-jitter all-digital phase-locked loop in this application;

[0063] Figure 5 This is a flowchart illustrating a low-jitter all-digital phase-locked loop design method for SDH equipment's slave clock, as described in this application.

[0064] Figure 6 The output signal and its jitter magnitude of the low-jitter all-digital phase-locked loop in this application are shown in the test waveform diagram.

[0065] Figure 7 This is the output signal spectrum of the low-jitter all-digital phase-locked loop in this application. Detailed Implementation

[0066] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0067] The terms "comprising" and "having," and any variations thereof, in the specification, claims, and accompanying drawings of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus. The terms "first," "second," and "third," etc., are used to distinguish different objects, etc., and do not indicate a sequence, nor do they limit "first," "second," and "third" to different types.

[0068] In the description of the embodiments of this application, terms such as "exemplary," "for example," or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplary," "for example," or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary," "for example," or "for instance" is intended to present the relevant concepts in a concrete manner.

[0069] In the description of the embodiments of this application, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The "and / or" in the text is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of this application, "multiple" means two or more.

[0070] In some processes described in the embodiments of this application, multiple operations or steps are included in a specific order. However, it should be understood that these operations or steps may not be executed in the order they appear in the embodiments of this application, or they may be executed in parallel. The sequence number of the operation is only used to distinguish different operations, and the sequence number itself does not represent any execution order. In addition, these processes may include more or fewer operations, and these operations or steps may be executed sequentially or in parallel, and these operations or steps may be combined.

[0071] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0072] Firstly, referring to Figure 1 , Figure 1 This is a schematic diagram of a low-jitter all-digital phase-locked loop (PLL) applied to the clock of an SDH device, as described in this application. Figure 1 As shown, a low-jitter all-digital phase-locked loop (PLL) for use in SDH equipment with a clock source includes:

[0073] The first pulse generator is used to adjust the pulse width of the reference clock signal to match the crystal oscillator signal and output the reference clock pulse signal.

[0074] A filtered phase detector is used to compare the phase of the reference clock pulse signal and the feedback clock pulse signal, detect the phase difference, and perform preset processing to convert the phase difference signal into an output leading or lagging control signal.

[0075] A fractional frequency divider type numerically controlled oscillator is used to reduce the phase difference between the reference clock pulse signal and the feedback clock pulse signal by adjusting the output frequency according to the leading or lagging control signal, and output a first output signal and a second output signal.

[0076] The second pulse generator is used to adjust the pulse width of the second output signal to match the crystal oscillator signal and output the second output clock pulse signal.

[0077] A frequency divider is used to divide the second output clock pulse signal and output a feedback clock pulse signal to the filtered phase detector.

[0078] In this embodiment, a low-jitter all-digital phase-locked loop (PLL) applied to the slave clock of an SDH device includes: a first pulse generator, which adjusts the pulse width of a reference clock signal to match the crystal oscillator signal and outputs a reference clock pulse signal; a filtered phase detector, which compares the phase of the reference clock pulse signal with the feedback clock pulse signal, detects the phase difference, and performs preset processing to convert the phase difference signal into a leading or lagging control signal; a fractional-frequency-division digitally controlled oscillator, which reduces the phase difference between the reference clock pulse signal and the feedback clock pulse signal by adjusting the output frequency according to the leading or lagging control signal, and outputs a first output signal and a second output signal; a second pulse generator, which adjusts the pulse width of the second output signal to match the crystal oscillator signal and outputs a second output clock pulse signal; and a frequency divider, which divides the second output clock pulse signal and outputs a feedback clock pulse signal to the filtered phase detector. This results in a clock signal jitter significantly lower than the standard specified in ITU-T G.813 for slave clock modules in SDH devices, exhibiting low jitter and a high harmonic rejection ratio.

[0079] See Figure 2 , Figure 2 This is a schematic diagram of the architecture of the low-jitter all-digital phase-locked loop in this application, where 1-first pulse generator, 2-filtered phase detector, 3-fractional frequency divider digitally controlled oscillator, 4-second pulse generator, and 5-frequency divider.

[0080] The first pulse generator is an ultra-low duty cycle pulse generator, which generates a signal with a duty cycle of 0.0122%, and is used for:

[0081] Obtain the crystal oscillator signal period;

[0082] Adjust the pulse width of the reference clock pulse signal to be the same as the period of the crystal oscillator signal;

[0083] The adjusted reference clock pulse signal is output to the filtered phase detector.

[0084] It is worth noting that in some embodiments, the crystal oscillator signal f TCXO The operating clock signal for each module is provided at a frequency of 65.536MHz with a period of 15.26ns; the SDH equipment receives a reference clock signal f with a 50% duty cycle from the clock front-end module to provide the ADPLL. CLK The frequency is 8kHz; f CLK After processing by an ultra-low duty cycle pulse generator, an 8kHz reference clock pulse signal f with a pulse width of only 15.26ns is generated. REF Therefore, it exhibits an extremely low duty cycle of 0.0122%.

[0085] See Figure 3 , Figure 3 This is a schematic diagram of the application of the filtered phase detector in this application. The filtered phase detector receives a reference clock pulse signal.

[0086] Obtain the number of crystal pulses between the falling edge of the reference clock pulse signal and the rising edge of the feedback clock pulse signal;

[0087] The number of crystal oscillator pulses is compared with the number of crystal oscillator pulses within half a cycle of the reference clock pulse signal;

[0088] When the number of crystal oscillator pulses is greater than or equal to the number of crystal oscillator pulses in half a cycle of the reference clock pulse signal, an advance control signal is output.

[0089] When the number of crystal oscillator pulses is less than the number of crystal oscillator pulses in half a cycle of the reference clock pulse signal, a hysteresis control signal is output.

[0090] The lead control signal or the lag control signal is output to the fractional frequency division type numerically controlled oscillator.

[0091] Among them, see Figure 4 , Figure 4 This is a schematic diagram of the phase detection timing of the low-jitter all-digital phase-locked loop in this application. The 8kHz reference signal contains N = 4096 crystal oscillator signal cycles of 65.536MHz within half a period. If this count value is greater than N = 4096, it is determined to be f. FB ahead of f REF Output a lead control signal; if the count value is less than N = 4096, then it is determined to be f. FB Lagging behind f REF Output a delayed control signal.

[0092] The fractional frequency-division digitally controlled oscillator is used for:

[0093] Receive leading or lagging control signals;

[0094] When the received signal is a lead control signal, the counter in the fractional frequency divider CNC oscillator decreases its count value, which reduces the output signal frequency, reduces the phase difference between the feedback signal and the reference signal, and outputs the first output signal and the second output signal.

[0095] When the received signal is a hysteresis control signal, the counter in the fractional frequency divider CNC oscillator increases its count value, increases the frequency of the output signal, decreases the phase difference between the feedback signal and the reference signal, and outputs the first output signal and the second output signal.

[0096] The second output signal is output to the second pulse generator.

[0097] In this embodiment, the fractional-frequency-division CNC oscillator can respond to a 65.536MHz enable signal to oscillate at 9.72MHz and output a 9.72MHz clock signal. Structurally, the fractional-frequency-division CNC oscillator uses a counter to perform frequency division, with the weighting factor being the fractional division coefficient, approximately 6.74. The fractional-frequency-division CNC oscillator adjusts the actual output frequency according to the obtained control signal value: when it is a lead control signal, the counter increment of the fractional-frequency-division CNC oscillator decreases by (4096-N) of the value, causing the next high-level output to be delayed, which manifests as a decrease in the output signal frequency, reducing f. FB with f REF The phase difference; when the control signal is delayed, the counter value of the fractional frequency divider CNC oscillator increases by the value corresponding to N, causing the next high level to be output earlier, which manifests as an increase in the output signal frequency and a decrease in f. FB with f REF The phase difference. It is worth noting that, in this embodiment, when the fractional frequency divider CNC oscillator adjusts the output frequency, the frequency change value is proportional to the phase difference count during phase detection. This innovative algorithm greatly reduces the jitter of the ADPLL.

[0098] The second pulse generator is a low duty cycle pulse generator. The second output signal is generated into a 9.72MHz pulse signal with a pulse width of 15.26ns by the low duty cycle pulse generator, which has a low duty cycle of 14.8%. The specific steps are as follows:

[0099] Receive the second output signal to obtain the crystal oscillator signal period;

[0100] The pulse width of the second output signal is adjusted to be the same as the period of the crystal oscillator signal to generate the second output clock pulse signal;

[0101] Output the second output clock pulse signal to the frequency divider.

[0102] The frequency divider is an ultra-low duty cycle frequency divider. The second output clock pulse signal is divided by 1215 by the ultra-low duty cycle frequency divider to generate an 8kHz pulse signal with a pulse width of 15.26ns, which has an ultra-low duty cycle of 0.0122%.

[0103] The specific steps are as follows:

[0104] Receive the second output clock pulse signal;

[0105] Set the feedback clock pulse signal to low level at the rising edge of the crystal oscillator signal;

[0106] When the rising edge count of the second output clock pulse signal reaches a preset value, a high level is retained as a feedback clock pulse signal;

[0107] The feedback clock pulse signal is output to the filtered phase detector.

[0108] Secondly, see Figure 5 , Figure 5 This is a flowchart illustrating a low-jitter all-digital phase-locked loop (PLL) design method for a slave clock in SDH equipment, as described in this application. The low-jitter all-digital PLL design method for a slave clock in SDH equipment includes:

[0109] S1. The pulse width of the reference clock signal is adjusted to match the crystal oscillator signal by the first pulse generator, and the reference clock pulse signal is output to the filtered phase detector;

[0110] S2. The reference clock pulse signal and the feedback clock pulse signal are compared by a filtered phase detector to detect the phase difference and perform preset processing to convert the phase difference signal into an output leading or lagging control signal, and the output leading or lagging control signal is output to a fractional frequency division numerical control oscillator.

[0111] S3. Using a fractional frequency divider type numerically controlled oscillator, the output frequency is adjusted according to the leading or lagging control signal to reduce the phase difference between the reference clock pulse signal and the feedback clock pulse signal, and a first output signal and a second output signal are output, and the second output signal is output to the second pulse generator;

[0112] S4. The second pulse generator is used to adjust the pulse width of the second output signal to match the crystal oscillator signal, and output the second output clock pulse signal to the frequency divider.

[0113] S5. The second output clock pulse signal is divided by a frequency divider to output a feedback clock pulse signal. The feedback clock pulse signal is output to a filtered phase detector. The phase difference is detected by the filtered phase detector. When the loop reaches a stable state, the output signal is locked with the reference signal.

[0114] In some embodiments, adjusting the pulse width of the reference clock signal to match the crystal oscillator signal via a first pulse generator and outputting the reference clock pulse signal to a filtered phase detector includes:

[0115] Obtain the crystal oscillator signal period;

[0116] The pulse width of the reference clock signal is adjusted to be the same as the period of the crystal oscillator signal to generate the reference clock pulse signal;

[0117] Output a reference clock pulse signal to a filtered phase detector.

[0118] In some embodiments, the step of comparing the phase of the reference clock pulse signal and the feedback clock pulse signal using a filtered phase detector, detecting the phase difference, performing preset processing to convert the phase difference signal into an output leading or lagging control signal, and outputting the output leading or lagging control signal to a fractional-frequency-division numerically controlled oscillator includes:

[0119] Receive reference clock pulse signal;

[0120] Obtain the number of crystal pulses between the falling edge of the reference clock pulse signal and the rising edge of the feedback clock pulse signal;

[0121] The number of crystal oscillator pulses is compared with the number of crystal oscillator pulses within half a cycle of the reference clock pulse signal;

[0122] When the number of crystal oscillator pulses is greater than or equal to the number of crystal oscillator pulses in half a cycle of the reference clock pulse signal, an advance control signal is output.

[0123] When the number of crystal oscillator pulses is less than the number of crystal oscillator pulses in half a cycle of the reference clock pulse signal, a hysteresis control signal is output.

[0124] The lead control signal or the lag control signal is output to the fractional frequency division type numerically controlled oscillator.

[0125] In some embodiments, the step of adjusting the output frequency of a fractional-frequency-division digitally controlled oscillator to reduce the phase difference between the reference clock pulse signal and the feedback clock pulse signal according to the leading or lagging control signal, and outputting a first output signal and a second output signal, and outputting the second output signal to a second pulse generator, includes:

[0126] Receive leading or lagging control signals;

[0127] When the received signal is a lead control signal, the counter in the fractional frequency divider CNC oscillator decreases, the output signal frequency decreases, the phase difference between the feedback clock pulse signal and the reference clock pulse signal decreases, and the first output signal and the second output signal are output.

[0128] When the received signal is a hysteresis control signal, the counter in the fractional frequency divider CNC oscillator increases its count value, increases the output signal frequency, decreases the phase difference between the feedback clock pulse signal and the reference clock pulse signal, and outputs the first output signal and the second output signal.

[0129] The second output signal is output to the second pulse generator.

[0130] The following shows the test results of loading the low-jitter ADPLL disclosed in this application onto the FPGA platform, and further illustrates this embodiment.

[0131] See Figure 6 As shown, after the low-jitter ADPLL of this embodiment of the invention is loaded onto the PYNQ-Z2 FPGA, the test waveform shows that the jitter of the 9.72MHz output signal is only 1.6ns, about 0.015UI, which is far lower than the 0.50UI specified by ITU-T G.813.

[0132] Figure 7 The spectrum of the output signal, measured by a spectrum analyzer, is shown. The center frequency is 9.72 MHz, the signal power is 1.02 dBm, and the spurious signals are distributed at 9.56 MHz and 9.88 MHz, with signal powers of -43.28 dBm and -46.33 dBm, respectively. Clearly, the ADPLL of this invention, in addition to low jitter, also has the advantage of a high harmonic rejection ratio.

[0133] In summary, this embodiment provides a low-jitter all-digital phase-locked loop (PLL) for use in SDH equipment's slave clock. It can lock the output signal to the reference signal while ensuring the input signal frequency does not exceed the pulling range. The output signal exhibits significant low jitter, conforming to the ITU-T G.813 standard, and also boasts a high harmonic rejection ratio. The low-jitter all-digital PLL proposed in this invention offers advantages such as simple structure, strong practicality, good versatility, and suitability for multi-channel interface circuits, making it a promising candidate for widespread application in large-scale integrated circuits.

[0134] It should be noted that the sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0135] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A low-jitter all-digital phase-locked loop for use with clocks in SDH equipment, characterized in that, The low-jitter all-digital phase-locked loop applied to the clock of SDH equipment includes: The first pulse generator is used to adjust the pulse width of the reference clock signal to match the crystal oscillator signal and output the reference clock pulse signal. A filtered phase detector is used to compare the phase of the reference clock pulse signal and the feedback clock pulse signal, detect the phase difference, and perform preset processing to convert the phase difference signal into an output leading or lagging control signal. A fractional frequency divider type numerically controlled oscillator is used to reduce the phase difference between the reference clock pulse signal and the feedback clock pulse signal by adjusting the output frequency according to the leading or lagging control signal, and output a first output signal and a second output signal. The second pulse generator is used to adjust the pulse width of the second output signal to match the crystal oscillator signal and output the second output clock pulse signal. A frequency divider is used to divide the second output clock pulse signal and output a feedback clock pulse signal to the filtered phase detector.

2. The low-jitter all-digital phase-locked loop for SDH equipment slave clock as described in claim 1, characterized in that, The first pulse generator is used for: Obtain the crystal oscillator signal period; The pulse width of the reference clock signal is adjusted to be the same as the period of the crystal oscillator signal to generate the reference clock pulse signal; Output a reference clock pulse signal to a filtered phase detector.

3. The low-jitter all-digital phase-locked loop for SDH equipment slave clock as described in claim 1, characterized in that, The filtered phase detector is used for: Receive reference clock pulse signal; Obtain the number of crystal pulses between the falling edge of the reference clock pulse signal and the rising edge of the feedback clock pulse signal; The number of crystal oscillator pulses is compared with the number of crystal oscillator pulses within half a cycle of the reference clock pulse signal; When the number of crystal oscillator pulses is greater than or equal to the number of crystal oscillator pulses in half a cycle of the reference clock pulse signal, an advance control signal is output. When the number of crystal oscillator pulses is less than the number of crystal oscillator pulses in half a cycle of the reference clock pulse signal, a hysteresis control signal is output. The lead control signal or the lag control signal is output to the fractional frequency division type numerically controlled oscillator.

4. The low-jitter all-digital phase-locked loop for SDH equipment slave clock as described in claim 3, characterized in that, The fractional frequency-division digitally controlled oscillator is used for: Receive crystal oscillator signals; Receive leading or lagging control signals; When the received signal is a lead control signal, the counter in the fractional frequency divider CNC oscillator decreases, the output signal frequency decreases, the phase difference between the feedback clock pulse signal and the reference clock pulse signal decreases, and the first output signal and the second output signal are output. When the received signal is a hysteresis control signal, the counter in the fractional frequency divider CNC oscillator increases its count value, increases the output signal frequency, decreases the phase difference between the feedback clock pulse signal and the reference clock pulse signal, and outputs the first output signal and the second output signal. The second output signal is output to the second pulse generator.

5. A low-jitter all-digital phase-locked loop for use in SDH equipment's slave clock, as described in claim 4, is characterized in that... The second pulse generator is used for: Receive the second output signal to obtain the crystal oscillator signal period; The pulse width of the second output signal is adjusted to be the same as the period of the crystal oscillator signal to generate the second output clock pulse signal; Output the second output clock pulse signal to the frequency divider.

6. A low-jitter all-digital phase-locked loop for use with SDH equipment's slave clock, as described in claim 5, is characterized in that... The frequency divider is used for: Receive the second output clock pulse signal; Set the feedback clock pulse signal to low level at the rising edge of the crystal oscillator signal; When the rising edge count of the second output clock pulse signal reaches a preset value, a high level is retained as a feedback clock pulse signal; The feedback clock pulse signal is output to the filtered phase detector.

7. A method for designing a low-jitter all-digital phase-locked loop (PLL) for use in SDH equipment's slave clock, characterized in that... include: The pulse width of the reference clock pulse signal is adjusted to match the crystal oscillator signal by the first pulse generator, and the reference clock pulse signal is output to the filter phase detector. The reference clock pulse signal and the feedback clock pulse signal are compared by a filtered phase detector. The phase difference is detected and preset processing is performed to convert the phase difference signal into an output leading or lagging control signal. The output leading or lagging control signal is then output to a fractional frequency division numerically controlled oscillator. By using a fractional frequency divider type numerically controlled oscillator, the output frequency is adjusted according to the leading or lagging control signal to reduce the phase difference between the reference clock pulse signal and the feedback clock pulse signal, and a first output signal and a second output signal are output. The second output signal is then output to the second pulse generator. The second pulse generator is used to adjust the pulse width of the second output signal to match the crystal oscillator signal, and outputs the second output clock pulse signal to the frequency divider. The second output clock pulse signal is divided by a frequency divider to output a feedback clock pulse signal. The feedback clock pulse signal is then output to a filtered phase detector, which detects the phase difference. When the loop reaches a stable state, the output signal locks with the reference signal.

8. The low-jitter all-digital phase-locked loop design method for SDH equipment slave clock as described in claim 7, characterized in that, The step of adjusting the pulse width of the reference clock signal to match the crystal oscillator signal through the first pulse generator and outputting the reference clock pulse signal to the filtered phase detector includes: Obtain the crystal oscillator signal period; The pulse width of the reference clock signal is adjusted to be the same as the period of the crystal oscillator signal to generate the reference clock pulse signal; Output a reference clock pulse signal to a filtered phase detector.

9. The low-jitter all-digital phase-locked loop design method for SDH equipment slave clock as described in claim 8, characterized in that, The step of comparing the phase of the reference clock pulse signal and the feedback clock pulse signal using a filtered phase detector, detecting the phase difference, performing preset processing to convert the phase difference signal into an output lead or lag control signal, and outputting the output lead or lag control signal to a fractional frequency divider CNC oscillator includes: Receive reference clock pulse signal; Obtain the number of crystal pulses between the falling edge of the reference clock pulse signal and the rising edge of the feedback clock pulse signal; The number of crystal oscillator pulses is compared with the number of crystal oscillator pulses within half a cycle of the reference clock pulse signal; When the number of crystal oscillator pulses is greater than or equal to the number of crystal oscillator pulses in half a cycle of the reference clock pulse signal, an advance control signal is output. When the number of crystal oscillator pulses is less than the number of crystal oscillator pulses in half a cycle of the reference clock pulse signal, a hysteresis control signal is output. The lead control signal or the lag control signal is output to the fractional frequency division type numerically controlled oscillator.

10. The low-jitter all-digital phase-locked loop design method for SDH equipment slave clock as described in claim 9, characterized in that, The step of using a fractional-frequency-division digitally controlled oscillator to adjust the output frequency according to the leading or lagging control signal to reduce the phase difference between the reference clock pulse signal and the feedback clock pulse signal, and outputting a first output signal and a second output signal, and outputting the second output signal to a second pulse generator, includes: Receive crystal oscillator signals; Receive leading or lagging control signals; When the received signal is a lead control signal, the counter in the fractional frequency divider CNC oscillator decreases, the output signal frequency decreases, the phase difference between the feedback clock pulse signal and the reference clock pulse signal decreases, and the first output signal and the second output signal are output. When the received signal is a hysteresis control signal, the counter in the fractional frequency divider CNC oscillator increases its count value, increases the output signal frequency, decreases the phase difference between the feedback clock pulse signal and the reference clock pulse signal, and outputs the first output signal and the second output signal. The second output signal is output to the second pulse generator.

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