Four-port chip, chip system and data interaction method

Abstract

The application provides a four-port chip, which is powered through a main power port and a main ground port and performs data interaction through a main clock port and a main data port; the four-port chip comprises a clock module, a data input module, a main module and a data output module; the clock module is used for forming a synchronous clock according to an external clock input from the main clock port; the data input module is connected to an output end of the clock module and is used for receiving configuration information input from the main data port and storing under the control of the synchronous clock; the main module is connected to an output end of the data input module and is used for reading the configuration information, performing chip configuration and generating data to be transmitted under the control of a system clock; and the data output module is connected to the output end of the clock module and the output end of the main module and is used for outputting the data to be transmitted in a single end through the main data port under a set frame format according to the synchronous clock.

Description

Technical Field

[0001] This invention relates to the field of image sensor technology, and in particular to a four-port chip, chip system, and data interaction method. Background Technology

[0002] Image sensors are widely used in digital cameras, mobile phones, medical devices, automobiles and other applications to capture and identify optical image information of people or scenes and convert the optical image information into electrical signals.

[0003] Regardless of the application, image sensor chips often need to interact with other chips (such as processor chips) to output pixel signals. During this data interaction, how to quantize and output the pixel signals using a small number of ports is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a four-port chip, a chip system and a data interaction method, so as to realize the single-end output of pixel signals after quantization by a chip with a small number of ports.

[0005] To achieve the above and other related objectives, the present invention provides a four-port chip, powered by a main power port and a main ground port, and for data interaction via a main clock port and a main data port; the four-port chip includes:

[0006] A clock module is used to generate a synchronous clock based on an external clock input from the main clock port;

[0007] The data input module is connected to the output terminal of the clock module and is used to receive and store the configuration information input from the main data port under the control of the synchronization clock.

[0008] The main module is connected to the output of the data input module and is used to read the configuration information and configure the chip, and to generate the data to be transmitted under the control of the system clock.

[0009] The data output module connects the output terminal of the clock module and the output terminal of the main module, and is used to output the data to be transmitted in a set frame format through the main data port according to the synchronization clock.

[0010] Optionally, the clock module is further configured to multiply the synchronous clock to generate a multiplied clock, and the data output module outputs the data to be transmitted under the control of the multiplied clock.

[0011] Optionally, the clock module is implemented using an adjustable frequency multiplier phase-locked loop circuit, wherein the phase-locked loop circuit operates in a phase-locked state.

[0012] Optionally, the main module is also connected to the output of the clock module to form the system clock based on the synchronization clock.

[0013] Optionally, the four-port chip includes an image sensor chip, and the data to be transmitted includes image data in the form of digital signals.

[0014] The present invention also provides a chip system, the chip system comprising:

[0015] The main chip adopts a four-port chip as described in any of the above items;

[0016] The slave chip has a slave clock port and a slave data port, and the slave clock port and the slave data port are connected to the master clock port and the master data port respectively to perform data interaction. It is used to provide the external clock and the configuration information to the master chip, and to receive the data to be transmitted output by the master chip.

[0017] Optionally, the slave chip includes: a clock generation module for generating the external clock and outputting it through the slave clock port; a data generation module for generating the configuration information and outputting it through the slave data port; and a data processing module for receiving the data to be transmitted input from the slave data port.

[0018] Optionally, when the main chip includes an image sensor chip, the slave chip includes a processor chip.

[0019] The present invention also provides a data interaction method for a chip system, the chip system including a master chip and a slave chip, wherein the master clock port and master data port of the master chip are correspondingly connected to the slave clock port and slave data port of the slave chip for data interaction; the data interaction method includes:

[0020] The main chip receives the external clock sent by the slave chip through the main clock port and forms a synchronous clock;

[0021] Under the control of the synchronous clock, the master chip receives configuration information sent by the slave chip through the master data port;

[0022] The main chip is configured according to the configuration information;

[0023] The master chip outputs the data to be transmitted to the slave chip through the master data port based on the set frame format.

[0024] Optionally, the data interaction method further includes: the main chip generating a multiplied clock based on the synchronous clock, and outputting the data to be transmitted under the control of the multiplied clock.

[0025] Optionally, the main chip generates the frequency-doubled clock based on an adjustable frequency-doubled phase-locked loop circuit, wherein the phase-locked loop circuit operates in a phase-locked state.

[0026] Optionally, after the chip sends the external clock, it sends the configuration information after a set time.

[0027] Optionally, after the master chip receives the frame start field sent by the slave chip, the master chip switches from receive mode to send mode, and at this time, the slave chip switches from send mode to receive mode; after the slave chip receives the frame end field sent by the master chip, the slave chip switches from receive mode to send mode, and at this time, the master chip switches from send mode to receive mode.

[0028] Optionally, the frame format setting includes several row fields, and each row field has the same format, including {start of row field, clock synchronization field, data field, clock synchronization field, end of row field}.

[0029] Optionally, the data field includes n bits; the frame start field includes 10n bits; the frame end field includes 10n bits; the line start field includes 3n bits; the line end field includes 3n bits; and the clock synchronization field includes 8n bits, where n is an integer greater than 1.

[0030] Optionally, the frame start field includes 100 bits, which are 10 sets of cyclic {1111100000}; the frame end field includes 100 bits, which are 10 sets of cyclic {0000011111}; the line start field includes 30 bits, which are 3 sets of cyclic {0000000000}; the line end field includes 30 bits, which are 3 sets of cyclic {1111111111}; the clock synchronization field includes 80 bits, which are 8 sets of cyclic {0101010101}; and the data field includes 10 bits.

[0031] As described above, the four-port chip, chip system and data interaction method of the present invention use a four-port chip to quantize the pixel signal and output it at one end using a master-slave handshake mechanism. No more ports are needed, and stable data interaction can be achieved with only a small number of ports (four ports). Attached Figure Description

[0032] Figure 1 The diagram shown is a schematic of the four-port chip of the present invention.

[0033] Figure 2 The diagram shown is a schematic of the chip system of the present invention.

[0034] Figure 3 The flowchart shown is a data interaction method of the present invention.

[0035] Figure 4 This is a schematic diagram showing the format of the frame start field.

[0036] Figure 5 This is a schematic diagram showing the format of the frame end field.

[0037] Figure 6 The image shown is a specific structural example of the four-port chip of the present invention.

[0038] Component designation explanation

[0039] 10 Main Chips

[0040] 11. Clock Module

[0041] 12 Data Input Module

[0042] 13 Main Module

[0043] 14 Data Output Module

[0044] 20 From Chips

[0045] 21 Clock Generation Module

[0046] 22 Data Generation Module

[0047] 23 Data Processing Module Detailed Implementation

[0048] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0049] Please see Figures 1 to 6 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation, the shape, quantity and proportion of each component in the actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0050] Example 1

[0051] like Figure 1As shown, this embodiment provides a four-port chip 10, which is powered by the main power port VDD1 and the main ground port GND1, and performs data interaction through the main clock port SCL1 and the main data port SDA1; the four-port chip 10 includes: a clock module 11, a data input module 12, a main module 13 and a data output module 14.

[0052] The clock module 11 is used to generate a synchronization clock SYN_CLK based on the external clock EXT_CLK input to the master clock port SCL1. Furthermore, the clock module 11 is also used to multiply the synchronization clock SYN_CLK to generate a multiplied clock MUL_CLK.

[0053] In practical applications, the frequency of the synchronization clock SYN_CLK is the same as the frequency of the external clock EXT_CLK, and the frequency of the frequency multiplier clock MUL_CLK is m times the frequency of the synchronization clock SYN_CLK, where m is a positive number greater than 1.

[0054] Specifically, the clock module 11 is implemented using an adjustable frequency multiplier phase-locked loop circuit, wherein the phase-locked loop circuit operates in a phase-locked state.

[0055] In one example, the initial frequency multiplication value of the phase-locked loop (PLL) circuit can be assumed to be 1. At this initial state, the PLL circuit multiplies the external clock EXT_CLK by 1 to generate the synchronization clock SYN_CLK. Later, after chip configuration, the PLL circuit's frequency multiplication value is configured to m. Then, the PLL circuit multiplies the synchronization clock SYN_CLK by m to generate the multiplied clock MUL_CLK. It should be noted that throughout the entire operation, the PLL circuit operates in a phase-locked state, maintaining a constant frequency by keeping the phase difference constant, thereby obtaining a stable clock signal. The clock module can be implemented using any PLL circuit capable of frequency adjustment available in the prior art.

[0056] The data input module 12 is connected to the output terminal of the clock module 11 and is used to receive and store the configuration information input by the main data port SDA1 under the control of the synchronization clock SYN_CLK.

[0057] The main module 13 is connected to the output of the data input module 12, and is used to read the configuration information and configure the chip, as well as generate the data to be transmitted under the control of the system clock SYS_CLK. Furthermore, the main module 13 is also connected to the output of the clock module 11, and is used to generate the system clock SYS_CLK based on the synchronization clock SYN_CLK. In practical applications, the frequency of the system clock SYS_CLK and the frequency of the synchronization clock SYN_CLK can be the same. Of course, they can also be different; the required frequency of the system clock SYS_CLK can be generated based on the synchronization clock SYN_CLK according to actual needs.

[0058] Specifically, the main module 13 includes a clock / control unit and a data unit. The clock / control unit is connected to the output of the clock module 11 and the output of the data input module 12, and is used to generate the system clock SYS_CLK based on the synchronization clock SYN_CLK, and to read the configuration information and perform chip configuration, so as to generate a control signal based on the system clock SYS_CLK after the chip configuration is completed. The data unit is connected to the output of the clock / control unit and is used to generate the data to be transmitted based on the control signal. In another example, the system clock SYS_CLK can be generated based on the clock module 11, and the main module 13 can directly receive the system clock SYS_CLK to generate image data, etc. Of course, the main module 13 can also adopt other conventional modules of the prior art.

[0059] More specifically, when the four-port chip 10 includes an image sensor chip, the data unit includes: a pixel circuit and a quantization circuit; the pixel circuit is connected to the output of the clock / control unit and is used to perform photoelectric conversion according to the control signal to generate a pixel signal; the quantization circuit is connected to the output of the pixel circuit and is used to quantize the pixel signal and generate the data to be transmitted; wherein, the pixel signal is image data in analog signal form, and the data to be transmitted is image data in digital signal form.

[0060] In practical applications, the pixel circuit corresponds to a number of pixels arranged in rows and columns. The pixel circuit includes at least a photodiode, a transmission transistor, a reset transistor, a source follower transistor, and a selection transistor. The anode of the photodiode is grounded, and its cathode is connected to the first terminal of the transmission transistor. The control terminal of the transmission transistor receives a transmission control signal, and its second terminal is connected to a floating diffused active region. The control terminal of the reset transistor receives a reset control signal, its first terminal receives a power supply voltage, and its second terminal is connected to the floating diffused active region. The gate terminal of the source follower transistor is connected to the floating diffused active region, its drain terminal receives a power supply voltage, and its source terminal is connected to the first terminal of the selection transistor. The control terminal of the selection transistor receives a selection control signal, and its second terminal generates a pixel signal.

[0061] The quantization circuit includes a comparator and a counter. The comparator compares the pixel signal and the ramp signal, while the counter starts counting. When the ramp signal is greater than the pixel signal, the output of the comparator flips, and the counter stops counting. The counting result at this time is the digital code value of the quantized pixel signal.

[0062] The data output module 14 is connected to the output terminal of the clock module 11 and the output terminal of the main module 13, and is used to output the data to be transmitted in a set frame format through the main data port SDA1 in a single-ended manner according to the synchronization clock SYN_CLK. Furthermore, the data output module 14 outputs the data to be transmitted under the control of the frequency multiplication clock MUL_CLK.

[0063] Correspondingly, such as Figure 2 As shown, this embodiment also provides a chip system, which includes a master chip 10 and a slave chip 20. The master chip 10 is a four-port chip as described above. The slave chip 20 has a slave clock port SCL2 and a slave data port SDA2, and the slave clock port SCL2 and the slave data port SDA2 are correspondingly connected to the master clock port SCL1 and the master data port SDA1 for data interaction. This allows the slave chip 20 to provide the external clock EXT_CLK and the configuration information to the master chip 10, and to receive the data to be transmitted output by the master chip 10. It should be noted that the slave chip 20 also has a slave power supply port VDD2 and a slave ground port GND2 for powering the slave chip 20.

[0064] Specifically, the slave chip 20 includes a clock generation module 21, a data generation module 22, and a data processing module 23. The clock generation module 21 generates the external clock EXT_CLK and outputs it through the slave clock port SCL2. The data generation module 22 generates the configuration information and outputs it through the slave data port SDA2. The data processing module 23 receives the data to be transmitted input through the slave data port SDA2 for subsequent data processing. In practical applications, the master chip 10 includes an image sensor chip, and the slave chip 20 includes a processor chip.

[0065] Please see Figure 6 As shown, a specific example of the main chip provided in this embodiment is provided, wherein, Figure 6 The diagram shows a partial structure of the example chip. In this example, the main clock port SCL1 receives an external clock signal, which is then received via clock module 11. Clock module 11 includes a connected phase-locked loop (PLL), which can be implemented using existing circuitry. Additionally, in this example, the main module 13 includes a lens, an image array, a row select control circuit, a quantization circuit, a gain control circuit, and an image processing circuit (ISP). The quantization circuit includes a comparator circuit (COMP) and a sample-and-hold circuit (column sample / hold, such as a counter). All of these circuits can be implemented using existing circuitry. Of course, the main module can also include other modules from existing image sensors, designed according to requirements. In this example, the data output module 14 can include a low-votage single signal (LVSS) circuit; the data input module 12 includes a control register bank. Furthermore, in this example, the main data port SDA1 implements data input and output based on the SPI (Serial Peripheral Interface), which can be implemented using a lane.

[0066] Example 2

[0067] like Figure 3 As shown, this embodiment provides a data interaction method for a chip system, which includes steps 1), 2), 3), and 4). The chip system includes a master chip 10 and a slave chip 20. The master clock port SCL1 and master data port SDA1 of the master chip 10 are connected to the slave clock port SCL2 and slave data port SDA2 of the slave chip 20 for data interaction. In practical applications, the chip system described in Embodiment 1 can be used.

[0068] Step 1) The main chip 10 receives the external clock EXT_CLK sent by the slave chip 20 through the main clock port SCL1 and forms a synchronization clock SYN_CLK.

[0069] Step 2) Under the control of the synchronization clock SYN_CLK, the master chip 10 receives the configuration information sent by the slave chip 20 through the master data port SDA1.

[0070] Step 3) The main chip 10 performs chip configuration according to the configuration information.

[0071] Step 4) The main chip 10 outputs the data to be transmitted to the slave chip 20 through the main data port SDA1 based on the set frame format.

[0072] For the main chip 10, after the chip configuration is completed, the main chip 10 also generates a frequency multiplier clock MUL_CLK based on the synchronous clock SYN_CLK, and outputs the data to be transmitted under the control of the frequency multiplier clock MUL_CLK.

[0073] Specifically, the main chip 10 generates the synchronous clock SYN_CLK and the multiplied clock based on an adjustable frequency-multiplying phase-locked loop circuit, wherein the phase-locked loop circuit operates in a phase-locked state. In practical applications, the frequency of the synchronous clock SYN_CLK is the same as the frequency of the external clock EXT_CLK, and the frequency of the multiplied clock MUL_CLK is m times the frequency of the synchronous clock SYN_CLK, where m is a positive number greater than 1.

[0074] In one example, the initial frequency multiplication value of the phase-locked loop (PLL) circuit can be assumed to be 1. At this initial state, the PLL circuit multiplies the external clock EXT_CLK by 1 to generate the synchronization clock SYN_CLK. Later, after chip configuration, the PLL circuit's frequency multiplication value is configured to m. Then, the PLL circuit multiplies the synchronization clock SYN_CLK by m to generate the multiplied clock MUL_CLK. It should be noted that throughout the entire operation, the PLL circuit operates in a phase-locked state, maintaining a constant frequency by keeping the phase difference constant, thus obtaining a stable clock signal.

[0075] The main chip 10 also generates the system clock SYS_CLK based on the synchronization clock SYN_CLK, and generates the data to be transmitted under the control of the system clock SYS_CLK; wherein, the frequency of the system clock SYS_CLK is the same as the frequency of the synchronization clock SYN_CLK.

[0076] For the slave chip 20, after sending the external clock EXT_CLK, it sends the configuration information after a set time. During this set time, the master chip 10 receives the external clock EXT_CLK and forms the synchronization clock SYN_CLK based on the external clock EXT_CLK. By setting the external clock and configuration information to be sent in a time-division manner, the waiting time is placed at the beginning, which is conducive to smooth and stable subsequent operations.

[0077] When the master chip 10 and the slave chip 20 interact with each other, after the master chip 10 receives the start-of-frame field sent by the slave chip 20, the master chip 10 switches from receiving mode to sending mode, and at this time, the slave chip 20 switches from sending mode to receiving mode; after the slave chip 20 receives the end-of-frame field sent by the master chip 10, the slave chip 20 switches from receiving mode to sending mode, and at this time, the master chip 10 switches from sending mode to receiving mode.

[0078] When the master chip 10 sends the data to be transmitted to the slave chip 20 based on the set frame format, the set frame format includes several row fields, and each row field has the same format, including {row start field, clock synchronization field, data field, clock synchronization field, row end field}.

[0079] The data field comprises n bits; the frame start field comprises 10n bits; the frame end field comprises 10n bits; the line start field comprises 3n bits; the line end field comprises 3n bits; and the clock synchronization field comprises 8n bits, where n is an integer greater than 1.

[0080] In this example, n = 10. The frame start field includes 100 bits, which are 10 sets of cyclic {1111100000}; the frame end field includes 100 bits, which are 10 sets of cyclic {0000011111}; the line start field includes 30 bits, which are 3 sets of cyclic {0000000000}; the line end field includes 30 bits, which are 3 sets of cyclic {1111111111}; the clock synchronization field includes 80 bits, which are 8 sets of cyclic {0101010101}; the data field includes 10 bits (e.g., ...). Figure 4 and Figure 5 (As shown).

[0081] In practical applications, after the master chip 10 receives the frame start field sent by the slave chip 20, it begins to send a frame of data to the slave chip 20. This frame of data usually includes several lines of data, where the line start field is a marker that a line begins to be transmitted and the line end field is a marker that a line ends to be transmitted. Each line is transmitted sequentially until the slave chip 20 detects the frame end field, which indicates that the data transmission of this frame has ended.

[0082] In summary, the four-port chip, chip system, and data interaction method of the present invention utilize a four-port chip to quantize pixel signals and output them at one end using a master-slave handshake mechanism. This eliminates the need for additional ports, achieving stable data interaction with only a small number of ports. Therefore, the present invention effectively overcomes the various shortcomings of existing technologies and possesses high industrial application value.

[0083] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A four-port image sensor chip, characterized in that, Power is supplied through the main power port and the main ground port, and data is exchanged through the main clock port and the main data port. The four-port image sensor chip includes: A clock module is used to generate a synchronous clock based on an external clock input from the main clock port, and to multiply the synchronous clock to generate a frequency-multiplied clock; wherein, the clock module is implemented using a phase-locked loop circuit, and the phase-locked loop circuit operates in a phase-locked state; The data input module is connected to the output terminal of the clock module and is used to receive and store the configuration information input from the main data port under the control of the synchronization clock. The main module is connected to the output of the data input module and is used to read the configuration information and configure the chip, and to generate data to be transmitted under the control of the system clock. The data to be transmitted includes image data in the form of digital signals. The data output module connects the output terminal of the clock module and the output terminal of the main module, and is used to output the data to be transmitted in a set frame format through the main data port according to the frequency multiplication clock. The external clock and the configuration information are input in a time-division manner, and the external clock is input first, followed by the configuration information.

2. The four-port image sensor chip according to claim 1, characterized in that, The clock module is implemented using an adjustable frequency multiplication phase-locked loop circuit.

3. The four-port image sensor chip according to claim 1, characterized in that, The main module is also connected to the output of the clock module to form the system clock based on the synchronization clock.

4. A chip system, characterized in that, The chip system includes: The main chip is a four-port image sensor chip as described in any one of claims 1-3; The slave chip has a slave clock port and a slave data port, and the slave clock port and the slave data port are connected to the master clock port and the master data port respectively to perform data interaction. It is used to provide the external clock and the configuration information to the master chip, and to receive the data to be transmitted output by the master chip.

5. The chip system according to claim 4, characterized in that, The slave chip includes: A clock generation module is used to generate the external clock and output it through the clock port. The data generation module is used to generate the configuration information and output it through the data port; The data processing module is used to receive the data to be transmitted input from the data port.

6. The chip system according to claim 4, characterized in that, The slave chip includes a processor chip.

7. A data interaction method for a chip system as described in any one of claims 4-6, characterized in that, The data interaction method includes: The main chip receives the external clock sent by the slave chip through the main clock port and forms a synchronous clock, and multiplies the synchronous clock to generate a multiplied clock. Under the control of the synchronous clock, the master chip receives configuration information sent by the slave chip through the master data port; The main chip is configured according to the configuration information; Under the control of the frequency multiplier clock, the master chip outputs the data to be transmitted to the slave chip through the master data port in a single-ended manner based on the set frame format.

8. The data interaction method for a chip system according to claim 7, characterized in that, The main chip generates the frequency-doubled clock based on an adjustable frequency-doubled phase-locked loop circuit.

9. The data interaction method for a chip system according to claim 7, characterized in that, After the master chip receives the start-of-frame field sent by the slave chip, the master chip switches from receive mode to send mode, and at this time, the slave chip switches from send mode to receive mode; after the slave chip receives the end-of-frame field sent by the master chip, the slave chip switches from receive mode to send mode, and at this time, the master chip switches from send mode to receive mode.

10. The data interaction method for a chip system according to claim 7, characterized in that, The frame format setting includes several row fields, and each row field has the same format, including {start of row field, clock synchronization field, data field, clock synchronization field, end of row field}.

11. The data interaction method for a chip system according to claim 10, characterized in that, The data field includes n bits; the frame start field includes 10n bits; the frame end field includes 10n bits; the line start field includes 3n bits; the line end field includes 3n bits; and the clock synchronization field includes 8n bits, where n is an integer greater than 1.

12. The data interaction method for a chip system according to claim 11, characterized in that, The frame start field comprises 100 bits, consisting of 10 cyclic {1111100000}; the frame end field comprises 100 bits, consisting of 10 cyclic {0000011111}; the line start field comprises 30 bits, consisting of 3 cyclic {0000000000}; the line end field comprises 30 bits, consisting of 3 cyclic {1111111111}; the clock synchronization field comprises 80 bits, consisting of 8 cyclic {0101010101}; and the data field comprises 10 bits.

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