Memory, semiconductor structure and method of forming the same

Abstract

The present disclosure relates to the technical field of semiconductor technology, and discloses a memory, a semiconductor structure and a forming method thereof. The forming method comprises the following steps: providing a substrate, wherein the substrate comprises a plurality of conductive contact plugs arranged in an array and insulating layers separating the conductive contact plugs; forming a plurality of capacitor layers stacked in a direction perpendicular to the substrate on a surface of the substrate, wherein each capacitor layer comprises a plurality of spaced-apart capacitors, and each capacitor is connected to a different conductive contact plug. The forming method can improve the storage capacity of the capacitors and improve the yield of products.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a memory, a semiconductor structure, and a method for forming the same. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is widely used in mobile devices such as smartphones and tablets due to its advantages of small size, high integration, and high transfer speed. Capacitors, as the core component of DRAM, are mainly used to store electrical charge. However, existing capacitors have relatively small storage capacities and, due to limitations in manufacturing processes, have low device yields.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a memory, a semiconductor structure and a method for forming the same, which can improve the storage capacity of capacitors and improve product yield.

[0005] According to one aspect of this disclosure, a method for forming a semiconductor structure is provided, comprising:

[0006] A substrate is provided, the substrate comprising a plurality of conductive contact plugs arranged in an array and an insulating layer separating each of the conductive contact plugs;

[0007] Multiple capacitor layers are formed on the surface of the substrate, stacked in a direction perpendicular to the substrate. Each capacitor layer includes multiple capacitors spaced apart, and each capacitor is connected to a different conductive contact plug.

[0008] In one exemplary embodiment of this disclosure, the formation of multiple capacitor layers stacked along a direction perpendicular to the substrate on the surface of the substrate, each capacitor layer comprising a plurality of spaced capacitors, each capacitor being connected to a different conductive contact plug, includes:

[0009] A first capacitor layer is formed on the surface of the substrate. The first capacitor layer includes a plurality of first capacitors, and each first capacitor is connected to a different conductive contact plug.

[0010] A second capacitor layer is formed on the side of the first capacitor layer away from the substrate. The second capacitor layer includes a plurality of second capacitors, each of which is connected to a different conductive contact plug. The conductive contact plug connected to the second capacitor and the conductive contact plug connected to the first capacitor are different conductive contact plugs.

[0011] In one exemplary embodiment of this disclosure, forming a first capacitor layer on the substrate surface, the first capacitor layer including a plurality of first capacitors, each of the first capacitors being connected to a different conductive contact plug, includes:

[0012] A first stacked film layer is formed on the surface of the substrate;

[0013] A plurality of spaced-apart first capacitor holes are formed within the first stacked film layer, and each first capacitor hole exposes at least one of the conductive contact plugs;

[0014] A first capacitor is formed within the first capacitor hole.

[0015] In an exemplary embodiment of this disclosure, the first stacked film layer includes a first support layer and a first sacrificial layer, the first sacrificial layer being formed on the side of the first support layer facing away from the substrate, and the formation of a first capacitor within the first capacitor aperture includes:

[0016] The lower electrode layer of the first capacitor is formed on the sidewall and bottom of the first capacitor hole;

[0017] Remove the first sacrificial layer;

[0018] A dielectric layer of the first capacitor is formed on the surface of the lower electrode layer of the first capacitor;

[0019] An upper electrode layer of the first capacitor is formed on the surface of the dielectric layer of the first capacitor.

[0020] In one exemplary embodiment of this disclosure, the forming method further includes:

[0021] A first semiconductor layer is formed to cover the first capacitor layer, and the first semiconductor layer fills the gaps in the first capacitor and the gaps between each of the first capacitors.

[0022] In one exemplary embodiment of this disclosure, a second capacitor layer is formed on the side of the first capacitor layer facing away from the substrate. The second capacitor layer includes a plurality of second capacitors, each of which is connected to a different conductive contact plug. The conductive contact plugs connected to the second capacitors and the conductive contact plugs connected to the first capacitors are different conductive contact plugs.

[0023] A through-hole is formed through the first semiconductor layer and the first support layer. The orthographic projection of the through-hole on the substrate does not overlap with the orthographic projection of the first capacitor hole on the substrate, and each through-hole exposes at least one of the conductive contact plugs.

[0024] An insulating material layer is formed on the sidewall of the through hole;

[0025] The through-hole is filled with conductive material to form a conductive pillar, and the insulating material layer is in contact with the sidewall of the conductive pillar.

[0026] A second stacked film layer is formed on the side of the first semiconductor layer and the conductive pillar that is away from the substrate;

[0027] A plurality of spaced-apart second capacitor holes are formed within the second stacked film layer, and each second capacitor hole exposes at least one of the conductive pillars;

[0028] A second capacitor is formed within the second capacitor hole.

[0029] In one exemplary embodiment of this disclosure, the second stacked film layer includes a second support layer and a second sacrificial layer, the second sacrificial layer being formed on the side of the second support layer facing away from the substrate, and the formation of a second capacitor within the second capacitor aperture includes:

[0030] The lower electrode layer of the second capacitor is formed on the sidewall and bottom of the second capacitor hole;

[0031] Remove the second sacrificial layer;

[0032] A dielectric layer of the second capacitor is formed on the surface of the lower electrode layer of the second capacitor;

[0033] An upper electrode layer of the second capacitor is formed on the surface of the dielectric layer of the second capacitor.

[0034] In one exemplary embodiment of this disclosure, the forming method further includes:

[0035] A second semiconductor layer is formed to cover the second capacitor layer. The second semiconductor layer fills the gaps in the second capacitor and the gaps between each of the second capacitors, and the second semiconductor layer is in contact with the first semiconductor layer.

[0036] According to one aspect of this disclosure, a semiconductor structure is provided, comprising:

[0037] The substrate includes a plurality of conductive contact plugs arranged in an array and an insulating layer separating each of the conductive contact plugs;

[0038] A multilayer capacitor layer, wherein each capacitor layer is formed on the surface of the substrate and stacked in a direction perpendicular to the substrate, each capacitor layer includes a plurality of spaced capacitors, and each capacitor is connected to a different conductive contact plug.

[0039] In one exemplary embodiment of this disclosure, the multilayer capacitor layer includes:

[0040] A first capacitor layer is located on the surface of the substrate and includes a plurality of first capacitors, each of which is connected to a different conductive contact plug.

[0041] The second capacitor layer is located on the side of the first capacitor layer away from the substrate. The second capacitor layer includes a plurality of second capacitors, each of which is connected to a different conductive contact plug. The conductive contact plugs connected to the second capacitors and the conductive contact plugs connected to the first capacitors are different conductive contact plugs.

[0042] In one exemplary embodiment of this disclosure, the first capacitor layer includes:

[0043] A plurality of first capacitors are provided, each first capacitor being spaced apart, and each first capacitor being connected to a conductive contact plug.

[0044] In one exemplary embodiment of this disclosure, the first capacitor layer includes a first support layer, the first capacitor includes a lower electrode layer, a dielectric layer and an upper electrode layer, the first support layer covers the outer periphery of the lower electrode layer near the substrate, the dielectric layer is formed on the surface of the lower electrode layer, and the upper electrode layer is formed on the surface of the dielectric layer.

[0045] In one exemplary embodiment of this disclosure, the semiconductor structure further includes:

[0046] A first semiconductor layer covers the first capacitor layer, and the first semiconductor layer fills the gaps within the first capacitor and the gaps between each of the first capacitors.

[0047] In an exemplary embodiment of this disclosure, through-holes are formed in the first semiconductor layer and the first support layer, the orthographic projection of the through-holes on the substrate does not overlap with the orthographic projection of the first capacitor hole on the substrate, and each through-hole exposes at least one of the conductive contact plugs.

[0048] Semiconductor structures also include:

[0049] An insulating material layer is formed on the sidewall of the through hole;

[0050] A conductive post is located inside the through hole, and the insulating material layer is in contact with the sidewall of the conductive post;

[0051] The second capacitor layer includes:

[0052] Multiple second capacitors are located on the side of the first semiconductor layer and the conductive pillars away from the substrate. The second capacitors are spaced apart and each second capacitor is connected to each conductive pillar in a one-to-one correspondence.

[0053] In an exemplary embodiment of this disclosure, the second capacitor layer includes a second support layer, the second capacitor includes a lower electrode layer, a dielectric layer and an upper electrode layer, the second support layer covers the outer periphery of the lower electrode layer of the second capacitor near the substrate, the dielectric layer of the second capacitor is formed on the surface of the lower electrode layer of the second capacitor, and the upper electrode layer of the second capacitor is formed on the surface of the dielectric layer of the second capacitor.

[0054] In one exemplary embodiment of this disclosure, the semiconductor structure further includes:

[0055] A second semiconductor layer covers the second capacitor layer, the second semiconductor layer fills the gaps in the second capacitor and the gaps between each of the second capacitors, and the second semiconductor layer is in contact with the first semiconductor layer.

[0056] According to one aspect of this disclosure, a memory is provided, comprising the semiconductor structure described in any one of the foregoing claims.

[0057] The memory, semiconductor structure, and method for forming the present disclosure, on the one hand, can increase the number of capacitors by designing multiple capacitor layers. During use, each capacitor in the multiple capacitor layers can charge and discharge simultaneously, thereby increasing the storage capacity. On the other hand, during the capacitor arrangement process, since the arrangement space of each layer is relatively large, the radial dimension of each capacitor in each layer can be appropriately increased, thereby increasing the surface area of ​​each capacitor and further increasing the storage capacity. During the manufacturing process, the height of each capacitor layer can be appropriately reduced, thereby reducing the difficulty of etching to form capacitor holes and the difficulty of depositing films in the capacitor holes to form capacitors. This ensures that each capacitor hole can be etched through, so that each capacitor formed inside can be connected to the conductive structure at the bottom of the capacitor hole. This ensures that the charge collected by each capacitor can be stored and prevents some capacitors from failing or collapsing due to being suspended, thereby improving product yield. In addition, there is no need to arrange the capacitors in a hexagonal shape, avoiding the preparation of conductive layers that require hexagonal capacitor arrangement, simplifying the process and reducing manufacturing costs.

[0058] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0059] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0060] Figure 1 This is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0061] Figure 2 This is a top view of the substrate in an embodiment of this disclosure;

[0062] Figure 3 This is a schematic diagram of the substrate in an embodiment of the present disclosure;

[0063] Figure 4 This is a top view after step S110 is completed in this embodiment of the present disclosure;

[0064] Figure 5 This is a schematic diagram of the structure after step S110 is completed in the embodiment of this disclosure;

[0065] Figure 6 This is a flowchart of step S120 in the embodiment of this disclosure;

[0066] Figure 7 This is a schematic diagram of the first capacitor layer in an embodiment of this disclosure;

[0067] Figure 8 This is a flowchart of step S210 in the embodiment of this disclosure;

[0068] Figure 9 This is a schematic diagram of the structure after step S211 is completed in the embodiment of this disclosure;

[0069] Figure 10 This is a top view of the structure after step S212 is completed in this embodiment of the present disclosure;

[0070] Figure 11 This is a cross-sectional view of the structure after step S212 is completed in the embodiment of this disclosure;

[0071] Figure 12 This is a flowchart of step S213 in the embodiment of this disclosure;

[0072] Figure 13 This is a top view of the structure after step S2131 is completed in the embodiment of this disclosure;

[0073] Figure 14 This is a cross-sectional view of the structure after step S2131 is completed in this embodiment of the present disclosure;

[0074] Figure 15 This is a schematic diagram of the structure after removing the first mask layer in the embodiment of this disclosure;

[0075] Figure 16 This is a schematic diagram of the structure after step S220 is completed in the embodiment of this disclosure;

[0076] Figure 17 This is a flowchart of a method for forming a semiconductor structure according to another embodiment of the present disclosure;

[0077] Figure 18 This is a schematic diagram of the structure after step S130 is completed in the embodiment of this disclosure;

[0078] Figure 19 This is a flowchart of step S220 in the embodiment of this disclosure;

[0079] Figure 20 This is a top view of the structure after step S221 is completed in the embodiment of this disclosure;

[0080] Figure 21 This is a cross-sectional view of the structure after step S221 is completed in this embodiment of the present disclosure;

[0081] Figure 22 This is a schematic diagram of the structure after step S223 is completed in the embodiment of this disclosure;

[0082] Figure 23 This is a schematic diagram of the structure after step S224 is completed in the embodiment of this disclosure;

[0083] Figure 24 This is a top view of the structure after step S225 is completed in the embodiment of this disclosure;

[0084] Figure 25 This is a cross-sectional view of the structure after step S225 is completed in the embodiment of this disclosure;

[0085] Figure 26 This is a flowchart of step S226 in the embodiment of this disclosure;

[0086] Figure 27 This is a schematic diagram of the structure after step S2261 is completed in the embodiment of this disclosure;

[0087] Figure 28 This is a schematic diagram of the structure after step S140 is completed in the embodiment of this disclosure.

[0088] Explanation of reference numerals in the attached figures:

[0089] 1. Substrate; 11. Conductive contact plug; 12. Insulating layer; 13. Bit line structure; 101. Capacitor contact hole; 21. First capacitor layer; 211. First capacitor; 2111. Lower electrode layer of the first capacitor; 2112. Dielectric layer of the first capacitor; 2113. Upper electrode layer of the first capacitor; 212. First stacked film layer; 2120. First capacitor hole; 2121. First support layer; 2122. First sacrificial layer; 2123. First mask layer; 2 2. Second capacitor layer; 221. Second capacitor; 2211. Lower electrode layer of the second capacitor; 2212. Dielectric layer of the second capacitor; 2213. Upper electrode layer of the second capacitor; 222. Second stacked film layer; 2220. Second capacitor via; 2221. Reference support layer; 2222. Second sacrificial layer; 2223. Third mask layer; 3. First semiconductor layer; 310. Second mask layer; 301. Through hole; 4. Conductive pillar; 5. Second semiconductor layer. Detailed Implementation

[0090] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0091] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0092] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0093] With the development of semiconductor technology, there is a huge demand for smaller and more integrated memory. Capacitors are the core component of memory, primarily used to store electrical charge. As memory size shrinks, achieving the same capacitance or increasing it further becomes increasingly difficult, as stated in the capacitance formula (…). As can be seen from A=2πr*h), when using materials with the same dielectric constant, the only way to increase the storage capacity of a capacitor is to reduce the thickness of the dielectric layer and increase the surface area of ​​the capacitor. However, reducing the thickness of the dielectric layer can easily lead to excessive leakage current and low product yield.

[0094] In related technologies, increasing the capacitor's surface area is commonly used to increase its storage capacity. During capacitor manufacturing, a conductive layer is deposited in the capacitor array region to arrange the capacitors in a hexagonal pattern. Overlapping support and sacrificial layers are formed on the substrate, and these layers are etched to create a porous structure with a high aspect ratio (typically 1000nm–1500nm deep). The sacrificial layer is then removed after capacitor formation. However, due to limitations in the fabrication process, the etching depth varies in different areas during the formation of the porous structure. After removing the sacrificial layer, some capacitors fail due to being suspended, and these capacitors are prone to collapse, resulting in low device yield.

[0095] Based on this, the present disclosure provides a method for forming a semiconductor structure to solve the above-mentioned technical problems. Figure 1 A flowchart illustrating a method for forming a semiconductor structure according to an embodiment of this disclosure is shown. See also... Figure 1 As shown, the forming method may include steps S110 and S120, wherein:

[0096] Step S110, providing a substrate, the substrate comprising a plurality of conductive contact plugs arranged in an array and an insulating layer separating each of the conductive contact plugs;

[0097] Step S120: A multilayer capacitor layer is formed on the surface of the substrate, which is stacked and distributed in a direction perpendicular to the substrate. Each capacitor layer includes a plurality of capacitors distributed at intervals, and each capacitor is connected to a different conductive contact plug.

[0098] The semiconductor structure formation method disclosed herein, on the one hand, increases the number of capacitors by designing multiple capacitor layers. During use, each capacitor in the multiple capacitor layers can charge and discharge simultaneously, thereby increasing the capacitor storage capacity. On the other hand, during the capacitor placement process, since the placement space of each layer is relatively large, the radial dimension of each capacitor in each layer can be appropriately increased, thereby increasing the surface area of ​​each capacitor and further improving the capacitor storage capacity. During the manufacturing process, the height of each capacitor layer can be appropriately reduced, thereby reducing the difficulty of etching to form capacitor holes and the difficulty of depositing films in the capacitor holes to form capacitors. This ensures that each capacitor hole can be etched through, allowing each capacitor formed inside to connect with the conductive structure at the bottom of the capacitor hole. This ensures that the charge collected by each capacitor can be stored and prevents some capacitors from failing or collapsing due to being suspended, thus improving product yield. In addition, there is no need to arrange the capacitors in a hexagonal shape, avoiding the preparation of conductive layers that would require hexagonal capacitor arrangement, simplifying the process and reducing manufacturing costs.

[0099] The steps of the method for forming a semiconductor structure according to the present disclosure will be described in detail below:

[0100] like Figure 1 As shown, in step S110, a substrate is provided, the substrate comprising a plurality of conductive contact plugs arranged in an array and an insulating layer separating each of the conductive contact plugs.

[0101] Figure 2 A top view of the substrate in an embodiment of this disclosure is shown; Figure 3 It shows along Figure 2 A cross-sectional view of the substrate cut by the dashed line, as shown below. Figure 2 and Figure 3 As shown, the substrate 1 can be a flat plate structure, and the substrate 1 contains a bit line structure 13. The bit line structure 13 forming area and the capacitor contact hole 101 forming area can be predefined on the substrate 1. The bit line structure 13 forming area can be used to form the bit line structure 13, and the capacitor contact hole 101 forming area can be used to form a conductive contact plug.

[0102] Figure 4 This diagram shows the structure after step S110 is completed in the embodiment of this disclosure; Figure 5 It shows along Figure 4 A cross-sectional view of a conductive contact plug cut by a dashed line, as shown below. Figure 4 and Figure 5As shown, the substrate 1 may include an insulating layer 12, which may cover the top and sidewalls of each bit line structure 13. For example, after forming the bit line structure 13 in the bit line structure 13 forming area, the insulating layer 12 material may be deposited on the surface of the bit line structure 13 to form the insulating layer 12. Subsequently, the insulating material is etched in the portion corresponding to the forming area of ​​each capacitor contact hole 101 to form a plurality of spaced capacitor contact holes 101 in the insulating layer 12. Conductive contact plugs 11 are formed in the capacitor contact holes 101. Each conductive contact plug 11 may be separated by the insulating layer 12 to avoid coupling or short circuit between each conductive contact plug 11.

[0103] The conductive contact plug 11 can be made of a conductor or semiconductor material, such as tungsten, copper, or polycrystalline silicon. The conductive contact plug 11 can be formed in the capacitor contact hole 101 by means of vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, other methods can also be used to form the conductive contact plug 11, which will not be listed here.

[0104] like Figure 2 As shown, this disclosure may include multiple groups of conductive contact plugs 11 spaced apart along a first direction A. For example, the conductive contact plugs 11 in each group may be equally spaced along the first direction A; the multiple groups of conductive contact plugs 11 may be spaced apart along a second direction B. For example, each group of conductive contact plugs 11 may be equally spaced apart along the second direction B. The first direction A and the second direction B may be perpendicular to each other. That is, the conductive contact plugs 11 may be arranged in an array in rows and columns.

[0105] It should be noted that perpendicularity can be absolute or approximate. Deviations are inevitable during manufacturing. In this disclosure, angular deviations may occur due to manufacturing limitations, resulting in a slight difference in the angle between the first direction A and the second direction B. As long as the angular deviation between the first direction A and the second direction B is within a preset range, the first direction A and the second direction B can be considered perpendicular. For example, the preset range can be 10°, meaning that the angle between the first direction A and the second direction B can be considered perpendicular when it is greater than or equal to 80° and less than or equal to 100°.

[0106] like Figure 1 As shown, in step S120, multiple capacitor layers are formed on the surface of the substrate, stacked in a direction perpendicular to the substrate. Each capacitor layer includes multiple capacitors spaced apart, and each capacitor is connected to a different conductive contact plug.

[0107] The capacitor layer may include multiple capacitors, which may be spaced apart and arranged in an array. For example, the number of capacitors in each capacitor layer may be 2, 4, 6, 8, or 10, and of course, more may be added, which will not be listed here. There may be multiple capacitor layers, which may be stacked and distributed along a direction perpendicular to the substrate 1. For example, there may be two, three, four, or five capacitor layers, and of course, other numbers may also be added, which will not be listed here.

[0108] In one exemplary embodiment of this disclosure, the capacitors in adjacent capacitor layers can be staggered, and each capacitor can be directly or indirectly connected to different conductive contact plugs 11, so that the charge collected in each capacitor can be stored separately through each conductive contact plug 11. During use, the capacitors in the multi-layer capacitor layers can be charged and discharged simultaneously, which can improve the capacitor storage capacity. During the capacitor layout process, the layout space of each capacitor layer is relatively large, and the radial dimension of the capacitor in each capacitor layer can be appropriately increased, thereby increasing the surface area of ​​each capacitor and further improving the capacitor storage capacity.

[0109] For example, multiple capacitor layers can be formed on the surface of substrate 1 by means of vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition or atomic layer deposition. Of course, other methods can also be used to form each capacitor layer. No special limitation is made on the formation method of each capacitor layer here.

[0110] In one exemplary embodiment of this disclosure, the number of capacitor layers can be two, namely a first capacitor layer 21 and a second capacitor layer 22. Multiple capacitor layers are formed on the surface of the substrate 1, stacked and distributed along a direction perpendicular to the substrate 1. Each capacitor layer includes multiple spaced capacitors, and each capacitor is connected to a different conductive contact plug 11. That is, step S120 may include steps S210 and S220, such as... Figure 6 As shown, where:

[0111] Step S210: A first capacitor layer is formed on the surface of the substrate. The first capacitor layer includes a plurality of first capacitors, and each first capacitor is connected to a different conductive contact plug.

[0112] like Figure 7 As shown, the first capacitor layer 21 may include a plurality of first capacitors 211 spaced apart. The cross-section of each first capacitor 211 may be circular, triangular or square, without any special limitation.

[0113] In one embodiment of this disclosure, the surface area of ​​each first capacitor 211 can be appropriately increased. Taking a circular cross-section of the first capacitor 211 as an example, the circumference of each first capacitor 211 can be increased by 20% to 60% of the original circumference length. Since the capacitance is proportional to the surface area of ​​the capacitor, the etching height of the first capacitor 211 can be reduced by 20% to 60% while keeping the capacitance unchanged. This reduces the difficulty of etching to form the first capacitor hole and also reduces the difficulty of plating the first capacitor hole to form the first capacitor 211. This ensures that each first capacitor hole can be etched through, so that each first capacitor 211 formed inside can be connected to the conductive contact plug 11. This ensures that the charge collected by each first capacitor 211 can be stored and also prevents some first capacitors 211 from failing or collapsing due to being suspended, thereby improving product yield.

[0114] Below each first capacitor 211, a corresponding conductive contact plug 11 may be distributed. The orthographic projection of each first capacitor 211 on the substrate 1 may at least partially overlap with the conductive contact plug 11 below it. In this embodiment of the disclosure, the first capacitor 211 may be in contact with the conductive contact plug 11 below it.

[0115] In one exemplary embodiment of this disclosure, a first capacitor layer 21 is formed on the surface of the substrate 1. The first capacitor layer 21 includes a plurality of first capacitors 211, and each first capacitor 211 is connected to a different conductive contact plug 11. That is, step S210 may include steps S211-S213, such as... Figure 8 As shown, where:

[0116] Step S211: A first stacked film layer is formed on the surface of the substrate.

[0117] like Figure 9 As shown, the first stacked film layer 212 may include a first support layer 2121, a first sacrificial layer 2122 and a first mask layer 2123 stacked and distributed along a direction perpendicular to the substrate 1, wherein the first support layer 2121 is formed on the surface of the substrate 1, the first sacrificial layer 2122 is formed on the surface of the first support layer 2121 away from the substrate 1, and the first mask layer 2123 is formed on the surface of the first sacrificial layer 2122 away from the substrate 1.

[0118] For example, the first support layer 2121, the first sacrificial layer 2122, and the first mask layer 2123 can be sequentially formed on the surface of the substrate 1 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, or magnetron sputtering. Of course, the first support layer 2121, the first sacrificial layer 2122, and the first mask layer 2123 can also be formed by other methods. No special limitation is made here on the formation method of the first support layer 2121, the first sacrificial layer 2122, and the first mask layer 2123.

[0119] The first support layer 2121 may be a thin film formed on the surface of the substrate 1, and its material may be Si3N4 or SiCN, and its thickness may range from 20nm to 200nm; the first sacrificial layer 2122 may be a thin film formed on the surface of the first support layer 2121 away from the substrate 1, and its material may be SiO2 or BPSG, and its thickness may range from 400nm to 900nm; the first mask layer 2123 may be a thin film or coating formed on the surface of the first sacrificial layer 2122 away from the substrate 1. In one embodiment, the first mask layer 2123 may be an anti-reflective coating, and its material may be silicon, silicon nitride, silicon oxide, or carbide, etc. The specific material may be selected according to the design and requirements of the subsequent photolithography process. For example, the material of the first mask layer 2123 may be the same as the material of the first support layer 2121. For example, the material of the first mask layer 2123 and the material of the first support layer 2121 may both be silicon nitride, and their thickness may range from 10nm to 80nm.

[0120] Step S212: A plurality of spaced first capacitor holes are formed in the first stacked film layer, and each first capacitor hole exposes at least one of the conductive contact plugs.

[0121] A photoresist layer can be formed on the side of the first mask layer 2123 facing away from the substrate 1 by spin coating or other methods. The material of the photoresist layer can be positive or negative photoresist, without special limitation. The shape of the surface of the photoresist layer away from the first mask layer 2123 can be the same as the shape of the surface of the first mask layer 2123. A mask can be used to expose the photoresist layer, and the pattern of the mask can match the required pattern of the first capacitor hole 2120. Subsequently, the exposed photoresist layer can be developed to form a developed area, which exposes the first mask layer 2123, and the pattern of the developed area can be the same as the required pattern of the first capacitor hole 2120. The size of the developed area can be the same as the required size of the first capacitor hole 2120. The first mask layer 2123, the first sacrificial layer 2122, and the first support layer 2121 can be dry-etched in the developing area by biasing to expose the conductive contact plug 11 corresponding to the first capacitor hole 2120. In this embodiment, the top view of the structure after step S212 is as follows. Figure 10 As shown; Figure 11 As described in the embodiments of this disclosure Figure 10 A schematic diagram of the structure after being cut along the dashed line.

[0122] The etching gases used in dry etching may include SF6 and CF2. x It contains at least one gas selected from Cl2 or Ar. For example, it may include Ar, and may also include SF6 or CF2. x Or at least one of the gases, such as Cl2.

[0123] It should be noted that when there are N capacitor layers, in the row or column arrangement, there can be at least N-1 conductive contact plugs 11 between two adjacent conductive contact plugs 11 in each capacitor layer. For example, when there are two capacitor layers, in the row or column arrangement, there can be at least one conductive contact plug 11 between two adjacent conductive contact plugs 11 corresponding to the first capacitor layer 21, that is, the conductive contact plugs 11 corresponding to each capacitor in the first capacitor layer 21 and the conductive contact plugs 11 corresponding to each capacitor in the second capacitor layer 22 are arranged alternately.

[0124] Step S213: A first capacitor is formed in the first capacitor hole.

[0125] The first capacitor 211 can be formed in the first capacitor hole 2120 by means of vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition or atomic layer deposition. In order to increase the storage capacity of the capacitor, the first capacitor 211 can be set as a double-sided capacitor.

[0126] In one exemplary embodiment of this disclosure, a first capacitor 211 is formed within the first capacitor hole 2120, i.e., step S213 may include steps S2131-S2134, such as... Figure 12 As shown, where:

[0127] Step S2131: The lower electrode layer of the first capacitor is formed on the sidewall and bottom of the first capacitor hole.

[0128] A lower electrode layer 2111 of the first capacitor 211 can be formed on the sidewall and bottom of the first capacitor hole 2120. Specifically, a lower electrode layer conformally fitted to the bottom and sidewall surfaces of the first capacitor hole 2120 can be formed within the first capacitor hole 2120. For ease of manufacturing, the lower electrode layer can be formed simultaneously within the first capacitor hole 2120 and on its top surface. Subsequently, the lower electrode layer on the top surface of the first capacitor hole 2120 can be removed, leaving only the lower electrode layers on its bottom and sidewalls. Furthermore, the lower electrode layer 2111 of the first capacitor 211 can be connected to the conductive contact plug 11 through the first capacitor hole 2120 to input the stored charge in the lower electrode layer 2111 of the first capacitor 211 to the conductive contact plug 11, thereby achieving capacitance storage. In this embodiment, a top view of the structure after step S2131 is shown below. Figure 13 As shown; Figure 14 As described in the embodiments of this disclosure Figure 13 A schematic diagram of the structure after being cut along the dashed line.

[0129] For example, the lower electrode layer 2111 of the first capacitor 211 can be formed in the first capacitor hole 2120 by means of vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition or atomic layer deposition. Of course, the lower electrode layer 2111 of the first capacitor 211 can also be formed by other processes. The material of the lower electrode layer 2111 of the first capacitor 211 can be titanium, titanium nitride or tungsten, etc. Of course, it can also be other materials that can be used as electrodes. No special limitation is made on the material and formation process of the lower electrode layer 2111 of the first capacitor 211 here.

[0130] It should be noted that after forming the lower electrode layer 2111 of the first capacitor 211, the first mask layer 2123 can be removed, thereby exposing the first sacrificial layer 2122. For example, a dry etching process can be used to remove the first mask layer 2123. Of course, other methods can also be used to remove the first mask layer 2123, and no specific limitation is made here on the method of removing the first mask layer 2123. In the embodiments of this disclosure, the structure after removing the first mask layer is as follows: Figure 15 As shown.

[0131] Step S2132: Remove the first sacrificial layer.

[0132] After the lower electrode layer 2111 of the first capacitor 211 is formed, the first sacrificial layer 2122 can be removed, while the first support layer 2121 is retained. At this time, the first support layer 2121 covers the outer periphery of the lower electrode layer 2111 of the first capacitor 211, which can increase the capacitance storage density and support the bottom of the lower electrode layer 2111 of the first capacitor 211, preventing the lower electrode layer 2111 of the first capacitor 211 from deforming outward and reducing the risk of short circuit.

[0133] For example, the first sacrificial layer 2122 can be removed by a wet etching process. For example, an acidic solution can be used for wet etching, such as hydrofluoric acid, such as buffered hydrofluoric acid (BHF), 49% hydrofluoric acid, or dilute hydrofluoric acid (DHF). When DHF is used as the etching solution, the ratio of hydrofluoric acid to deionized water can be 1:1 to 1:10. No special restrictions are placed on the ratio and concentration of the etching solution.

[0134] Step S2133: A dielectric layer of the first capacitor is formed on the surface of the lower electrode layer of the first capacitor.

[0135] A dielectric layer 2112 of the first capacitor 211 can be formed on the surface of the lower electrode layer 2111 of the first capacitor 211. For example, the dielectric layer 2112 of the first capacitor 211 can be a thin film formed on the surface of the lower electrode layer 2111 of the first capacitor 211. It can be formed by vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, other methods can also be used to form the dielectric layer 2112 of the first capacitor 211, which will not be listed here. The dielectric layer 2112 of the first capacitor 211 can be a single-layer film structure made of the same material, or it can be a mixed film structure made of film layers of different materials. For example, it can include materials with a high dielectric constant, such as alumina, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, tantalum oxide, niobium oxide, strontium oxide, silicon nitride, or mixtures thereof. Of course, other materials can also be used, which will not be listed here.

[0136] Step S2134: Form the upper electrode layer of the first capacitor on the surface of the dielectric layer of the first capacitor.

[0137] The upper electrode layer 2113 of the first capacitor 211 can be formed on the surface of the dielectric layer 2112 of the first capacitor 211 using methods such as vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, other processes can also be used to form the upper electrode layer 2113 of the first capacitor 211, and no particular limitation is made here. The material of the upper electrode layer 2113 of the first capacitor 211 can be a conductive material, for example, titanium, titanium nitride, or tungsten. Of course, other materials that can serve as electrodes can also be used; no particular limitation is made here regarding the material and formation process of the upper electrode layer 2113 of the first capacitor 211. In the embodiments of the formation method disclosed herein, the structure after step S2134 is as follows... Figure 7 As shown.

[0138] Step S220: A second capacitor layer is formed on the side of the first capacitor layer away from the substrate. The second capacitor layer includes a plurality of second capacitors, each of which is connected to a different conductive contact plug. The conductive contact plug connected to the second capacitor and the conductive contact plug connected to the first capacitor are different conductive contact plugs.

[0139] The second capacitor layer 22 may be disposed on the side of the first capacitor layer 21 facing away from the substrate 1. The second capacitor layer 22 may include a plurality of spaced second capacitors 221, and the cross-section of each second capacitor 221 may be circular or square, without special limitation. In the embodiment of this disclosure, the structure after completing step S220 is as follows: Figure 16 As shown.

[0140] In one embodiment of this disclosure, the surface area of ​​each second capacitor 221 can be appropriately increased. Taking a circular cross-section of the second capacitor 221 as an example, the circumference of each second capacitor 221 can be increased by 20% to 60% of the original capacitor circumference length. Since the capacitance is proportional to the capacitor surface area, the etching height of the second capacitor 221 can be reduced by 20% to 60% while keeping the capacitance unchanged. This reduces the difficulty of etching to form the second capacitor hole and also reduces the difficulty of plating the second capacitor hole to form the second capacitor 221. This ensures that each second capacitor hole can be etched through, so that each second capacitor 221 formed inside can be connected to the conductive contact plug 11. This ensures that the charge collected by each second capacitor 221 can be stored and also prevents some second capacitors 221 from failing or collapsing due to being suspended, thereby improving product yield.

[0141] Below each second capacitor 221, a corresponding conductive contact plug 11 may be distributed. The orthographic projection of each second capacitor 221 on the substrate 1 may at least partially overlap with the conductive contact plug 11 below it. In this embodiment of the present disclosure, the second capacitor 221 may be indirectly connected to the conductive contact plug 11 below it through other conductive structures.

[0142] In one exemplary embodiment of this disclosure, such as Figure 17 As shown, the method for forming the semiconductor structure disclosed herein further includes:

[0143] Step S130: A first semiconductor layer is formed covering the first capacitor layer, the first semiconductor layer filling the gaps in the first capacitor and the gaps between each of the first capacitors.

[0144] After forming the first capacitor layer 21, a first semiconductor layer 3 covering the first capacitor layer 21 can be formed by vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The first semiconductor layer 3 can make full contact with the upper electrode layer 2113 of each first capacitor 211, which helps to improve the capacitor charging efficiency. Specifically, the first semiconductor layer 3 can cover the surface of the upper electrode layer 2113 of each first capacitor 211, and can fill the gaps within the first capacitor 211 and the gaps between each first capacitor 211, which can both lead out the electrical components of the first capacitor 211 and enhance the stability of each capacitor in the first capacitor layer 21. In the embodiment of this disclosure, the structure after completing step S130 is as follows: Figure 18 As shown.

[0145] The first semiconductor layer 3 may be made of silicon, metal, or metal compound. For example, it may be silicon, germanium silicon, tungsten, titanium silicide, titanium oxide, or tungsten oxide, etc., without any special limitation.

[0146] In one embodiment, the orthographic projection of the first support layer 2121 and each first capacitor 211 on the substrate 1 can be within the orthographic projection of the first semiconductor layer 3 on the substrate 1, so that each first capacitor 211 can be completely enclosed by the first semiconductor layer 3 to avoid leakage.

[0147] In one exemplary embodiment of this disclosure, a second capacitor layer 22 is formed on the side of the first capacitor layer 21 facing away from the substrate 1. The second capacitor layer 22 includes a plurality of second capacitors 221, each of which is connected to a different conductive contact plug 11. The conductive contact plug 11 connected to the second capacitor 221 and the conductive contact plug 11 connected to the first capacitor 211 are different conductive contact plugs 11. That is, step S220 includes steps S221-S226, as follows... Figure 19 As shown, where:

[0148] Step S221: A via is formed through the first semiconductor layer and the first support layer. The orthographic projection of the via on the substrate does not overlap with the orthographic projection of the first capacitor hole on the substrate, and each via exposes at least one of the conductive contact plugs.

[0149] In one exemplary embodiment of this disclosure, a through-hole 301 penetrating the first semiconductor layer 3 and the first support layer 2121 can be formed by etching. There can be multiple through-holes 301, and at least one conductive contact plug 11 can be exposed at the bottom of each through-hole 301. Preferably, each through-hole 301 can expose one conductive contact plug 11, which can be a conductive contact plug 11 other than the conductive contact plug 11 connected to the first capacitor 211.

[0150] For example, a second mask layer 310 may be formed on the surface of the first semiconductor layer 3 away from the substrate 1. The second mask layer 310 may be an anti-reflective coating, and its material may be an insulating material. For example, its material may be silicon, silicon nitride, silicon oxide, or carbide. The specific material may be selected according to the design and requirements of the subsequent photolithography process. In one embodiment, the material of the second mask layer 310 may be silicon nitride.

[0151] A photoresist layer can be formed on the surface of the second mask layer 310 away from the substrate 1 by spin coating or other methods. The material of the photoresist layer can be positive or negative photoresist, without special limitation. A mask can be used to expose the photoresist layer, and the pattern of the mask can match the pattern required for the via 301. Subsequently, the exposed photoresist layer can be developed to form multiple development areas. Each development area exposes the second mask layer 310, and the pattern of the development area can be the same as the pattern required for the via 301. The width of the development area can be the same as the required size of the via 301.

[0152] The second mask layer 310, the first semiconductor layer 3, and the first support layer 2121 can be dry-etched in the developing area using a bias voltage to expose the conductive contact plug 11. The etching gas used in the dry etching process may include SF6 or CF2. x It contains at least one gas selected from Cl2 or Ar. For example, it may include Ar, and may also include SF6 or CF2. x Or at least one gas, such as Cl2. In this embodiment, a top view of the structure after step S221 is shown below. Figure 20 As shown; Figure 21 As described in the embodiments of this disclosure Figure 20 A schematic diagram of the structure after being cut along the dashed line.

[0153] Step S222: An insulating material layer is formed on the sidewall of the through hole.

[0154] An insulating material layer can be formed on the sidewall of the via 301 by vacuum evaporation or chemical vapor deposition. The insulating material layer can isolate the structure inside the via 301 from the first semiconductor layer 3, preventing short circuits between the structure inside the via 301 and the first semiconductor layer 3 due to leakage. The material of the insulating material layer can be a material with a low dielectric constant, for example, it can be SICo, carbon-doped oxide or silicon nitride, etc., and its thickness can be 1 to 3 nm. No special limitation is made on the material and thickness of the insulating material layer here.

[0155] Step S223: Fill the through hole with conductive material to form a conductive pillar, and the insulating material layer is in contact with the sidewall of the conductive pillar.

[0156] Conductive material can be filled into the through hole 301 using processes such as vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, other methods can also be used to fill the through hole 301 with conductive material. No special restrictions are placed on the filling method of conductive material here.

[0157] In one embodiment, conductive material can fill the through-hole 301 to form a conductive post 4 within the through-hole 301. The conductive post 4 can contact and connect with the conductive contact plug 11 at the bottom of the through-hole 301, allowing the conductive contact plug 11 to be electrically led out through the conductive post 4. The conductive material can be the same as the material of the conductive contact plug 11, for example, it can be tungsten metal. In this embodiment of the present disclosure, the structure after completing step S223 is as follows: Figure 22 As shown.

[0158] Step S224: A second stacked film layer is formed on the side of the first semiconductor layer and the conductive pillar that is away from the substrate.

[0159] The second stacked film layer 222 may include a reference support layer 2221, a second sacrificial layer 2222, and a third mask layer 2223 stacked and distributed along a direction perpendicular to the substrate 1. The reference support layer 2221 is formed on the surface of the second mask layer 310, the second sacrificial layer 2222 is formed on the surface of the reference support layer 2221 facing away from the substrate 1, and the third mask layer 2223 is formed on the surface of the second sacrificial layer 2222 facing away from the substrate 1.

[0160] For example, the reference support layer 2221, the second sacrificial layer 2222, and the third mask layer 2223 can be sequentially formed on the surface of the second mask layer 310 by means of chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, or magnetron sputtering. Of course, the reference support layer 2221, the second sacrificial layer 2222, and the third mask layer 2223 can also be formed by other means. No special limitation is made here on the formation method of the reference support layer 2221, the second sacrificial layer 2222, and the third mask layer 2223.

[0161] In one embodiment, the reference support layer 2221 may be a thin film formed on the surface of the second mask layer 310, and its material may be Si3N4 or SiCN, with a thickness ranging from 20 nm to 200 nm. The reference support layer 2221 and the second mask layer 310 may be made of the same material, and the reference support layer 2221 and the second mask layer 310 may together constitute the second support layer. That is, the second stacked film layer 222 may include the second support layer and the second sacrificial layer 2222. The second sacrificial layer 2222 may be a thin film formed on the surface of the second support layer away from the substrate 1, and its material may be SiO2 or BPSG, with a thickness ranging from 400 nm to 900 nm. The third mask layer 2223 may be a thin film or coating formed on the surface of the second sacrificial layer 2222 away from the substrate 1. For example, the third mask layer 2223 may be an anti-reflective coating. In one embodiment, the third mask layer 2223 may be made of the same material as the second support layer, with a thickness ranging from 10 nm to 80 nm. In this embodiment, the structure after step S224 is as follows: Figure 23 As shown.

[0162] Step S225: A plurality of spaced second capacitor holes are formed in the second stacked film layer, each second capacitor hole exposing at least one of the conductive pillars.

[0163] A photoresist layer can be formed on the side of the third mask layer 2223 facing away from the substrate 1 by spin coating or other methods. The material of the photoresist layer can be positive or negative photoresist, without special limitation. The shape of the surface of the photoresist layer away from the third mask layer 2223 can be the same as the shape of the surface of the third mask layer 2223. A mask can be used to expose the photoresist layer, and the pattern of the mask can match the required pattern of the second capacitor hole 2220. Subsequently, the exposed photoresist layer can be developed to form a developed area, which exposes the third mask layer 2223, and the pattern of the developed area can be the same as the required pattern of the second capacitor hole 2220. The size of the developed area can be the same as the required size of the second capacitor hole. The third mask layer 2223, the second sacrificial layer 2222, and the second support layer can be dry etched in the developed area by biasing to expose the conductive pillar 4 corresponding to the second capacitor hole 2220.

[0164] The etching gases used in dry etching may include SF6 and CF2. x It contains at least one gas selected from Cl2 or Ar. For example, it may include Ar, and may also include SF6 or CF2. x Or at least one gas, such as Cl2. In this embodiment, a top view of the structure after step S225 is shown below. Figure 24 As shown; Figure 25 As described in the embodiments of this disclosure Figure 24 A schematic diagram of the structure after being cut along the dashed line.

[0165] Step S226: A second capacitor is formed inside the second capacitor hole.

[0166] The second capacitor 221 can be formed in the second capacitor hole 2220 by means of vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition or atomic layer deposition. In order to increase the storage capacity of the capacitor, the second capacitor 221 can be set as a double-sided capacitor.

[0167] In one exemplary embodiment of this disclosure, a second capacitor 221 is formed within the second capacitor hole 2220, i.e., step S226 may include steps S2261-S2264, such as... Figure 26 As shown, where:

[0168] Step S2261: The lower electrode layer of the second capacitor is formed on the sidewall and bottom of the second capacitor hole.

[0169] The lower electrode layer 2211 of the second capacitor 221 can be formed on the sidewall and bottom of the second capacitor hole 2220. Specifically, a lower electrode layer conformally fitted to the bottom and sidewall surfaces of the second capacitor hole 2220 can be formed inside the second capacitor hole 2220. For ease of manufacturing, the lower electrode layer can be formed simultaneously inside and on the top surface of the second capacitor hole 2220. Subsequently, the lower electrode layer on the top surface of the second capacitor hole 2220 can be removed, leaving only the lower electrode layers on the bottom and sidewalls. The final structure of the lower electrode layer 2211 of the second capacitor 221 is as follows: Figure 27 As shown. In addition, the lower electrode layer 2211 of the second capacitor 221 can be connected to the conductive post 4 through the second capacitor hole 2220, so that the charge stored in the lower electrode layer 2211 of the second capacitor 221 can be input to the conductive contact plug 11 through the conductive post 4, thereby realizing capacitor storage.

[0170] For example, the lower electrode layer 2211 of the second capacitor 221 can be formed in the second capacitor hole 2220 using methods such as vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, the lower electrode layer 2211 of the second capacitor 221 can also be formed by other processes. The material of the lower electrode layer 2211 of the second capacitor 221 can be titanium, titanium nitride, or tungsten, etc., or other materials that can be used as electrodes. No special limitations are made here on the material and formation process of the lower electrode layer 2211 of the second capacitor 221.

[0171] It should be noted that after the lower electrode layer 2211 of the second capacitor 221 is formed, the third mask layer 2223 can be removed to expose the second sacrificial layer 2222. For example, the third mask layer 2223 can be removed by a dry etching process. Of course, other methods can also be used to remove the third mask layer 2223. No special limitation is made here on the method of removing the third mask layer 2223.

[0172] Step S2262: Remove the second sacrificial layer.

[0173] After forming the lower electrode layer 2211 of the second capacitor 221, the second sacrificial layer 2222 can be removed while the second support layer is retained. This can increase the capacitance storage density and support the bottom of the lower electrode layer 2211 of the second capacitor 221, preventing the lower electrode layer 2211 of the second capacitor 221 from deforming outward and reducing the risk of short circuit.

[0174] For example, the second sacrificial layer 2222 can be removed by a wet etching process. For instance, an acidic solution can be used for wet etching, such as hydrofluoric acid, for example, buffered hydrofluoric acid (BHF), 49% hydrofluoric acid, or dilute hydrofluoric acid (DHF). When DHF is used as the etching solution, the ratio of hydrofluoric acid to deionized water can be 1:1 to 1:10. No special restrictions are placed on the ratio and concentration of the etching solution.

[0175] Step S2263: A dielectric layer of the second capacitor is formed on the surface of the lower electrode layer of the second capacitor.

[0176] A dielectric layer 2212 of the second capacitor 221 can be formed on the surface of the lower electrode layer 2211 of the second capacitor 221. For example, the dielectric layer 2212 of the second capacitor 221 can be a thin film formed on the surface of the lower electrode layer 2211 of the second capacitor 221. The dielectric layer 2212 of the second capacitor 221 can be formed by vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, other methods can also be used to form the dielectric layer 2212 of the second capacitor 221, which will not be listed here. The dielectric layer 2212 of the second capacitor 221 can be a single-layer film structure made of the same material, or a mixed film structure made of film layers of different materials. For example, it can include materials with a high dielectric constant, such as alumina, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, tantalum oxide, niobium oxide, strontium oxide, silicon nitride, or mixtures thereof. Of course, other materials can also be used, which will not be listed here.

[0177] Step S2264: Form the upper electrode layer of the second capacitor on the surface of the dielectric layer of the second capacitor.

[0178] The upper electrode layer 2213 of the second capacitor 221 can be formed on the surface of the dielectric layer 2212 of the second capacitor 221 using methods such as vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, other processes can also be used to form the upper electrode layer 2213 of the second capacitor 221, and no particular limitation is made here. The material of the upper electrode layer 2213 of the second capacitor 221 can be titanium nitride, and other materials are also possible, which will not be listed here. In the embodiment of the formation method disclosed herein, the structure after step S2264 is as follows... Figure 16 As shown.

[0179] In one exemplary embodiment of this disclosure, the method for forming the semiconductor structure further includes:

[0180] Step S140: A second semiconductor layer is formed covering the second capacitor layer. The second semiconductor layer fills the gaps in the second capacitor and the gaps between each of the second capacitors, and the second semiconductor layer is in contact with the first semiconductor layer.

[0181] After the second capacitor layer 22 is formed, a second semiconductor layer 5 covering the second capacitor layer 22 can be formed by vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The second semiconductor layer 5 can make full contact with the upper electrode layer 2213 of each second capacitor 221, which helps to improve the charging efficiency of the capacitor. Specifically, the second semiconductor layer 5 can cover the surface of the upper electrode layer 2213 of each second capacitor 221, and can fill the gaps within the second capacitor 221 and the gaps between each second capacitor 221, which can both lead out the electrical components of the second capacitor 221 and enhance the stability of each capacitor in the second capacitor layer 22. The second semiconductor layer 5 can be made of silicon, metal, or metal compound. For example, it can be silicon, germanium silicon, tungsten, titanium silicide, titanium oxide, or tungsten oxide, etc., without special limitation.

[0182] In one embodiment, the orthographic projection of the second support layer and each of the second capacitors 221 onto the substrate 1 can be within the orthographic projection of the second semiconductor layer 5 onto the substrate 1, so that each of the second capacitors 221 is completely enclosed by the second semiconductor layer 5, preventing leakage. Furthermore, the second semiconductor layer 5 can also be in contact with the first semiconductor layer 3, thereby allowing the charges collected by the first capacitor layer 21 and the second capacitor layer 22 to be combined and led out together through the first semiconductor layer 3 and the second semiconductor layer 5. In this embodiment, the structure after step S140 is as follows... Figure 28 As shown.

[0183] It should be noted that although the steps of the semiconductor structure formation method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0184] This disclosure also provides a semiconductor structure, such as Figure 16 As shown, the semiconductor structure may include a substrate 1 and multiple capacitor layers, wherein:

[0185] The substrate 1 includes a plurality of conductive contact plugs 11 arranged in an array and an insulating layer 12 separating each conductive contact plug 11;

[0186] Each capacitor layer is formed on the surface of the substrate 1 and stacked in a direction perpendicular to the substrate 1. Each capacitor layer includes multiple capacitors spaced apart, and each capacitor is connected to a different conductive contact plug 11.

[0187] The semiconductor structure disclosed herein, on the one hand, can increase the number of capacitors by designing multiple capacitor layers. During use, each capacitor in the multiple capacitor layers can charge and discharge simultaneously, thereby increasing the capacitor storage capacity. On the other hand, during the capacitor placement process, since the placement space of each layer is relatively large, the radial dimension of each capacitor in each layer can be appropriately increased, thereby increasing the surface area of ​​each capacitor and further improving the capacitor storage capacity. During the manufacturing process, the height of each capacitor layer can be appropriately reduced, thereby reducing the difficulty of etching to form capacitor holes and reducing the difficulty of depositing films in the capacitor holes to form capacitors. This ensures that each capacitor hole can be etched through, so that each capacitor formed inside can be connected to the conductive structure at the bottom of the capacitor hole. This ensures that the charge collected by each capacitor can be stored and prevents some capacitors from failing or collapsing due to being suspended, thereby improving product yield.

[0188] The specific details of the semiconductor structure according to the embodiments of this disclosure are described in detail below:

[0189] like Figure 2 and Figure 3 As shown, the substrate 1 can be a flat plate structure, and the substrate 1 contains a bit line structure 13. The bit line structure 13 forming area and the capacitor contact hole 101 forming area can be predefined on the substrate 1. The bit line structure 13 forming area can be used to form the bit line structure 13, and the capacitor contact hole 101 forming area can be used to form the conductive contact plug 11.

[0190] like Figure 4 and Figure 5 As shown, the substrate 1 may include an insulating layer 12, which may cover the top and sidewalls of each bit line structure 13. For example, after forming the bit line structure 13 in the bit line structure 13 forming area, the insulating layer 12 material may be deposited on the surface of the bit line structure 13 to form the insulating layer 12. Subsequently, the insulating material is etched in the portion corresponding to the forming area of ​​each capacitor contact hole 101 to form a plurality of spaced capacitor contact holes 101 in the insulating layer 12. Conductive contact plugs 11 are formed in the capacitor contact holes 101. Each conductive contact plug 11 may be separated by the insulating layer 12 to avoid coupling or short circuit between each conductive contact plug 11.

[0191] The conductive contact plug 11 can be made of a conductor or semiconductor material, such as tungsten, copper, or polycrystalline silicon. The conductive contact plug 11 can be formed in the capacitor contact hole 101 by means of vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, other methods can also be used to form the conductive contact plug 11, which will not be listed here.

[0192] like Figure 2 As shown, this disclosure may include multiple groups of conductive contact plugs 11 spaced apart along a first direction A. For example, the conductive contact plugs 11 in each group may be equally spaced along the first direction A; the multiple groups of conductive contact plugs 11 may be spaced apart along a second direction B. For example, each group of conductive contact plugs 11 may be equally spaced apart along the second direction B. The first direction A and the second direction B may be perpendicular to each other. That is, the conductive contact plugs 11 may be arranged in an array in rows and columns.

[0193] The capacitor layer may include multiple capacitors, which may be spaced apart and arranged in an array. For example, the number of capacitors in each capacitor layer may be 2, 4, 6, 8, or 10, and of course, more may be added, which will not be listed here. There may be multiple capacitor layers, which may be stacked and distributed along a direction perpendicular to the substrate 1. For example, there may be two, three, four, or five capacitor layers, and of course, other numbers may also be added, which will not be listed here.

[0194] In one exemplary embodiment of this disclosure, the capacitors in adjacent capacitor layers can be staggered, and each capacitor can be directly or indirectly connected to different conductive contact plugs 11, so that the charge collected in each capacitor can be stored separately through each conductive contact plug 11. During use, the capacitors in the multi-layer capacitor layers can be charged and discharged simultaneously, which can improve the capacitor storage capacity. During the capacitor layout process, the layout space of each capacitor layer is relatively large, and the radial dimension of the capacitor in each capacitor layer can be appropriately increased, thereby increasing the surface area of ​​each capacitor and further improving the capacitor storage capacity.

[0195] In one exemplary embodiment of this disclosure, the number of capacitor layers can be two, which can be a first capacitor layer 21 and a second capacitor layer 22, wherein:

[0196] like Figure 7 As shown, the first capacitor layer 21 may include a plurality of first capacitors 211 spaced apart. The cross-section of each first capacitor 211 may be circular, triangular or square, without any special limitation.

[0197] In one embodiment of this disclosure, the surface area of ​​each first capacitor 211 can be appropriately increased. Taking a circular cross-section of the first capacitor 211 as an example, the circumference of each first capacitor 211 can be increased by 20% to 60% of the original circumference length. Since the capacitance is proportional to the surface area of ​​the capacitor, the etching height of the first capacitor 211 can be reduced by 20% to 60% while keeping the capacitance unchanged. This reduces the difficulty of etching to form capacitor holes and also reduces the difficulty of plating in the first capacitor holes to form the first capacitor 211, ensuring that each first capacitor hole can be etched through. This allows each first capacitor 211 formed inside to be connected to the conductive contact plug 11, ensuring that the charge collected by each first capacitor 211 can be stored and preventing some first capacitors 211 from failing or collapsing due to being suspended, thus improving product yield.

[0198] Below each first capacitor 211, a corresponding conductive contact plug 11 may be distributed. The orthographic projection of each first capacitor 211 on the substrate 1 may at least partially overlap with the conductive contact plug 11 below it. In this embodiment of the disclosure, the first capacitor 211 may be in contact with the conductive contact plug 11 below it.

[0199] In one exemplary embodiment of this disclosure, the first capacitor 211 may include a lower electrode layer, a dielectric layer, and an upper electrode layer, wherein:

[0200] The lower electrode layer 2111 of the first capacitor 211 can be in contact with the conductive contact plug 11 below it, and can extend away from the substrate 1 in a direction perpendicular to the substrate 1. The electrical charge stored in the first capacitor 211 can be input to the conductive contact plug 11 through the lower electrode layer 2111 of the first capacitor 211, thereby realizing capacitor storage.

[0201] The material of the lower electrode layer 2111 of the first capacitor 211 can be a conductive material. For example, the material can be titanium, titanium nitride or tungsten, etc. Of course, it can also be other materials that can be used as electrodes. No special limitation is made on the material of the lower electrode layer 2111 of the first capacitor 211 here.

[0202] In one exemplary embodiment of this disclosure, the first capacitor layer 21 may further include a first support layer 2121. The first support layer 2121 may be located on the surface of the substrate 1 and may cover the outer periphery of the lower electrode layer 2111 of each first capacitor 211. The first support layer 2121 can support the bottom of the lower electrode layer 2111 of the first capacitor 211, thereby preventing the lower electrode layer 2111 of the first capacitor 211 from deforming outward and reducing the risk of short circuit.

[0203] The first support layer 2121 can be a thin film or coating formed on the surface of the substrate 1. Its material can be Si3N4 or SiCN, and its thickness can range from 20nm to 200nm.

[0204] The dielectric layer 2112 of the first capacitor 211 can be formed on the surface of the lower electrode layer 2111 of the first capacitor 211. For example, the dielectric layer 2112 of the first capacitor 211 can be a thin film formed on the surface of the lower electrode layer 2111 of the first capacitor 211, or it can be a coating formed on the surface of the lower electrode layer 2111 of the first capacitor 211. No specific limitation is made on the specific form of the dielectric layer 2112 of the first capacitor 211 here.

[0205] The dielectric layer 2112 of the first capacitor 211 can be a single-layer film structure made of the same material, or a mixed film structure made of film layers of different materials. For example, it may include materials with a high dielectric constant, such as aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, tantalum oxide, niobium oxide, strontium oxide, silicon nitride, or mixtures thereof. Of course, it can also be other materials, which will not be listed here.

[0206] The upper electrode layer 2113 of the first capacitor 211 can be formed on the surface of the dielectric layer 2112 of the first capacitor 211. The material of the upper electrode layer 2113 of the first capacitor 211 can be a conductive material. For example, the material can be titanium, titanium nitride or tungsten, etc. Of course, it can also be other materials that can be used as electrodes. No special limitation is made on the material of the upper electrode layer 2113 of the first capacitor 211 here.

[0207] like Figure 16 As shown, the second capacitor layer 22 may be disposed on the side of the first capacitor layer 21 away from the substrate 1. The second capacitor layer 22 may include a plurality of second capacitors 221 spaced apart. The cross-section of each second capacitor 221 may be circular or square, without any special limitation.

[0208] In one embodiment of this disclosure, the surface area of ​​each second capacitor 221 can be appropriately increased. Taking a circular cross-section of the second capacitor 221 as an example, the circumference of each second capacitor 221 can be increased by 20% to 60% of the original capacitor circumference length. Since the capacitance is proportional to the capacitor surface area, the etching height of the second capacitor 221 can be reduced by 20% to 60% while keeping the capacitance unchanged. This reduces the difficulty of etching to form the second capacitor hole and also reduces the difficulty of plating the second capacitor hole to form the second capacitor 221. This ensures that each second capacitor hole can be etched through, so that each second capacitor 221 formed inside can be connected to the conductive contact plug 11. This ensures that the charge collected by each second capacitor 221 can be stored and also prevents some second capacitors 221 from failing or collapsing due to being suspended, thereby improving product yield.

[0209] Below each second capacitor 221, a corresponding conductive contact plug 11 may be distributed. The orthographic projection of each second capacitor 221 on the substrate 1 may at least partially overlap with the conductive contact plug 11 below it. In this embodiment of the present disclosure, the second capacitor 221 may be indirectly connected to the conductive contact plug 11 below it through other conductive structures.

[0210] In one exemplary embodiment of this disclosure, such as Figure 18 As shown, the semiconductor structure of this disclosure may further include a first semiconductor layer 3, which may cover the first capacitor layer 21. The first semiconductor layer 3 can make full contact with the upper electrode layer 2113 of each first capacitor 211, which helps to improve the capacitor charging efficiency. Specifically, the first semiconductor layer 3 may cover the surface of the upper electrode layer 2113 of each first capacitor 211, and may fill the gaps within the first capacitor 211 and the gaps between each first capacitor 211, which can both lead out the electrical components of the first capacitor 211 and enhance the stability of each capacitor in the first capacitor layer 21.

[0211] The first semiconductor layer 3 may be made of silicon, metal, or metal compound. For example, it may be silicon, germanium silicon, tungsten, titanium silicide, titanium oxide, or tungsten oxide, etc., without any special limitation.

[0212] In one embodiment, the orthographic projection of the first support layer 2121 and each first capacitor 211 on the substrate 1 can be within the orthographic projection of the first semiconductor layer 3 on the substrate 1, so that each first capacitor 211 can be completely enclosed by the first semiconductor layer 3 to avoid leakage.

[0213] In one exemplary embodiment of this disclosure, a through-hole 301 penetrating the first semiconductor layer 3 and the first support layer 2121 can be formed by etching. There can be multiple through-holes 301, and at least one conductive contact plug 11 can be exposed at the bottom of each through-hole 301. Preferably, each through-hole 301 can expose one conductive contact plug 11, which can be a conductive contact plug 11 other than the conductive contact plug 11 connected to the first capacitor 211.

[0214] An insulating material layer is formed on the sidewall of the via 301. The insulating material layer can isolate the structure inside the via 301 from the first semiconductor layer 3, and prevent short circuit between the structure inside the via 301 and the first semiconductor layer 3 due to leakage. The material of the insulating material layer can be a material with a low dielectric constant. For example, it can be SICo, carbon-doped oxide or silicon nitride, etc., and its thickness can be 1 to 3 nm. No special limitation is made on the material and thickness of the insulating material layer here.

[0215] Conductive material can be filled into the through hole 301 to form a conductive post 4. The conductive post 4 can be connected to the conductive contact plug 11 at the bottom of the through hole 301, and the conductive contact plug 11 can be electrically led out through the conductive post 4. The conductive material can be the same as the material of the conductive contact plug 11, for example, it can be tungsten.

[0216] In one exemplary embodiment of this disclosure, the second capacitor layer 22 may be formed on the side of the first semiconductor layer 3 facing away from the substrate 1, and the second capacitor 221 may include a lower electrode layer, a dielectric layer, and an upper electrode layer, wherein:

[0217] The lower electrode layer 2211 of the second capacitor 221 can be connected to the conductive post 4 below it in a one-to-one contact, and can extend away from the substrate 1 in a direction perpendicular to the substrate 1. The electrical charge stored in the second capacitor 221 can be input to the conductive contact plug 11 through the conductive post 4 through the lower electrode layer 2211 of the second capacitor 221, thereby realizing capacitor storage.

[0218] The material of the lower electrode layer 2211 of the second capacitor 221 can be a conductive material. For example, it can be titanium, titanium nitride or tungsten, etc. Of course, it can also be other materials that can be used as electrodes. No special limitation is made on the material of the lower electrode layer 2211 of the second capacitor 221 here.

[0219] In one exemplary embodiment of this disclosure, the second capacitor layer 22 may further include a second support layer. The second support layer may be located on the surface of the first semiconductor layer 3 and may cover the outer periphery of the lower electrode layer 2211 of each second capacitor 221. The second support layer can support the bottom of the lower electrode layer 2211 of the second capacitor 221, thereby preventing the lower electrode layer 2211 of the second capacitor 221 from deforming outward and reducing the risk of short circuit.

[0220] The second support layer can be a thin film or coating formed on the surface of the first semiconductor layer 3. Its material can be Si3N4 or SiCN, and its thickness can range from 20nm to 200nm.

[0221] The dielectric layer 2212 of the second capacitor 221 can be formed on the surface of the lower electrode layer 2211 of the second capacitor 221. For example, the dielectric layer 2212 of the second capacitor 221 can be a thin film formed on the surface of the lower electrode layer 2211 of the second capacitor 221, or it can be a coating formed on the surface of the lower electrode layer 2211 of the second capacitor 221. The specific form of the dielectric layer 2212 of the second capacitor 221 is not specifically limited here.

[0222] The dielectric layer 2212 of the second capacitor 221 can be a single-layer film structure made of the same material, or a mixed film structure made of film layers of different materials. For example, it may include materials with a high dielectric constant, such as aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, tantalum oxide, niobium oxide, strontium oxide, silicon nitride, or mixtures thereof. Of course, it can also be other materials, which will not be listed here.

[0223] The upper electrode layer 2213 of the second capacitor 221 can be formed on the surface of the dielectric layer 2212 of the second capacitor 221. The material of the upper electrode layer 2213 of the second capacitor 221 can be a conductive material. For example, the material can be titanium, titanium nitride or tungsten, etc. Of course, it can also be other materials that can be used as electrodes. No special limitation is made on the material of the upper electrode layer 2213 of the second capacitor 221 here.

[0224] In one exemplary embodiment of this disclosure, such as Figure 28 As shown, the semiconductor structure of this disclosure may further include a second semiconductor layer 5, which may cover the second capacitor layer 22. The second semiconductor layer 5 can make full contact with the upper electrode layer 2213 of each second capacitor 221, which helps to improve the capacitor charging efficiency. Specifically, the second semiconductor layer 5 may cover the surface of the upper electrode layer 2213 of each second capacitor 221, and may fill the gaps within the second capacitor 221 and the gaps between each second capacitor 221, which can both lead out the electrical components of the second capacitor 221 and enhance the stability of each capacitor in the second capacitor layer 22.

[0225] The second semiconductor layer 5 may be made of silicon, metal, or metal compound. For example, it may be silicon, germanium silicon, tungsten, titanium silicide, titanium oxide, or tungsten oxide, etc., without any special limitation.

[0226] In one embodiment, the orthographic projection of the second support layer and each of the second capacitors 221 onto the substrate 1 can be within the orthographic projection of the second semiconductor layer 5 onto the substrate 1, so that each of the second capacitors 221 is completely enclosed by the second semiconductor layer 5 to prevent leakage. Furthermore, the second semiconductor layer 5 can also be in contact with the first semiconductor layer 3, thereby allowing the charges collected by the first capacitor layer 21 and the second capacitor layer 22 to be combined and led out together through the first semiconductor layer 3 and the second semiconductor layer 5.

[0227] This disclosure also provides a memory, which may include the semiconductor structure described in any of the above embodiments. The specific details, formation process and beneficial effects of the memory have been described in detail in the corresponding semiconductor structure formation method and semiconductor structure, and will not be repeated here.

[0228] For example, the memory can be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. Of course, it can also be other storage devices, which will not be listed here.

[0229] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a plurality of conductive contact plugs arranged in an array and an insulating layer separating each of the conductive contact plugs; Multiple capacitor layers are formed on the surface of the substrate, stacked in a direction perpendicular to the substrate. Each capacitor layer includes multiple spaced capacitors, and each capacitor is connected to a different conductive contact plug. The process involves forming multiple capacitor layers stacked along a direction perpendicular to the substrate on the surface of the substrate. Each capacitor layer includes multiple spaced capacitors, each capacitor being connected to a different conductive contact plug. A first capacitor layer is formed on the surface of the substrate. The first capacitor layer includes a plurality of first capacitors, and each first capacitor is connected to a different conductive contact plug. A second capacitor layer is formed on the side of the first capacitor layer away from the substrate. The second capacitor layer includes a plurality of second capacitors, each of which is connected to a different conductive contact plug. The conductive contact plug connected to the second capacitor and the conductive contact plug connected to the first capacitor are different conductive contact plugs. The forming method further includes: A first semiconductor layer is formed to cover the first capacitor layer, and the first semiconductor layer fills the gaps in the first capacitor and the gaps between each of the first capacitors.

2. The forming method according to claim 1, characterized in that, The first capacitor layer is formed on the surface of the substrate. The first capacitor layer includes a plurality of first capacitors, each of which is connected to a different conductive contact plug. A first stacked film layer is formed on the surface of the substrate; A plurality of spaced-apart first capacitor holes are formed within the first stacked film layer, and each first capacitor hole exposes at least one of the conductive contact plugs; A first capacitor is formed within the first capacitor hole.

3. The forming method according to claim 2, characterized in that, The first stacked film layer includes a first support layer and a first sacrificial layer, the first sacrificial layer being formed on the side of the first support layer facing away from the substrate, and the formation of a first capacitor within the first capacitor aperture includes: The lower electrode layer of the first capacitor is formed on the sidewall and bottom of the first capacitor hole; Remove the first sacrificial layer; A dielectric layer of the first capacitor is formed on the surface of the lower electrode layer of the first capacitor; An upper electrode layer of the first capacitor is formed on the surface of the dielectric layer of the first capacitor.

4. The forming method according to claim 3, characterized in that, A second capacitor layer is formed on the side of the first capacitor layer facing away from the substrate. The second capacitor layer includes a plurality of second capacitors, each of which is connected to a different conductive contact plug. The conductive contact plugs connected to the second capacitors and the conductive contact plugs connected to the first capacitors are different conductive contact plugs. A through-hole is formed through the first semiconductor layer and the first support layer. The orthographic projection of the through-hole on the substrate does not overlap with the orthographic projection of the first capacitor hole on the substrate, and each through-hole exposes at least one of the conductive contact plugs. An insulating material layer is formed on the sidewall of the through hole; The through-hole is filled with conductive material to form a conductive pillar, and the insulating material layer is in contact with the sidewall of the conductive pillar. A second stacked film layer is formed on the side of the first semiconductor layer and the conductive pillar that is away from the substrate; A plurality of spaced-apart second capacitor holes are formed within the second stacked film layer, and each second capacitor hole exposes at least one of the conductive pillars; A second capacitor is formed within the second capacitor hole.

5. The forming method according to claim 4, characterized in that, The second stacked film layer includes a second support layer and a second sacrificial layer, the second sacrificial layer being formed on the side of the second support layer opposite to the substrate, and the formation of a second capacitor within the second capacitor aperture includes: The lower electrode layer of the second capacitor is formed on the sidewall and bottom of the second capacitor hole; Remove the second sacrificial layer; A dielectric layer of the second capacitor is formed on the surface of the lower electrode layer of the second capacitor; An upper electrode layer of the second capacitor is formed on the surface of the dielectric layer of the second capacitor.

6. The forming method according to claim 1, characterized in that, The forming method further includes: A second semiconductor layer is formed to cover the second capacitor layer. The second semiconductor layer fills the gaps in the second capacitor and the gaps between each of the second capacitors, and the second semiconductor layer is in contact with the first semiconductor layer.

7. A semiconductor structure, characterized in that, include: The substrate includes a plurality of conductive contact plugs arranged in an array and an insulating layer separating each of the conductive contact plugs; A multilayer capacitor layer, wherein each capacitor layer is formed on the surface of the substrate and stacked in a direction perpendicular to the substrate, each capacitor layer includes a plurality of spaced capacitors, and each capacitor is connected to a different conductive contact plug. The multilayer capacitor layer includes: A first capacitor layer is located on the surface of the substrate and includes a plurality of first capacitors, each of which is connected to a different conductive contact plug. The second capacitor layer is located on the side of the first capacitor layer away from the substrate. The second capacitor layer includes a plurality of second capacitors, each of which is connected to a different conductive contact plug. The conductive contact plug connected to the second capacitor and the conductive contact plug connected to the first capacitor are different conductive contact plugs. The semiconductor structure also includes: A first semiconductor layer covers the first capacitor layer, and the first semiconductor layer fills the gaps within the first capacitor and the gaps between each of the first capacitors.

8. The semiconductor structure according to claim 7, characterized in that, The first capacitor layer includes: A plurality of first capacitors are provided, each first capacitor being spaced apart, and each first capacitor being connected to a conductive contact plug.

9. The semiconductor structure according to claim 8, characterized in that, The first capacitor layer includes a first support layer, and the first capacitor includes a lower electrode layer, a dielectric layer and an upper electrode layer. The first support layer covers the outer periphery of the lower electrode layer near the substrate, and the dielectric layer is formed on the surface of the lower electrode layer. The upper electrode layer is formed on the surface of the dielectric layer.

10. The semiconductor structure according to claim 9, characterized in that, Through-holes are formed in the first semiconductor layer and the first support layer. The orthographic projection of the through-holes on the substrate does not overlap with the orthographic projection of the first capacitor hole on the substrate, and each through-hole exposes at least one of the conductive contact plugs. Semiconductor structures also include: An insulating material layer is formed on the sidewall of the through hole; A conductive post is located inside the through hole, and the insulating material layer is in contact with the sidewall of the conductive post; The second capacitor layer includes: Multiple second capacitors are located on the side of the first semiconductor layer and the conductive pillars away from the substrate. The second capacitors are spaced apart and each second capacitor is connected to each conductive pillar in a one-to-one correspondence.

11. The semiconductor structure according to claim 10, characterized in that, The second capacitor layer includes a second support layer. The second capacitor includes a lower electrode layer, a dielectric layer, and an upper electrode layer. The second support layer covers the outer periphery of the lower electrode layer of the second capacitor on the side close to the substrate. The dielectric layer of the second capacitor is formed on the surface of the lower electrode layer of the second capacitor. The upper electrode layer of the second capacitor is formed on the surface of the dielectric layer of the second capacitor.

12. The semiconductor structure according to claim 7, characterized in that, The semiconductor structure also includes: A second semiconductor layer covers the second capacitor layer, the second semiconductor layer fills the gaps in the second capacitor and the gaps between each of the second capacitors, and the second semiconductor layer is in contact with the first semiconductor layer.

13. A memory, characterized in that, Includes the semiconductor structure described in any one of claims 7-12.

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