Semiconductor structure and method of fabricating the same

Abstract

The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductor, and is used to solve the technical problem of low yield of semiconductor structure. The semiconductor structure comprises a substrate, a memory cell array located on the substrate, the memory cell array comprising a plurality of transistor units, each transistor unit comprising a first transistor and a second transistor which are electrically connected and extend along a first direction; the first direction is parallel to the substrate; a first bit line penetrating the memory cell array and electrically connected with the first transistor; a second bit line penetrating the memory cell array and electrically connected with the second transistor; a first word line electrically connected with the first transistor, and a second word line electrically connected with the second transistor. By horizontally placing the first transistor and the second transistor relative to the substrate, the manufacturing of the first transistor and the second transistor is facilitated, and the yield of the semiconductor structure is improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for fabricating the same. Background Technology

[0002] With the development of semiconductor technology, memory, especially dynamic random access memory (DRAM), is widely used in various electronic devices due to its high storage density and fast read / write speed.

[0003] Dynamic random access memory (DRAM) typically includes multiple memory cells. Each memory cell includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line (WL) of the DRAM, and the voltage on the word line controls the transistor's on and off states. One of the transistor's source and drain terminals is electrically connected to the bit line (BL), and the other of the source and drain terminals is electrically connected to the capacitor. Data information is stored or output through the bit line.

[0004] However, in the aforementioned memory, as the aspect ratio of the capacitor increases, the manufacturing difficulty of the capacitor increases, and the yield of the semiconductor structure is lower. Summary of the Invention

[0005] In view of the above problems, this disclosure provides a semiconductor structure and a method for fabricating the same, which is used to improve the yield of semiconductor structures.

[0006] According to some embodiments, a first aspect of this disclosure provides a semiconductor structure comprising: a substrate; a memory cell array located on the substrate, the memory cell array including a plurality of transistor cells, each transistor cell including a first transistor and a second transistor extending along a first direction and electrically connected thereto; the first direction being parallel to the substrate; a first bit line passing through the memory cell array and electrically connected to the first transistor; a second bit line passing through the memory cell array and electrically connected to the second transistor; a first word line electrically connected to the first transistor; and a second word line electrically connected to the second transistor.

[0007] In some possible embodiments, there are multiple first bit lines, multiple first word lines, multiple second bit lines and multiple second word lines; multiple first word lines and multiple second word lines extend along a third direction and are electrically isolated from each other; multiple first bit lines and multiple second bit lines extend along a second direction and are electrically isolated from each other; and / or, a first step is formed at one end of the multiple first bit lines away from the memory cell array, and a second step is formed at one end of the multiple second bit lines away from the memory cell array.

[0008] In some possible embodiments, the first step and the second step are located on the same side of the storage cell array.

[0009] In some possible embodiments, each first bit line is electrically connected to a plurality of first transistors located in the same row along the second direction; each first word line is electrically connected to a plurality of first transistors located in the same column along the third direction; each second bit line is electrically connected to a plurality of second transistors located in the same row along the second direction; and each second word line is electrically connected to a plurality of second transistors located in the same column along the third direction.

[0010] In some possible embodiments, both the first transistor and the second transistor include: a channel having a accommodating space formed therein; a gate having a first end and a second end opposite to each other along the first direction, the first end of the gate being located outside the accommodating space and the second end of the gate being located inside the accommodating space; a dielectric layer located between the gate and the channel, insulating and isolating the gate and the channel; a source disposed at one end of the channel away from the gate; and a drain disposed at the other end of the channel, with the drain and the source spaced apart along the first direction.

[0011] In some possible embodiments, the channel includes a top wall, a bottom wall, and a side wall surrounding the receiving space, the top wall having an opening through which a second end of the gate is exposed outside the receiving space; the source covers the bottom wall of the channel and a portion of the side wall near the bottom wall, and the drain covers the top wall of the channel and a portion of the side wall near the top wall.

[0012] In some possible embodiments, the channel material includes indium gallium zinc oxide, polycrystalline silicon, monocrystalline silicon, silicon germanide, or silicon carbide.

[0013] In some possible embodiments, the first bit line is electrically connected to the drain of the first transistor, and the first word line is electrically connected to the source of the first transistor; the second bit line is electrically connected to the source of the second transistor, and the second word line is electrically connected to the gate of the second transistor; the gate of the first transistor is electrically connected to the drain of the second transistor.

[0014] In some possible embodiments, a first isolation layer is further disposed between the second bit line and the second word line along the first direction to insulate and isolate the second bit line and the second word line, and the second transistor passes through the first isolation layer.

[0015] In some possible embodiments, the semiconductor structure further includes a first bit line plug, a second bit line plug, a first word line plug, and a second word line plug extending in a third direction; the first bit line plug, the second bit line plug, the first word line plug, and the second word line plug are electrically connected to the first bit line, the second bit line, the first word line, and the second word line, respectively.

[0016] The semiconductor structure provided in this disclosure has at least the following advantages:

[0017] The semiconductor structure provided in this disclosure electrically connects a first transistor and a second transistor, both extending along a first direction parallel to the substrate. This allows the first and second transistors to be placed horizontally relative to the substrate, facilitating their fabrication and improving the yield of the semiconductor structure. It also increases the number of stacked first and second transistors, thereby increasing the storage capacity of the semiconductor structure. Furthermore, by using one of the first and second transistors as a storage node, a 2T0C semiconductor structure is formed, reducing the volume occupied by the storage cell and thus increasing the storage density of the semiconductor structure.

[0018] According to some embodiments, a second aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising:

[0019] Provide substrate;

[0020] A memory cell array, a first bit line, a second bit line, a first word line, and a second word line are formed on the substrate;

[0021] The memory cell array includes a plurality of transistor cells, each transistor cell including a first transistor and a second transistor that extend along a first direction and are electrically connected; the first direction is parallel to the substrate;

[0022] The first bit line passes through the memory cell array and is electrically connected to the first transistor; the second bit line passes through the memory cell array and is electrically connected to the second transistor; the first word line is electrically connected to the first transistor; and the second word line is electrically connected to the second transistor.

[0023] In some possible embodiments, a memory cell array, a first bit line, a second bit line, a first word line, and a second word line are formed on the substrate, including:

[0024] A first gate array and a second gate array are formed on the substrate at intervals along the first direction; the first gate array includes a plurality of first gates at intervals along the second direction and at intervals along the third direction, and the second gate array includes a plurality of second gates at intervals along the second direction and at intervals along the third direction.

[0025] A dielectric layer is formed on the first gate and the second gate, and a channel is formed on the dielectric layer; the first ends of the first gate and the second gate both extend out of the channel;

[0026] A first metal layer and a second metal layer are formed, the first metal layer covering the channel located at the second end of the first gate, and the second metal layer covering the channel near the first end of the second gate; the second end is opposite to the first end along the first direction;

[0027] A first bit line and a second bit line are formed extending along a second direction; the first bit line covers the first metal layer, and the second bit line covers the second metal layer.

[0028] A third metal layer and a fourth metal layer are formed, the third metal layer covering the channel located near the first end of the first gate, the fourth metal layer covering the channel at the second end of the second gate, the third metal layer being spaced apart from the first metal layer, the fourth metal layer being spaced apart from the second metal layer, and the fourth metal layer being in contact with the first end of the first gate;

[0029] A first word line and a second word line are formed extending in a third direction; the first word line covers the third metal layer, and the second word line covers the first end of the second gate.

[0030] In some possible embodiments, a first gate array and a second gate array spaced apart along the first direction are formed on the substrate, including:

[0031] A first stacked structure is formed on the substrate, the first stacked structure having a first region and a second region, the first stacked structure including a first sacrificial layer and an initial gate layer alternately disposed sequentially along the third direction;

[0032] A portion of the first stacked structure is removed, a first trench extending in a first direction is formed in the first region, and a second trench extending in a second direction is formed in the second region; the first trench divides the initial gate layer located in the first region into a plurality of initial gate pillars, and the second trench divides the initial gate layer located in the second region into a first interconnect layer and a second interconnect layer.

[0033] The plurality of initial gate pillars are divided along the first direction into the first gate array and the second gate array.

[0034] In some possible embodiments, the initial gate layer located in the first region is divided into the first gate array and the second gate array along the first direction, including:

[0035] A second sacrificial layer is formed within the first trench and the second trench;

[0036] A first support layer, a second support layer, and a third support layer are formed in the second sacrificial layer and the first stacked structure, which are spaced apart along the first direction. The first support layer connects the initial gate pillar and the first connection layer, the third support layer connects the initial gate pillar and the second connection layer, and the second support layer connects the initial gate pillar.

[0037] Remove a portion of the second sacrificial layer, the first sacrificial layer, and the initial gate pillar on the side of the second support layer in the first region to form the first gate array and the second gate array;

[0038] Remove the remaining second sacrificial layer and the first sacrificial layer.

[0039] In some possible embodiments, a dielectric layer is formed on the first gate and the second gate, and a channel is formed on the dielectric layer, including:

[0040] A dielectric layer is formed on the first gate, the second gate, the first interconnect layer, and the second interconnect layer.

[0041] In some possible embodiments, forming a first metal layer and a second metal layer includes:

[0042] A second isolation layer is formed between the first support layer and the second support layer, and a third isolation layer is formed between the second support layer and the third support layer;

[0043] A third sacrificial layer is formed between the second isolation layer and the second support layer, and between the second support layer and the third isolation layer;

[0044] The first metal layer is formed on the channel of the first gate, and the second metal layer is formed on the channel of the second gate.

[0045] In some possible embodiments, a third metal layer and a fourth metal layer are formed, including:

[0046] A fourth sacrificial layer is formed between the first support layer and the second isolation layer, and between the third isolation layer and the third support layer, the fourth sacrificial layer covering the first connecting layer and the second connecting layer;

[0047] The third metal layer is formed on the channel of the first gate, and the fourth metal layer is formed on the channel of the second gate.

[0048] The method for fabricating a semiconductor structure provided in this disclosure has at least the following advantages:

[0049] In the semiconductor structure fabrication method provided in this disclosure, a first transistor and a second transistor are electrically connected, and both the first transistor and the second transistor extend along a first direction parallel to the substrate. This facilitates the fabrication of the first transistor and the second transistor, improves the yield of the semiconductor structure, and also increases the number of stacked first and second transistors, thereby increasing the storage capacity of the semiconductor structure. Furthermore, by using one of the first transistor and the second transistor as a storage node, a 2T0C semiconductor structure is formed, reducing the volume occupied by the storage cell and thus increasing the storage density of the semiconductor structure. Attached Figure Description

[0050] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0051] Figure 1 This is a schematic diagram of the structure of the storage cell array in the embodiments of this disclosure;

[0052] Figure 2 This is a schematic diagram of the structure of the first transistor in an embodiment of this disclosure;

[0053] Figure 3 This is a schematic diagram of the cross-section at point AA in Figure 1.

[0054] Figure 4 This is a schematic diagram of the structure of the transistor unit in the embodiments of this disclosure;

[0055] Figure 5This is a schematic diagram of the semiconductor structure in an embodiment of this disclosure;

[0056] Figure 6 This is a circuit schematic diagram of the transistor unit in an embodiment of this disclosure;

[0057] Figure 7 This is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

[0058] Figure 8 This is a schematic diagram of the first stacked structure in an embodiment of the present disclosure;

[0059] Figure 9 This is a schematic diagram of the structure after the first and second trenches are formed in an embodiment of this disclosure;

[0060] Figure 10 This is a schematic diagram of the structure after the second sacrificial layer is formed in an embodiment of this disclosure;

[0061] Figure 11 This is a schematic diagram of the structure after the first support layer, the second support layer, and the third support layer are formed in the embodiments of this disclosure;

[0062] Figure 12 This is a schematic diagram of the structure after removing part of the first sacrificial layer, the second sacrificial layer and the initial gate layer in an embodiment of this disclosure;

[0063] Figure 13 This is a schematic diagram of the structure after removing the first sacrificial layer in an embodiment of this disclosure;

[0064] Figure 14 This is a schematic diagram of the structure after the dielectric layer is formed in an embodiment of this disclosure;

[0065] Figure 15 This is a schematic diagram of the structure after the channel is formed in an embodiment of this disclosure;

[0066] Figure 16 This is a schematic diagram of the structure after the second and third isolation layers are formed in the embodiments of this disclosure;

[0067] Figure 17 This is a schematic diagram of the structure after the third sacrificial layer is formed in an embodiment of this disclosure;

[0068] Figure 18 This is a schematic diagram of the structure after the formation of the first metal layer and the second metal layer in an embodiment of this disclosure;

[0069] Figure 19 This is a schematic diagram of the structure forming the fourth sacrificial layer in an embodiment of this disclosure;

[0070] Figure 20 This is a schematic diagram of the structure after the formation of the third and fourth metal layers in an embodiment of this disclosure. Detailed Implementation

[0071] The related technologies suffer from low yield rates for semiconductor structures. The inventors discovered that this is due to several factors: Firstly, increasing the aspect ratio of capacitors makes them prone to collapse during manufacturing, leading to lower yield rates. Secondly, the larger size of the memory cell, which includes capacitors and transistors, further reduces the storage density of the semiconductor structure.

[0072] Therefore, this disclosure provides a semiconductor structure and its fabrication method. In this semiconductor structure, a first transistor and a second transistor are electrically connected, and both the first and second transistors extend along a first direction parallel to the substrate. This allows the first and second transistors to be placed horizontally relative to the substrate, facilitating their fabrication, improving the yield of the semiconductor structure, and increasing the number of stacked first and second transistors, thereby increasing the storage capacity of the semiconductor structure. Furthermore, by using one of the first and second transistors as a storage node, a 2T0C semiconductor structure is formed, reducing the volume occupied by the storage cell and thus increasing the storage density of the semiconductor structure.

[0073] To make the above-mentioned objects, features, and advantages of the embodiments of this disclosure more apparent and understandable, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0074] The first aspect of this disclosure provides a semiconductor structure, which can be a memory device or a non-memory device. The memory device may include Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), flash memory, Electrically Erasable Programmable Read-Only Memory (EEPROM), Phase Change Random Access Memory (PRAM), or Magnetoresistive Random Access Memory (MRAM). The non-memory device may be a logic device, such as a microprocessor, digital signal processor, or microcontroller, or a similar device. This disclosure uses Dynamic Random Access Memory as an example for illustration.

[0075] See Figure 1 The semiconductor structure includes:

[0076] Substrate, Figure 1 The substrate is not shown. The substrate can provide a supporting foundation for the structural layers on the substrate. It can be made of semiconductor material, which can be one or more of silicon, germanium, silicon germanide, silicon carbide, silicon on insulator (SOI) or germanium on insulator (GOI).

[0077] A memory cell array is disposed on a substrate and used to store data information. The memory cell array includes multiple transistor cells 10, each transistor cell 10 including a first transistor 11 and a second transistor 12. The first transistor 11 and the second transistor 12 extend along a first direction and are electrically connected along the first direction, which is parallel to the substrate.

[0078] In some possible examples, the multiple transistor cells 10 in the memory cell array can be arranged in an array. Specifically, the multiple transistor cells 10 are not only spaced apart along the second direction, but also spaced apart along a third direction, and all the multiple transistor cells 10 extend along the first direction. The second direction intersects the third direction, and the first direction is perpendicular to both the second and third directions. This arrangement allows for a more compact and optimized arrangement of the transistor cells 10 in the memory cell array, maximizing the number of transistor cells 10 in the array and increasing the storage density of the semiconductor structure.

[0079] In this arrangement, the first direction is parallel to the substrate 30, so that the first transistor 11 and the second transistor 12 are placed parallel to the substrate. Compared with the technical solution where the transistor unit 10 is placed perpendicular to the substrate, this arrangement can reduce the etching depth of the transistor unit 10, reduce the etching difficulty of the semiconductor structure, and improve the stability of the transistor unit 10, reducing the risk of transistor unit 10 collapse. Furthermore, it facilitates increasing the number of stacked transistor units 10, thereby increasing the storage capacity of the semiconductor structure.

[0080] Among them, the first direction, the second direction, and the third direction are perpendicular to each other, and the first direction is parallel to the substrate, such as... Figure 1 As shown in the diagram, the X direction is parallel to the substrate, and the plane formed by the first and second directions is parallel to the substrate. The second direction is as follows: Figure 1 The Y direction is shown. The third direction is perpendicular to the substrate, and the third direction is as follows: Figure 1 The Z-direction is shown. This arrangement facilitates the fabrication of the transistor unit 10, thereby reducing the difficulty of fabricating the semiconductor structure.

[0081] It is understood that the transistor unit 10 includes a first transistor 11 and a second transistor 12. By using one of the first transistor 11 and the second transistor 12 as a storage node, on the one hand, there is no need to set up a capacitor, which enables the storage cell array to achieve a smaller feature size; on the other hand, the arrangement of the storage cell array is optimized, the volume occupied by the storage cell array is reduced, thereby improving the storage density of the semiconductor structure.

[0082] See Figure 2 and Figure 3In some possible embodiments, both the first transistor 11 and the second transistor 12 include: a channel 14 having a receiving space formed therein; a gate 16 having a first end and a second end opposite to each other along a first direction, the first end of the gate 16 being located outside the receiving space and the second end of the gate 16 being located inside the receiving space; a dielectric layer 17 located between the gate 16 and the channel 14, insulating and isolating the gate 16 and the channel 14; a drain 13 disposed at one end of the channel 14 away from the gate 16; and a source 15 disposed at the other end of the channel 14, with the source 15 and the drain 13 spaced apart along the first direction. For ease of distinction, the gate of the first transistor 11 is defined as the first gate, and the gate of the second transistor 12 is defined as the second gate.

[0083] Specifically, the first transistor 11 includes a drain 13, a source 15, a gate 16, a channel 14, and a dielectric layer 17, with a receiving space formed inside the channel 14. In some possible examples, the channel 14 includes a top wall, a bottom wall, and a side wall surrounding the receiving space, with an opening in the top wall, through which a first end of the gate 16 is exposed outside the receiving space. The channel 14 includes a top wall and a bottom wall disposed opposite each other along a first direction, and a side wall located between the top wall and the bottom wall, with one end of the side wall connected to the top wall and the other end of the side wall connected to the bottom wall, the top wall, the bottom wall, and the side wall enclosing the receiving space.

[0084] The channel 14 can be made of semiconductor materials, such as indium gallium zinc oxide (IGZO), polysilicon, single-crystal silicon, silicon germanide (SiGe), or silicon carbide (SiC). Specifically, the channel 14 is made of indium gallium zinc oxide. IGZO is transparent, allowing the first transistor 11 to be used in the fabrication of transparent semiconductor devices. IGZO can be fabricated at low temperatures, enabling the first transistor 11 to also be used in the fabrication of flexible semiconductor devices. IGZO has a high carrier mobility, which can improve the information transmission capacity and sensitivity of the first transistor 11 while reducing its power consumption. Furthermore, IGZO has a high on / off ratio (I0). on / I off By adjusting the ratio and off-state current, the gate-induced drain leakage (GIDL) of the first transistor 11 can be reduced, thereby improving the performance of the first transistor 11.

[0085] The gate 16 may be columnar, extending along a first direction, with its first end and second end disposed opposite to each other along the first direction. For example, the first end of the gate 16 is the top end of the gate 16. Figure 2 The upper end of the gate 16 is shown), and the second end of the gate 16 is the bottom end of the gate 16. Figure 2(See the lower end shown). The second end of the gate 16 is located within the receiving space, and the first end of the gate 16 is located outside the receiving space. This arrangement allows a portion of the gate 16 to be located within the receiving space to control the carriers in the channel 14, while another portion of the gate 16 is located outside the receiving space to connect with the peripheral circuitry. The gate 16 can be made of metal or its alloy, such as titanium (Ti), titanium nitride (TiN), tungsten (W), aluminum (Al), etc.

[0086] A dielectric layer 17 is disposed between the gate 16 and the channel 14 to electrically isolate the channel 14 and the gate 16, forming a channel-all-around transistor to mitigate or even overcome the short-channel effect and improve the performance of the first transistor 11. In addition, the channel-all-around transistor can also overcome the floating body effect, further improving the performance of the first transistor 11. The material of the dielectric layer 17 may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), hafnium oxide (HfO2), hafnium silicon oxide (HfSiO2), lanthanum oxide (LaO), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), barium strontium titanium oxide (BaSrTiO3), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3), lithium oxide (Li2O), aluminum oxide (Al2O3), lead scandium tantalum oxide (PbScTaO), lead zinc niobate (PbZnNbO3), or combinations thereof.

[0087] The drain 13 is disposed at one end of the channel 14, and the source 15 is disposed at the other end of the channel 14. The source 15 and the drain 13 are spaced apart along a first direction to avoid contact between the source 15 and the drain 13, thereby ensuring that the first transistor 11 can operate normally. In some possible examples, one of the drain 13 and the source 15 covers the bottom wall of the channel 14 and a portion of the sidewall near the bottom wall; the other of the drain 13 and the source 15 covers the top wall of the channel 14 and a portion of the sidewall near the top wall. That is, the drain 13 and the source 15 respectively cover the two opposite ends of the channel 14 along the first direction to increase the contact area between the drain 13 and the channel 14, and between the source 15 and the channel 14, thereby improving the sensitivity of the first transistor 11 and improving the performance of the semiconductor structure. For example, the drain 13 is close to the second end of the gate 16, and the source 15 is close to the first end of the gate 16.

[0088] The drain 13 and source 15 can be made of the same material, which can be a metallic material or a semiconductor material. For example, both the drain 13 and source 15 can be made of molybdenum (Mo), or both can be made of monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium compound, or silicon-on-insulator. Furthermore, the drain 13 and source 15 can be doped with phosphorus or boron. Using semiconductor materials for the drain 13 and source 15 overcomes the Schottky barrier between the drain 13 and channel 14, and between the source 15 and channel 14, resulting in a smaller reverse leakage current and thus improving the performance of the first transistor 11.

[0089] It should be noted that the second transistor 12 has the same structure as the first transistor 11. Therefore, the specific structure of the second transistor 12 and the arrangement of its components can be referred to the specific structure of the first transistor 11 and the arrangement of its components, and will not be repeated here.

[0090] In addition, see Figure 4 and Figure 5 The semiconductor structure also includes: a first bit line 21, which runs through the memory cell array and is electrically connected to the first transistor 11; a second bit line 23, which runs through the memory cell array and is electrically connected to the second transistor 12; a first word line 22, which is electrically connected to the first transistor 11; and a second word line 24, which is electrically connected to the second transistor 12.

[0091] In some possible embodiments, there are multiple first bit lines 21, first word lines 22, second bit lines 23, and second word lines 24; the multiple first word lines 22 and the multiple second word lines 24 extend along a third direction and are electrically isolated; the multiple first bit lines 21 and the multiple second bit lines 23 extend along a second direction and are electrically isolated; and / or, the ends of the multiple first bit lines 21 away from the memory cell array form a first step, and the ends of the multiple second bit lines 23 away from the memory cell array form a second step.

[0092] Specifically, such as Figure 5 As shown, multiple first word lines 22 extend along a third direction (Z direction), and each first word line 22 is spaced apart along a second direction (Y direction) to provide electrical isolation between them. Multiple second word lines 24 extend along a third direction, and each second word line 24 is spaced apart along the second direction to provide electrical isolation between them. This arrangement optimizes the arrangement of the first word lines 22 and the second word lines 24, reduces space requirements, and facilitates increasing the number of first transistors 11 and second transistors 12, thereby improving the storage density of the semiconductor structure.

[0093] Each first word line 22 is electrically connected to a plurality of first transistors 11 located in the same column along a third direction; each second word line 24 is electrically connected to a plurality of second transistors 12 located in the same column along a third direction. See also Figure 5 Each first word line 22 extends along a third direction, passing through a plurality of first transistors 11 arranged along the third direction, thereby electrically connecting with the corresponding plurality of first transistors 11. Similarly, each second word line 24 extends along a third direction, passing through a plurality of second transistors 12 arranged along the third direction, thereby electrically connecting with the corresponding plurality of second transistors 12.

[0094] Specifically, such as Figure 5 As shown, multiple first bit lines 21 extend along a second direction (Y direction), and each first bit line 21 is spaced apart along a third direction (Z direction) to provide electrical isolation between them. Multiple second bit lines 23 extend along the second direction, and each second bit line 23 is spaced apart along a third direction to provide electrical isolation between them. This arrangement optimizes the arrangement of the first bit lines 21 and the second bit lines 23, reduces space requirements, and facilitates increasing the number of first transistors 11 and second transistors 12, thereby improving the storage density of the semiconductor structure.

[0095] Each first bit line 21 is electrically connected to a plurality of first transistors 11 located in the same row along the second direction; each second bit line 23 is electrically connected to a plurality of second transistors 12 located in the same row along the second direction. (See reference...) Figure 5 Each first bit line 21 extends along the second direction, passing through a plurality of first transistors 11 arranged along the second direction, thereby electrically connecting with the corresponding plurality of first transistors 11. Similarly, each second bit line 23 extends along the second direction, passing through a plurality of second transistors 12 arranged along the second direction, thereby electrically connecting with the corresponding plurality of second transistors 12.

[0096] Specifically, the ends of multiple first bit lines 21 away from the memory cell array form a first step, and the ends of multiple second bit lines 23 away from the memory cell array form a second step. By setting the first step and the second step, multiple first bit lines 21 and multiple second bit lines 23 can be led out to be electrically connected to the external circuit.

[0097] In some possible implementations, the lengths of the plurality of first bit lines 21 gradually decrease along the direction away from the substrate, so that the ends of the plurality of first bit lines 21 away from the memory cell array form a first step. For example... Figure 5 As shown, the first step extends upwards along the second direction and upwards along the third direction. This arrangement exposes a portion of the end of each first line 21, allowing for the formation of a corresponding first line plug on each first line 21, thereby connecting each first line 21 to the peripheral circuitry.

[0098] Similarly, along the direction away from the substrate, the length of the plurality of second bit lines 23 gradually decreases, so that the ends of the plurality of second bit lines 23 away from the memory cell array form a second step. Figure 5 As shown, the second step is upward along the second direction and upward along the third direction. With this configuration, each second bit line 23 has a portion of its end exposed, so as to form a corresponding second bit line plug on each second bit line 23, thereby connecting each second bit line 23 to the peripheral circuit.

[0099] In this arrangement, the first step and the second step are located on the same side of the memory cell array. This arrangement optimizes the layout of the first bit line 21 and the second bit line 23, reducing the space occupied by the first bit line 21 and the second bit line 23 along the second direction. This facilitates increasing the number of first transistors 11 and second transistors 12, thereby improving the storage density of the semiconductor structure. Of course, the first step and the second step can also be located on opposite sides of the memory cell array, but this is not a limitation of the present disclosure.

[0100] In some possible embodiments, such as Figure 4 As shown, the first bit line 21 is electrically connected to the drain 13 of the first transistor 11, and the first word line 22 is electrically connected to the source 15 of the first transistor 11; the second bit line 23 is electrically connected to the source 15 of the second transistor 12, and the second word line 24 is electrically connected to the gate 16 of the second transistor 12; the gate 16 of the first transistor 11 is electrically connected to the drain 13 of the second transistor 12. With this connection, the first transistor 11 can be used as a memory cell, and the memory cell array forms a 2TOC array to improve the storage capacity of the semiconductor structure.

[0101] Alternatively, the first bit line 21 is electrically connected to the source 15 of the first transistor 11, and the first word line 22 is electrically connected to the drain 13 of the first transistor 11; the first bit line 21 is electrically connected to the drain 13 of the second transistor 12, and the first word line 22 is electrically connected to the gate 16 of the second transistor 12; the gate 16 of the first transistor 11 is electrically connected to the source 15 of the second transistor 12. That is, the source 15 and drain 13 of the first transistor 11 can be interchanged, and the source 15 and drain 13 of the second transistor 12 can also be interchanged. This embodiment does not limit the positions of the source 13 and drain 15 of the first transistor 11 and the second transistor 12.

[0102] For details, please refer to Figure 6The first bit line 21 is the Read Bit Line (RBL), the second bit line 23 is the Write Bit Line (WBL), the first word line 22 is the Read Word Line (RWL), and the second word line 24 is the Write Word Line (WWL).

[0103] In some possible embodiments, a first isolation layer 25 is further disposed between the second bit line 23 and the second word line 24 along the first direction to insulate and isolate the second bit line 23 and the second word line 24, with the second transistor 12 passing through the first isolation layer 25. This arrangement prevents the second bit line 23 and the second word line 24 from being electrically connected, improving the yield of the semiconductor structure. The material of the first isolation layer may include silicon nitride or silicon oxynitride, but is not limited to these.

[0104] In some possible embodiments, the semiconductor structure further includes a first bit line plug, a second bit line plug, a first word line plug, and a second word line plug extending in a third direction; the first bit line plug, the second bit line plug, the first word line plug, and the second word line plug are electrically connected to the first bit line 21, the second bit line 23, the first word line 22, and the second word line 24, respectively.

[0105] Specifically, there are multiple first line plugs, which extend along a third direction and are spaced apart. Each first line plug is electrically connected to a first line 21. For example, the first line plugs are in contact with the surface of the first line 21 facing away from the substrate. The length of each first line plug can vary in a stepped manner to make each first line plug flush with the surface facing away from the substrate, facilitating the formation of a connecting layer on the first line plug to lead it out.

[0106] Multiple second bit line plugs are provided, extending along a third direction and spaced apart. Each second bit line plug is electrically connected to a second bit line 23. Exemplarily, the second bit line plugs are in contact with the surface of the second bit line 23 facing away from the substrate. The length of each second bit line plug may vary in a stepped manner to make each second bit line plug flush with the surface facing away from the substrate, facilitating the formation of a connection layer on the second bit line plug, thereby leading out the second bit line plug.

[0107] Multiple first-letter plugs are provided, extending along a third direction and spaced apart. Each first-letter plug is electrically connected to a first-letter wire 22. The lengths of the first-letter plugs can be the same to facilitate their manufacture. Multiple second-letter plugs are also provided, extending along a third direction and spaced apart. Each second-letter plug is electrically connected to a second-letter wire 24. The lengths of the second-letter plugs can be the same to facilitate their manufacture.

[0108] In summary, the semiconductor structure provided in this disclosure electrically connects the first transistor 11 and the second transistor 12, both extending along a first direction parallel to the substrate. This allows the first transistor 11 and the second transistor 12 to be placed horizontally relative to the substrate, facilitating their fabrication and improving the yield of the semiconductor structure. Furthermore, it increases the number of stacked transistors 11 and 12, thereby increasing the storage capacity of the semiconductor structure. Additionally, by using one of the first transistor 11 and the second transistor 12 as a storage node, a 2TOC semiconductor structure is formed, reducing the volume occupied by the storage cell and thus increasing the storage density of the semiconductor structure.

[0109] A second aspect of this disclosure provides a method for fabricating a semiconductor structure, which can be used to fabricate the aforementioned semiconductor structure. For example... Figure 7 The method for fabricating this semiconductor structure is shown below:

[0110] Step S10: Provide a substrate. See [link / reference] Figure 8 The substrate 30 can provide a supporting foundation for the structural layer on the substrate 30, which can be made of semiconductor material, which can be one or more of silicon, germanium, silicon germanide, silicon carbide, silicon-on-insulator or germanium-on-insulator.

[0111] Step S20: Form a memory cell array, a first bit line, a second bit line, a first word line, and a second word line on a substrate; wherein, the memory cell array includes a plurality of transistor cells, each transistor cell including a first transistor and a second transistor extending along a first direction and electrically connected; the first direction is parallel to the substrate; the first bit line passes through the memory cell array and is electrically connected to the first transistor; the second bit line passes through the memory cell array and is electrically connected to the second transistor; the first word line is electrically connected to the first transistor; and the second word line is electrically connected to the second transistor.

[0112] For details, please refer to Figure 1 and Figure 5 The memory cell array is disposed on the substrate and is used to store data information. The memory cell array includes a plurality of transistor cells 10, each transistor cell 10 including a first transistor 11 and a second transistor 12, the first transistor 11 and the second transistor 12 extending along a first direction and electrically connected along the first direction, the first direction being parallel to the substrate.

[0113] In some possible examples, the multiple transistor cells 10 in the memory cell array can be arranged in an array. Specifically, the multiple transistor cells 10 are not only spaced apart along the second direction, but also spaced apart along a third direction, and all the multiple transistor cells 10 extend along the first direction. The second direction intersects the third direction, and the first direction is perpendicular to both the second and third directions. This arrangement allows for a more compact and optimized arrangement of the transistor cells 10 in the memory cell array, maximizing the number of transistor cells 10 in the array and increasing the storage density of the semiconductor structure.

[0114] In this arrangement, the first direction is parallel to the substrate 30, causing the first transistor 11 and the second transistor 12 to be placed parallel to the substrate. Compared to the technical solution where the transistor cells 10 are placed perpendicular to the substrate, this arrangement can, on the one hand, reduce the etching depth of the transistor cells 10, making the etching of the semiconductor structure easier, and on the other hand, improve the stability of the transistor cells 10, reducing the risk of transistor cells 10 collapsing. Furthermore, it facilitates increasing the number of stacked transistor cells 10, thereby increasing the storage capacity of the semiconductor structure.

[0115] Among them, the first direction, the second direction, and the third direction are perpendicular to each other, and the first direction is parallel to the substrate, such as... Figure 1 As shown in the diagram, the X direction is parallel to the substrate, and the plane formed by the first and second directions is parallel to the substrate. The second direction is as follows: Figure 1 The Y direction is shown. The third direction is perpendicular to the substrate, and the third direction is as follows: Figure 1 The Z-direction is shown. This arrangement facilitates the fabrication of the transistor unit 10, thereby reducing the difficulty of fabricating the semiconductor structure.

[0116] Specifically, the transistor unit 10 includes a first transistor 11 and a second transistor 12. By using one of the first transistor 11 and the second transistor 12 as a storage node, on the one hand, there is no need to set up capacitors in related technologies, which enables the storage cell array to achieve a smaller feature size; on the other hand, the arrangement of the storage cell array is optimized, the volume occupied by the storage cell array is reduced, thereby improving the storage density of the semiconductor structure.

[0117] See Figure 2 and Figure 3 The first transistor 11 and the second transistor 12 each include: a channel 14, in which a receiving space is formed; a gate 16, having a first end and a second end opposite to each other along a first direction, the first end of the gate 16 being located outside the receiving space and the second end of the gate 16 being located inside the receiving space; a dielectric layer 17, located between the gate 16 and the channel 14, insulating and isolating the gate 16 and the channel 14; a drain 13, disposed at one end of the channel 14; and a source 15, disposed at the other end of the channel 14, with the source 15 and the drain 13 spaced apart along the first direction.

[0118] The first bit line 21 passes through the memory cell array and is electrically connected to the first transistor 11; the second bit line 23 passes through the memory cell array and is electrically connected to the second transistor 12; the first word line 22 is electrically connected to the first transistor 11; and the second word line 24 is electrically connected to the second transistor 12.

[0119] Each first word line 22 is electrically connected to a plurality of first transistors 11 located in the same column along a third direction; each second word line 24 is electrically connected to a plurality of second transistors 12 located in the same column along a third direction; each first bit line 21 is electrically connected to a plurality of first transistors 11 located in the same row along a second direction; each second bit line 23 is electrically connected to a plurality of second transistors 12 located in the same row along a second direction.

[0120] Specifically, the first bit line 21 is electrically connected to the source 15 of the first transistor 11, and the first word line 22 is electrically connected to the drain 13 of the first transistor 11; the first bit line 21 is electrically connected to the drain 13 of the second transistor 12, and the first word line 22 is electrically connected to the gate 16 of the second transistor 12; the gate 16 of the first transistor 11 is electrically connected to the drain of the second transistor 12. With this connection, the first transistor 11 can be used as a memory cell, and the memory cell array forms a 2TOC array to improve the storage capacity of the semiconductor structure.

[0121] In some possible implementations, forming a memory cell array, a first bit line, a second bit line, a first word line, and a second word line 24 on the substrate (step S20) includes:

[0122] Step S21: A first gate array and a second gate array are formed on the substrate at intervals along a first direction; the first gate array includes a plurality of first gates at intervals along a second direction and at intervals along a third direction, and the second gate array includes a plurality of second gates at intervals along a second direction and at intervals along a third direction.

[0123] See Figures 8 to 13 The first gate array and the second gate array are spaced apart along a first direction to facilitate the formation of other structures in the first gate array and the second gate array. The first gate array includes a plurality of first gates 61 (e.g., ...). Figure 13 As shown), a plurality of first gates 61 are spaced apart along a second direction and spaced apart along a third direction. The second gate array includes a plurality of second gates 62 (as shown). Figure 13 As shown, a plurality of second gates 62 are spaced apart along a second direction and spaced apart along a third direction. A plurality of first gates 61 and a plurality of second gates 62 extend along a first direction and correspond one-to-one.

[0124] It is understood that the extension direction of the first gate 61 is the same as the extension direction of the first gate array, and the extension direction of the second gate 62 is the same as the extension direction of the second gate array. Both the first gate array and the second gate array extend along the first direction and are spaced apart along the first direction.

[0125] The first gate 61, when projected along the first direction, partially overlaps with the corresponding second gate 62, when projected along the first direction. This facilitates the electrical connection between the first transistor 11 formed by the first gate 61 and the second transistor 12 formed by the second gate 62, forming a transistor unit 10. This allows the use of either the first transistor 11 or the second transistor 12 as a storage node, thus realizing a 2TOC structure. It can be understood that the first gate 61 is the gate 16 of the first transistor 11, and the second gate 62 is the gate 16 of the second transistor.

[0126] In this configuration, the center line of the first gate 61 coincides with the center line of the corresponding second gate 62. This arrangement allows for a larger contact area between the first transistor 11 formed by the first gate 61 and the second transistor 12 formed by the second gate 62, thereby improving the electrical performance of the transistor unit 10.

[0127] In one possible implementation, the step of forming a first gate array and a second gate array spaced apart along a first direction on the substrate (step S21) specifically includes:

[0128] Step S21-1: A first stacked structure is formed on the substrate. The first stacked structure has a first region and a second region. The first stacked structure includes a first sacrificial layer and an initial gate layer that are alternately disposed along a third direction.

[0129] The first region is used to form the first transistor and the second transistor, and the second region is used to form the first interconnect layer 46 and the second interconnect layer 47. The first interconnect layer 46 and the second interconnect layer 47 provide support when forming the first bit line and the second bit line, respectively, so as to facilitate the formation of the first bit line and the second bit line.

[0130] For details, please refer to Figure 8The first stacked structure 40 includes multiple first sacrificial layers 41 and multiple initial gate layers 42, which are alternately arranged sequentially along a third direction. The innermost layer of the first stacked structure 40 closest to the substrate 30 is the first sacrificial layer 41, and the outermost layer of the first stacked structure 40 furthest from the substrate 30 is the initial gate layer 42. This arrangement, with the innermost layer of the first stacked structure 40 being the first sacrificial layer 41, can electrically isolate the substrate and the initial gate layer 42, thereby increasing the number of subsequently formed first transistors and second transistors. Having the innermost layer of the first stacked structure 40 as the initial gate layer 42 can reduce the height of the first stacked structure 40, increasing the storage density of the semiconductor structure. The first sacrificial layer 41 can be made of silicon oxide, and the initial gate layer 42 can be made of polysilicon.

[0131] Specifically, multiple first sacrificial layers 41 and multiple initial gate layers 42 can be formed by a deposition process, which may include chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0132] Step S21-2: Remove part of the first stacked structure, form a first trench extending in a first direction in a first region, and form a second trench extending in a second direction in a second region. The first trench divides the initial gate layer located in the first region into a plurality of initial gate pillars, and the second trench divides the initial gate layer located in the second region into a first interconnect layer and a second interconnect layer.

[0133] See Figure 8 and Figure 9 The first stacked structure 40 is etched using either dry or wet etching to form a first trench 43 in a first region and a second trench 45 in a second region. The first trench 43 extends along a first direction, and there can be multiple first trenches 43. These multiple first trenches 43 are spaced apart along a second direction to divide the first stacked structure 40 in the first region into multiple segments, thereby forming an array of initial gate pillars 44 in the initial gate layer 42. Along the second direction, the multiple initial gate pillars 44 are separated by the first trenches 43; along a third direction, the multiple initial gate pillars 44 are separated by a first sacrificial layer 41, and all the multiple initial gate pillars 44 extend along the third direction.

[0134] The second trench 45 extends along the second direction, dividing the initial gate layer 42 located in the second region into a first interconnect layer 46 and a second interconnect layer 47. The first interconnect layer 46 and the second interconnect layer 47 are respectively located at both ends of the initial gate pillar 44 along the first direction. Figure 9 As shown, the first connection layer 46 and the second connection layer 47 are located at the left and right ends of the initial gate pillar 44, respectively. Each initial gate pillar 44 corresponds to one first connection layer 46 and one second connection layer 47, and the corresponding initial gate pillar 44, first connection layer 46 and second connection layer 47 are disposed on the same layer.

[0135] This configuration allows for the simultaneous etching of the initial gate layer 42 located in the first region and the initial gate layer 42 located in the second region, thereby forming the desired structure on both regions simultaneously and reducing the number of fabrication steps in the semiconductor structure. Furthermore, the first interconnect layer 46 and the second interconnect layer 47 provide support to facilitate the subsequent fabrication of the first bit line and the second bit line.

[0136] Step S21-3: Divide the multiple initial gate pillars along the first direction into a first gate array and a second gate array.

[0137] See Figure 12 Multiple initial gate pillars 44 are etched to disconnect each initial gate pillar 44 along a first direction, thereby forming a first gate array and a second gate array. It is understood that along a third direction, there is still a first sacrificial layer 41 between two adjacent initial gate pillars 44, and the first sacrificial layer 41 is also etched when multiple initial gate pillars 44 are etched.

[0138] See Figure 11 and Figure 13 ,by Figure 13 Taking the orientation shown as an example, the multiple initial gate pillars 44 on the left side form a first gate array, where each initial gate pillar 44 forms a first gate 61, and the multiple initial gate pillars 44 on the right side form a second gate array, where each initial gate pillar 44 forms a second gate 62. By breaking the integral initial gate pillars 44 to form the first gate 61 and the second gate 62, the alignment of the first gate 61 and the second gate 62 can be well guaranteed, and the manufacturing process is simple.

[0139] In one possible implementation, the initial gate layer located in the first region is divided into a first gate array and a second gate array along a first direction (steps S21-3), including:

[0140] A second sacrificial layer 48 is formed within the first trench 43 and the second trench 45. (See also...) Figure 9 and Figure 10 The second sacrificial layer 48 fills the first trench 43 and the second trench 45, and can flatten the first trench 43 and the second trench 45. The surface of the second sacrificial layer 48 facing away from the substrate 30 can be flush with the surface of the first stacked structure facing away from the substrate 30, forming a relatively flat surface, so as to facilitate the fabrication of other structural layers thereon.

[0141] After the second sacrificial layer 48 is formed, a first support layer 51, a second support layer 52 and a third support layer 53 are formed in the second sacrificial layer 48 and the first stacked structure 40, which are spaced apart along the first direction. The first support layer 51 connects the initial gate pillar 44 and the first connection layer 46, the third support layer 53 connects the initial gate pillar 44 and the second connection layer 47, and the second support layer 52 connects the initial gate pillar 44.

[0142] For details, please refer to Figure 9 and Figure 11 The process involves etching the second sacrificial layer 48, the first sacrificial layer 41, and the initial gate pillar 44. Filling trenches are formed in the second sacrificial layer 48 and the first stacked structure 40. Support material is then deposited within the filling trenches, and the deposited material is etched back to form the first support layer 51, the second support layer 52, and the third support layer 53. The first support layer 51, the second support layer 52, and the third support layer 53 are arranged along a first direction, with the second support layer 52 located between the first support layer 51 and the third support layer 53. The first support layer 51 connects the initial gate pillar 44 and the first interconnect layer 46, and subsequently primarily supports the first interconnect layer 46. The third support layer 53 connects the initial gate pillar 44 and the second interconnect layer 47, and subsequently supports both the initial gate pillar 44 and the second interconnect layer 47. The second support layer 52 connects the initial gate pillar 44, and subsequently primarily supports the initial gate pillar 44.

[0143] In one specific example, a first support layer 51 is located at the first end of the initial gate pillar 44 and the first connection layer 46, covering the first end of the initial gate pillar 44 and the first connection layer 46, as well as the side surface near the first end. A second support layer 52 is located in the middle of the initial gate pillar 44, covering the middle side surface of the initial gate pillar 44, and is not in contact with the first connection layer 46 and the second connection layer 47. A third support layer 53 is located at the second end of the second connection layer 47, covering the second end of the second connection layer 47, the side surface near the second end, and the side surface of the initial gate pillar 44 near the second end. That is, along the first direction, the second connection layer 47 extends into the third support layer 53, and the initial gate pillar 44 passes through the third support layer 53 to facilitate the subsequent fabrication of a second word line at the second end of the initial gate pillar 44.

[0144] After forming the first support layer 51, the second support layer 52, and the third support layer 53, the second sacrificial layer 48, the first sacrificial layer 41, and the initial gate pillar 44 beside the second support layer 52 in the first region are removed to form the first gate array and the second gate array. (See also...) Figure 12 A portion of the first sacrificial layer 41 and the initial gate pillars 44 beside the second support layer 52 are removed to form a separation trench. The separation trench exposes the substrate 30 to ensure that each initial gate pillar 44 is disconnected. See also Figure 11and Figure 13 After being disconnected, each initial gate post 44 is divided into a corresponding first gate 61 and second gate 62 along the first direction. The end faces of the first gate 61 and the second gate 62 face each other. Multiple first gates 61 form a first gate array, and multiple second gates 62 form a second gate array.

[0145] In some possible examples, while removing the second sacrificial layer 48, the first sacrificial layer 41, and the initial gate pillar 44 beside the second support layer 52 in the first region, the second sacrificial layer 48, the first sacrificial layer 41, and the initial gate pillar 44 beside the first support layer 51 in the first region can also be removed. That is, removing the second sacrificial layer 48, the first sacrificial layer 41, and the initial gate pillar 44 beside the first support layer 51 and the second support layer 52 in the first region exposes the ends of the first gate array and the second gate array, facilitating the formation of other structures thereon, such as the channel 14, to ensure that the channel 14 can cover one end of the first gate 61 and the second gate 62, reducing the leakage current of the first gate 61 and the second gate 62.

[0146] After forming the first gate array and the second gate array, refer to Figure 12 and Figure 13 The remaining second sacrificial layer 48 and first sacrificial layer 41 are removed. The remaining first sacrificial layer 41 and second sacrificial layer 48 are etched away to expose the first gate array and the second gate array, facilitating the formation of channels 14 on the first gate array and the second gate array. The first end of each first gate 61 in the first gate array is covered by a second support layer 52; this end will not subsequently form a channel 14, ensuring that the first end of the first gate 61 extends beyond the channel 14. The first ends of each second gate 62 in the second gate array also need to extend beyond the channel 14; therefore, before subsequent fabrication, a protective layer is formed on the first end of each second gate 62, covering the first end of each second gate 62.

[0147] In other possible implementations, see [reference] Figure 13 After forming the first gate array and the second gate array, the second sacrificial layer 48 and the first sacrificial layer 41 located between the first support layer 51 and the third support layer 53 are removed. In this way, the remaining second sacrificial layer 48 and the first sacrificial layer 41 cover the first end of each second gate 62 in the second gate array, eliminating the need to fabricate a separate protective layer.

[0148] Step S22: A dielectric layer is formed on the first gate and the second gate, and a channel is formed on the dielectric layer; the first ends of the first gate and the second gate both extend out of the channel.

[0149] See Figure 13 and Figure 14A dielectric layer 17 is formed on the first gate 61 and the second gate 62, covering the exposed surfaces of the first gate 61 and the second gate 62. (See also...) Figure 14 and Figure 15 A channel 14 is deposited on the dielectric layer 17, and the channel 14 covers the surface of the dielectric layer 17. The first end of the first gate 61 ( Figure 15 The right end shown), and the first end of the second gate 62 (shown on the right end ...). Figure 15 The right end (as shown) extends outward from the channel 14.

[0150] In an embodiment where a first connection layer 46 and a second connection layer 47 are provided in the second region, a dielectric layer 17 is formed on the first gate 61 and the second gate 62, and a channel 14 is formed on the dielectric layer 17, including: forming a dielectric layer 17 on the first gate 61, the second gate 62, the first connection layer 46 and the second connection layer 47.

[0151] This configuration eliminates the need for a mask in the second region, facilitating the fabrication of dielectric layer 17. Furthermore, as... Figure 13 As shown, the first interconnect layer 46 corresponds to the first gate 61, and the second interconnect layer 47 corresponds to the second gate 62. The first gate 61 and the first interconnect layer 46 are disposed on the same layer, and the corresponding second gate 62 and the second interconnect layer 47 are disposed on the same layer. A dielectric layer 17 is formed on the first gate 61, the second gate 62, the first interconnect layer 46, and the second interconnect layer 47, and a channel 14 is formed on the dielectric layer 17. This can better ensure the consistency between the first gate 61 and the corresponding first interconnect layer 46, and the consistency between the second gate 62 and the corresponding second interconnect layer 47, making it easier to form relatively flat first bit lines and second bit lines on them respectively.

[0152] Step S23: Form a first metal layer and a second metal layer, wherein the first metal layer covers the channel located at the second end of the first gate, and the second metal layer covers the channel near the first end of the second gate; the second end and the first end are opposite to each other along a first direction.

[0153] See Figures 15 to 18 A first metal layer 81 covers the channel 14 at the second end of the first gate 61, covering the end face of the channel 14 and the outer periphery near the end face. The first metal layer 81 forms the drain 13 or source 15 of the first transistor 11. A second metal layer 82 covers the channel 14 near the first end of the second gate 62, covering the outer periphery of the channel 14. The second metal layer 82 forms the drain 13 or source 15 of the second transistor 12. Along the first direction, the first end of the first gate 61 is opposite to the second end of the first gate 61, and the first end of the second gate 62 is opposite to the second end of the second gate 62.

[0154] In some possible implementations, forming a first metal layer 81 and a second metal layer 82 (step S23) includes:

[0155] Step S23-1: A second isolation layer is formed between the first support layer and the second support layer, and a second isolation layer is formed between the second support layer and the third support layer.

[0156] See Figure 13 , Figure 15 and Figure 16 The second isolation layer 71 is disposed between the first support layer 51 and the second support layer 52, and the second isolation layer 72 is disposed between the second support layer 52 and the third support layer 53. Figure 16 As shown, along the first direction, the first support layer 51, the second isolation layer 71, the second support layer 52, the second isolation layer 72, and the third support layer 53 are arranged sequentially at intervals. The first connecting layer 46 is located between the first support layer 51 and the second isolation layer 71, and the second connecting layer 47 is located between the second isolation layer 72 and the third support layer 53.

[0157] The second isolation layer 71 divides the channel 14 located between the first support layer 51 and the second support layer 52 into two parts. The drain 13 of the first transistor 11 is formed on one part of the channel 14, and the source 15 of the first transistor 11 is formed on the other part of the channel 14. The second isolation layer 72 divides the channel 14 located between the second support layer 52 and the third support layer 53 into two parts. The drain 13 of the second transistor 12 is formed on one part of the channel 14, and the source 15 of the second transistor 12 is formed on the other part of the channel 14.

[0158] Step S23-2: A third sacrificial layer is formed between the second isolation layer and the second support layer, and between the second support layer and the second isolation layer.

[0159] See Figure 16 and Figure 17 The third sacrificial layer 74 is filled between the second isolation layer 71 and the second support layer 52, as well as between the second support layer 52 and the second isolation layer 72. After the third sacrificial layer 74, the channels 14 on the first connecting layer 46 and the second connecting layer 47 are exposed.

[0160] In some possible examples, after the third sacrificial layer 74 is formed, a first barrier layer 75 is also formed on the third sacrificial layer 74. The first barrier layer 75 also covers the second isolation layer 71, the second support layer 52 and the second isolation layer 72. The first barrier layer 75 is made of a harder material, which can reduce the damage to the third sacrificial layer 74 and the channel 14 located inside the third sacrificial layer 74 when the first metal layer 81 and the second metal layer 82 are formed.

[0161] Step S23-3: A first metal layer is formed on the channel of the first gate, and a second metal layer is formed on the channel of the second gate.

[0162] See Figure 17 and Figure 18 A first metal layer 81 forms one of the drain 13 or source 15 of the first transistor 11, and a second metal layer 82 forms one of the drain 13 or source 15 of the second transistor 12. For example, the first metal layer 81 forms the drain 13 of the first transistor 11, and the second metal layer 82 forms the drain of the second transistor 12. The second metal layer 82 is in contact with a first end of the first gate 61 to achieve electrical connection between the second metal layer 82 and the first gate 61, so that the subsequently formed first transistor 11 and second transistor 12 are connected along a first direction to form a transistor unit 10.

[0163] In some possible embodiments, a first metal layer 81 is formed on the channel 14 of each first gate 61, and the first metal layers 81 are spaced apart. A second metal layer 82 is formed on the channel 14 of each second gate 62, and the second metal layers 82 are spaced apart. With this configuration, each first transistor 11 and each second transistor 12 is independent of each other. Subsequently, a first bit line 21 covering the plurality of first metal layers 81 located in the same row is formed to electrically connect them, and a second bit line 23 covering the plurality of second metal layers 82 located in the same row is formed to electrically connect them.

[0164] In other possible embodiments, such as Figure 18 As shown, a first metal layer 81 is formed on the channel 14 of the first gate 61, and a second metal layer 82 is formed on the channel 14 of the second gate 62 (step S23-3). This may further include: forming the first metal layer 81 on the first interconnect layer 46 and the channel 14 of the first gate 61, which are disposed in the same layer, and forming the second metal layer 82 on the second interconnect layer 47 and the channel 14 of the second gate 62, which are disposed in the same layer. In this case, it is not necessary to separately fabricate the first bit line 21 and the second bit line 23, i.e., the subsequent step S24 is unnecessary, simplifying the semiconductor structure fabrication process.

[0165] For details, please refer to Figure 13 and Figure 18 Along the third direction, each first connection layer 46 corresponds to and is disposed on the same layer as a first gate 61, and each second connection layer 47 corresponds to and is disposed on the same layer as a second gate 62. A channel 14 is formed on the first connection layer 46, the first gate 61, the second connection layer 47 and the second gate 62.

[0166] A first metal layer 81 is formed on the channel 14 of the first interconnect layer 46 and the first gate 61, which are disposed on the same layer. The first metal layers 81 on the channel 14 of the first interconnect layer 46 and the first gate 61, which are disposed on different layers, are spaced apart. That is, the first metal layers 81 corresponding to the first interconnect layer 46 and the first gate 61 are integrally formed along the second direction, and the first metal layers 81 are stacked and spaced apart along the third direction. The first metal layer 81 serves as the first bit line 21, and the first metal layer 81 opposite to the first gate 61 forms the drain 13 / source 15 of the first transistor 11. The first bit line 21 and the drain 13 / source 15 of the first transistor 11 can be fabricated simultaneously, simplifying the semiconductor structure fabrication steps.

[0167] A second metal layer 82 is formed on the channel 14 of the second interconnect layer 47 and the second gate 62, which are disposed on the same layer. The second metal layers 82 on the channel 14 of the second interconnect layer 47 and the second gate 62, which are disposed on different layers, are spaced apart. That is, the second metal layers 82 corresponding to the second interconnect layer 47 and the second gate 62 are integrally formed along a second direction, and the second metal layers 82 are stacked and spaced apart along a third direction. The second metal layer 82 serves as the second bit line 23, and the second metal layer 82 opposite to the second gate 62 forms the drain 13 / source 15 of the second transistor 12. The second bit line 23 and the drain 13 / source 15 of the second transistor 12 can be fabricated simultaneously, further simplifying the semiconductor structure fabrication steps.

[0168] Step S24: Form a first bit line and a second bit line extending along the second direction; the first bit line covers the first metal layer, and the second bit line covers the second metal layer.

[0169] The first bit line 21 extends along the second direction, is stacked along the third direction and spaced apart, and each first bit line 21 covers the first metal layer 81 located in the same row along the second direction. The second bit lines 23 extend along the second direction, are stacked along the third direction and spaced apart, and each second bit line 23 covers the second metal layer 82 located in the same row along the second direction.

[0170] Step S25: Form a third metal layer and a fourth metal layer. The third metal layer covers the channel located near the first end of the first gate, and the fourth metal layer covers the channel at the second end of the second gate. The third metal layer is spaced apart from the first metal layer, and the fourth metal layer is spaced apart from the second metal layer. The fourth metal layer is in contact with the first end of the first gate.

[0171] See Figure 19 and Figure 20The third metal layer 83 covers the outer periphery of the channel 14 at the first end of the first gate 61, and forms the drain 13 or source 15 of the first transistor 11. The fourth metal layer 84 covers the end face of the channel 14 near the first end of the second gate 62, and the outer periphery near the end face, and forms the drain 13 or source 15 of the second transistor 12.

[0172] In some possible implementations, forming a third metal layer and a fourth metal layer (step S25) includes:

[0173] Step S25-1: A fourth sacrificial layer is formed between the first support layer and the second isolation layer, and between the second isolation layer and the third support layer, the fourth sacrificial layer covering the first connecting layer and the second connecting layer.

[0174] See Figure 13 and Figure 19 The fourth sacrificial layer 75 is filled between the first support layer 51 and the second isolation layer 71, and between the second isolation layer 72 and the third support layer 53. After the fourth sacrificial layer 75 is formed, the channels 14 on the first connecting layer 46 and the second connecting layer 47 are not exposed. It is understood that before forming the fourth sacrificial layer 75, the process also includes removing the third sacrificial layer 74 to expose the channels 14.

[0175] In some possible examples, after the fourth sacrificial layer 75 is formed, a second barrier layer 76 is also formed on the fourth sacrificial layer 75. The second barrier layer 76 also covers the second isolation layer 71, the first support layer 51, the second isolation layer 72 and the third support layer 53. The material of the second barrier layer 76 is relatively hard, which can reduce the damage to the fourth sacrificial layer 75 and the channel 14 located inside the fourth sacrificial layer 75 when the third metal layer 83 and the fourth metal layer 84 are formed.

[0176] Step S25-2: A third metal layer is formed on the channel of the first gate, and a fourth metal layer is formed on the channel of the second gate.

[0177] See Figure 5 and Figure 20 The third metal layer 83 forms the other terminal of the drain 13 or source 15 of the first transistor 11, and the fourth metal layer 84 forms the other terminal of the drain 13 or source 15 of the second transistor 12. For example, the third metal layer 83 forms the source 15 of the first transistor 11, and the fourth metal layer 84 forms the drain 13 of the second transistor 12.

[0178] Step S26: Form a first word line and a second word line extending along a third direction; the first word line covers the third metal layer, and the second word line covers the first end of the second gate.

[0179] See Figure 5 and Figure 20 The first word line 22 extends along a third direction, is arranged along a second direction and is spaced apart, and each first word line 21 covers the third metal layer 83 located in the same column along the third direction. The second word line 24 extends along a third direction, is arranged along the second direction and is spaced apart, and each second word line 24 covers the end of the second gate 62 located in the same column along the third direction.

[0180] In summary, the semiconductor structure fabrication method provided in this disclosure, by forming an electrically connected first transistor 11 and a second transistor 12, both extending along a first direction parallel to the substrate 30, facilitates the fabrication of the first transistor 11 and the second transistor 12, improving the yield of the semiconductor structure. It also increases the number of stacked first transistors 11 and second transistors 12, thereby increasing the storage capacity of the semiconductor structure. Furthermore, by using one of the first transistors 11 and the second transistor 12 as a storage node to form a 2TOC semiconductor structure, the volume occupied by the storage cell is reduced, thereby increasing the storage density of the semiconductor structure.

[0181] The embodiments or implementation methods described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples.

[0182] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A 2T0C semiconductor structure, characterized in that, include: Substrate; A memory cell array located on the substrate, the memory cell array including a plurality of transistor cells, each of the transistor cells including a first transistor and a second transistor extending along a first direction and electrically connected; The first direction is parallel to the substrate; The first bit line extends through the memory cell array and is electrically connected to the first transistor; the first bit line extends along a second direction, passing through a plurality of the first transistors arranged along the second direction, the second direction being parallel to the substrate; The second bit line extends through the memory cell array and is electrically connected to the second transistor; the second bit line extends along the second direction and passes through a plurality of the second transistors arranged along the second direction; The first word line is electrically connected to the first transistor; The second word line is electrically connected to the second transistor; The first bit line, the first word line, the second bit line, and the second word line each have multiple lines; Each of the first bit lines is electrically connected to a plurality of first transistors located in the same row along the second direction; each of the first word lines is electrically connected to a plurality of first transistors located in the same column along a third direction; the third direction is perpendicular to the substrate; Each second bit line is electrically connected to a plurality of second transistors located in the same row along the second direction; each second word line is electrically connected to a plurality of second transistors located in the same column along the third direction; Both the first transistor and the second transistor include: The channel has an internal space for containment; A gate has a first end and a second end opposite to each other along the first direction, wherein the first end of the gate is located outside the receiving space and the second end of the gate is located inside the receiving space; A dielectric layer is located between the gate and the channel, insulating and isolating the gate and the channel; The source electrode is located at one end of the channel; The drain is disposed at the other end of the channel, and the drain and the source are spaced apart along the first direction; The gate of the first transistor is electrically connected to the drain of the second transistor.

2. The semiconductor structure according to claim 1, characterized in that, The multiple first word lines and the multiple second word lines all extend along the third direction and are electrically isolated from each other; The plurality of first bit lines and the plurality of second bit lines extend along a second direction and are electrically isolated from each other; and / or, the ends of the plurality of first bit lines away from the memory cell array form a first step, and the ends of the plurality of second bit lines away from the memory cell array form a second step.

3. The semiconductor structure according to claim 2, characterized in that, The first step and the second step are located on the same side of the storage cell array.

4. The semiconductor structure according to claim 1, characterized in that, The channel includes a top wall, a bottom wall, and a side wall that enclose the receiving space, the top wall having an opening, and the second end of the gate being exposed outside the receiving space through the opening; The source electrode covers the bottom wall of the channel and a portion of the sidewall near the bottom wall, and the drain electrode covers the top wall of the channel and a portion of the sidewall near the top wall.

5. The semiconductor structure according to claim 1, characterized in that, The channel material includes indium gallium zinc oxide, polycrystalline silicon, monocrystalline silicon, silicon germanide, or silicon carbide.

6. The semiconductor structure according to claim 1, characterized in that, The first bit line is electrically connected to the drain of the first transistor, and the first word line is electrically connected to the source of the first transistor. The second bit line is electrically connected to the source of the second transistor, and the second word line is electrically connected to the gate of the second transistor.

7. The semiconductor structure according to claim 6, characterized in that, Along the first direction, a first isolation layer is further provided between the second bit line and the second word line to insulate and isolate the second bit line and the second word line, and the second transistor passes through the first isolation layer.

8. The semiconductor structure according to any one of claims 1-3, characterized in that, The semiconductor structure further includes a first bit line plug, a second bit line plug, a first word line plug, and a second word line plug extending along the third direction; The first bit line plug, the second bit line plug, the first word line plug, and the second word line plug are electrically connected to the first bit line, the second bit line, the first word line, and the second word line, respectively.

9. A method for fabricating a 2T0C semiconductor structure, characterized in that, include: Provide substrate; A memory cell array, a first bit line, a second bit line, a first word line, and a second word line are formed on the substrate; The memory cell array includes a plurality of transistor cells, each transistor cell including a first transistor and a second transistor that extend along a first direction and are electrically connected; the first direction is parallel to the substrate; The first bit line passes through the memory cell array and is electrically connected to the first transistor; the first bit line extends along a second direction, passing through a plurality of first transistors arranged along the second direction, the second direction being parallel to the substrate; the second bit line passes through the memory cell array and is electrically connected to the second transistor; the second bit line extends along the second direction, passing through a plurality of second transistors arranged along the second direction; the first word line is electrically connected to the first transistor; the second word line is electrically connected to the second transistor. The first bit line, the first word line, the second bit line, and the second word line each have multiple lines; Each of the first bit lines is electrically connected to a plurality of first transistors located in the same row along the second direction; each of the first word lines is electrically connected to a plurality of first transistors located in the same column along a third direction; the third direction is perpendicular to the substrate; Each second bit line is electrically connected to a plurality of second transistors located in the same row along the second direction; each second word line is electrically connected to a plurality of second transistors located in the same column along the third direction; Both the first transistor and the second transistor include: The channel has an internal space for containment; A gate has a first end and a second end opposite to each other along the first direction, wherein the first end of the gate is located outside the receiving space and the second end of the gate is located inside the receiving space; A dielectric layer is located between the gate and the channel, insulating and isolating the gate and the channel; The source electrode is located at one end of the channel; The drain is disposed at the other end of the channel, and the drain and the source are spaced apart along the first direction; The gate of the first transistor is electrically connected to the drain of the second transistor.

10. The manufacturing method according to claim 9, characterized in that, A memory cell array, a first bit line, a second bit line, a first word line, and a second word line are formed on the substrate, including: A first gate array and a second gate array are formed on the substrate at intervals along the first direction; the first gate array includes a plurality of first gates at intervals along the second direction and at intervals along the third direction, and the second gate array includes a plurality of second gates at intervals along the second direction and at intervals along the third direction. A dielectric layer is formed on the first gate and the second gate, and a channel is formed on the dielectric layer; the first ends of the first gate and the second gate both extend out of the channel; A first metal layer and a second metal layer are formed, the first metal layer covering the channel located at the second end of the first gate, and the second metal layer covering the channel near the first end of the second gate; the second end is opposite to the first end along the first direction; A first bit line and a second bit line are formed extending along a second direction; the first bit line covers the first metal layer, and the second bit line covers the second metal layer. A third metal layer and a fourth metal layer are formed, the third metal layer covering the channel located near the first end of the first gate, the fourth metal layer covering the channel at the second end of the second gate, the third metal layer being spaced apart from the first metal layer, the fourth metal layer being spaced apart from the second metal layer, and the fourth metal layer being in contact with the first end of the first gate; A first word line and a second word line are formed extending along the third direction; the first word line covers the third metal layer, and the second word line covers the first end of the second gate.

11. The manufacturing method according to claim 10, characterized in that, Forming a first gate array and a second gate array spaced apart along the first direction on the substrate includes: A first stacked structure is formed on the substrate, the first stacked structure having a first region and a second region, the first stacked structure including a first sacrificial layer and an initial gate layer alternately disposed sequentially along the third direction; A portion of the first stacked structure is removed, a first trench extending in a first direction is formed in the first region, and a second trench extending in a second direction is formed in the second region; the first trench divides the initial gate layer located in the first region into a plurality of initial gate pillars, and the second trench divides the initial gate layer located in the second region into a first interconnect layer and a second interconnect layer. The plurality of initial gate pillars are divided along the first direction into the first gate array and the second gate array.

12. The manufacturing method according to claim 11, characterized in that, Dividing the initial gate layer located in the first region into the first gate array and the second gate array along the first direction includes: A second sacrificial layer is formed within the first trench and the second trench; A first support layer, a second support layer, and a third support layer are formed in the second sacrificial layer and the first stacked structure, which are spaced apart along the first direction. The first support layer connects the initial gate pillar and the first connection layer, the third support layer connects the initial gate pillar and the second connection layer, and the second support layer connects the initial gate pillar. Remove a portion of the second sacrificial layer, the first sacrificial layer, and the initial gate pillar on the side of the second support layer in the first region to form the first gate array and the second gate array; Remove the remaining second sacrificial layer and the first sacrificial layer.

13. The manufacturing method according to claim 12, characterized in that, A dielectric layer is formed on the first gate and the second gate, and a channel is formed on the dielectric layer, including: A dielectric layer is formed on the first gate, the second gate, the first interconnect layer, and the second interconnect layer.

14. The manufacturing method according to claim 13, characterized in that, Forming a first metal layer and a second metal layer includes: A second isolation layer is formed between the first support layer and the second support layer, and a third isolation layer is formed between the second support layer and the third support layer; A third sacrificial layer is formed between the second isolation layer and the second support layer, and between the second support layer and the third isolation layer; The first metal layer is formed on the channel of the first gate, and the second metal layer is formed on the channel of the second gate.

15. The manufacturing method according to claim 14, characterized in that, Forming a third metal layer and a fourth metal layer, including: A fourth sacrificial layer is formed between the first support layer and the second isolation layer, and between the third isolation layer and the third support layer, the fourth sacrificial layer covering the first connecting layer and the second connecting layer; The third metal layer is formed on the channel of the first gate, and the fourth metal layer is formed on the channel of the second gate.

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