Display panel, display device

Abstract

A display panel and a display device, the display panel comprising a pixel driving circuit, the pixel driving circuit comprising: a driving transistor (T3), a first capacitor (C1), a second capacitor (C2), a first transistor (T1), and a fifth transistor (T5), a first electrode of the driving transistor (T3) being connected to a first power supply line (VDD1); a first electrode of the first capacitor (C1) being connected to a gate electrode of the driving transistor (T3); a first electrode of the second capacitor (C2) being connected to a second electrode of the first capacitor (C1); a first electrode of the first transistor (T1) being connected to a data line (Da), and a second electrode of the first transistor (T1) being connected to a second electrode of the second capacitor (C2); and a first electrode of the fifth transistor (T5) being connected to the second electrode of the first capacitor (C1), and a second electrode of the fifth transistor (T5) being connected to a stable power supply end.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] In related technologies, display panels generally include pixel driving circuits. The pixel driving circuits need to compensate the threshold of the driving transistors during the threshold compensation stage. However, due to the limited duration of the threshold compensation stage, the threshold compensation effect of the driving transistors is poor.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] According to one aspect of this disclosure, a display panel is provided, wherein the display panel includes a pixel driving circuit, the pixel driving circuit including: a driving transistor, a first capacitor, a second capacitor, a first transistor, and a fifth transistor; a first electrode of the driving transistor is connected to a first power supply line; a first electrode of the first capacitor is connected to the gate of the driving transistor; a first electrode of the second capacitor is connected to a second electrode of the first capacitor; a first electrode of the first transistor is connected to a data line, and a second electrode of the first transistor is connected to the second electrode of the second capacitor; a first electrode of the fifth transistor is connected to the second electrode of the first capacitor, and a second electrode of the fifth transistor is connected to a stable power supply terminal.

[0005] In one exemplary embodiment of this disclosure, the display panel further includes: a substrate, a first conductive layer, a second conductive layer, and a third conductive layer. The first conductive layer is located on one side of the substrate and includes a first conductive portion, which is used to form the gate of the driving transistor and the first electrode of the first capacitor. The second conductive layer is located on the side of the first conductive layer away from the substrate and includes a second conductive portion. The orthographic projection of the second conductive portion on the substrate at least partially overlaps with the orthographic projection of the first conductive portion on the substrate. The second conductive portion is used to form the second electrode of the first capacitor and the first electrode of the second capacitor. The third conductive layer is located on the side of the second conductive layer away from the substrate and includes a third conductive portion. The orthographic projection of the third conductive portion on the substrate at least partially overlaps with the orthographic projection of the second conductive layer on the substrate, and the orthographic projection of the third conductive portion on the substrate at least partially overlaps with the orthographic projection of the first conductive portion on the substrate. The third conductive portion is used to form the second electrode of the second capacitor.

[0006] In one exemplary embodiment of this disclosure, the orthographic projection of the second conductive portion on the substrate covers the overlapping area of ​​the orthographic projections of the first conductive portion and the third conductive portion on the substrate.

[0007] In one exemplary embodiment of this disclosure, the display panel further includes: a fourth conductive layer and a fifth conductive layer, wherein the fourth conductive layer is located on the side of the third conductive layer opposite to the substrate; the fifth conductive layer is located on the side of the fourth conductive layer opposite to the substrate, and the fifth conductive layer includes the data line, wherein the orthographic projection of the data line on the substrate extends along a second direction.

[0008] In one exemplary embodiment of this disclosure, the orthographic projection of the data line on the substrate does not overlap with the orthographic projection of the third conductive portion on the substrate.

[0009] In one exemplary embodiment of this disclosure, the display panel includes a plurality of pixel driving circuits distributed in a first direction, wherein the orthographic projections of the third conductive portions in adjacent pixel driving circuits on the substrate are adjacent and spaced apart in the first direction, and the first direction and the second direction intersect; at least a portion of the orthographic projection of the data line on the substrate is located between the orthographic projections of adjacent third conductive portions on the substrate.

[0010] In one exemplary embodiment of this disclosure, the display panel further includes: an active layer located between the substrate and the first conductive layer, the active layer including a ninth active portion connected to a first electrode of the first transistor, and the data line connected to the ninth active portion through at least one via; the first conductive layer further includes a reset signal line, the orthographic projection of the reset signal line on the substrate extending along a first direction, and the reset signal line connected to the gate of the first transistor; in the first direction, the orthographic projection of the via on the substrate is located between the orthographic projections of adjacent third conductive portions on the substrate, and the orthographic projection of the via on the substrate is at least partially located on the side of the orthographic projection of the reset signal line on the substrate away from the orthographic projection of the third conductive portion on the substrate.

[0011] In one exemplary embodiment of this disclosure, the fourth conductive layer further includes a plurality of first power lines, the orthographic projections of the plurality of first power lines on the substrate extending along the second direction and spaced apart along the first direction, the first direction and the second direction intersecting; the third conductive layer further includes a plurality of second power lines, the orthographic projections of the plurality of second power lines on the substrate extending along the first direction and spaced apart along the second direction; at least a portion of the first power lines and at least a portion of the second power lines are connected through vias.

[0012] In one exemplary embodiment of this disclosure, the fifth conductive layer further includes: a plurality of third power lines, wherein the orthographic projections of the plurality of third power lines on the substrate extend along the second direction and are spaced apart along the first direction; wherein the orthographic projections of the third power lines on the substrate and the orthographic projections of the first power lines on the substrate at least partially overlap, and the third power lines are connected to the first power lines through vias.

[0013] In one exemplary embodiment of this disclosure, the display panel includes a plurality of pixel driving circuits distributed in a first direction, and the fourth conductive layer includes a plurality of first power lines corresponding one-to-one with the plurality of pixel driving circuits. The first power lines are connected to driving transistors in their corresponding pixel driving circuits, and the first direction and the second direction intersect. The orthographic projections of the plurality of first power lines on the substrate extend along the second direction and are spaced apart along the first direction. The third conductive portion includes a first side facing the data line, and the orthographic projection of the first side on the substrate extends along the second direction. The data line includes a first extension portion, and the first extension portion and the first side are disposed opposite to each other in the first direction. Among the plurality of first power lines, one of the first power lines has an orthographic projection on the substrate that covers the orthographic projection of the first extension portion on the substrate and also covers the orthographic projection of the first side on the substrate.

[0014] In an exemplary embodiment of this disclosure, the orthographic projection of the third conductive portion on the substrate is located between the orthographic projection of the data line on the substrate and the orthographic projection of the first power line on the substrate. The first power line includes a second extension and a first protrusion. The orthographic projection of the second extension on the substrate extends along a second direction. The first protrusion is connected to the second extension, and the orthographic projection of the first protrusion on the substrate is located on a side of the orthographic projection of the second extension on the substrate that is opposite to the orthographic projection of the data line on the substrate. The plurality of pixel driving circuits includes a first pixel driving circuit and a second pixel driving circuit adjacent to each other in a first direction. The orthographic projection of the first power line in the first pixel driving circuit on the substrate is located on a side of the orthographic projection of the data line in the second pixel driving circuit that is away from the orthographic projection of the first power line in the second pixel driving circuit on the substrate. The orthographic projection of the first protrusion on the first power line in the first pixel driving circuit on the substrate covers the orthographic projection of the first extension on the data line in the second pixel driving circuit on the substrate and the orthographic projection of the first side of the third conductive portion in the second pixel driving circuit on the substrate.

[0015] In one exemplary embodiment of this disclosure, the display panel includes a plurality of pixel driving circuits arrayed along a first direction and a second direction, wherein the first direction is a row direction and the second direction is a column direction; each pixel driving circuit further includes a second transistor, wherein a first terminal of the second transistor is connected to the gate of the driving transistor, and a second terminal is connected to the second terminal of the driving transistor. The display panel further includes a substrate and a first conductive layer, the first conductive layer being located on one side of the substrate, the first conductive layer including a gate driving signal line, the gate driving signal line extending along the first direction by its orthogonal projection onto the substrate, and the gate driving signal line connecting the gate of the second transistor in the current row of pixel driving circuits and the gate of the fifth transistor in the next row of pixel driving circuits.

[0016] In one exemplary embodiment of this disclosure, the display panel further includes a light-emitting unit, and the pixel driving circuit is used to drive the light-emitting unit to emit light. The pixel driving circuit further includes a sixth transistor, the first electrode of the sixth transistor is connected to a first initial signal line, and the second electrode is connected to the first electrode of the light-emitting unit. The gate driving signal line is connected to the gate of the sixth transistor in the current row of pixel driving circuits and the gate of the fifth transistor in the next row of pixel driving circuits.

[0017] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a fourth transistor, the first terminal of which is connected to a first initial signal line, and the second terminal of which is connected to the gate of the driving transistor. The display panel further includes a substrate and a first conductive layer, the first conductive layer being located on one side of the substrate. The first conductive layer includes a reset signal line, the orthographic projection of which on the substrate extends along a first direction, and the reset signal line is simultaneously connected to the gate of the first transistor and the gate of the fourth transistor.

[0018] In one exemplary embodiment of this disclosure, the display panel further includes: a second conductive layer and a fifth conductive layer. The second conductive layer is located on the side of the first conductive layer opposite to the substrate. The second conductive layer includes a plurality of first initial signal lines, the orthographic projections of the plurality of first initial signal lines on the substrate extending along a first direction and spaced apart along a second direction, the first direction intersecting the second direction. The fifth conductive layer is located on the side of the second conductive layer opposite to the substrate. The fifth conductive layer includes a plurality of second initial signal lines, the orthographic projections of the plurality of second initial signal lines on the substrate extending along the first direction and spaced apart along the second direction. At least a portion of the first initial signal lines and at least a portion of the second initial signal lines are connected through vias.

[0019] In one exemplary embodiment of this disclosure, the display panel further includes an active layer located between the substrate and the first conductive layer. The active layer includes a tenth active portion, an eleventh active portion, and a twelfth active portion. The tenth active portion is used to form a first channel region of the fifth transistor, the eleventh active portion is used to form a second channel region of the fifth transistor, and the twelfth active portion is connected between the tenth active portion and the eleventh active portion. The orthographic projection of the second conductive portion on the substrate at least partially overlaps with the orthographic projection of the twelfth active portion on the substrate.

[0020] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a fourth transistor, the first terminal of which is connected to a first initial signal line, and the second terminal of which is connected to the gate of the driving transistor. The display panel further includes an active layer located between the substrate and the first conductive layer. The active layer includes a thirteenth active portion, a fourteenth active portion, and a fifteenth active portion. The thirteenth active portion is used to form a first channel region of the fourth transistor, the fourteenth active portion is used to form a second channel region of the fourth transistor, and the fifteenth active portion is connected between the thirteenth and fourteenth active portions. The orthographic projection of the second conductive portion on the substrate at least partially overlaps with the orthographic projection of the fifteenth active portion on the substrate.

[0021] In one exemplary embodiment of this disclosure, the display panel includes a plurality of pixel driving circuits, including a first pixel driving circuit and a second pixel driving circuit that are adjacent to each other in a first direction; a first power line in the first pixel driving circuit is connected to the second electrode of the fifth transistor in the second pixel driving circuit.

[0022] In one exemplary embodiment of this disclosure, the display panel further includes a light-emitting unit, and the pixel driving circuit is used to drive the light-emitting unit to emit light. The pixel driving circuit further includes a seventh transistor and an eighth transistor. The first electrode of the seventh transistor is connected to the first power line, and the second electrode is connected to the second electrode of the first transistor. The first electrode of the eighth transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the first electrode of the light-emitting unit. The display panel further includes a substrate and a first conductive layer. The first conductive layer is located on one side of the substrate and includes an enable signal line. The orthogonal projection of the enable signal line on the substrate extends along a first direction, and the enable signal line connects the gates of the seventh transistor and the eighth transistor.

[0023] In one exemplary embodiment of this disclosure, the display panel further includes a light-emitting unit, and the pixel driving circuit is used to drive the light-emitting unit to emit light. The pixel driving circuit further includes a seventh transistor and an eighth transistor. The first electrode of the seventh transistor is connected to a first initial signal line, and the second electrode is connected to the second electrode of the first transistor. The first electrode of the eighth transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the first electrode of the light-emitting unit. The display panel further includes a substrate and a first conductive layer. The first conductive layer is located on one side of the substrate and includes an enable signal line. The orthogonal projection of the enable signal line on the substrate extends along a first direction, and the enable signal line is simultaneously connected to the gates of the seventh transistor and the eighth transistor.

[0024] According to one aspect of this disclosure, a display device is provided, wherein the display panel described above is included.

[0025] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0026] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0027] Figure 1 This is a schematic diagram of an exemplary embodiment of the pixel driving circuit in the display panel of this disclosure;

[0028] Figure 2 This is a schematic diagram of the pixel driving circuit in another exemplary embodiment of the display panel disclosed herein;

[0029] Figure 3 for Figure 2 The timing diagram of each node in a driving method of the pixel driving circuit shown is shown.

[0030] Figure 4 This is a structural layout diagram of an exemplary embodiment of the display panel disclosed herein;

[0031] Figure 5 for Figure 4 The structural layout of the active layer;

[0032] Figure 6 for Figure 4 Structural layout of the first conductive layer;

[0033] Figure 7 for Figure 4 Structural layout of the second conductive layer;

[0034] Figure 8 for Figure 4 Structural layout of the third conductive layer;

[0035] Figure 9 for Figure 4 Structural layout of the fourth conductive layer;

[0036] Figure 10 for Figure 4 The structural layout of the fifth conductive layer;

[0037] Figure 11 for Figure 4 The structural layout of the active layer and the first conductive layer is shown.

[0038] Figure 12 for Figure 4 The structural layout includes an active layer, a first conductive layer, and a second conductive layer.

[0039] Figure 13 for Figure 4The structural layout includes an active layer, a first conductive layer, a second conductive layer, and a third conductive layer.

[0040] Figure 14 for Figure 4 The structural layout includes an active layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer.

[0041] Figure 15 for Figure 4 A partial sectional view along the dashed line AA in the center;

[0042] Figure 16 This is a schematic diagram of the pixel driving circuit in another exemplary embodiment of the display panel disclosed herein;

[0043] Figure 17 This is a structural layout diagram of another exemplary embodiment of the display panel disclosed herein;

[0044] Figure 18 for Figure 17 The structural layout of the active layer;

[0045] Figure 19 for Figure 17 Structural layout of the first conductive layer;

[0046] Figure 20 for Figure 17 Structural layout of the second conductive layer;

[0047] Figure 21 for Figure 17 Structural layout of the third conductive layer;

[0048] Figure 22 for Figure 17 Structural layout of the fourth conductive layer;

[0049] Figure 23 for Figure 17 The structural layout of the fifth conductive layer;

[0050] Figure 24 for Figure 17 The structural layout of the active layer and the first conductive layer is shown.

[0051] Figure 25 for Figure 17 The structural layout includes an active layer, a first conductive layer, and a second conductive layer.

[0052] Figure 26 for Figure 17 The structural layout includes an active layer, a first conductive layer, a second conductive layer, and a third conductive layer.

[0053] Figure 27 for Figure 17The structural layout includes an active layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer.

[0054] Figure 28 for Figure 17 A partial sectional view along the dashed line AA. Detailed Implementation

[0055] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0056] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0057] This exemplary embodiment provides a display panel including a pixel driving circuit, such as... Figure 1 The diagram shown is a schematic representation of an exemplary embodiment of the pixel driving circuit in the display panel of this disclosure. The pixel driving circuit includes: a driving transistor T3, a first capacitor C1, a second capacitor C2, a first transistor T1, and a fifth transistor T5. The first electrode of the driving transistor T3 is connected to a first power supply terminal VDD; the first electrode of the first capacitor C1 is connected to the gate of the driving transistor T3; the first electrode of the second capacitor C2 is connected to the second electrode of the first capacitor C1; the first electrode of the first transistor T1 is connected to a data signal terminal Da, and its second electrode is connected to the second electrode of the second capacitor C2; the first electrode of the fifth transistor T5 is connected to the second electrode of the first capacitor C1, and its second electrode is connected to a stable power supply terminal Vx.

[0058] In this exemplary embodiment, when the fifth transistor T5 is turned on, the stable power supply terminal Vx writes a stable voltage to the second electrode of the first capacitor C1 and the first electrode of the second capacitor C2. Due to the shielding effect of the second electrodes of the first capacitors C1 and C2, the first electrodes of the first and second capacitors are not coupled to each other. When the fifth transistor T5 is turned off, the second electrodes of the first capacitors C1 and C2 are in a floating state, and can be coupled to each other. This pixel driving circuit can write a threshold compensation voltage to the gate of the driving transistor T3 and a data signal to the second electrode of the first transistor T1 at different time periods when the fifth transistor is on. When the fifth transistor is off, the pixel driving circuit can couple the data signal from the second electrode of the first transistor T1 to the gate of the driving transistor T3. Therefore, this pixel driving circuit can arbitrarily set the duration of the threshold compensation stage while keeping the data writing duration constant, i.e., while ensuring that the refresh rate of the display panel remains constant, thereby achieving a better threshold compensation effect.

[0059] In this exemplary embodiment, as Figure 1 As shown, the first transistor T1, the driving transistor T3, and the fifth transistor T5 can all be P-type transistors. It should be understood that in other exemplary embodiments, the aforementioned transistors can also be N-type transistors. The stable power supply terminal Vx can be a signal terminal at the same potential as the first power line. Furthermore, the stable power supply terminal Vx can also be other stable power supply terminals with constant voltage; for example, the stable power supply terminal Vx can be a signal terminal at the same potential as the initial signal line.

[0060] It should be noted that the transistors used in all embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. In all embodiments of this disclosure, the first electrode can be the drain electrode and the second electrode can be the source electrode, or the first electrode can be the source electrode and the second electrode can be the drain electrode. In this exemplary embodiment, "connection" can include physical connection and electrical connection.

[0061] like Figure 2The diagram shown is a schematic of the pixel driving circuit in another exemplary embodiment of the display panel disclosed herein. This pixel driving circuit is used to drive an OLED light-emitting unit. The pixel driving circuit may include a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a first capacitor C1, and a second capacitor C2. The first terminal of the driving transistor T3 is connected to the first power supply terminal VDD, and its gate is connected to the first node N1. The first capacitor C1 is connected between the first node N1 and the second node N2. The second capacitor C2 is connected between the second node N2 and the third node N3. The first terminal of the first transistor is connected to the data signal terminal Da, its second terminal is connected to the third node N3, and its gate is connected to the reset signal terminal Re. The first terminal of the second transistor T2 is connected to the first node N1, its second terminal is connected to the second terminal of the driving transistor T3, and its gate is connected to the second gate driving signal terminal Gate2. The first terminal of the fourth transistor T4 is connected to the initial signal terminal Vinit, its second terminal is connected to the first node N1, and its gate is connected to the reset signal terminal Re. The fifth transistor... The first terminal of transistor T5 is connected to the second node N2, the second terminal is connected to the first power supply terminal VDD, and the gate is connected to the first gate drive signal terminal Gate1; the first terminal of the sixth transistor T6 is connected to the initial signal terminal Vinit, the second terminal is connected to the first electrode of the light-emitting unit OLED, and the gate is connected to the second gate drive signal terminal Gate2; the first terminal of the seventh transistor is connected to the first power supply terminal VDD, the second terminal is connected to the third node N3, and the gate is connected to the enable signal terminal EM; the first terminal of the eighth transistor T8 is connected to the second terminal of the driving transistor T3, the second terminal is connected to the first electrode of the light-emitting unit OLED, and the gate is connected to the enable signal terminal EM; the second electrode of the light-emitting unit OLED is connected to the second power supply terminal VSS. These transistors can be P-type transistors, and the voltage of the first power supply terminal VDD can be greater than the voltage of the second power supply terminal VSS. In this exemplary embodiment, the first power supply terminal VDD can form the aforementioned stable power supply terminal. It should be understood that in other exemplary embodiments, the second terminal of the fifth transistor T5 can also be connected to other stable power supply terminals.

[0062] like Figure 3 As shown, Figure 2The diagram shows the timing of each node in a driving method of the pixel driving circuit. EM is the timing diagram for the enable signal terminal; Re is the timing diagram for the reset signal terminal; Gate1 is the timing diagram for the first gate driving signal terminal; and Gate2 is the timing diagram for the second gate driving signal terminal. The driving method of this pixel driving circuit can include four stages: data writing stage t1, threshold compensation node t2, buffering stage t3, and light emission stage t4. In the data writing stage t1: the reset signal terminal Re and the first gate driving signal terminal Gate1 output low-level signals; the enable signal terminal EM and the second gate driving signal terminal Gate2 output high-level signals; the first transistor T1, the fourth transistor T4, and the fifth transistor T5 are turned on; the data signal terminal Da writes a data signal to the third node N3; the first power supply terminal VDD writes a power supply voltage to the second node N2; and the initial signal terminal Vinit writes an initial signal to the first node N1. At threshold compensation node t2: the first gate drive signal terminal Gate1 and the second gate drive signal terminal Gate2 output low-level signals, the enable signal terminal EM and the reset signal terminal Re output high-level signals, the fifth transistor T5, the second transistor T2, and the sixth transistor T6 are turned on, and the first power supply terminal VDD writes voltage Vdd+Vth to the first node N1 through the driving transistor T3, where Vdd is the voltage of the first power supply terminal VDD, and Vth is the threshold voltage of the driving transistor T3. At the same time, the voltage of the third node N3 remains unchanged. In addition, the initial signal terminal Vinit writes the initial signal to the first electrode of the light-emitting unit through the sixth transistor T6. At buffer stage t3: the second gate drive signal terminal Gate2 outputs a low-level signal, the first gate drive signal terminal Gate1, the enable signal terminal EM, and the reset signal terminal Re output high-level signals, the fifth transistor T5 is turned off, and the second node is in a floating state. During the light-emitting phase t4: the enable signal terminal EM outputs a low-level signal, the first gate drive signal terminal Gate1, the second gate drive signal terminal Gate2, and the reset signal terminal Re output high-level signals. The seventh transistor T7 and the eighth transistor T8 are turned on. The voltage of the third node N3 changes from Vdata to Vdd, where Vdata is the voltage of the data signal. Under the coupling effect of the second capacitor C2, the voltage of the second node N2 changes to Vdd + Vdd - Vdata. Under the coupling effect of the first capacitor C1, the voltage of the first node N1 changes to Vdd + Vth + Vdd - Vdata. According to the formula for the output current of the driving transistor in the pixel driving circuit, I = (μWCox / 2L)(Vgs - Vth). 2Where μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the width of the driving transistor channel; L is the length of the driving transistor channel; Vgs is the gate-source voltage difference of the driving transistor; and Vth is the threshold voltage of the driving transistor. In the pixel driving circuit of this disclosure, the output current of the driving transistor I = (μWCox / 2L)(Vdd + Vth + Vdd - Vdata - Vdd - Vth) 2 =(μWCox / 2L)(Vdd-Vdata) 2 This pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.

[0063] It should be understood that, in other exemplary embodiments, at least some of the transistors among the first transistor T1, second transistor T2, fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, and eighth transistor T8 can be N-type transistors. N-type transistors have lower turn-off leakage current, thereby improving leakage current issues at each node in the pixel driving circuit. For example, in other exemplary embodiments, the second transistor T2 and the fourth transistor T4 can be N-type transistors, which can reduce the leakage current of the first node N1 through the second transistor T2 and the fourth transistor T4 during the light-emitting phase. As another example, the first transistor T1 and the seventh transistor T7 can be N-type transistors, which can reduce the leakage current of the third node through the first transistor T1 and the seventh transistor T7 during the threshold compensation node t2 and the buffering phase t3. As yet another example, the eighth transistor T8 can also be an N-type transistor, which can reduce the leakage current of the first node N1 sequentially through the second transistor T2 and the eighth transistor T8 during the light-emitting phase. For example, the fifth transistor T5 and the sixth transistor T6 can also be N-type transistors. This configuration can reduce the leakage current through the fifth transistor T5 at the first power supply terminal VDD during the light-emitting stage, and the leakage current through the sixth transistor T6 at the second terminal of the driving transistor during the light-emitting stage.

[0064] In this exemplary embodiment, the display panel may further include: a substrate, an active layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer stacked sequentially, wherein an insulating layer may be disposed between the aforementioned layers. Figure 4-14 As shown, Figure 4 This is a structural layout diagram of an exemplary embodiment of the display panel disclosed herein. Figure 5 for Figure 4 The structural layout of the active layer is shown. Figure 6 for Figure 4 The structural layout of the first conductive layer in the middle. Figure 7 for Figure 4 Layout of the second conductive layer. Figure 8 for Figure 4 The structural layout of the third conductive layer in the middle. Figure 9 for Figure 4 The structural layout of the fourth conductive layer in the middle. Figure 10 for Figure 4 Schematic diagram of the fifth conductive layer. Figure 11 for Figure 4 The structural layout includes an active layer and a first conductive layer. Figure 12 for Figure 4 The structural layout includes an active layer, a first conductive layer, and a second conductive layer. Figure 13 for Figure 4 The structural layout includes an active layer, a first conductive layer, a second conductive layer, and a third conductive layer. Figure 14 for Figure 4 The diagram shows a structural layout comprising an active layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer. This display panel may include... Figure 2 The pixel driving circuit shown.

[0065] like Figure 4 , 5 As shown in Figure 11, the active layer may include a first active section 61, a third active section 63, a sixth active section 66, a seventh active section 67, an eighth active section 68, a ninth active section 69, a tenth active section 610, an eleventh active section 611, a twelfth active section 612, a thirteenth active section 613, a fourteenth active section 614, a fifteenth active section 615, a sixteenth active section 616, a seventeenth active section 617, and an eighteenth active section 618. The first active portion 61 is used to form the channel region of the first transistor T1, the third active portion 63 is used to form the channel region of the driving transistor T3, the sixth active portion 66 is used to form the channel region of the sixth transistor, the seventh active portion 67 is used to form the channel region of the seventh transistor T7, the eighth active portion 68 is used to form the channel region of the eighth transistor, the tenth active portion 610 is used to form the first channel region of the fifth transistor, the eleventh active portion 611 is used to form the second channel region of the fifth transistor, and the twelfth active portion 612 is connected between the tenth active portion 610 and the eleventh active portion 611. The thirteenth active portion 613 is used to form the first channel region of the fourth transistor, the fourteenth active portion 614 is used to form the second channel region of the fourth transistor, the fifteenth active portion 615 is connected between the fourteenth active portion 614 and the thirteenth active portion 613, the sixteenth active portion 616 is used to form the first channel region of the second transistor T2, the seventeenth active portion 617 is used to form the second channel region of the second transistor T2, the eighteenth active portion 618 is connected between the seventeenth active portion 617 and the sixteenth active portion 616, and the ninth active portion 69 is connected to the end of the first active portion 61 away from the seventh active portion 67. The active layer can be formed of polycrystalline silicon semiconductor, and all of the above transistors can be P-type low-temperature polycrystalline silicon thin-film transistors.

[0066] like Figure 4 ,6 As shown in Figure 11, the first conductive layer may include a gate drive signal line (Gate), a reset signal line (Re), an enable signal line (EM), a protrusion 12, a protrusion 13, and a protrusion 14. The orthographic projections of the gate drive signal line (Gate), the reset signal line (Re), and the enable signal line (EM) on the substrate can all extend along a first direction X, which can be a row direction. The first conductive layer may include multiple gate drive signal lines (Gate), multiple reset signal lines (Re), and multiple enable signal lines (EM). Each row of pixel driving circuits can correspondingly provide one gate drive signal line (Gate), one reset signal line (Re), and one enable signal line (EM). The orthographic projection of the gate drive signal line (Gate) on the substrate can cover the orthographic projections of the sixteenth active portion 616 and the seventeenth active portion 617 on the substrate. A portion of the structure of the gate drive signal line (Gate) can be used to form the two gates of the second transistor. The protrusion 12 is connected to the gate drive signal line Gate. The orthogonal projection of the protrusion 12 onto the substrate covers the orthogonal projection of the sixth active part 66 onto the substrate. A portion of the structure of the protrusion 12 can be used to form the gate of the sixth transistor T6. The orthogonal projection of the enable signal line EM onto the substrate covers the orthogonal projection of the seventh active part 67 onto the substrate. A portion of the structure of the enable signal line EM can be used to form the gate of the seventh transistor T7. The protrusion 14 is connected to the enable signal line. The orthogonal projection of the protrusion 14 onto the substrate covers the orthogonal projection of the eighth active part 68 onto the substrate. A portion of the structure of the protrusion 14 is used to form the gate of the eighth transistor T8. The orthogonal projection of the reset signal line Re onto the substrate covers the orthogonal projections of the thirteenth active part 613 and the fourteenth active part 614 onto the substrate. A portion of the structure of the reset signal line Re is used to form the two gates of the fourth transistor. The protrusion 13 is connected to the reset signal line Re. The orthogonal projection of the protrusion 13 on the substrate covers the orthogonal projection of the first active part 61 on the substrate. A portion of the structure of the protrusion 13 is used to form the gate of the first transistor T1. Figure 3As shown, the signal waveforms on the first gate driving signal terminal Gate1 and the second gate driving signal terminal Gate2 are the same, differing only in timing. Therefore, the orthogonal projection of the gate driving signal line Gate in the previous row pixel driving circuit onto the substrate can cover the orthogonal projection of the eleventh active part 611 in the current row pixel driving circuit onto the substrate. A portion of the structure of the gate driving signal line Gate in the previous row pixel driving circuit can be used to form the second gate of the fifth transistor in the current row pixel driving circuit. The orthogonal projection of the protrusion 12 in the previous row pixel driving circuit onto the substrate can cover the orthogonal projection of the tenth active part 610 in the current row pixel driving circuit onto the substrate. A portion of the structure of the protrusion 12 in the previous row pixel driving circuit can be used to form the first gate of the fifth transistor in the current row pixel driving circuit. This arrangement allows the second and sixth transistors in the previous row pixel driving circuit and the fifth transistor in the current row pixel driving circuit to share a single gate driving signal line, thereby reducing the layout space of the pixel driving circuit and increasing the pixel density of the display panel. Furthermore, the first conductive layer may also include a first conductive portion 11, the orthogonal projection of the first conductive portion 11 on the substrate can cover the orthogonal projection of the third active portion 63 on the substrate, and the first conductive portion 11 can be used to form Figure 2 The first electrode of the first capacitor and the gate of the driving transistor.

[0067] It should be noted that, in this exemplary embodiment, the display panel can use the first conductive layer as a mask to perform conductor treatment on the active layer. That is, the active layer covered by the first conductive layer forms the channel region of the transistor, and the area not covered by the first conductive layer forms a conductor structure. Furthermore, in this exemplary embodiment, the orthographic projection of a structure on the substrate extends along a certain direction. This can be understood as the orthographic projection of the structure on the substrate extending entirely along that direction, that is, the orthographic projection of the structure on the substrate can extend in a straight line or bend along that direction.

[0068] like Figure 4 , 7As shown in Figure 12, the second conductive layer may include a second conductive portion 22 and a first initial signal line Vinit1. The orthographic projection of the second conductive portion 22 on the substrate may at least partially intersect with the orthographic projection of the first conductive portion 11 on the substrate. The second conductive portion 22 may be used to form the second electrode of the first capacitor C1 and the first electrode of the second capacitor C2. The orthographic projection of the second conductive portion 22 on the substrate may at least partially coincide with the orthographic projection of the fifteenth active portion 615 on the substrate. The second conductive portion 22 may provide voltage regulation for the fifteenth active portion 615, thereby reducing the leakage current from the fifteenth active portion 615 to the source and drain of the fourth transistor T4. An opening 221 is also formed on the second conductive portion 22. The orthographic projection of the first initial signal line Vinit1 on the substrate may extend along the first direction X. The first initial signal line Vinit1 may be used to provide... Figure 1 The initial signal terminal in the middle. The second conductive layer may include multiple first initial signal lines Vinit1, and each row of pixel driving circuits may be provided with one first initial signal line Vinit1.

[0069] like Figure 4 , 8 As shown in Figure 13, the third conductive layer may include a third conductive portion 33 and a second power line VDD2. The orthographic projection of the third conductive portion 33 on the substrate may at least partially coincide with the orthographic projection of the second conductive portion 22 on the substrate, and the orthographic projection of the third conductive portion 33 on the substrate may at least partially intersect with the orthographic projection of the first conductive portion 11 on the substrate. The third conductive portion 33 can be used to form the second electrode of the second capacitor C2. This exemplary embodiment forms the first capacitor C1 and the second capacitor C2 by stacking three conductive layers. This arrangement can reduce the layout space of the first capacitor C1 and the second capacitor C2, thereby increasing the pixel density of the display panel. It should be noted that in other exemplary embodiments, as long as the display panel includes Figure 1 The pixel driving circuit shown in this embodiment allows the display panel to reduce the layout space of the first capacitor C1 and the second capacitor C2 by using a three-layer conductive layer stack. In this exemplary embodiment, the orthographic projection of the second conductive portion 22 on the substrate can cover the overlapping area of ​​the orthographic projections of the first conductive portion 11 and the third conductive portion 33 on the substrate. This arrangement can improve the shielding effect of the second conductive portion 22 on the first conductive portion 11 and the third conductive portion 33. An opening 331 is formed on the third conductive portion 33, and the orthographic projection of the opening 331 on the substrate at least partially overlaps with the orthographic projection of the opening 221 on the substrate. The orthographic projection of the second power line VDD2 on the substrate can extend along the first direction X. The third conductive layer can include multiple second power lines VDD2, and each row of pixel driving circuits can be provided with one second power line VDD2.

[0070] like Figure 4 , 9 As shown in Figure 14, the fourth conductive layer may include multiple first power lines VDD1, a first connection portion 41, a second connection portion 42, a third connection portion 43, a fourth connection portion 44, a fifth connection portion 45, a sixth connection portion 46, and a seventh connection portion 47. The orthographic projections of the multiple first power lines VDD1 onto the substrate can be spaced apart along a first direction X and extend along a second direction Y. The first direction X may intersect with the second direction Y; for example, the second direction can be a column direction. The multiple first power lines VDD1 can be correspondingly disposed in multiple column pixel driving circuits. The first power lines VDD1 are connected to the driving transistor T3 in their corresponding pixel driving circuits, and the first power lines VDD1 can provide... Figure 1 The first power supply terminal in the system. For example... Figure 4 , 9 As shown in Figure 14, the first power line VDD1 can be connected to the active layer on one side of the third active section 63 through via H, thereby connecting the first terminal of the driving transistor T3 and the first power supply terminal. It should be noted that... Figure 4 , 14The black squares in the diagram represent vias; this exemplary embodiment only annotates the locations of some vias. Furthermore, the first power line VDD1 can also be connected to the intersecting second power line VDD2 via a via. This arrangement allows the power lines to form a grid structure. The grid structure of the power lines has lower resistance, thereby reducing the voltage difference between the power lines at different locations on the display panel and improving the uniformity of the display. It should be understood that in other exemplary embodiments, only a portion of the first power line and a portion of the second power line may be connected via vias. The first power line VDD1 can also be connected via a via to the active layer of the seventh active portion 67 on the side away from the first active portion 61, to connect the first electrode of the seventh transistor T7 and the first power supply terminal. The first connection portion 41 can be connected via vias to the active layers of the second conductive portion 22 and the eleventh active portion 611 on the side away from the twelfth active portion 612, respectively, to connect the first electrode of the fifth transistor and the second electrode of the first capacitor. The second connection portion 42 can be connected via vias to the active layers between the third conductive portion 33 and the first active portion 61 and the seventh active portion 67, respectively, to connect the second electrode of the first transistor and the second electrode of the second capacitor. The third connection portion 43 can be connected via vias to the active layers of the first conductive portion 11, the fourteenth active portion 614 away from the fifteenth active portion 615, and the sixteenth active portion 616 away from the eighteenth active portion 618, respectively, to connect the gate of the driving transistor, the second electrode of the fourth transistor, and the first electrode of the second transistor. The orthographic projection of the via connecting the third connection portion 43 and the first conductive portion 11 onto the substrate is within the orthographic projection of the opening 221 onto the substrate, and also within the orthographic projection of the opening 331 onto the substrate, to prevent the conductive structure within the via from being electrically connected to the second conductive portion 22 and the third conductive portion 33. The fourth connection portion 44 can be connected via vias to the active layer on the other side of the third active portion 63, the active layer between the eighth active portion 68 and the seventeenth active portion 617, to connect the second electrode of the driving transistor, the second electrode of the second transistor, and the first electrode of the eighth transistor. The fifth connection portion 45 is connected via vias to the active layer between the sixth active portion 66 and the eighth active portion 68, to connect the second electrode of the sixth transistor and the second electrode of the eighth transistor. The fifth connection portion 45 is used to transfer the first electrode of the light-emitting unit. The sixth connection portion 46 is connected via vias to the first initial signal line Vinit1, the active layer of the sixth active portion 66 away from the eighth active portion 68, and the active layer of the thirteenth active portion 613 away from the fifteenth active portion 615, to connect the initial signal terminal, the first electrode of the sixth transistor, and the first electrode of the fourth transistor. The seventh connection portion 47 is connected via vias to the ninth active portion 69, to connect the first electrode of the first transistor. The first power line VDD1 can form the stable power supply terminal described above. It should be understood that in other exemplary embodiments, the display panel can also form the stable power supply terminal described above through other voltage lines.

[0071] like Figure 4 , 9 As shown in Figure 14, the display panel may include multiple pixel driving circuits distributed along the row and column directions. Among these multiple pixel driving circuits, a first pixel driving circuit P1 and a second pixel driving circuit P2 may be adjacently distributed in the first direction X. A first power line VDD1, corresponding to the first pixel driving circuit P1, can be connected to the second terminal of the fifth transistor in the second pixel driving circuit via a via.

[0072] like Figure 4 , 10 As shown, the fifth conductive layer may include multiple data lines Da, multiple second initial signal lines Vinit2, multiple third power lines VDD3, and a connection portion 51. The connection portion 51 can be connected to the fifth connection portion 45 via vias, and the connection portion 51 can be used to transfer the first electrode of the light-emitting unit. The data lines Da are used to provide... Figure 2The data signal terminal is located in the middle. Multiple data lines Da are configured one-to-one with multiple columns of pixel driving circuits, and each data line Da is connected to the first terminal of the first transistor in its corresponding pixel driving circuit. The data line Da can be connected to the seventh connection part 47 through a via to connect to the first terminal of the first transistor. In this exemplary embodiment, the display panel can be driven row by row from the previous row of pixel driving circuits to the next row of pixel driving circuits. The data writing stage in the current row of pixel driving circuits can correspond to a part of the threshold compensation stage in the previous row of pixel driving circuits. Therefore, when the current row of pixel driving circuits writes data signals, the data signals on the data lines will cause noise to the third conductive part in the previous row of pixel driving circuits, thereby causing the voltage of the third node in the previous row of pixel driving circuits to change, ultimately resulting in inaccurate data signals written to the first node during the light emission stage. In this exemplary embodiment, within the same pixel driving circuit, the orthographic projection of the via connecting the seventh connection portion 47 and the ninth active portion 69 onto the substrate can be located on the side of the orthographic projection of the reset signal line Re onto the substrate that is away from the orthographic projection of the third conductive portion 33 onto the substrate. Furthermore, in the first direction X, the orthographic projection of the via connecting the seventh connection portion 47 and the ninth active portion 69 onto the substrate can be located between the orthographic projections of adjacent third conductive portions 33 onto the substrate. This arrangement can reduce the parasitic capacitance between the via and the third conductive portion 33 by increasing the distance between them, thereby reducing the noise impact of the signal on the data line Da on the third conductive portion 33. Additionally, the orthographic projection of the data line Da onto the substrate can be located between the orthographic projections of adjacent third conductive portions 33 onto the substrate, meaning the orthographic projections of the data line Da and the third conductive portion 33 do not overlap. This arrangement can reduce the noise impact of the signal on the data line Da on the third conductive portion 33 by reducing the parasitic capacitance between the data line Da and the third conductive portion 33. Figure 4 , 10 As shown, in the same pixel driving circuit, the orthogonal projection of the via connecting the seventh connection portion 47 and the data line Da on the substrate can at least partially be located on the side where the orthogonal projection of the reset signal line Re on the substrate is far from the orthogonal projection of the third conductive portion 33 on the substrate. Similarly, this arrangement can reduce the noise impact of the signal on the data line Da on the third conductive portion 33. Furthermore, in this exemplary embodiment, the data line Da is disposed on the fifth conductive layer, thereby increasing the distance between the data line Da and conductive portions such as the third conductive portion 33, thereby reducing the coupling effect of the data line Da on conductive portions such as the third conductive portion 33.

[0073] like Figure 4 , 10As shown, the orthographic projections of multiple third power lines VDD3 on the substrate can be spaced apart along a first direction and extend along a second direction. Each of the multiple third power lines VDD3 can correspond one-to-one with a multiple first power lines VDD1. The third power lines VDD3 can be connected to their corresponding first power lines VDD1 via multiple vias, which reduces the self-resistance of the power lines. Furthermore, the orthographic projections of the third power lines VDD3 on the substrate can at least partially overlap with the orthographic projections of their corresponding first power lines VDD1 on the substrate, thereby reducing the light-shielding effect of the third power lines VDD3 on the display panel. It should be understood that in other embodiments, multiple third power lines VDD3 can also correspond to the same first power line VDD1, or a single third power line VDD3 can correspond to multiple first power lines VDD1.

[0074] like Figure 4 , 10 As shown, the orthographic projections of multiple second initial signal lines Vinit2 on the substrate can be distributed at intervals along a first direction and extend along a second direction. Each of the multiple second initial signal lines Vinit2 can be configured to correspond one-to-one with a multiple column of pixel driving circuits. The second initial signal lines Vinit2 can be connected to multiple sixth connection portions 46 in the same column of pixel driving circuits via vias to connect to multiple first initial signal lines Vinit1. This configuration can form a grid structure of initial signal lines, thereby reducing the voltage difference between initial signal lines at different positions on the display panel and improving the uniformity of the display panel. It should be noted that the second initial signal lines Vinit2 can be connected to each of the sixth connection portions 46 in the same column of pixel driving circuits via vias, or they can be connected to some of the sixth connection portions 46 in the same column of pixel driving circuits via vias. The orthographic projection of the second initial signal line Vinit2 on the substrate can at least partially overlap with the orthographic projection of the eighteenth active part 618 on the substrate. The second initial signal line Vinit2 can stabilize the voltage of the eighteenth active part 618, thereby reducing the leakage current from the eighteenth active part 618 to the source and drain of the second transistor.

[0075] like Figure 15 As shown, Figure 4A partial cross-sectional view along the dashed line AA. The display panel may also include a buffer layer 72, a first insulating layer 73, a second insulating layer 74, a third insulating layer 75, a dielectric layer 76, a passivation layer 77, and a planarization layer 78. The substrate 71, buffer layer 72, active layer, first insulating layer 73, first conductive layer, second insulating layer 74, second conductive layer, third insulating layer 75, third conductive layer, dielectric layer 76, fourth conductive layer, passivation layer 77, planarization layer 78, and fifth conductive layer are stacked sequentially. The first insulating layer 73, second insulating layer 74, and third insulating layer 75 may be silicon oxide layers; the dielectric layer 76 and passivation layer 77 may be silicon nitride layers; the planarization layer 78 may be made of organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonded structure (SOG), etc. The substrate 71 may include a glass substrate, a barrier layer, and a polyimide layer stacked sequentially. The barrier layer may be an inorganic material. The materials of the first conductive layer, the second conductive layer, and the third conductive layer may be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy, or a stack thereof. The materials of the fourth conductive layer and the fifth conductive layer may include metallic materials, such as one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy, or a stack thereof, or a titanium / aluminum / titanium stack thereof. The material of the fourth conductive layer may be indium tin oxide.

[0076] like Figure 16 The diagram shown is a schematic diagram of the pixel driving circuit in another exemplary embodiment of the display panel of this disclosure. Figure 16 The pixel driving circuit shown is Figure 2 The pixel driving circuit shown is only different in that the first terminal of the seventh transistor is connected to the initial signal terminal. Figure 16 The pixel driving circuit shown can be used with Figure 2 The pixel driving circuits shown have the same driving method.

[0077] like Figure 17-27 As shown, Figure 17 This is a structural layout diagram of another exemplary embodiment of the display panel disclosed herein. Figure 18 for Figure 17 The structural layout of the active layer is shown. Figure 19 for Figure 17 The structural layout of the first conductive layer in the middle. Figure 20 for Figure 17 Layout of the second conductive layer. Figure 21 for Figure 17 The structural layout of the third conductive layer in the middle. Figure 22 for Figure 17 The structural layout of the fourth conductive layer in the middle. Figure 23 for Figure 17 Schematic diagram of the fifth conductive layer. Figure 24 for Figure 17 The structural layout includes an active layer and a first conductive layer. Figure 25 for Figure 17 The structural layout includes an active layer, a first conductive layer, and a second conductive layer. Figure 26 for Figure 17 The structural layout includes an active layer, a first conductive layer, a second conductive layer, and a third conductive layer. Figure 27 for Figure 17 The diagram shows a structural layout comprising an active layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer. This display panel may include... Figure 16 The pixel driving circuit shown.

[0078] like Figure 17 , 18 As shown in Figure 24, the active layer may include a first active section 61, a third active section 63, a sixth active section 66, a seventh active section 67, an eighth active section 68, a tenth active section 610, an eleventh active section 611, a twelfth active section 612, a thirteenth active section 613, a fourteenth active section 614, a fifteenth active section 615, a sixteenth active section 616, a seventeenth active section 617, and an eighteenth active section 618. The first active portion 61 is used to form the channel region of the first transistor T1, the third active portion 63 is used to form the channel region of the driving transistor T3, the sixth active portion 66 is used to form the channel region of the sixth transistor T6, the seventh active portion 67 is used to form the channel region of the seventh transistor T7, the eighth active portion 68 is used to form the channel region of the eighth transistor T8, the tenth active portion 610 is used to form the first channel region of the fifth transistor T5, the eleventh active portion 611 is used to form the second channel region of the fifth transistor T5, and the twelfth active portion 612 is connected between the tenth active portion 610 and the eleventh active portion 611. The thirteenth active portion 613 is used to form the first channel region of the fourth transistor T4, the fourteenth active portion 614 is used to form the second channel region of the fourth transistor T4, the fifteenth active portion 615 is connected between the fourteenth active portion 614 and the thirteenth active portion 613, the sixteenth active portion 616 is used to form the first channel region of the second transistor T2, the seventeenth active portion 617 is used to form the second channel region of the second transistor T2, and the eighteenth active portion 618 is connected between the seventeenth active portion 617 and the sixteenth active portion 616. The active layer can be formed of polycrystalline silicon semiconductor, and all of the above transistors can be P-type low-temperature polycrystalline silicon thin-film transistors.

[0079] like Figure 17 , 19As shown in Figure 24, the first conductive layer may include a gate driving signal line (Gate), a reset signal line (Re), an enable signal line (EM), a protrusion 12, a protrusion 13, a protrusion 14, and a protrusion 15. The orthographic projections of the gate driving signal line (Gate), the reset signal line (Re), and the enable signal line (EM) on the substrate can all extend along a first direction X, which can be a row direction. The first conductive layer may include multiple gate driving signal lines (Gate), multiple reset signal lines (Re), and multiple enable signal lines (EM). Each row of pixel driving circuits can correspondingly have one gate driving signal line (Gate), one reset signal line (Re), and one enable signal line (EM). The gate driving signal line (Gate) can be connected to the second transistor in its corresponding pixel driving circuit. The orthographic projection of the gate driving signal line (Gate) on the substrate can cover the orthographic projections of the sixteenth active portion 616 and the seventeenth active portion 617 on the substrate. A portion of the structure of the gate driving signal line (Gate) can be used to form the two gates of the second transistor. Protrusions 12, 13, and 15 are connected to the gate drive signal line. The orthogonal projection of protrusion 12 on the substrate can cover the orthogonal projection of the tenth active part 610 on the substrate, and a portion of the structure of protrusion 12 can be used to form the first gate of the fifth transistor. The orthogonal projection of protrusion 13 on the substrate can cover the orthogonal projection of the eleventh active part 611 on the substrate, and a portion of the structure of protrusion 13 can be used to form the second gate of the fifth transistor. The orthogonal projection of protrusion 15 on the substrate covers the orthogonal projection of the sixth active part 66 on the substrate, and a portion of the structure of protrusion 15 is used to form the gate of the sixth transistor. Figure 3As shown, the signal waveforms on the first gate driving signal terminal Gate1 and the second gate driving signal terminal Gate2 are the same, differing only in timing. Therefore, the orthographic projection of the protrusion 12 in the previous row pixel driving circuit onto the substrate can cover the orthographic projection of the tenth active part 610 in the current row pixel driving circuit onto the substrate, and the orthographic projection of the protrusion 13 in the previous row pixel driving circuit onto the substrate can cover the orthographic projection of the eleventh active part 611 in the current row pixel driving circuit onto the substrate. The gate driving signal line Gate in the previous row pixel driving circuit can be connected to the gate of the fifth transistor in the current row pixel driving circuit. That is, the first gate driving signal terminal in the current row pixel driving circuit can be provided through the gate driving signal line in the previous row. This arrangement can reduce the layout area of ​​the pixel driving circuit and increase the pixel density of the display panel. The orthographic projection of the enable signal line EM onto the substrate can cover the orthographic projection of the seventh active part 67 onto the substrate, and part of the structure of the enable signal line EM can be used to form the gate of the seventh transistor T7. The protrusion 14 is connected to the enable signal line. The orthographic projection of the protrusion 14 on the substrate covers the orthographic projection of the eighth active part 68 on the substrate. A portion of the structure of the protrusion 14 is used to form the gate of the eighth transistor T8. The orthographic projection of the reset signal line Re on the substrate covers the orthographic projections of the thirteenth active part 613, the fourteenth active part 614, and the first active part 61 on the substrate. A portion of the structure of the reset signal line Re is used to form the two gates of the fourth transistor T4, and the remaining portion of the reset signal line Re is used to form the gate of the first transistor T1. Furthermore, the first conductive layer may also include a first conductive part 11. The orthographic projection of the first conductive part 11 on the substrate can cover the orthographic projection of the third active part 63 on the substrate. The first conductive part 11 can be used to form... Figure 2 The first electrode of the first capacitor and the gate of the driving transistor.

[0080] It should be noted that in this exemplary embodiment, the display panel can use the first conductive layer as a mask to perform conductor processing on the active layer, that is, the active layer covered by the first conductive layer forms the channel region of the transistor, and the area not covered by the first conductive layer forms a conductor structure.

[0081] like Figure 17 , 20As shown in Figure 25, the second conductive layer may include a second conductive portion 22 and a first initial signal line Vinit1. The orthographic projection of the second conductive portion 22 on the substrate may at least partially coincide with the orthographic projection of the first conductive portion 11 on the substrate. The second conductive portion 22 may be used to form the second electrode of the first capacitor C1 and the first electrode of the second capacitor C2. The orthographic projection of the second conductive portion 22 on the substrate may also at least partially coincide with the orthographic projection of the fifteenth active portion 615 on the substrate. The second conductive portion 22 may provide voltage regulation and shielding for the fifteenth active portion 615, thereby reducing the leakage current from the fifteenth active portion 615 to the source and drain of the fourth transistor T4. The orthographic projection of the second conductive portion 22 on the substrate may at least partially coincide with the orthographic projection of the twelfth active portion 612 on the substrate. The second conductive portion 22 may provide voltage regulation and shielding for the twelfth active portion 612, thereby reducing the leakage current from the twelfth active portion 612 to the source and drain of the second transistor T2. There can be multiple first initial signal lines Vinit1, and each of these multiple Vinit1 lines can be configured to correspond one-to-one with a multi-row pixel driving circuit. The orthographic projection of the multiple first initial signal lines Vinit1 onto the substrate can extend along a first direction X and be spaced apart along a second direction Y. The second direction Y can intersect with the first direction X; for example, the second direction can be a column direction. The first initial signal lines Vinit1 can be used to provide... Figure 1 The initial signal terminal in the process.

[0082] like Figure 17 , 21 As shown in Figure 26, the third conductive layer may include a third conductive portion 33 and a second power line VDD2. The orthographic projection of the third conductive portion 33 on the substrate may at least partially intersect with the orthographic projection of the second conductive portion 22 on the substrate, and the orthographic projection of the third conductive portion 33 on the substrate may at least partially intersect with the orthographic projection of the first conductive portion 11 on the substrate. The third conductive portion 33 may be used to form the second electrode of the second capacitor C2. This exemplary embodiment forms the first capacitor C1 and the second capacitor C2 by stacking three conductive layers. This arrangement can reduce the layout space of the first capacitor C1 and the second capacitor C2, thereby increasing the pixel density of the display panel. The orthographic projection of the second power line VDD2 on the substrate may extend along the first direction X. The third conductive layer may include multiple second power lines VDD2, and one second power line VDD2 may be provided for each row of pixel driving circuits.

[0083] like Figure 17 , 22As shown in Figure 27, the fourth conductive layer may include multiple first power lines VDD1, a first connection portion 41, a second connection portion 42, a third connection portion 43, a fourth connection portion 44, a fifth connection portion 45, a sixth connection portion 46, and a seventh connection portion 47. The orthographic projection of the multiple first power lines VDD1 on the substrate may be distributed at intervals along the first direction X and extend along the second direction Y. The multiple first power lines VDD1 are arranged one-to-one in multiple columns of pixel driving circuits. The first power lines VDD1 are connected to the driving transistors T3 in their corresponding pixel driving circuits, and the first power lines VDD1 can provide... Figure 1 The first power supply terminal in the system. For example... Figure 17 , 22 As shown in Figure 27, the first power line VDD1 can be connected to the active layer on one side of the third active section 63 via via H, thereby connecting the first terminal of the driving transistor and the first power supply terminal. It should be noted that... Figure 17 , 27The black squares in the diagram represent vias; this exemplary embodiment only annotates the locations of some vias. Furthermore, the first power line VDD1 can also be connected to the intersecting second power line VDD2 via a via. This arrangement allows the power lines to form a grid structure. The grid structure of the power lines has lower resistance, thereby reducing the voltage difference between the power lines at different locations on the display panel and improving the uniformity of the display. The first connection portion 41 can connect the second conductive portion 22 and the active layer of the eleventh active portion 611 away from the twelfth active portion 612 via vias to connect the first electrode of the fifth transistor and the second electrode of the first capacitor. The second connection portion 42 can connect the active layer between the third conductive portion 33, the first active portion 61, and the seventh active portion 67 via vias to connect the second electrode of the first transistor and the second electrode of the second capacitor. The third connection portion 43 can be connected via vias to the active layer on the side of the first conductive portion 11, the fourteenth active portion 614 away from the fifteenth active portion 615, and the active layer on the side of the sixteenth active portion 616 away from the eighteenth active portion 618, to connect the gate of the driving transistor, the second electrode of the fourth transistor, and the first electrode of the second transistor. The fourth connection portion 44 can be connected via vias to the active layer on the other side of the third active portion 63, and the active layer between the eighth active portion 68 and the seventeenth active portion 617, to connect the second electrode of the driving transistor, the second electrode of the second transistor, and the first electrode of the eighth transistor. The fifth connection portion 45 can be connected via vias to the active layer between the sixth active portion 66 and the eighth active portion 68, to connect the second electrode of the sixth transistor and the second electrode of the eighth transistor. The fifth connection portion 45 can be used to transfer the first electrode of the light-emitting unit. The sixth connection portion 46 connects vias to the first initial signal line Vinit1, the active layer between the sixth active portion 66 and the seventh active portion 67, and the active layer of the thirteenth active portion 613 away from the fifteenth active portion 615, to connect the initial signal terminal, the first electrode of the sixth transistor, the first electrode of the fourth transistor, and the first electrode of the seventh transistor. The seventh connection portion 47 connects vias to the active layer of the first active portion 61 away from the seventh active portion 67, to connect the first electrode of the first transistor. The first power line VDD1 can form the aforementioned stable power supply terminal. It should be understood that in other exemplary embodiments, the display panel can also form the aforementioned stable power supply terminal through other voltage lines.

[0084] like Figure 17 , 22 As shown in Figure 27, the display panel may include multiple pixel driving circuits arranged in an array along the row and column directions. Among these multiple pixel driving circuits, a first pixel driving circuit P1 and a second pixel driving circuit P2 may be adjacently distributed in the first direction X. A first power line VDD1, corresponding to the first pixel driving circuit P1, can be connected to the second terminal of the fifth transistor in the second pixel driving circuit via a via.

[0085] like Figure 17 , 23 As shown, the fifth conductive layer may include multiple data lines Da, multiple second initial signal lines Vinit2, multiple third power lines VDD3, and a connection portion 51. Data lines Da are used to provide... Figure 2 The data signal terminals are located in the circuit. Multiple data lines Da are configured one-to-one with multiple pixel driving circuits, and each data line Da is connected to the first terminal of the first transistor in its corresponding pixel driving circuit. Data lines Da can be connected to the seventh connection part 47 via vias to connect to the first terminal of the first transistor. For example... Figure 17 , 22 As shown, the first power line VDD1 may include a first protrusion VDD11 and a second extension VDD12. The orthographic projection of the second extension VDD12 on the substrate extends along the second direction Y. The first protrusion VDD11 is connected to the second extension VDD12. In the same pixel driving circuit, the orthographic projection of the third conductive portion 33 on the substrate is located between the orthographic projection of the first power line VDD1 on the substrate and the orthographic projection of the data line Da on the substrate. The orthographic projection of the first protrusion VDD11 on the substrate is located on the side of the orthographic projection of the second extension VDD12 on the substrate that is opposite to the orthographic projection of the data line Da on the substrate. Figure 17 , 21 As shown, the third conductive portion 33 includes a first side 331 facing the data line Da. The orthographic projection of the first side 331 on the substrate extends along the second direction Y. The data line Da may include a first extension Da1. In the same pixel driving circuit, the first extension Da1 and the first side 331 are disposed opposite each other in the first direction X. The fact that the first extension Da1 and the first side 331 are disposed opposite each other in the first direction X can be understood as the area covered by the orthographic projection of the first extension Da1 on the substrate moving infinitely in the first direction coincides with the area covered by the orthographic projection of the first side 331 on the substrate moving infinitely in the first direction. The orthographic projection of the first protrusion VDD11 of the first power line in the first pixel driving circuit P1 on the substrate can cover the orthographic projection of the first extension Da1 on the substrate in the second pixel driving circuit P2, and the orthographic projection of the first protrusion VDD11 of the first power line in the first pixel driving circuit P1 on the substrate covers the orthographic projection of the first side 331 on the substrate in the second pixel driving circuit P2. This setup can shield the data line Da from noise affecting the third conductive part 33 via the first power line VDD1. The connecting part 51 can be connected to the fifth connecting part 45 via a through-hole, and the connecting part 51 can be used to transfer the first electrode of the light-emitting unit.

[0086] like Figure 17 , 23 As shown, the orthographic projections of multiple third power lines VDD3 on the substrate can be spaced apart along a first direction and extend along a second direction. The multiple third power lines VDD3 can be configured one-to-one with multiple first power lines VDD1. Each third power line VDD3 can be connected to its corresponding first power line VDD1 via multiple vias, which reduces the self-resistance of the power lines. Furthermore, the orthographic projections of the third power lines VDD3 and the first power lines VDD1 on the substrate at least partially overlap to reduce the light-shielding effect of the third power lines VDD3 on the display panel. It should be understood that in other embodiments, multiple third power lines VDD3 can also be configured corresponding to the same first power line VDD1, or a single third power line VDD3 can be configured corresponding to multiple first power lines VDD1.

[0087] like Figure 17 , 23 As shown, the orthographic projections of multiple second initial signal lines Vinit2 on the substrate can be distributed at intervals along a first direction and extend along a second direction. Each of the multiple second initial signal lines Vinit2 can be configured to correspond one-to-one with a multi-column pixel driving circuit. The second initial signal lines Vinit2 can be connected to the sixth connecting portion 46 via vias to connect to the first initial signal line Vinit1. This configuration forms a grid structure of the initial signal lines, thereby reducing the voltage difference between the initial signal lines at different locations on the display panel and improving the uniformity of the display panel. The orthographic projection of the second initial signal lines Vinit2 on the substrate can also at least partially overlap with the orthographic projection of the eighteenth active portion 618 on the substrate. The second initial signal lines Vinit2 can stabilize the voltage of the eighteenth active portion 618, thereby reducing the leakage current from the eighteenth active portion 618 to the source and drain of the second transistor.

[0088] like Figure 28 As shown, Figure 17A partial cross-sectional view along the dashed line AA. The display panel may also include a buffer layer 72, a first insulating layer 73, a second insulating layer 74, a third insulating layer 75, a dielectric layer 76, a passivation layer 77, and a planarization layer 78. The substrate 71, buffer layer 72, active layer, first insulating layer 73, first conductive layer, second insulating layer 74, second conductive layer, third insulating layer 75, third conductive layer, dielectric layer 76, fourth conductive layer, passivation layer 77, planarization layer 78, and fifth conductive layer are stacked sequentially. The first insulating layer 73, second insulating layer 74, and third insulating layer 75 may be silicon oxide layers; the dielectric layer 76 and passivation layer 77 may be silicon nitride layers; the planarization layer 78 may be made of organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonded structure (SOG), etc. The substrate 71 may include a glass substrate, a barrier layer, and a polyimide layer stacked sequentially. The barrier layer may be an inorganic material. The materials of the first conductive layer, the second conductive layer, and the third conductive layer may be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy, or a stack thereof. The materials of the fourth conductive layer and the fifth conductive layer may include metallic materials, such as one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy, or a stack thereof, or a titanium / aluminum / titanium stack thereof. The material of the fourth conductive layer may be indium tin oxide.

[0089] In other exemplary embodiments, when at least some of the transistors among the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are N-type transistors, the channel region of the N-type transistor may be located between the second conductive layer and the third conductive layer, the top gate of the N-type transistor may be located in the third conductive layer, and the bottom gate of the N-type transistor may be located in the second conductive layer.

[0090] This exemplary embodiment also provides a display device, which includes the display panel described above. The display device can be a mobile phone, tablet computer, television, or other display device.

[0091] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0092] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. A display panel, wherein, The display panel includes a pixel driving circuit, which includes: The driving transistor has its first terminal connected to the first power supply line. A first capacitor, wherein the first electrode of the first capacitor is connected to the gate of the driving transistor; A second capacitor, wherein the first electrode of the second capacitor is connected to the second electrode of the first capacitor; The first transistor has its first electrode connected to the data line and its second electrode connected to the second electrode of the second capacitor. The fifth transistor has its first electrode connected to the second electrode of the first capacitor, and its second electrode connected to the stable power supply terminal. The display panel also includes: Substrate; A first conductive layer is located on one side of the substrate. The first conductive layer includes a first conductive portion, which is used to form the gate of the driving transistor and the first electrode of the first capacitor. The second conductive layer is located on the side of the first conductive layer away from the substrate. The second conductive layer includes a second conductive portion. The orthographic projection of the second conductive portion on the substrate at least partially overlaps with the orthographic projection of the first conductive portion on the substrate. The second conductive portion is used to form the second electrode of the first capacitor and the first electrode of the second capacitor. A third conductive layer is located on the side of the second conductive layer away from the substrate. The third conductive layer includes a third conductive portion. The orthographic projection of the third conductive portion on the substrate at least partially coincides with the orthographic projection of the second conductive portion on the substrate, and the orthographic projection of the third conductive portion on the substrate at least partially coincides with the orthographic projection of the first conductive portion on the substrate. The third conductive portion is used to form the second electrode of the second capacitor. The orthographic projection of the second conductive portion on the substrate covers the overlapping area of ​​the orthographic projections of the first conductive portion and the third conductive portion on the substrate.

2. The display panel according to claim 1, wherein, The display panel also includes: A fourth conductive layer is located on the side of the third conductive layer that is away from the substrate. The fifth conductive layer is located on the side of the fourth conductive layer opposite to the substrate. The fifth conductive layer includes the data line, and the orthogonal projection of the data line on the substrate extends along the second direction.

3. The display panel according to claim 2, wherein, The orthographic projection of the data line on the substrate does not overlap with the orthographic projection of the third conductive part on the substrate.

4. The display panel according to claim 2, wherein, The display panel includes a plurality of pixel driving circuits distributed in a first direction, wherein the orthographic projections of the third conductive portions in adjacent pixel driving circuits on the substrate are adjacent and spaced apart in the first direction, and the first direction and the second direction intersect. At least a portion of the orthographic projection of the data line onto the substrate lies between the orthographic projections of the adjacent third conductive portion onto the substrate.

5. The display panel according to claim 4, wherein, The display panel also includes: An active layer is located between the substrate and the first conductive layer. The active layer includes a ninth active portion, which is connected to the first electrode of the first transistor. The data line is connected to the ninth active portion through at least one via. The first conductive layer further includes a reset signal line, the reset signal line extending along the first direction by its orthogonal projection on the substrate, and the reset signal line being connected to the gate of the first transistor; In the first direction, the orthogonal projection of the via on the substrate is located between the orthogonal projections of the adjacent third conductive portion on the substrate, and the orthogonal projection of the via on the substrate is at least partially located on the side of the orthogonal projection of the reset signal line on the substrate away from the orthogonal projection of the third conductive portion on the substrate.

6. The display panel according to claim 2, wherein, The fourth conductive layer further includes a plurality of the first power lines, the orthographic projection of the plurality of the first power lines on the substrate extending along the second direction and spaced apart along the first direction, the first direction and the second direction intersecting; The third conductive layer further includes multiple second power lines, the orthographic projections of which on the substrate extend along the first direction and are spaced apart along the second direction; At least a portion of the first power line and at least a portion of the second power line are connected via a via.

7. The display panel according to claim 6, wherein, The fifth conductive layer further includes: Multiple third power lines, wherein the orthographic projection of the multiple third power lines on the substrate extends along the second direction and is spaced apart along the first direction; Wherein, the orthographic projection of the third power line on the substrate and the orthographic projection of the first power line on the substrate at least partially overlap, and the third power line is connected to the first power line through a via.

8. The display panel according to claim 2, wherein, The display panel includes a plurality of pixel driving circuits distributed in a first direction, and the fourth conductive layer includes a plurality of first power lines corresponding to the plurality of pixel driving circuits. The first power lines are connected to driving transistors in the corresponding pixel driving circuits, and the first direction and the second direction intersect. The orthographic projections of the plurality of first power lines on the substrate extend along the second direction and are spaced apart along the first direction; The third conductive portion includes a first side facing the data line, the orthographic projection of the first side on the substrate extends along the second direction, and the data line includes a first extension portion, the first extension portion and the first side are disposed opposite to each other in the first direction. At least one of the multiple first power lines has its orthographic projection on the substrate covering the orthographic projection of the first extension on the substrate, and also covering the orthographic projection of the first side on the substrate.

9. The display panel according to claim 8, wherein, The orthographic projection of the third conductive portion on the substrate is located between the orthographic projection of the data line on the substrate and the orthographic projection of the first power line on the substrate. The first power line includes: The second extension extends along the second direction in the orthogonal projection onto the substrate. A first protrusion is connected to a second extension, and the orthographic projection of the first protrusion on the substrate is located on the side of the orthographic projection of the second extension on the substrate that is opposite to the orthographic projection of the data line on the substrate. The plurality of pixel driving circuits include a first pixel driving circuit and a second pixel driving circuit that are adjacent to each other in a first direction; The orthographic projection of the first power line in the first pixel driving circuit onto the substrate is located on the side of the orthographic projection of the data line in the second pixel driving circuit away from the orthographic projection of the first power line in the second pixel driving circuit onto the substrate. The orthographic projection of the first protrusion on the first power line in the first pixel driving circuit onto the substrate covers the orthographic projection of the first extension on the data line in the second pixel driving circuit onto the substrate, and also covers the orthographic projection of the first side of the third conductive part in the second pixel driving circuit onto the substrate.

10. The display panel according to claim 1, wherein, The display panel includes a plurality of pixel driving circuits arranged in an array along a first direction and a second direction, wherein the first direction is a row direction and the second direction is a column direction; The pixel driving circuit further includes a second transistor, wherein the first terminal of the second transistor is connected to the gate of the driving transistor, and the second terminal is connected to the second terminal of the driving transistor; The display panel also includes: Substrate; A first conductive layer is located on one side of the substrate. The first conductive layer includes a gate driving signal line. The orthographic projection of the gate driving signal line on the substrate extends along the first direction. The gate driving signal line is connected to the gate of the second transistor in the current row pixel driving circuit and the gate of the fifth transistor in the next row pixel driving circuit.

11. The display panel according to claim 10, wherein, The display panel further includes a light-emitting unit, and the pixel driving circuit is used to drive the light-emitting unit to emit light. The pixel driving circuit further includes a sixth transistor, the first electrode of the sixth transistor is connected to a first initial signal line, and the second electrode is connected to the first electrode of the light-emitting unit. The gate drive signal line is connected to the gate of the sixth transistor in the current row pixel drive circuit and the gate of the fifth transistor in the next row pixel drive circuit.

12. The display panel according to claim 1, wherein, The pixel driving circuit further includes a fourth transistor, wherein the first terminal of the fourth transistor is connected to the first initial signal line and the second terminal is connected to the gate of the driving transistor. The display panel also includes: Substrate; A first conductive layer is located on one side of the substrate. The first conductive layer includes a reset signal line. The orthographic projection of the reset signal line on the substrate extends along a first direction. The reset signal line is simultaneously connected to the gate of the first transistor and the gate of the fourth transistor.

13. The display panel according to claim 12, wherein, The display panel also includes: The second conductive layer is located on the side of the first conductive layer away from the substrate. The second conductive layer includes a plurality of the first initial signal lines. The orthographic projection of the plurality of the first initial signal lines on the substrate extends along the first direction and is spaced apart along the second direction. The first direction intersects the second direction. A fifth conductive layer is located on the side of the second conductive layer away from the substrate. The fifth conductive layer includes a plurality of second initial signal lines. The orthographic projections of the plurality of second initial signal lines on the substrate extend along the first direction and are spaced apart along the second direction. Wherein, at least a portion of the first initial signal line and at least a portion of the second initial signal line are connected by vias.

14. The display panel according to claim 1, wherein, The display panel also includes: An active layer is located between the substrate and the first conductive layer. The active layer includes a tenth active portion, an eleventh active portion, and a twelfth active portion. The tenth active portion is used to form the first channel region of the fifth transistor, the eleventh active portion is used to form the second channel region of the fifth transistor, and the twelfth active portion is connected between the tenth active portion and the eleventh active portion. The orthographic projection of the second conductive portion on the substrate at least partially overlaps with the orthographic projection of the twelfth active portion on the substrate.

15. The display panel according to claim 1, wherein, The pixel driving circuit further includes a fourth transistor, the first terminal of which is connected to a first initial signal line, and the second terminal of which is connected to the gate of the driving transistor. The display panel further includes: An active layer is located between the substrate and the first conductive layer. The active layer includes a thirteenth active portion, a fourteenth active portion, and a fifteenth active portion. The thirteenth active portion is used to form the first channel region of the fourth transistor, the fourteenth active portion is used to form the second channel region of the fourth transistor, and the fifteenth active portion is connected between the thirteenth active portion and the fourteenth active portion. The orthographic projection of the second conductive portion on the substrate at least partially overlaps with the orthographic projection of the fifteenth active portion on the substrate.

16. The display panel according to claim 1, wherein, The display panel includes a plurality of pixel driving circuits, among which a first pixel driving circuit and a second pixel driving circuit are distributed adjacently in a first direction. The first power line in the first pixel driving circuit is connected to the second terminal of the fifth transistor in the second pixel driving circuit.

17. The display panel according to claim 1, wherein, The display panel further includes a light-emitting unit, and the pixel driving circuit is used to drive the light-emitting unit to emit light. The pixel driving circuit further includes a seventh transistor and an eighth transistor. The first electrode of the seventh transistor is connected to the first power line, and the second electrode is connected to the second electrode of the first transistor. The first electrode of the eighth transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the first electrode of the light-emitting unit. The display panel also includes: Substrate; A first conductive layer is located on one side of the substrate. The first conductive layer includes an enable signal line. The orthographic projection of the enable signal line on the substrate extends along a first direction. The enable signal line connects the gates of the seventh transistor and the eighth transistor.

18. The display panel according to claim 1, wherein, The display panel further includes a light-emitting unit, and the pixel driving circuit is used to drive the light-emitting unit to emit light. The pixel driving circuit further includes a seventh transistor and an eighth transistor. The first electrode of the seventh transistor is connected to a first initial signal line, and the second electrode is connected to the second electrode of the first transistor. The first electrode of the eighth transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the first electrode of the light-emitting unit. The display panel also includes: Substrate; A first conductive layer is located on one side of the substrate. The first conductive layer includes an enable signal line. The orthographic projection of the enable signal line on the substrate extends along a first direction. The enable signal line is connected to the gates of both the seventh transistor and the eighth transistor.

19. A display device, wherein, Includes the display panel as described in any one of claims 1-18.

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