A high-speed, low-power pixel biasing circuit

Abstract

The present application can provide an imaging sensor circuit disposed in a pixel located at a particular row and a particular column in a pixel array. The imaging sensor circuit can include a read unit for reading data of the pixel, wherein the read unit includes an output line of the pixel and a parasitic capacitance associated with the output line; a feedback unit for feeding back a boost current to the output line, wherein the feedback unit includes a first capacitor, a second capacitor, a third capacitor, a first inverter, a second inverter, a first switch, a second switch, and a current mirror element. In the imaging sensor circuit, a portion of current on the output line as an input current of the feedback unit, the boost current can be generated by the first capacitor, the second capacitor, the third capacitor, the first inverter, the second inverter, the first switch, the second switch, and the current mirror element, which can be used to discharge the parasitic capacitance.

Description

Technical Field

[0001] This application relates to the field of imaging device technology, and in particular to an imaging sensor and its driving method, which can reduce the stabilization time of pixel output of the imaging sensor. Background Technology

[0002] In recent years, with the informatization of society, broadband communication technology has developed rapidly. This development has made it easier to process relatively large amounts of data, resulting in the frequent transmission of image information. In this context, digital cameras, as imaging devices for acquiring image information, have become dominant, and most mobile phones now possess this imaging function. The core function of a digital camera is a charge-coupled device (CCD) imaging sensor or a complementary metal-oxide-semiconductor (CMOS) imaging sensor. CMOS sensors have been developed for various applications such as mobile devices, monitoring equipment, and automotive equipment.

[0003] The demand for high-speed, low-power, and high-resolution imaging sensors is constantly increasing, whether for CCD or CMOS imaging sensors. One approach to achieving high-speed, low-power, and high-resolution imaging sensors is to provide feedback current to the output signal lines of the pixels through one or more additional feedback circuits. However, this approach encounters three difficulties as described below.

[0004] In other words, the implementation of such high-speed imaging sensors typically requires a large amount of power consumption. The reason for this high power consumption is that such implementations usually require a large bias current in order to discharge the parasitic capacitance on the pixel output signal line as quickly as possible, and to make the pixel output transistor, which acts as a source follower, have a large transconductance.

[0005] Furthermore, the settling time (t) of the pixel output signal line during the large signal response time settle ) and bias current (I bias ) and parasitic capacitance (C para Proportional to (t) settle ∝C para / I bias On the other hand, within the small signal response time, the settling time (t) settle ) and g m -1 Proportional to parasitic capacitance (t) settle ∝C para / g m ), where g m It is the transconductance of the pixel output transistor. Furthermore, g m With bias current (I) biasThe current is proportional to the square root of the bias current. For example, the larger the bias current, the shorter the settling time, and therefore the greater the power consumption, even if the settling time is reduced by feeding the bias current to the signal output line of the pixel. Therefore, there is a trade-off between settling time and power consumption. Several techniques have been proposed to mitigate this trade-off by providing the pixel with a readout circuit having one or more additional circuits that can temporarily increase the bias current.

[0006] Between CCD and CMOS imaging sensors, CMOS imaging sensors are more convenient because they easily integrate peripheral CMOS circuitry and allow for the integration of various image processing functions into a single chip. However, due to variations in the driving transistor elements, CMOS imaging sensors generate greater fixed pattern noise (FPN) and thermal noise than CCD imaging sensors. In particular, CMOS imaging sensors produce FPN due to variations in the threshold voltage of the MOSFETs used in the pixel cell circuitry. Variations in bias current can increase the FPN value. That is, providing feedback current to the pixel's output signal line through one or more additional feedback circuits can have serious side effects, namely, a decrease in the imager's signal-to-noise ratio due to a larger FPN.

[0007] The following two examples illustrate how to provide feedback current to the output signal line of a pixel through one or more additional feedback circuits.

[0008] According to Japanese Patent Publication No. 2011-234243 (Document 1), a high-speed pixel readout circuit can be achieved by adding a source follower transistor, a capacitor, a reference current source, and a current mirror element (such as...). Figure 10 This is achieved as shown in the figure. The high-speed pixel readout circuit in Reference 1 can temporarily increase the pixel bias current during the pixel output voltage drop.

[0009] According to US Patent No. 9,729,807 B2 (Document 2), a high-speed pixel readout circuit can be implemented by adding an additional feedback circuit, which includes a capacitor, two current mirrors, and a voltage source (such as...). Figure 11 As shown in the figure, this high-speed pixel readout circuit can reduce the stabilization time of the imaging sensor circuit. The high-speed pixel readout circuit in Reference 2 can detect the transient current of the capacitor connected between the pixel output signal line and the voltage source to detect the rate of voltage drop on the pixel output signal line. The detected transient current is fed back to the pixel output signal line through two current mirrors. The current fed back to the pixel output signal line increases the bias current of the pixel output signal line.

[0010] However, the high-speed pixel readout circuit in Reference 1 has drawbacks: it increases the power consumption, die size, and fixed pattern noise (FPN) of the imaging sensor device. The high-speed pixel readout circuit in Reference 1 requires an additional current source and a capacitor with a large, non-reducible capacitance value. Therefore, when the additional current source is used in an imaging sensor circuit with a large number of columns that cannot be reduced, the current variation from the additional current source will increase the FPN. That is, since the output of the current mirror element is directly connected (non-AC coupled) to the pixel output signal line, changes in the pixel output signal line voltage will change the output current of the current mirror element, leading to an increase in the FPN of the imaging sensor device. Furthermore, since the output of the current mirror element is directly connected to the pixel output signal line, changes in the mirror ratio of the current mirror element will cause fluctuations in the pixel bias current, resulting in an even larger FPN. In addition, the addition of a essentially normally open additional current source will significantly increase the power consumption of the imaging sensor circuit.

[0011] Similar to Reference 1, the high-speed pixel readout circuit in Reference 2 can also increase the FPN value. This is because the high-speed pixel readout circuit includes two sets of current mirror elements, and the outputs of the two current mirror elements are directly connected to the pixel output signal line. The mirror ratio of the two current mirrors can vary with changes in the manufacturing process, and more importantly, with changes in the DC voltage level on the pixel output signal line. That is, since the outputs of the two current mirror elements are directly connected to the pixel output signal line, changes in the pixel output signal line voltage will change the output current of the current mirror elements. Furthermore, since the outputs of the two current mirror elements are directly connected to the pixel output signal line, changes in the mirror ratio will cause fluctuations in the pixel bias current, thus leading to a larger FPN. The increased power consumption of the high-speed pixel readout circuit in Reference 2 presents another problem, because the voltage source includes an operational amplifier that must operate at a large bandwidth that cannot be reduced. Therefore, the high-speed pixel readout circuit in Reference 2 will require a considerable bias current. The die size occupied by the voltage source circuit and capacitors also poses a problem. Summary of the Invention

[0012] In view of the above challenges, several embodiments of this application aim to provide an imaging sensor circuit and a driving method thereof, which can reduce the stabilization time of the pixel output of the imaging sensor.

[0013] In a first aspect, this application provides an imaging sensor circuit, comprising:

[0014] A reading unit for reading pixel data, wherein the reading unit includes an output line of the pixel and a parasitic capacitance associated with the output line.

[0015] A feedback unit is used to feed back boost current to the output line. The feedback unit includes a first capacitor, a second capacitor, a third capacitor, a first inverter, a second inverter, a first switch, a second switch, and a current mirror element.

[0016] The boost current is generated through the first capacitor, the second capacitor, the third capacitor, the first inverter, the second inverter, the first switch, the second switch, and the current mirror element, and the boost current is used to discharge the parasitic capacitor.

[0017] As mentioned above, the conventional method of providing feedback current to the output signal line of a pixel through one or more additional feedback circuits may have serious side effects, namely, the data obtained from the pixel will be strongly interfered with by a large FPN.

[0018] Some fixed pattern noise (FPN) may be caused by variations in the manufacturing process of the transistor used as a source follower. On the other hand, the current mirror ratio of the current mirror element 7 may also vary due to variations in the manufacturing process. Furthermore, in addition to variations in the current mirror ratio voltage of the current mirror element, variations in the output current of the current mirror element may also be caused by the voltage dependence of the current mirror element's output voltage. Since the voltage dependence itself can be quite large, and the variation in voltage dependence can also be quite large, the value of FPN can be large when the DC component of the output current of the current mirror element is fed back. Furthermore, since the output voltage of the current mirror element can significantly depend on the output voltage characteristics of the pixel, variations in the pixel threshold can affect the output voltage of the current mirror element. Therefore, the value of FPN can be even larger when the DC component of the output current of the current mirror element is fed back to the output pixel signal line. Therefore, the feedback unit in the imaging sensor circuit according to the embodiments of this application needs not to feed back any direct current (DC) component of the feedback current to the pixel output signal line.

[0019] The imaging sensor circuit according to the first aspect of this application may include a feedback unit with a simple structure, comprising two inverters, a current mirror, and three capacitors. The capacitance values ​​of these three capacitors can be much smaller than those in conventional capacitors. In the two inverters of the feedback unit, the input terminal of the inverter located on the input side of the feedback unit is connected to the pixel output signal line via a capacitor. Therefore, the feedback unit in the imaging sensor circuit can provide a pixel output signal line without a direct current (DC) component. The imaging sensor circuit according to the first aspect of this application can ensure that the feedback current generated by the feedback unit does not increase the value of fixed pattern noise (FPN) due to variations in the transistor used for the source follower gate during manufacturing. Furthermore, since the capacitance values ​​of the three capacitors can be much smaller than those in conventional capacitors, the imaging sensor circuit according to the embodiments of this application can save power compared to conventional technologies. Additionally, the die size of the two inverters can also be much smaller than that of inverters in conventional technologies.

[0020] In one possible implementation of the first aspect, the input terminal of the first inverter may be connected to one terminal of the first capacitor, one terminal of the second capacitor, and one terminal of the first switch, and the output terminal of the first inverter may be connected to the other terminal of the second capacitor, the other terminal of the first switch, and the input terminal of the second inverter.

[0021] The input terminal of the second inverter can be connected to one terminal of the third capacitor and one terminal of the second switch, and the output terminal of the second inverter can be connected to the other terminal of the third capacitor, the other terminal of the second switch, and the input terminal of the current mirror element.

[0022] The output terminal of the current mirror element can be connected to the output line and another terminal of the first capacitor.

[0023] In one possible implementation of the first aspect, the imaging sensor circuit may be disposed in pixels located in specific rows and columns of a pixel array, wherein the output of the pixel array may be connected to an analog-to-digital converter (ADC) array, and the feedback unit further includes a third switch, one terminal of which is connected to a ground terminal, and the other terminal of which may be connected to the first terminal of the first capacitor and the input of the first inverter.

[0024] According to this implementation, in response to the ADC array generating the pixel output signal, the third switch can be turned on; a low-level voltage can be applied to the input terminal of the first inverter; the first inverter can generate a high-level voltage as its output, and the second inverter can correspondingly generate a low-level voltage as its output. That is, in response to the analog-to-digital converter (ADC) array generating the pixel array output signal, both inverters in the feedback unit can be turned on. Therefore, the imaging sensor circuit can save power after the ADC array generates the pixel array output signal.

[0025] In one possible implementation of the first aspect, the readout unit may further include a photodetector element for temporarily storing charge converted from incident light, and a transfer gate for transferring the charge stored in the photodetector element to a floating diffusion (FD) node in response to a transfer signal (TX).

[0026] The boost current can be generated by the first capacitor, the second capacitor, the third capacitor, the first inverter, the second inverter, the first switch, the second switch, and the current mirror element, and may include:

[0027] In response to the transmission signal (TX), the first switch and the second switch can be turned off, enabling the transmission gate to transfer the charge stored in the photodetector element to the FD node.

[0028] The first capacitor can be adjusted according to the voltage (V) on the output line. sig The current generated by the voltage difference between the first capacitor and the threshold level of the first inverter propagates from one terminal of the first capacitor to the input terminal of the current mirror element.

[0029] The current mirror element can generate a current, which is determined based on the current ratio of the current mirror element and the current propagating to the input terminal of the current mirror element.

[0030] In one possible implementation of the first aspect, the read unit may further include a select gate connected between the FD node and the output line.

[0031] The selection signal (SEL) can be fed to the selection gate, which enables the selection gate to select a row at a specific column in the pixel array as a specific row.

[0032] The current mirror element can be used to feed back a current determined based on the current ratio of the current mirror element and the current propagating to the input terminal of the current mirror element to the output line. The current fed back to the output line can be used as a current to release the charge stored in the parasitic capacitor.

[0033] In one possible implementation of the first aspect, the read unit may further include a reset gate for resetting the voltage level of the floating diffusion (FD) node, the reset gate being connected between the power supply voltage line and the FD node. According to this implementation, after feeding a select signal (SEL) to the select gate and before feeding a transmit signal (TX) to the transmit gate, a reset signal (RST) is fed to the reset gate, causing the FD node to be pulled up to the power supply voltage (V). DD ).

[0034] According to the first aspect, due to the cooperation between the first capacitor, the second capacitor, the third capacitor, the first inverter, the second inverter, the first switch, and the second switch, the direct current (DC) component can be prevented from being fed back to the output line, so that the boost current can reduce the stabilization time of the imaging sensor circuit without increasing the fixed pattern noise (FPN) of the imaging sensor circuit.

[0035] Secondly, this application can provide a method for driving an imaging sensor circuit using a driving circuit in a pixel array, wherein the imaging sensor circuit may include a readout unit and a feedback unit.

[0036] The readout unit may include a photodetector for temporarily storing charge converted from incident light, a selection gate, a transfer gate, an output line of a pixel, and a parasitic capacitance associated with the output line.

[0037] The feedback unit may include a first capacitor, a second capacitor, a third capacitor, a first inverter, a second inverter, a first switch, a second switch, and a current mirror element.

[0038] The method may include the following steps:

[0039] A selection signal (SEL) is fed to the selection gate, wherein the selection signal (SEL) enables the selection gate to select a row at a specific column in the pixel array as a specific row.

[0040] A transmission signal (TX) is fed to the transmission gate, wherein the transmission signal (TX) enables the transmission gate to transfer the charge stored in the photodetector to the floating diffusion (FD) node.

[0041] A boost current is generated through the first capacitor, the second capacitor, the third capacitor, the first inverter, the second inverter, the first switch, the second switch, and the current mirror element, and the boost current is used to discharge the parasitic capacitor.

[0042] The current determined based on the current ratio of the current mirror element and the current propagating to the input terminal of the current mirror element is fed back to the output line. The current fed back to the output line is used as a current to release the charge stored in the parasitic capacitor.

[0043] The method according to the second aspect of this application can be implemented using an imaging sensor circuit according to an embodiment of this application. The imaging sensor circuit may include a feedback unit with a simple structure, comprising two inverters, a current mirror, and three capacitors. The capacitance values ​​of these three capacitors can be much smaller than those of capacitors in conventional technology. In the two inverters in the feedback unit, the input terminal of the inverter located on the input side of the feedback unit is connected to the pixel output signal line via a capacitor. Therefore, the feedback unit in the imaging sensor circuit can provide a pixel output signal line without a direct current (DC) component. According to an embodiment of this application, the method implemented using the imaging sensor circuit ensures that the feedback current generated by the feedback unit does not increase the value of fixed pattern noise (FPN) due to variations in the transistor used for the source follower gate during manufacturing. Furthermore, since the capacitance values ​​of the three capacitors can be much smaller than those of capacitors in conventional technology, the imaging sensor circuit according to an embodiment of this application can save power compared to conventional technology. Additionally, the die size of the two inverters can also be much smaller than the die size of inverters in conventional technology.

[0044] In one possible implementation of the second aspect, the input terminal of the first inverter may be connected to one terminal of the first capacitor, one terminal of the second capacitor, and one terminal of the first switch, and the output terminal of the first inverter may be connected to the other terminal of the second capacitor, the other terminal of the first switch, and the input terminal of the second inverter.

[0045] The input terminal of the second inverter can be connected to one terminal of the third capacitor and one terminal of the second switch, and the output terminal of the second inverter can be connected to the other terminal of the third capacitor, the other terminal of the second switch, and the input terminal of the current mirror element.

[0046] The output terminal of the current mirror element can be connected to the output line and another terminal of the first capacitor.

[0047] In one possible implementation of the second aspect, the readout unit may further include a reset gate for resetting the voltage level of the floating diffusion (FD) node. The reset gate may be connected between a power supply voltage line and the FD node. The method may further include:

[0048] After feeding a select signal (SEL) to the select gate and before feeding a transmit signal (TX) to the transmit gate, a reset signal (RST) is fed to the reset gate, causing the FD node to be pulled up to the supply voltage (V). DD ).

[0049] In one possible implementation of the second aspect, the output of the pixel array can be connected to an analog-to-digital converter (ADC) array, the feedback unit can further include a third switch, one terminal of the third switch can be connected to a ground terminal, and the other terminal of the third switch can be connected to the first terminal of the first capacitor and the input terminal of the first inverter. The method can further include:

[0050] In response to the ADC array generating the pixel output signal, the third switch is turned on.

[0051] A low-level voltage is applied to the input terminal of the first inverter.

[0052] A high-level voltage is generated as the output of the first inverter, and a low-level voltage is generated as the output of the second inverter, thereby saving power consumption after the ADC array generates pixel output signals.

[0053] In response to the analog-to-digital converter (ADC) array that generates the pixel array output signal, the two inverters in the feedback unit can be turned on. Therefore, the method according to this implementation of the second aspect can save power consumption after the ADC array generates the pixel array output signal.

[0054] According to the second aspect, due to the cooperation between the first capacitor, the second capacitor, the third capacitor, the first inverter, the second inverter, the first switch, and the second switch, the direct current (DC) component can be prevented from being fed back to the output line, so that the boost current can reduce the stabilization time of the imaging sensor circuit without increasing the fixed pattern noise (FPN) of the imaging sensor circuit. Attached Figure Description

[0055] The following drawings and description illustrate one or more embodiments in detail. Other features, objects, and advantages will be apparent from the description, drawings, and claims.

[0056] Figure 1 A block diagram illustrating an exemplary configuration of an imaging sensor circuit according to an embodiment of this application is shown;

[0057] Figure 2 A block diagram illustrating an exemplary configuration of a pixel array according to an embodiment of this application is shown;

[0058] Figure 3 An exemplary configuration of the readout unit of an imaging sensor circuit according to an embodiment of this application is shown;

[0059] Figure 4 An example of a timing diagram of the output voltage at multiple nodes of the readout unit of an imaging sensor circuit according to an embodiment of this application is shown;

[0060] Figure 5 A circuit diagram illustrating an exemplary configuration of an imaging sensor circuit according to an embodiment of this application is shown;

[0061] Figure 6 An example of a timing diagram of the output voltage at multiple nodes of an imaging sensor circuit according to an embodiment of this application is shown;

[0062] Figure 7 A circuit diagram showing another exemplary configuration of an imaging sensor circuit according to another embodiment of this application is illustrated;

[0063] Figure 8 An example of a timing diagram of the output voltage at multiple nodes of an imaging sensor circuit according to another embodiment of this application is shown;

[0064] Figure 9 A circuit diagram of an inverter element used in an imaging sensor circuit according to an embodiment of this application is shown;

[0065] Figure 10 A circuit diagram of an imaging sensor circuit in a conventional technology is shown;

[0066] Figure 11 A circuit diagram of an imaging sensor circuit in a conventional technology is shown.

[0067] In the following text, the same reference numerals refer to the same or at least functionally equivalent features, unless otherwise expressly stated. Detailed Implementation

[0068] In the following description, reference is made to the accompanying drawings, which form part of this invention, which illustrate by way of description specific aspects of embodiments of the invention or aspects in which embodiments of the invention may be used. It should be understood that embodiments of the invention may be used in other aspects and may include structural or logical variations not depicted in the drawings. Therefore, the following detailed description should not be construed in a limiting sense, and the scope of the invention is defined by the appended claims.

[0069] For example, it should be understood that the disclosure relating to the described method also applies to the corresponding device or system for performing the method, and vice versa. For example, if a specific apparatus is described based on one or more units (e.g., functional units), the corresponding method may include a step to perform the function of one or more units (e.g., a step performing the function of one or more units, or multiple steps performing the function of one or more units of a plurality of units respectively), even if the one or more units are not explicitly described or shown in the drawings. On the other hand, for example, if one or more specific method steps are described, the corresponding device may include one or more units (e.g., functional units) to perform the described one or more method steps (e.g., a unit performing one or more steps, or multiple units performing one or more of a plurality of steps respectively), even if the one or more units are not explicitly described or shown in the drawings. Furthermore, it should be understood that, unless otherwise expressly stated, features of the various exemplary embodiments and / or aspects described herein may be combined with each other.

[0070] Figure 1 A block diagram illustrating an exemplary configuration of an imaging sensor circuit according to an embodiment of this application is shown. Figure 1 In this imaging sensor device, a pixel array 1, an analog-to-digital converter (ADC) array 2, a digital signal horizontal transmission circuit 3, a comparator circuit 4, a counter 5, a row driver 6, and a ramp reference generator 7 may be included. The pixel array 1 may include multiple pixels arranged in a two-dimensional matrix. Each of these pixels can convert incident light into an electrical signal, and the converted electrical signal can be output to the ADC2 via a readout unit and a voltage output line (VOL). By referencing the ramp voltage provided by the ramp reference generator 7, each ADC2 can convert the analog signal into a digital signal.

[0071] In CMOS imaging sensors, pixel operation can be controlled row-by-row by pulses provided by row drivers (e.g., reset pulse (RST), transfer pulse (Tx), row selection pulse (SEL)). The row drivers act as circuits generating these row control pulses. The imaging sensor configuration can be of various types, such as a configuration where pixel output amplification and fixed pattern noise (FPN) suppression are arranged in parallel columns; a configuration with an AD conversion circuit at the final stage; a configuration where AD conversion is performed in parallel columns; a configuration where column-parallel circuits are positioned above and below the pixel array; a system-on-chip configuration that outputs AD-converted digital data after processing camera signals (typically used in sensors for mobile phone cameras); or a configuration where pixel outputs are output as analog signals without performing AD conversion (typically used in sensors for digital SLR cameras).

[0072] Figure 2 A block diagram illustrating an exemplary configuration of a pixel array according to an embodiment of this application is shown. Figure 1 and Figure 2 As shown, the digital signal horizontal transmission circuit 3 selects a column from a predetermined number of columns deployed in the pixel array sequentially from left to right along the horizontal direction to determine the column to be scanned. More specifically, the digital signal horizontal transmission circuit 3 sequentially turns on a predetermined number of column selection switches in a horizontal order from left to right, and then the row driver 6 sequentially selects the row to be scanned in the selected column in a top-to-bottom order. The row driver 6 feeds a selection signal (SEL) to the selection gate M2 disposed in the pixel in the selected row.

[0073] Figure 3 An exemplary configuration of the readout unit of an imaging sensor circuit according to an embodiment of this application is shown. Figure 3In this array, the readout unit for reading pixel data (e.g., luminance and chrominance data) may include a power line 1, a pixel output signal line 2, a photodetector D1, a transfer gate M3, a reset gate M4, a select gate M2, a source follower M1, and a parasitic capacitance C1 associated with the pixel output signal line 2. The photodetector D1 may be a photodiode (PD). The photodetector D1 detects incident light, converts the incident light into charge, and stores the converted charge in its internal potential well. The transfer gate M3 receives a transfer signal Tx from the row driver 6 and, in response to the transfer signal Tx, transfers the stored charge to the floating diffusion (FD) node. The reset gate M4 receives a reset signal (RST) from the row driver 6 and, in response to the reset signal (RST), resets the level of the FD node. The select gate M2 receives a row selection signal (SEL) from the row driver 6 and, in response to the row selection signal (SEL), selects a row at a specific column in the pixel array 1 as the specific row to be scanned by the readout unit. The source follower M1 can buffer the gate voltage of pixel output signal line 2. A current source can provide bias current to the source follower M1.

[0074] As mentioned above, CMOS imaging sensors are more convenient than CCD imaging sensors because they easily integrate peripheral CMOS circuitry and allow for the integration of various image processing functions into a single chip. However, due to variations in the driving transistor elements, CMOS imaging sensors generate greater fixed pattern noise (FPN) and thermal noise than CCD imaging sensors. In particular, CMOS imaging sensors produce fixed pattern noise (FPN) due to variations in the threshold values ​​of the MOSFETs used in the pixel unit circuitry.

[0075] In a CMOS imaging sensor, at the start of the imaging cycle, the reset gate M4 is turned on via the RST signal to charge the photodetector D1 to its initial voltage. The potential of the floating diffusion (FD) node is greater than the supply voltage (V) of the power line. DDThe difference is the threshold of the reset gate M4. When the photodetector D1 is illuminated, the photocurrent flows through the photodetector D1 and releases charge, causing the potential of the floating diffusion (FD) node to decrease according to the light intensity. The source follower M1 receives this potential of the floating diffusion (FD) node and provides the row selection signal (SEL) to the selection gate M2, so that the image signal is sent to the pixel output signal line. The main problem with this readout unit is that when there is a threshold change in the source follower M1, the threshold change affects the signal output, which is the main cause of FPN. Even if the transistors used in the source follower M1 are integrated on the same single chip, the threshold of the source follower M1 will inevitably change due to variations that occur during manufacturing.

[0076] Fixed pattern noise (FPN) can include fixed pattern noise caused by changes in the characteristics of transistors in pixels (occurring randomly in space, with noise amplitude not fluctuating over time), fixed pattern noise caused by changes in the dark current of each pixel (occurring randomly in space, with noise amplitude proportional to the integration time), and fixed pattern noise caused by changes in the signal processing circuitry set for each column (appearing in the form of vertical stripes, with noise amplitude not fluctuating over time).

[0077] The operation of the feedback unit is described below with reference to the timing diagram. Figure 4 An example of a timing diagram showing the output voltage at multiple nodes of the readout unit of an imaging sensor circuit according to an embodiment of this application is illustrated. Figure 4 At time t1, a select signal (SEL) is fed from row driver 6 to select gate M2. The select signal (SEL) enables select gate M2 to select a row at a specific column in the pixel array as a specific row. At time t2, after feeding the select signal (SEL) to select gate M2 and before feeding the transmit signal (TX) to transmit gate M3, a reset signal (RST) is fed to reset gate M4, causing the FD node to be pulled up to the power supply voltage (V). DD At time t3, a transmission signal (TX) is fed to the transmission gate M3. The transmission signal (TX) enables the transmission gate M3 to transfer the charge stored in the photodetector element to the floating diffusion (FD) node. In this embodiment, the potential at the FD node decreases when the charge is transferred to the FD node because the charge is considered to be electrons. The pixel output signal line 2 has a parasitic capacitance C1 of a specific value. Therefore, its voltage sway rate is affected by the bias current (I0) of the current source I1. bias ), parasitic capacitance C1 and transconductance of source follower M1 (g) m(restrictions)

[0078] The total duration of the settling time for pixel output signal line 2 can be divided into two parts: a large signal range and a small signal range. For the large signal range, the settling time (t) of pixel output signal line 2 is... settle ) can be achieved through bias current (I bias The parasitic capacitance C1 and the parasitic capacitance C1 are determined according to the following equation:

[0079] t settle =k×C1 / I bias (1)

[0080] Among them, t settle I represents the settling time of pixel output signal line 2. bias Let represent the bias current of current source I1, and k represent a constant. For a small signal range, the settling time (t) of pixel output signal line 2... settle ) can be achieved through the g of the source follower transistor m C1 and C1 are determined according to the following equation:

[0081] t settle =C1 / g m (2)

[0082] Due to g m with 1 / I bias Proportional, therefore for large signal range and small signal range, the settling time (t) of pixel output signal line 2 is... settle All are proportional to it. For example, the bias current (I) bias The larger the ), the longer the settling time (t) settle The shorter the settling time (t), the better. Therefore, for large signal ranges and small signal ranges, the settling time (t) is... settle Both ) and power consumption are trade-offs. This invention can improve stabilization time (t) without increasing the fixed pattern noise (FPN) of the imaging sensor circuitry. settle This trade-off between power consumption and energy consumption.

[0083] As described above, the imaging sensor circuit according to embodiments of this application can reduce the stabilization time of the pixel source follower circuit output by feeding a boost current to the pixel output without increasing the fixed pattern noise (FPN) of the imaging sensor circuit. The power consumption increase of the additional feedback circuit is smaller than that of conventional technologies. These advantages stem from the adaptive nature of the simple capacitively coupled circuit and its power-off function.

[0084] Figure 5 A circuit diagram illustrating an exemplary configuration of an imaging sensor circuit according to one embodiment of this application is shown. Figure 5 In this embodiment of the application, the imaging sensor circuit can be disposed in pixels located in specific rows and columns of a pixel array. The imaging sensor circuit may include a readout unit for reading pixel data and a feedback unit for feeding back boost current to the pixel output signal line. The readout unit may include a power line 1, a pixel output signal line 2, a photodetector D1, a transmission gate M3, a reset gate M4, a selection gate M2, a source follower M1, and a parasitic capacitance C1 associated with the pixel output signal line 2. The feedback unit includes a first capacitor C2, a second capacitor C3, a third capacitor C4, a first inverter 5, a second inverter 6, a first switch 3, a second switch 4, and a current mirror element 7.

[0085] like Figure 5 As shown, the input terminal of the first inverter 5 is connected to one terminal of the first capacitor C2, one terminal of the second capacitor C3, and one terminal of the first switch 3. The output terminal of the first inverter 5 is connected to the other terminal of the second capacitor C3, the other terminal of the first switch 3, and the input terminal of the second inverter 6. The input terminal of the second inverter 6 is connected to one terminal of the third capacitor C4, one terminal of the second switch 4, and the output terminal of the first inverter 5. The output terminal of the second inverter 6 is connected to the other terminal of the third capacitor C4, the other terminal of the second switch 4, and the input terminal of the current mirror element 7. The output terminal of the current mirror element 7 is connected to the pixel output signal line 2 and the other terminal of the first capacitor C2.

[0086] The operation of an imaging sensor circuit according to an embodiment of this application is described below with reference to timing diagrams. Figure 6 An example timing diagram of the output voltage at multiple nodes of an imaging sensor circuit according to an embodiment of this application is shown. Figure 6 As shown, at time t1, Figure 1 The row driver 6 in the pixel array feeds a select signal (SEL) to the select gate M2. The select signal (SEL) enables the select gate M2 to select the row at a specific column in the pixel array as a specific row. At time t2, after feeding the select signal (SEL) to the select gate M2 and before feeding the transmit signal (TX) to the transmit gate M3, a reset signal (RST) is fed to the reset gate M4, causing the voltage level at the FD node to be pulled up to the supply voltage (V). DD ).like Figure 6 As shown, the voltage level at the FD node is pulled up to the supply voltage (V). DD The potential on pixel output signal line 2 is pulled up to V. reset .

[0087] exist Figure 4 In the middle, signal P switch It can be when pulse P switchWhen the voltage level is high, the pulses of the first switch 3 and the second switch 4 are activated. On the other hand, when pulse P... switch When the voltage level is low, pulse P switch Turn off the first switch 3 and the second switch 4. As described above, at time t1, the row selection signal (SEL) can be fed to the selection gate M2, activating the selection gate M2 so that pixels located in a specific row of the pixel array are ready to be scanned. In other words, the selection gate M2 allows pixel data (such as luminance data and chrominance data) temporarily stored in the photodetector D1 within the pixel to be ready to be read out. At time t2, the reset signal (RST) can be fed to the reset gate M4, activating the reset gate M4 so that the voltage level at the FD node can be pulled up to the power supply voltage (V). DD The voltage level at pixel output signal line 2 can reach an equal voltage level (V). DD –V gs1 V reset V gs1 The value is equal to the voltage difference between the gate terminal and the source terminal of the source follower M1.

[0088] At the same time, at time t2, pulse P switch The voltage level can be raised to a high level, causing the first switch 3 and the second switch 4 to conduct. When the input and output terminals of the first inverter 5 and the second inverter 6 are short-circuited through the first switch 3 and the second switch 4 with a negative feedback effect, the output terminals of the first inverter 5 and the second inverter 6 can be stabilized near their threshold levels. In other words, when the first switch 3 and the second switch 4 are on, the input and output terminals of the first inverter element 5 and the second inverter element 6 can be short-circuited, and the first inverter element 5 and the second inverter element 6 can act as voltage followers, but not as inverting amplifier circuits. Furthermore, when the first switch 3 and the second switch 4 are on, the second capacitor C3 and the third capacitor C4 can discharge, leaving no stored charge. When the first switch 3 and the second switch 4 are off, the second capacitor C3 and the third capacitor C4 connected between the input and output terminals of the first inverter element 5 and the second inverter element 6 can act as negative feedback capacitors, outputting the inverter's input current from the output terminal. The threshold level of the inverter is represented here as V. inv The first capacitor C2 is connected to two voltages V. inv and V reset Charging is performed. It should be noted that the AC operation in this application refers only to the current received by the first capacitor C2.

[0089] At time t3, the transmission signal (Tx) can be fed to the transmission gate M3, enabling the photodetector D1 to transfer the charge stored in the photodetector D1 to the FD node. The voltage level of the pixel output signal line 2 can then drop to a lower level (V). sig At time t3, the feedback unit in the imaging sensor circuit can be used to: use a portion of the current on pixel output signal line 2 as the input current of the feedback unit, and generate a boost current as the feedback current through the first capacitor C2, the second capacitor C3, the third capacitor C4, the first inverter 5, the second inverter 6, the first switch 3, the second switch 4, and the current mirror element 7. More specifically, at time t3, in response to the transmission signal (TX), the first switch 3 and the second switch 4 can be turned off, so that the transmission gate M3 can transfer the charge stored in the photodetector element D1 to the FD node. The first capacitor C2 can be adjusted according to the voltage (V) on pixel output signal line 2. sig ) and the threshold level (V) of the first inverter 5 inv The current generated by the voltage difference between the capacitors C1 and C2 propagates from one terminal of the first capacitor C2 to the input terminal of the current mirror element 7. The current mirror element 7 can generate a current, which is determined based on the current ratio of the current mirror element 7 and the current propagating to the input terminal of the current mirror element 7.

[0090] For example, such as Figure 5 and Figure 6 As shown, when the transmission signal (TX) enables the transmission gate M3 to transfer the charge stored in the photodetector element D1 to the FD node, the signal (P) switch The voltage level of the first inverter 5 and the second inverter 6 can drop to a lower level, and the first switch 3 and the second switch 4 can be turned off. When the first switch 3 and the second switch 4 are turned off, the second capacitor C3 and the third capacitor C4 connected between the input and output terminals of the first inverter 5 and the second inverter 6 can act as negative feedback capacitors, and the input current of the inverter can be output from the output terminal. Since the voltage level of one terminal of the first capacitor C2 can drop to a lower level, the voltage level of the other terminal of the first capacitor C2 can be maintained at a V with feedback effect. inv The charging current can be determined based on the voltage difference (V). reset –V sig The current flows through the first capacitor C2. Figure 6 The middle is represented as I C1The current flowing through the first capacitor C2 can also flow through the second capacitor C3 and the third capacitor C4, and can propagate to the input terminal of the current mirror element 7. The current mirror element 7 can generate a current, the value of which is determined based on the current ratio of the current mirror element 7 and the input current of the current mirror element 7. The output current of the current mirror element 7 can be used as an additional discharge current for the parasitic capacitor C1. Therefore, the voltage slew rate can be increased, and the stabilization time of the pixel output can be reduced.

[0091] In embodiments of this application, the current mirror element 7 can be used to feed back the current determined based on the current ratio of the current mirror element 7 and the current propagating to the input terminal of the current mirror element 7 to the pixel output signal line 2. The current fed back to the output line can be used as a current to release the charge stored in the parasitic capacitor C1. The feedback current fed back to the pixel output signal line 2 can consist only of the alternating current (AC) of the first capacitor C2, therefore, there is no direct current (DC) component fed back to the pixel output signal line 2.

[0092] The following explains why the feedback unit in the imaging sensor circuit of this application uses not only the second capacitor C3 but also the third capacitor C4 to generate the feedback current fed back to the pixel output signal line 2. That is, since most current imaging sensors can process signals represented by negative charges, the stronger the incident light, the greater the amount of negative charge. Because the negative charge is stored in the capacitor and output as a specific voltage, the polarity of the pixel output may become negative. Therefore, the imaging sensor according to the embodiment of this application needs to use two inverters to make the polarity of the feedback current negative (absorb the feedback current).

[0093] The following explains why the feedback unit in the imaging sensor circuit of this application does not feed back any direct current (DC) component of the feedback current to the pixel output signal line 2. Specifically, fixed pattern noise (FPN) may be caused by variations in the transistor used in the gate M1 during manufacturing, where the gate M1 can be used as a source follower. On the other hand, the current mirror ratio of the current mirror element 7 may also vary due to variations in manufacturing. Furthermore, in addition to variations in the current mirror ratio, variations in the output current of the current mirror element 7 may also be caused by the voltage dependence of the output voltage of the current mirror element 7. Since the voltage dependence itself can be quite large, and variations in voltage dependence during manufacturing can also be quite large, the value of FPN can be large when the DC component of the output current of the current mirror element 7 is fed back. Moreover, since the output current of the current mirror element 7 can significantly depend on the output voltage characteristics of the pixel, variations in the threshold of the source follower transistor can affect the output current of the current mirror element 7. Therefore, the value of FPN can be even larger when the DC component of the output current of the current mirror element 7 is fed back to the output pixel signal line 2. Therefore, the feedback unit in the imaging sensor circuit according to the embodiments of this application needs not to feed back any direct current (DC) component of the feedback current to the pixel output signal line 2.

[0094] Therefore, in the feedback unit of the imaging sensor circuit according to the embodiments of this application, due to the cooperation between the first capacitor, the second capacitor, the third capacitor, the first inverter, the second inverter, the first switch, and the second switch, the direct current (DC) component can be avoided from being fed back to the pixel output signal line 2, so that the boost current can reduce the stabilization time of the imaging sensor circuit without increasing the fixed pattern noise (FPN) of the imaging sensor circuit.

[0095] In summary, according to the first aspect, this application can provide an imaging sensor circuit, wherein the imaging sensor circuit is disposed in pixels located in specific rows and columns of a pixel array. The imaging sensor circuit may include a readout unit for reading pixel data, wherein the readout unit includes an output line of the pixel and a parasitic capacitance associated with the output line; and a feedback unit for feeding back a boost current to the output line, wherein the feedback unit includes a first capacitor, a second capacitor, a third capacitor, a first inverter, a second inverter, a first switch, a second switch, and a current mirror element. In the imaging sensor circuit, a portion of the current on the output line is used as the input current of the feedback unit. The boost current can be generated by the first capacitor, second capacitor, third capacitor, first inverter, second inverter, first switch, second switch, and current mirror element, and the boost current can be used to discharge the parasitic capacitance.

[0096] The imaging sensor circuit according to embodiments of this application may include a feedback unit with a simple structure, comprising two inverters, a current mirror, and three capacitors. The capacitance values ​​of these three capacitors can be much smaller than those in conventional technologies. In the two inverters within the feedback unit, the input terminal of the inverter located on the input side of the feedback unit is connected to the pixel output signal line via a capacitor. Therefore, the feedback unit in the imaging sensor circuit can provide a pixel output signal line without a direct current (DC) component. The imaging sensor circuit according to embodiments of this application can ensure that the feedback current generated by the feedback unit does not increase the value of fixed pattern noise (FPN) due to variations in the transistor used for the source follower gate during manufacturing. Furthermore, since the capacitance values ​​of the three capacitors can be much smaller than those in conventional technologies, the imaging sensor circuit according to embodiments of this application can save power compared to conventional technologies. Additionally, the die size of the two inverters can also be much smaller than that of inverters in conventional technologies.

[0097] Figure 7 A circuit diagram showing another exemplary configuration of an imaging sensor circuit according to another embodiment of this application is illustrated. Figure 7 and Figure 5 The difference lies in whether the feedback unit in the imaging sensor circuit includes a third switch 8. For example... Figures 1 to 3 and Figure 7 As shown, the output of pixel array 1 can be connected to analog-to-digital converter (ADC) array 2. The feedback unit may also include a third switch 8, one terminal of which can be connected to a ground terminal, and the other terminal of the third switch 8 can be connected to one terminal of the first capacitor and the input terminal of the first inverter 5.

[0098] Figure 8 An example timing diagram of the output voltage at multiple nodes of an imaging sensor circuit according to another embodiment of this application is shown. The operation of the imaging sensor circuit according to another embodiment of this application will now be described. Figure 8 The operations performed from time t1 to time t3 and Figure 6 The operations performed from time t1 to time t3 are the same. Therefore, details will not be elaborated further here. Regarding... Figure 8 For detailed information on the operations from time t1 to time t3, please refer to [link / reference]. Figure 6 The corresponding descriptions of the operations from time t1 to time t3. For example... Figure 8 As shown, at time t4, in response to the ADC array generating the pixel output signal, the third switch 8 can be turned on; a low-level voltage can be applied to the input terminal of the first inverter 5; the first inverter 5 can generate a high-level voltage as output, and the second inverter 6 can correspondingly generate a low-level voltage as output, thereby saving the power consumption after the ADC array generates the pixel output signal.

[0099] For example, at time t4, the analog-to-digital conversion of the pixel array output is completed. Signal P can be generated after the signal from the ADC. off This allows the third switch 8 to be turned on. Since the input level of the first inverter 5 can drop to a lower level when switch 8 is on, the output level of the first inverter 5 can rise to a higher level, and the output level of the second inverter 6 can correspondingly drop to a lower level. These operations can cut off the power supply current to the first inverter 5 and the second inverter 6, because only the NMOS or PMOS in the first inverter 5 and the second inverter 6 can be turned on when their input level is high or low. Figure 8 An example of an inverter composed of NMOS and PMOS is shown, wherein the inverter may include a power line 1, an input terminal 2, and an output terminal 3.

[0100] According to another embodiment of this application, the imaging sensor circuit can save power consumption after the ADC array generates the output signal of the pixel array.

[0101] Secondly, this application provides a method for driving an imaging sensor circuit in pixels located at specific rows and columns in a pixel array using a driving circuit in the pixel array. The imaging sensor circuit used in the method may include a readout unit and a feedback unit. The readout unit may include a photodetector element for temporarily storing charge converted from incident light, a selection gate, a transfer gate, an output line of the pixel, and a parasitic capacitance associated with the output line. The feedback unit may include a first capacitor, a second capacitor, a third capacitor, a first inverter, a second inverter, a first switch, a second switch, and a current mirror element. The method may include the following steps:

[0102] S1201: Feed a selection signal (SEL) to the selection gate, wherein the selection signal (SEL) enables the selection gate to select a row at a specific column in the pixel array as a specific row.

[0103] S1203: Feed a transmission signal (TX) to the transmission gate, wherein the transmission signal (TX) enables the transmission gate to transfer the charge stored in the photodetector to the floating diffusion (FD) node.

[0104] S1204: A portion of the current on the output line is used as the input current of the feedback unit, and a boost current is generated through the first capacitor, the second capacitor, the third capacitor, the first inverter, the second inverter, the first switch, the second switch and the current mirror element. The boost current is used to discharge the parasitic capacitor.

[0105] S1205: The current determined based on the current ratio of the current mirror element and the current propagating to the input terminal of the current mirror element is fed back to the output line. The current fed back to the output line is used as a current to release the charge stored in the parasitic capacitor.

[0106] The method according to embodiments of this application can be executed by an imaging sensor circuit according to embodiments of this application. The imaging sensor circuit may include a feedback unit with a simple structure, comprising two inverters, a current mirror, and three capacitors. The capacitance values ​​of these three capacitors can be much smaller than those of capacitors in conventional technology. In the two inverters in the feedback unit, the input terminal of the inverter located on the input side of the feedback unit is connected to the pixel output signal line via a capacitor. Therefore, the feedback unit in the imaging sensor circuit can provide a pixel output signal line without a direct current (DC) component. According to embodiments of this application, the method executed using the imaging sensor circuit ensures that the feedback current generated by the feedback unit does not increase the value of fixed pattern noise (FPN) due to variations in the transistor used for the source follower gate during manufacturing. Furthermore, since the capacitance values ​​of the three capacitors can be much smaller than those of capacitors in conventional technology, the imaging sensor circuit according to embodiments of this application can save power compared to conventional technology. Additionally, the die size of the two inverters can also be much smaller than the die size of inverters in conventional technology.

[0107] In one possible implementation according to an embodiment of this application, the readout unit in the imaging sensor circuit for the method may further include a reset gate, the reset gate being used to reset the voltage level of the floating diffusion (FD) node, the reset gate being connected between the power supply voltage line and the FD node. The method may further include:

[0108] S1202: After feeding a select signal (SEL) to the select gate and before feeding a transmit signal (TX) to the transmit gate, a reset signal (RST) is fed to the reset gate, causing the FD node to be pulled up to the power supply voltage (V). DD ).

[0109] In one possible implementation according to an embodiment of this application, the output of the pixel array can be connected to an analog-to-digital converter (ADC) array. The feedback unit in the imaging sensor circuit for the method may further include a third switch. One terminal of the third switch may be connected to a ground terminal, and the other terminal of the third switch may be connected to one terminal of the first capacitor and the input terminal of the first inverter. The method may further include the following steps:

[0110] S1206: In response to the ADC array generating the pixel output signal, the third switch is turned on.

[0111] S1207: Apply a low-level voltage to the input terminal of the first inverter.

[0112] S1208: Generates a high-level voltage as the output of the first inverter and correspondingly generates a low-level voltage as the output of the second inverter, thereby saving power consumption after the ADC array generates pixel output signals.

[0113] According to another embodiment of this application, the imaging sensor circuitry used in the method can save power consumption after the ADC array generates the output signal of the pixel array.

[0114] Further details regarding the embodiments of the method can be found in the foregoing description of the corresponding operation of the imaging sensor circuit. These details will not be repeated here.

[0115] The embodiments and functions described herein can be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, these functions can be stored as one or more instructions or code in a computer-readable medium or transmitted via a communication medium and executed by a hardware-based processing unit. A computer-readable medium may include a computer-readable storage medium corresponding to a tangible medium (e.g., a data storage medium), or any communication medium that facilitates the transmission of a computer program from one place to another according to a communication protocol, etc. In this way, a computer-readable medium can generally correspond to (1) a non-transitory tangible computer-readable storage medium or (2) a communication medium such as a signal or carrier wave. A data storage medium can be any available medium accessible via one or more computers or one or more processors to retrieve instructions, code, and / or data structures for implementing the techniques described herein. A computer program product may include a computer-readable medium.

[0116] By way of example and not limitation, such computer-readable storage media may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage, disk storage or other magnetic storage devices, flash memory, or any other medium that can be used to store required program code in the form of instructions or data structures and that can be accessed by a computer. Furthermore, any connection may also be suitably defined as a computer-readable medium. For example, if instructions are transmitted from a website, server, or other remote source via coaxial cable, fiber optic cable, twisted pair and DSL, or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair and DSL, or wireless technologies such as infrared, radio, and microwave are also included in the above definition of media. However, it should be understood that computer-readable storage media and data storage media do not include connections, carrier waves, signals, or other transient media, but rather refer to non-transient tangible storage media. The disks and optical discs used herein include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of the above items should also be included within the scope of computer-readable media.

[0117] Obviously, those skilled in the art can make various modifications and changes to this application without departing from the scope of this application. Thus, this application is also intended to cover such modifications and changes, provided that such modifications and changes fall within the scope of protection defined by the appended claims and their equivalents.

Claims

1. An imaging sensor circuit, characterized in that, include: A reading unit for reading pixel data, wherein the reading unit includes an output line of the pixel and a parasitic capacitance associated with the output line; A feedback unit is used to feed back boost current to the output line. The feedback unit includes a first capacitor, a second capacitor, a third capacitor, a first inverter, a second inverter, a first switch, a second switch, and a current mirror element. The input terminal of the first inverter is connected to one terminal of the first capacitor, one terminal of the second capacitor, and one terminal of the first switch. The output terminal of the first inverter is connected to the other terminal of the second capacitor, the other terminal of the first switch, and the input terminal of the second inverter. The input terminal of the second inverter is connected to one terminal of the third capacitor and one terminal of the second switch. The output terminal of the second inverter is connected to the other terminal of the third capacitor, the other terminal of the second switch, and the input terminal of the current mirror element. The output terminal of the current mirror element is connected to the output line and the other terminal of the first capacitor. The boost current is generated through the first capacitor, the second capacitor, the third capacitor, the first inverter, the second inverter, the first switch, the second switch, and the current mirror element, and the boost current is used to discharge the parasitic capacitor.

2. The imaging sensor circuit according to claim 1, characterized in that, The imaging sensor circuit is located in any pixel of the pixel array, wherein the output of the pixel array is connected to the analog-to-digital converter (ADC) array, and the feedback unit further includes a third switch, one terminal of which is connected to a ground terminal, and the other terminal of which is connected to the first terminal of the first capacitor and the input of the first inverter.

3. The imaging sensor circuit according to claim 1 or 2, characterized in that, The readout unit also includes a photodetector for temporarily storing the charge converted from the incident light, and a transfer gate for transferring the charge stored in the photodetector to the floating diffused FD node in response to the transfer signal TX. The boost current is generated through the first capacitor, the second capacitor, the third capacitor, the first inverter, the second inverter, the first switch, the second switch, and the current mirror element, including: In response to the transmission signal TX, the first switch and the second switch are turned off, enabling the transmission gate to transfer the charge stored in the photodetector to the FD node; The first capacitor is adjusted according to the voltage V on the output line. sig The current generated by the voltage difference between the voltage level of the first inverter and the threshold level of the first inverter propagates from one terminal of the first capacitor to the input terminal of the current mirror element; The current mirror element generates a current, which is determined based on the current ratio of the current mirror element and the current propagating to the input terminal of the current mirror element.

4. The imaging sensor circuit according to claim 3, characterized in that, The readout unit further includes a selection gate connected between the FD node and the output line; The selection signal SEL is fed to the selection gate, and the selection signal SEL enables the selection gate to select the target row in the pixel array; The current mirror element is used to: feed back the current determined based on the current ratio of the current mirror element and the current propagating to the input terminal of the current mirror element to the output line, and the current fed back to the output line is used as a current to release the charge stored in the parasitic capacitor.

5. The imaging sensor circuit according to claim 4, characterized in that, The readout unit further includes a reset gate, which is used to reset the voltage level of the floating diffuse FD node, and the reset gate is connected between the power supply voltage line and the FD node.

6. A method for driving an imaging sensor circuit using a driving circuit in a pixel array, characterized in that, The imaging sensor circuit includes a readout unit and a feedback unit; The readout unit includes a photodetector for temporarily storing charge converted from incident light, a selection gate, a transfer gate, an output line of a pixel, and a parasitic capacitance associated with the output line. The feedback unit includes a first capacitor, a second capacitor, a third capacitor, a first inverter, a second inverter, a first switch, a second switch, and a current mirror element. The input terminal of the first inverter is connected to one terminal of the first capacitor, one terminal of the second capacitor, and one terminal of the first switch. The output terminal of the first inverter is connected to the other terminal of the second capacitor, the other terminal of the first switch, and the input terminal of the second inverter. The input terminal of the second inverter is connected to one terminal of the third capacitor and one terminal of the second switch. The output terminal of the second inverter is connected to the other terminal of the third capacitor, the other terminal of the second switch, and the input terminal of the current mirror element. The output terminal of the current mirror element is connected to the output line and the other terminal of the first capacitor. The method includes the following steps: A selection signal SEL is fed to the selection gate, wherein the selection signal SEL enables the selection gate to select a target row in the pixel array; A transmission signal TX is fed to the transmission gate, wherein the transmission signal TX enables the transmission gate to transfer the charge stored in the photodetector to the floating diffusion FD node; A boost current is generated through the first capacitor, the second capacitor, the third capacitor, the first inverter, the second inverter, the first switch, the second switch, and the current mirror element, and the boost current is used to discharge the parasitic capacitor. The current determined based on the current ratio of the current mirror element and the current propagating to the input terminal of the current mirror element is fed back to the output line. The current fed back to the output line is used as a current to release the charge stored in the parasitic capacitor.

7. The method according to claim 6, characterized in that, The readout unit further includes a reset gate, which is used to reset the voltage level of the floating diffused FD node. The reset gate is connected between the power supply voltage line and the FD node. The method further includes: After feeding the select signal SEL to the select gate and before feeding the transmit signal TX to the transmit gate, a reset signal RST is fed to the reset gate, causing the FD node to be pulled up to the supply voltage V. DD .

8. The method according to claim 6, characterized in that, The output of the pixel array is connected to the analog-to-digital converter (ADC) array. The feedback unit further includes a third switch, one terminal of which is connected to a ground terminal, and the other terminal of which is connected to the first terminal of the first capacitor and the input terminal of the first inverter. The method further includes: In response to the ADC array generating the pixel output signal, the third switch is turned on; Apply a low-level voltage to the input terminal of the first inverter; A high-level voltage is generated as the output of the first inverter, and a low-level voltage is generated as the output of the second inverter, thereby saving power consumption after the ADC array generates pixel output signals.

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