Wafer offset correction method for maskless exposure machine

Abstract

A wafer offset correction method for a maskless exposure machine includes the steps of calculating the positions of a plurality of wafers on a substrate to define coordinates of the wafers on the substrate, then dividing boundaries between the wafers according to the coordinate values of the wafers on the substrate to form a plurality of bonding areas corresponding to the wafers, then calculating conductive lines of the wafers in the bonding areas, and calculating compensation lines of the conductive lines crossing the boundaries to connect with adjacent conductive lines of the wafers, and finally forming a digital exposure layer according to the conductive lines and the compensation lines.

Description

Technical Field

[0001] This invention relates to photolithography, and in particular to a method for correcting wafer offset in a maskless exposure machine. Background Technology

[0002] Current photomaskless exposure technology involves coating a photoresist layer on a wafer, then using digital pattern output to irradiate the wafer with ultraviolet light corresponding to the pattern. The photoresist layer that has been irradiated by ultraviolet light will easily dissolve. After developing, etching and other processes, the remaining photoresist layer is removed, thus forming the preset pattern on the wafer.

[0003] However, when bonding wafers to the pre-processed lattice on the wafer, the wafers may not be bonded to the correct position, resulting in asymmetry or skewness. In particular, the different shapes and sizes of heterogeneous wafers can cause the wires between them to shift or become skewed, making it difficult to connect the wires. If the corresponding wires of heterogeneous wafers are directly connected to each other, the wires may come into contact with each other and cause interference, leading to short circuits. Summary of the Invention

[0004] The main objective of this invention is to provide a wafer offset correction method for a maskless exposure machine, which calculates compensation lines that cross the separation boundary so that the conductors of each wafer misalignment can be connected accordingly, thereby achieving the effect of correcting the error caused by wafer sticking.

[0005] To achieve the aforementioned objectives, the present invention provides a wafer offset correction method for a maskless exposure machine, wherein a plurality of wafers are bonded to a substrate, each wafer has a plurality of contacts, and a conductive line is formed by predetermined exposure on each of the contacts, characterized by comprising the following steps: a. Calculate the position of each wafer bonded to the substrate to define the coordinates of each wafer on the substrate; b. Based on the coordinate values ​​of each wafer on the substrate, a separation boundary is drawn between each wafer to form a plurality of bonding areas corresponding to accommodate each wafer; c. Calculate the conductors of each wafer located in its bonding area, and accordingly calculate a compensation line that crosses the separation boundary between the conductors of each wafer and the conductors corresponding to the adjacent wafers. d. A digital exposure layer is formed by the respective conductor and the respective compensation line.

[0006] Preferably, the dividing line is a virtual line that delineates each of the bonding areas.

[0007] Preferably, the dividing boundary is a virtual strip-shaped area with a predetermined width, which divides each of the bonding areas.

[0008] Preferably, the coordinate values ​​of the edges and corners of each wafer are calculated using projection geometry to measure the shape of each wafer after offset, and the separation boundary is defined accordingly. The conductor lines and compensation lines are then calculated to form the exposure layer. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a flowchart of the steps of the present invention.

[0011] Figure 2 This is a schematic diagram of the reference drawing file of the present invention.

[0012] Figure 3 This is a schematic diagram of an image showing that the dividing line of the present invention is a virtual line.

[0013] Figure 4 This is a schematic diagram of an image showing a virtual strip-shaped region as the dividing boundary of the present invention. Detailed Implementation

[0014] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] First, please refer to Figures 1-3 The present invention provides a wafer offset correction method for a maskless exposure machine, which is applied to the bonding of a plurality of wafers 1 to a substrate 2. As shown in Figure 2, a reference drawing is provided with reference state information such as the correct shape and position of each wafer 1 on the substrate 2. Each wafer 1 is disposed on the substrate 2 at intervals. Each wafer 1 has a plurality of contacts 11. The substrate 2 has a plurality of holes 21. Each contact 11 can be pre-exposed to form a conductor 12. A portion of the conductor 12 is pre-extended to the corresponding hole 21 position on the substrate 2, while another portion of the conductor 12 is pre-connected to the conductor 12 of the adjacent wafer 1.

[0016] When bonding the wafer 1 to the substrate 2, it is inevitable that it will not be bonded in the correct position, resulting in asymmetry or skew. This causes the wires 12 between the wafers 1 to also shift or become skewed, resulting in some wires 12 not being able to extend correctly to the corresponding hole 21 position on the substrate 2, while other wires 12 are difficult to connect to the corresponding wires 12 of the adjacent wafers 1.

[0017] Therefore, please continue reading Figure 1 , Figure 3 , and like Figure 1 The diagram shows the steps of the wafer offset correction method for the maskless exposure machine provided by the present invention. First, a pre-scanning method is used to obtain state information containing the shape and position of each wafer 1. In this embodiment, the scanning method uses projection geometry to project each point in three-dimensional space onto a two-dimensional plane, and connects the points projected on the plane to form a geometric figure. That is, the edges and corners of each wafer 1 are projected and calculated to define the coordinates of each wafer 1 on the substrate 2.

[0018] Next, based on the coordinate values ​​of each chip 1 on the substrate 2, the shape and offset of each chip 1 after offset are measured, and a dividing boundary 31 is divided between each chip 1 to form a plurality of bonding areas 3 corresponding to accommodate each chip 1, wherein the dividing boundary 31 is a virtual line.

[0019] Then, the wires 12 pre-exposed on each wafer 1 and located in its bonding area 3 are calculated, and a compensation line 4 is calculated between each wire 12 and the corresponding wires 12 connected to the adjacent wafer 1, which crosses the separation boundary 31. The compensation line 4 connects each wire 12 with the corresponding wire 12. Accordingly, as the wafer 1 tilts, the tilted wires 12 can be connected by the compensation line 4 to the corresponding wires 12 in the adjacent bonding area 3.

[0020] Finally, a digital exposure layer is formed based on each of the conductors 12 and each of the compensation lines 4, and exposure, development and etching are performed to form continuous and uninterrupted wiring between each of the wafers 1 to generate the required circuit diagram.

[0021] It should be noted that, such as Figure 4 As shown, the dividing boundary 31 can be a virtual strip-shaped area with a predetermined width, and each compensation line 4 crosses the dividing boundary 31 vertically, so that each compensation line 4 is arranged in parallel within the dividing boundary 31 to have a bundled effect, avoiding the problem of mutual interference of compensation lines 4 caused by the dense arrangement of the skewed conductors 12 of each chip 1.

[0022] Furthermore, the method for correcting the offset of each contact 11 is to compare the state information containing the shape and position of each wafer 1 obtained by the pre-scanning means with the reference state information such as the correct shape and position of each wafer 1 on the substrate 2 in the reference drawing file. After comparison, the difference between the two can be obtained, and then a compensation value is calculated to correct the reference state to be consistent with the actual shape and position of the wafer 1. Then, a compensation line 4 is calculated based on the compensation value, so that the conductor 12 can be connected to the corresponding hole 21 position through the compensation line 4 as shown in Figure 3, and a continuous and uninterrupted wiring is formed between each contact 11 of the wafer 1 and the corresponding hole 21 to correct the error caused by the offset of the contact 11 due to die bonding.

[0023] By means of the above-described correction method of the present invention, the skewed conductors 12 of each chip 1 are connected to each other through the compensation line 4 that crosses the separation boundary 31, so as to avoid the problem of short circuit caused by mutual contact interference due to the direct connection of the skewed conductors 12, thereby achieving the effect of correcting the error caused by the offset due to die sticking.

[0024] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for correcting wafer misalignment in a maskless exposure machine, characterized in that, A plurality of wafers are bonded on a substrate, each wafer having a plurality of contacts, and a conductive line is formed on each of the contacts by predetermined exposure, characterized by comprising the following steps: a. Calculate the position of each wafer bonded to the substrate to define the coordinates of each wafer on the substrate; including obtaining state information containing the shape and position of each wafer using a pre-scanning method, specifically using projection geometry to project each point in three-dimensional space onto a two-dimensional plane, and connecting the points projected on the plane to form a geometric figure, that is, projecting and calculating the position of the edge and end corner of each wafer bonded to the substrate to define the coordinates of each wafer on the substrate; b. Next, based on the coordinate values ​​of each wafer on the substrate, the shape and offset of each wafer after offset are measured, and a separation boundary is drawn between each wafer to form a plurality of bonding areas corresponding to accommodate each wafer; wherein, the separation boundary is a virtual line, or the separation boundary is a virtual strip area with a predetermined width. c. Calculate the conductors of each wafer located in its bonding area, and accordingly calculate a compensation line that crosses the separation boundary between the conductors of each wafer and the conductors corresponding to the adjacent wafers. d. A digital exposure layer is formed based on each conductor and each compensation line, and exposure, development and etching are performed to form continuous and uninterrupted wiring between each wafer to generate the required circuit diagram.

2. The wafer offset correction method for a maskless exposure machine according to claim 1, characterized in that, The coordinate values ​​of the edges and corners of each wafer are calculated using projection geometry to measure the shape of each wafer after offset. Based on this, the separation boundary is defined, and each conductor line and each compensation line are calculated to form the exposure layer.

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