Method of controlling process tasks and semiconductor apparatus

Abstract

The application provides a control method of a process task and a semiconductor device; the method comprises the following steps: calculating a bottleneck time of the semiconductor device and a maximum value of a job running period of a single process task (Job) according to a plurality of preset times in a process recipe; calculating a minimum Job number according to the bottleneck time and the maximum value of the job running period; calculating a target time interval according to the minimum Job number and the maximum value of the job running period, and controlling the interval between the starting times of two adjacent Jobs in the minimum Job number to be the target time interval, so that the yield of the semiconductor device reaches a target production yield. In the control method, the target production yield is calculated based on the bottleneck time, the minimum Job number and the target time interval are calculated in combination with the maximum value of the job running period, and the optimal starting time of the Job is determined, so that the production capacity of the semiconductor device reaches the target production yield.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to methods for controlling process tasks and semiconductor equipment. Background Technology

[0002] Currently, when semiconductor equipment is operating stably, its production capacity is typically measured by the number of wafers produced per unit time, or WPH (Wafers Per Hour). Existing methods mainly employ mixed-integer programming to mathematically model the semiconductor equipment. This involves constructing variables, generating constraints and objective functions based on these variables, and finally optimizing the model using a solver. The results are then statistically analyzed to derive production capacity data. While this method can analyze semiconductor equipment production capacity, it suffers from several drawbacks. If the data lacks regularity or periodicity, the production capacity gradually converges and fluctuates within a certain range as the number of process jobs increases, rarely stabilizing at a single value, leading to calculation errors. Furthermore, this method is time-consuming and prone to missing the optimal job start-up time, causing jobs that could have been started to fail, directly resulting in material stagnation in the process tanks and indirectly affecting the semiconductor equipment's production capacity. Therefore, controlling the process tasks of semiconductor equipment to achieve its theoretically optimal production capacity is a pressing issue that needs to be addressed. Summary of the Invention

[0003] In view of this, the purpose of the present invention is to provide a process task control method and semiconductor equipment to alleviate the above problems. Based on the bottleneck time, the target production volume is calculated, and the minimum number of jobs and the target time interval are calculated in combination with the maximum value of the job running cycle to determine the optimal start time of the job, thereby enabling the semiconductor equipment to achieve the target production volume and improving the control accuracy of process tasks in the semiconductor equipment.

[0004] In a first aspect, embodiments of the present invention provide a method for controlling a process task, applied to a semiconductor device, wherein the semiconductor device includes: a material storage area, a wafer transfer area, a first robotic arm, a second robotic arm, and multiple process chambers; the method includes: obtaining a process recipe; wherein the process recipe includes multiple preset times, the preset times including: transfer time, preparation time, dwell time, and process time, the transfer time being used to characterize the time for the wafer to be transferred between the wafer transfer area and the multiple process chambers by the first robotic arm, and the time for the wafer to be transferred between the material storage area and the wafer transfer area by the second robotic arm; the preparation time being used to characterize the movement time of the first robotic arm after the previous wafer transfer is completed and before the next wafer is transferred. The process time is used to characterize the maximum allowable dwell time of the wafer in the process chamber; the process time is used to characterize the time for the wafer to be processed in each process chamber; the bottleneck time of the semiconductor equipment and the maximum job cycle of a single process task (Job) are calculated based on multiple preset times; the minimum number of Jobs is calculated based on the bottleneck time and the maximum job cycle; the target time interval is calculated based on the minimum number of Jobs and the maximum job cycle, and the start time interval between two adjacent Jobs in the minimum number of Jobs is controlled as the target time interval so that the output of the semiconductor equipment reaches the target production volume; wherein, the target production volume is determined based on the bottleneck time and is used to characterize the maximum number of wafers generated by the semiconductor equipment in continuous operation per unit time.

[0005] Preferably, the transmission time includes: a first transmission time, a second transmission time, and a third transmission time; wherein, the first transmission time includes a first first transmission sub-time and a first second transmission sub-time, the first first transmission sub-time including: the time for transferring the current wafer in the current process chamber to the next process chamber via the first robot and the time for transferring the next wafer in the previous process chamber to the current process chamber via the first robot; the first second transmission sub-time including: the time for transferring the wafer from the wafer transfer area to the first process chamber via the first robot, and the time for transferring the wafer from the last process chamber to the wafer transfer area via the first robot; the second transmission time is used to characterize the time for transferring the wafer from the material storage area to the wafer transfer area via the second robot; the third transmission time is used to characterize the time for transferring the wafer from the wafer transfer area to the material storage area via the second robot; the step of calculating the bottleneck time of the semiconductor equipment and the maximum value of the job cycle of a single process task Job based on multiple preset times includes: calculating the process chamber based on the first first transmission sub-time, process time, and preparation time corresponding to each process chamber. The theoretical value of the independent operating cycle of multiple process chambers is used as the first bottleneck time. The first bottleneck time is used to characterize the theoretical bottleneck time corresponding to the process chamber. The second bottleneck time is calculated based on the first transfer sub-time and preparation time corresponding to multiple process chambers. The second bottleneck time is used to characterize the theoretical bottleneck time corresponding to the first robot arm. The third bottleneck time is calculated based on the first and second transfer sub-times, the second transfer time, the third transfer time, and the preparation time. The third bottleneck time is used to characterize the theoretical bottleneck time corresponding to the wafer execution of the JobIn and JobOut processes. The JobIn process is used to characterize the process of the wafer being transferred from the material storage area to the wafer transfer area by the second robot arm. The JobOut process is used to characterize the process of the wafer being transferred from the wafer transfer area to the material storage area by the second robot arm. The maximum value of the first bottleneck time, the second bottleneck time, and the third bottleneck time is used as the bottleneck time of the semiconductor equipment. The maximum value of the Job operating cycle is calculated based on the first transfer time, the second transfer time, the third transfer time, the dwell time, and the process time.

[0006] Preferably, the step of calculating the theoretical value of the independent operating cycle of each process chamber based on the first transmission sub-time, process time, and preparation time corresponding to each process chamber includes: The formula for calculating the theoretical value of an independent operating cycle is as follows:

[0007] in, Indicates the first The theoretical value of the independent operating cycle of each process chamber. Indicates the first The wafers processed in the first process chamber are then moved from the second process chamber by the first robotic arm. The process chamber is transferred to the first... The time for each process chamber Indicates that the first robotic arm starts from the... The process chamber moves to the first... Each process chamber is used to transfer the preparation time for the next wafer. Indicates the first The next wafer in the process chamber is transferred to the next process chamber by the first robotic arm. The time for each process chamber Indicates the next wafer in the... The process time for each process chamber to perform the processing. , Indicates the total number of process chambers. This indicates the time it takes for the wafer to be transferred from the wafer transfer area to the first process chamber by the first robotic arm; This indicates the time it takes for the wafer to be transferred from the last process chamber to the wafer transfer area by the first robotic arm; This indicates the preparation time for the first robotic arm to move from the second process chamber to the wafer transfer area to transfer the next wafer; This indicates that the first robotic arm has moved from the Wafer transfer area to the... Each process chamber is used to transfer the preparation time for the next wafer.

[0008] Preferably, the step of calculating the second bottleneck time based on the first transfer sub-time and preparation time corresponding to multiple process chambers includes: The formula for calculating the second bottleneck time is as follows:

[0009] in, This indicates the second bottleneck time. Indicates the first The wafers processed in the first process chamber are then moved from the second process chamber by the first robotic arm. The process chamber is transferred to the first... The time for each process chamber Indicates that the first robotic arm starts from the... The process chamber moves to the first... Each process chamber is used to transfer the preparation time for the next wafer. , This indicates the total number of process chambers. This indicates the time it takes for the wafer to be transferred from the wafer transfer area to the first process chamber by the first robotic arm. This indicates the preparation time for the first robotic arm to move from the first process chamber to the last process chamber. This indicates the preparation time for the first robotic arm to move from the second process chamber to the wafer transfer area to transfer the next wafer; This indicates that the first robotic arm has moved from the Wafer transfer area to the... Each process chamber is used to transfer the preparation time for the next wafer; This indicates the time it takes for the wafer to be transferred from the last process chamber to the wafer transfer area by the first robotic arm.

[0010] Preferably, the step of calculating the third bottleneck time based on the first and second transmission sub-times, the second transmission time, the third transmission time, and the preparation time includes: The formula for calculating the third bottleneck time is as follows:

[0011] in, Indicates the third bottleneck time. Indicates the third transmission time. Indicates the second transmission time. This indicates the time it takes for the wafer to be transferred from the wafer transfer area to the first process chamber by the first robotic arm. This indicates the time it takes for the first robotic arm to transfer the wafer from the last process chamber to the wafer transfer area. This indicates the preparation time for the first robotic arm to move from the first process chamber to the last process chamber. This indicates the total number of process chambers.

[0012] Preferably, the step of calculating the maximum value of the Job's operating cycle based on the first transmission time, the second transmission time, the third transmission time, the dwell time, and the process time includes: The formula for calculating the maximum value of a Job's execution cycle is as follows:

[0013] in, This indicates the maximum number of job execution cycles. Indicates the second transmission time. Indicates the third transmission time. Indicates the first The next wafer in the process chamber is transferred to the next process chamber by the first robotic arm. The time for each process chamber Indicates the next wafer in the... The process time for each process chamber to perform the processing. This indicates the time it takes for the first robotic arm to transfer the wafer from the last process chamber to the wafer transfer area. Indicates the wafer at the 1st The residence time in each process chamber , This indicates the total number of process chambers. This indicates the time it takes for the wafer to be transferred from the wafer transfer area to the first process chamber by the first robotic arm.

[0014] Preferably, the step of calculating the minimum number of jobs based on the bottleneck time and the maximum job cycle includes: The formula for calculating the minimum number of jobs is as follows:

[0015] in, This represents the minimum number of jobs. Indicates the bottleneck time for semiconductor equipment. This indicates the maximum number of job execution cycles.

[0016] Preferably, the step of calculating the target time interval based on the minimum number of jobs and the maximum job cycle includes: The formula for calculating the target time interval is as follows:

[0017] in, Indicates the target time interval. This represents the minimum number of jobs. This indicates the maximum number of job execution cycles.

[0018] Secondly, embodiments of the present invention also provide a semiconductor device, the semiconductor device including a controller and an execution mechanism connected to the controller; wherein the execution mechanism includes: a material storage area, a wafer transfer area, a first robotic arm, a second robotic arm, and a plurality of process chambers; the material storage area and the wafer transfer area are both used to store wafers, and the process chambers are used to perform process processing on the wafers; the first robotic arm is used to transfer wafers from the wafer transfer area to the process chambers; or, to transfer wafers from the process chambers to the wafer transfer area; or, to transfer wafers from one process chamber to another process chamber; the second robotic arm is used to transfer wafers from the material storage area to the wafer transfer area, or, to transfer wafers from the wafer transfer area to the material storage area; the controller is used to control the execution mechanism to execute a job using the process task control method of the first aspect, so that the output of the semiconductor device reaches the target production volume.

[0019] Thirdly, embodiments of the present invention also provide a computer-readable storage medium storing a computer program, wherein the computer program is executed by a processor to perform the steps of the control method for the process task described in the first aspect.

[0020] The embodiments of the present invention bring the following beneficial effects: This invention provides a method for controlling process tasks and a semiconductor device. The method calculates the bottleneck time and job cycle of a single process task (Job) based on multiple preset times in the process recipe. It then calculates the target production volume based on the bottleneck time, and calculates the minimum number of Jobs based on the maximum value of both the bottleneck time and the job cycle. Finally, it calculates the target time interval based on the minimum number of Jobs and the maximum value of the job cycle, and controls the start-up time interval between two adjacent Jobs to achieve the target production volume. In this control method, the target production volume is calculated based on the bottleneck time, and the minimum number of Jobs and the target time interval are calculated in conjunction with the maximum value of the job cycle to determine the optimal start-up time for the Jobs. This ensures that the semiconductor device's production capacity reaches the target production volume, thereby improving the control accuracy of process tasks in the semiconductor device.

[0021] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention are realized and obtained through the structures particularly pointed out in the description and the drawings.

[0022] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0023] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention; Figure 3 A flowchart of a process task control method provided in an embodiment of the present invention; Figure 4 A flowchart for calculating the theoretical value of the independent operating cycle of a process chamber is provided for an embodiment of the present invention; Figure 5 A flowchart of another process task control method provided in an embodiment of the present invention; Figure 6This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] For semiconductor devices, such as Figure 1 As shown, it includes: a material storage area, an FTR (Foup Transport Robot), a pre-scanning port, an ATM robot (ATM for short), a wafer transfer area, a wafer pre-storage area, a PTM robot (PTM for short), and a process area; among which, the material storage area serves as a temporary storage area for FOUP (Front Opening Unified) wafers. The Pod (Wafer Carrier) buffer area primarily supports simultaneous execution of multiple process jobs. The pre-scan port, including Pre-scan Port 1 and Pre-scan Port 2, is used to open and close Foup doors and scan and verify material information. Pre-scan Port 2 completes the job task, while Pre-scan Port 1 completes other tasks. The FTR (Foup Transfer Transmission) is mainly responsible for transferring Foups between the material storage area and the pre-scan port. The ATM (Augmentation Transfer Transmission) is mainly responsible for bidirectional wafer transfer between the pre-scan port and the wafer transfer area; however, wafers can only be transferred unidirectionally at any given time, and the ATM can grab a maximum of one set of 25 wafers at a time. The wafer transfer area can hold a maximum of two sets of 50 wafers at a time, mainly for moving wafers to the process area for processing. The wafer pre-storage area can hold a maximum of two sets of 50 wafers at a time, mainly responsible for performing calibration operations on the wafers. The process area includes multiple PMs (Process Modules), represented as a set. , PTM is used for bidirectional transmission of wafers between PMs, and can grab up to two groups of wafers, totaling 50 wafers, at a time.

[0027] Specifically, the process of material transfer in the aforementioned semiconductor equipment is as follows: ① The FTR moves the Foup from the material storage area to the pre-scan port 2 and opens the Foup gate; ② The ATM moves the wafer in the Foup on the pre-scan port 2 to the Wafer transfer area; ③ The Foup gate closes, and the FTR puts the empty Foup on the pre-scan port 2 back into the material storage area; ④ It is determined whether there is material in the process area. If yes, step ⑤ is executed; otherwise, step ⑥ is executed; ⑤ The PTM places the wafer in the Wafer transfer area into the Wafer pre-storage area. The process involves several steps: ⑥ Calibration is performed; ⑦ The PTM transfers the wafers from the wafer transfer area to the process area, ensuring all wafers complete the process according to the recipe sent from the factory; ⑧ After the process is complete, the FTR moves the empty Foup from the material storage area to the pre-scan port 2 and opens the Foup gate; ⑨ The PTM transfers the wafers from the process area to the wafer transfer area, and the ATM moves the wafers from the wafer transfer area to the Foup on the pre-scan port 2, closing the Foup gate; ⑨ The FTR returns the Foup on the pre-scan port 2 to the material storage area. Therefore, controlling the job in semiconductor equipment to achieve theoretically optimal production capacity is of great significance.

[0028] Based on this, embodiments of the present invention provide a process task control method and semiconductor equipment. Based on the bottleneck time, the target production volume is calculated, and the minimum number of jobs and the target time interval are calculated in combination with the maximum value of the job running cycle to determine the optimal start time of the job. This enables the semiconductor equipment to achieve the target production volume and improves the control accuracy of process tasks in the semiconductor equipment.

[0029] To facilitate understanding of this embodiment, the method for controlling the process task provided by this invention will first be described in detail below. This method is applied to semiconductor equipment, such as... Figure 2 As shown, the semiconductor device includes a controller (not shown) and actuators connected to the controller. The actuators include a material storage area (containing a material transfer unit, FTR), a wafer transfer area, a first robotic arm, a second robotic arm, and multiple process chambers (PMs). The first robotic arm is a PTM robotic arm, and the second robotic arm is an ATM robotic arm. Additionally, the semiconductor device includes a wafer pre-storage area, primarily responsible for performing calibration operations on the wafers.

[0030] The material storage area and wafer transfer area are both used to store wafers, while the process chamber (PM) is used to process the wafers. The first robotic arm is used to transfer wafers from the wafer transfer area to the process chamber, such as transferring unprocessed wafers in the wafer transfer area to a certain process chamber for processing; or transferring wafers from the process chamber to the wafer transfer area, such as transferring wafers that have been processed in the last process chamber to the wafer transfer area; or transferring wafers from one process chamber to another, such as transferring wafers that have been processed in the current process chamber to the next process chamber for processing, etc.

[0031] The second robotic arm is used to transfer wafers from the material storage area to the wafer transfer area, or vice versa. For example, the second robotic arm transfers unprocessed wafers from the material storage area to the wafer transfer area, or transfers processed wafers from the wafer transfer area to the material storage area. It should be noted that during the process of transferring wafers from or to the material storage area, the second robotic arm also needs to cooperate with the FTR of the material storage area to realize the wafer transfer. For details, please refer to the process of job transfer of materials in the semiconductor equipment described above. The embodiments of the present invention will not be described in detail here.

[0032] In addition, for ease of explanation, such as Figure 2 As shown, this embodiment of the invention divides the semiconductor device into a transfer area (i.e., module A) and a process area (i.e., module B). Module A includes the JobIn process (material storage area -> FTR -> pre-scan port 2 -> ATM -> Wafer transfer area) for transferring materials from the material storage area to the wafer transfer area, and the JobOut process (wafer transfer area -> ATM -> pre-scan port 2 -> FTR -> material storage area) for transferring materials from the wafer transfer area to the material storage area. In module B, the transfer and processing process of materials from the wafer transfer area to the process chamber and then back to the wafer transfer area is called JobMid (wafer transfer area -> wafer pre-storage area -> process chamber -> wafer transfer area). It should be noted that -> here indicates transfer to.

[0033] Furthermore, the aforementioned controller is used to control the actuator to execute the Job using the control method of the following process task, so that the output of the semiconductor equipment reaches the target production volume. This solves the shortcomings of the semiconductor equipment in terms of theoretical capacity (i.e. target production volume) assessment, provides a basis for the semiconductor equipment to achieve theoretical capacity assessment, and improves the control accuracy of process tasks in the semiconductor equipment.

[0034] Example 1 Based on the aforementioned semiconductor equipment, embodiments of the present invention provide a method for controlling process tasks, such as... Figure 3 As shown, the method includes the following steps: Step S302: Obtain the process formula; wherein, the process formula includes multiple preset times; Specifically, to ensure the precision and efficiency of wafer processing, the process recipe acquired by the controller includes not only multiple production steps but also multiple preset times. These preset times include: transfer time. Preparation time Residence time and process time In actual processing, transmission time This term is used to characterize the time taken for the wafer to be transferred between the wafer transfer area and multiple process chambers by the first robotic arm, and the time taken for it to be transferred between the material storage area and the wafer transfer area by the second robotic arm; that is, in the wafer processing process, the time taken for the wafer to be transferred is referred to as the transfer time. Figure 2 As shown, the minimum transmission time here includes: the transmission time corresponding to the JobIn process, the transmission time corresponding to the JobOut process, and the transmission time corresponding to the wafer in JobMid, etc.

[0035] In addition, preparation time The term "process time" is used to characterize the movement time of the first robotic arm after completing the transfer of the previous wafer and before transferring the next wafer; that is, the time from when the first robotic arm completes the transfer of the previous wafer to when it transfers the next wafer. Additionally, "dwell time" characterizes the maximum allowable dwell time of the wafer within the process chamber; process time... Used to characterize the processing time of a wafer in each process chamber. Since each process chamber performs different processing on the wafer, the processing time of each process chamber is... They may be the same or different, depending on the actual processing conditions.

[0036] Step S304: Calculate the bottleneck time of the semiconductor equipment and the maximum job cycle of a single process task based on multiple preset times; Specifically, such as Figure 2As shown, the job process in the entire semiconductor equipment can be divided into multiple bottleneck modules, including JobIn, JobOut, process modules (including multiple process chambers), and internal transfer modules (PTM). The process modules and PTM jointly implement the JobMid process. Based on multiple preset times, the independent operating cycle of each bottleneck module can be calculated, thus obtaining the bottleneck time of the entire semiconductor equipment. Furthermore, due to the wafer's dwell time constraint in the process chamber, the job operating cycle for a single process task job has a dynamic range, meaning the job operating cycle includes the maximum job operating cycle value. and the minimum value of the job execution cycle Therefore, the controller can calculate the bottleneck time and maximum job cycle value of the semiconductor equipment based on multiple preset times in the process recipe.

[0037] Step S306: Calculate the minimum number of jobs based on the bottleneck time and the maximum value of the job running cycle; In actual processing, the theoretical optimal capacity is achieved under the condition that the bottleneck module of the entire semiconductor equipment operates continuously. Once the bottleneck module has idle time during the job operation, the capacity of the semiconductor equipment will decrease and will not be able to reach the theoretical optimal capacity (i.e., the target production volume).

[0038] For example, the number of jobs running simultaneously in the process area When =1, it is equivalent to a single job running, and the job running time is the minimum value of the job running cycle. Semiconductor equipment production volume WPH lowest, As the number of jobs running simultaneously increases As the number of wafers increases, the number of wafers running simultaneously in the process area gradually increases, and the production capacity of semiconductor equipment gradually increases. However, due to the maximum dwell time constraint of wafers in the process chamber, the job runtime... It will not always be based on the minimum time. The job will run and will not exceed the maximum time, i.e., the maximum job cycle time. That is, the execution time range of each Job is within and It operates within a certain range. Therefore, to achieve the theoretically optimal production capacity (i.e., the target production volume)... It is necessary to calculate the minimum number of jobs that can run simultaneously within the execution cycle of a single job. Minimum number of jobs This is used to characterize the minimum number of jobs that can run simultaneously when the production volume of semiconductor equipment reaches the target production volume within a job cycle.

[0039] In addition, when a complete job run cycle Number of jobs running simultaneously At this time, bottleneck modules will be idle, and the actual production volume of semiconductor equipment will not reach the theoretical optimal capacity, i.e., the target production volume; when >> At times, the wafer may remain in the process area for too long; when Only then can the actual production volume of semiconductor equipment reach the target production volume; when When the minimum number of jobs exceeds the sum of the process chambers and the wafer transfer area, the semiconductor equipment experiences bottleneck module idleness due to insufficient wafers in the process area, and the actual production volume cannot reach the target production volume. For example, if there are 6 process chambers and the minimum number of jobs is 4, it means that at least 4 sets of jobs must exist in the process area at any given time to achieve the maximum production volume. If there are fewer than 4 sets, the bottleneck module will be idle, resulting in the actual production volume being lower than the target production volume.

[0040] Therefore, based on the bottleneck time and the maximum job cycle, the minimum number of jobs is calculated using the following formula: (1) in, This represents the minimum number of jobs. Indicates the bottleneck time for semiconductor equipment. This represents the maximum value of the Job running cycle. It should be noted that the minimum number of Jobs is determined according to the above formula (1), and the number of Jobs is run according to the minimum number of Jobs within the Job running cycle to ensure that the bottleneck module in the semiconductor equipment will not be idle, thereby enabling the production volume of the semiconductor equipment to reach the target production volume.

[0041] Step S308: Calculate the target time interval based on the minimum number of jobs and the maximum job cycle, and control the start time interval between two adjacent jobs in the minimum number of jobs to be the target time interval, so that the output of semiconductor equipment reaches the target production volume.

[0042] The target production volume characterizes the maximum number of wafers produced by the semiconductor equipment during continuous operation per unit time; this target production volume can also be referred to as the theoretical optimal capacity or theoretical maximum capacity of the semiconductor equipment. Specifically, the target production volume is determined based on the bottleneck time, and its calculation formula is as follows: (2) in, Indicates the target production volume. This indicates the bottleneck time for semiconductor equipment; 3600 represents 3600 seconds in one hour. MThis indicates the number of wafers in a job. For example, if a job has 50 wafers, then the above... M =50.

[0043] Specifically, in order to ensure the execution cycle of a Job Within this range, the minimum number of jobs that can run simultaneously is: The formula for calculating the interval between two adjacent job start times, i.e., the target time interval, is as follows: (3) in, Indicates the target time interval. This represents the minimum number of jobs. This indicates the maximum number of job execution cycles.

[0044] Therefore, in a job's execution cycle Within, the controller controls the number of jobs running simultaneously. There are 1, and the interval between the start times of two adjacent jobs in the minimum number of jobs is 1. At this point, not only will the bottleneck modules in the semiconductor equipment not be idle, but the wafer will also avoid being stuck in the process area for too long, thus enabling the semiconductor equipment to reach the target production capacity.

[0045] The process task control method provided in this embodiment of the invention calculates the target production volume based on the bottleneck time, and calculates the minimum number of jobs and the target time interval by combining the maximum value of the job running cycle, so as to determine the optimal start time of the job, thereby enabling the semiconductor equipment to achieve the target production volume and improving the control accuracy of process tasks in the semiconductor equipment.

[0046] In one embodiment, the aforementioned transfer time includes: a first transfer time, a second transfer time, and a third transfer time; wherein, the first transfer time includes a first first transfer sub-time and a first second transfer sub-time, the first first transfer sub-time including: the time for transferring the current wafer in the current process chamber to the next process chamber via the first robot and the time for transferring the next wafer in the previous process chamber to the current process chamber via the first robot; the first second transfer sub-time including: the time for transferring the wafer from the wafer transfer area to the first process chamber via the first robot, and the time for transferring the wafer from the last process chamber to the wafer transfer area via the first robot; the second transfer time is used to characterize the time for the wafer to be transferred from the material storage area to the wafer transfer area via the second robot, that is, the transfer time corresponding to the JobIn process. The third transfer time characterizes the time it takes for the wafer to be transferred from the wafer transfer area to the material storage area by the second robotic arm, i.e., the transfer time corresponding to the JobOut process. Specifically, for ease of explanation, the total number of process chambers is set to n.

[0047] Specifically, the process of calculating the bottleneck time of semiconductor equipment and the maximum job cycle of a single process task based on multiple preset times includes the following steps: (A1) The theoretical value of the independent operating cycle of each process chamber is calculated based on the first transmission sub-time, process time and preparation time corresponding to each process chamber, and the maximum value of the theoretical value of the independent operating cycle of multiple process chambers is taken as the first bottleneck time; wherein, the first bottleneck time is used to characterize the theoretical bottleneck time corresponding to the process chamber. Specifically, for the process module, such as Figure 4 As shown, the process first determines whether all process chambers have been fully calculated. If so, the calculation of the theoretical value of the independent operating cycle of the process module ends. If not, the process time of the current process chamber is obtained, as well as the transfer time of the wafer from the current process chamber to the next process chamber, and the preparation time of the first robot arm from the next process chamber to the previous process chamber. Finally, the transfer time of the next wafer from the previous process chamber to the current process chamber is obtained. This process is repeated until the theoretical value of the independent operating cycle of all process chambers has been calculated.

[0048] Therefore, in order to calculate the theoretical value of the independent operating cycle corresponding to each process chamber, the first transfer sub-time corresponding to each process chamber includes: the time to transfer the current wafer in the current process chamber to the next process chamber via the first robot and the time to transfer the next wafer in the previous process chamber to the current process chamber via the first robot.

[0049] For ease of understanding, let's use the first... Taking a process chamber as an example. ① When the wafer is in the... After the first process chamber completes its processing, the first robotic arm (PTM) transfers the wafer to the next process chamber, i.e., the second process chamber. The transmission time of each process chamber is ② The first robotic arm starts from the first The process chamber moves to the first... Each process chamber (i.e., the previous process chamber) has a preparation time for transferring the next wafer. ③ The first robotic arm moves the next wafer from the first... The process chamber is transferred to the first... Each process chamber, with a transmission time of [time missing]. ④ The next wafer is in the first Each process chamber is used for processing, and the processing time is... Therefore, for the first Each process chamber, and its corresponding first transfer sub-time includes: the time for transferring the current wafer in the current process chamber to the next process chamber via the first robotic arm. And the time it takes to transfer the next wafer from the previous process chamber to the current process chamber via the first robotic arm. .

[0050] Specifically, no. The formula for calculating the theoretical value of the independent operating cycle of each process chamber is as follows: (4) in, Indicates the first The theoretical value of the independent operating cycle of each process chamber. Indicates the first The wafers processed in the first process chamber are then moved from the second process chamber by the first robotic arm. The process chamber is transferred to the first... The time for each process chamber Indicates that the first robotic arm starts from the... The process chamber moves to the first... Each process chamber is used to transfer the preparation time for the next wafer. Indicates the first The next wafer in the process chamber is transferred to the next process chamber by the first robotic arm. The time for each process chamber Indicates the next wafer in the... The process time for each process chamber to perform the processing. , This indicates the total number of process chambers. This indicates the time it takes for the wafer to be transferred from the wafer transfer area to the first process chamber by the first robotic arm; This indicates the time it takes for the wafer to be transferred from the last process chamber to the wafer transfer area by the first robotic arm; This indicates the preparation time for the first robotic arm to move from the second process chamber to the wafer transfer area to transfer the next wafer; This indicates that the first robotic arm has moved from the Wafer transfer area to the... Each process chamber is used to transfer the preparation time for the next wafer.

[0051] Furthermore, based on the above formula (4) and repeating ①~④ above, the theoretical value of the independent operating cycle of each process chamber can be calculated. and through Determine the maximum theoretical value of the independent operating cycle of multiple process chambers, and... The first bottleneck time is the theoretical bottleneck time corresponding to the process module or process chamber.

[0052] (A2) The second bottleneck time is calculated based on the first transmission sub-time and preparation time corresponding to multiple process chambers; wherein, the second bottleneck time is used to characterize the theoretical bottleneck time corresponding to the first robot arm; Specifically, for the internal transfer module, since wafer transfer is mainly performed by the first robotic arm, the theoretical bottleneck time corresponding to the first robotic arm can be calculated as the theoretical value of the independent operating cycle of the internal transfer module. In this case, the first transfer sub-time for each process chamber includes the time taken by the first robotic arm to transfer the wafer from the process chamber to the next process chamber, such as for the first... Each process chamber, and its corresponding first transfer sub-time includes the time for transferring the current wafer in the current process chamber to the next process chamber via the first robotic arm. .

[0053] The formula for calculating the second bottleneck time is as follows: (5) in, This indicates the second bottleneck time. Indicates the first The wafers processed in the first process chamber are then moved from the second process chamber by the first robotic arm. The process chamber is transferred to the first... The time for each process chamber Indicates that the first robotic arm starts from the... The process chamber moves to the first... Each process chamber is used to transfer the preparation time for the next wafer. , This indicates the total number of process chambers. This indicates the time it takes for the wafer to be transferred from the wafer transfer area to the first process chamber by the first robotic arm. This indicates the preparation time for the first robotic arm to move from the first process chamber to the last process chamber. This indicates the preparation time for the first robotic arm to move from the second process chamber to the wafer transfer area to transfer the next wafer; This indicates that the first robotic arm has moved from the Wafer transfer area to the... Each process chamber is used to transfer the preparation time for the next wafer; This indicates the time it takes for the wafer to be transferred from the last process chamber to the wafer transfer area by the first robotic arm.

[0054] To facilitate understanding, an example is provided below. Assume that under steady-state conditions, the process path is JobIn -> Wafer Transfer Area -> PM1 -> PM2 -> PM3 -> Wafer Transfer Area -> JobOut, with three wafer sets located in PM1, PM2, and PM3 respectively. After the PM3 process is completed, the first robotic arm, PTM, performs a move from PM3 to the Wafer Transfer Area. The wafers processed in process chamber PM3 are transferred to the wafer transfer area; then, the wafers undergo JobOut (time not included in the calculation), while the first robotic arm PTM prepares for the wafer transfer area -> PM2 Move. Then the first robotic arm, PTM, performs the PM2 to PM3 transfer move. The process involves transferring the wafer from process chamber PM2 to PM3, followed by the first robotic arm PTM preparing for the PM3 to PM1 move. Then the first robotic arm, PTM, performs the PM1->PM2 transfer move. The process involves transferring the wafer from process chamber PM1 to PM2, followed by the first robotic arm PTM preparing the PM2->Wafer transfer area. Simultaneously, the wafer undergoes JobIn (time not included in the calculation), and then the first robotic arm, PTM, performs the move from the wafer transfer area to PM1. The wafer in the wafer transfer area is transferred to PM1, and then the first robotic arm PTM prepares for the PM1 to PM3 move. Right now This forms a closed loop, and the previous steps are repeated continuously. At this point, the theoretical value of the independent operating cycle of the internal transmission module (PTM) is calculated using the following formula: (6) Furthermore, in order to achieve the theoretically optimal capacity of semiconductor equipment, each module of the default bottleneck time will not have idle time. Therefore, the wafers in the Wafer transfer area do not need to be transferred to the Wafer pre-storage area for calibration in order to wait for wafer processing in the process chamber PM1. Thus, in the calculation of the theoretical value of the independent operating cycle of the internal transfer module (PTM), that is, the second bottleneck time corresponding to the first robot, there is no need to consider the situation of the wafer in the Wafer pre-storage area.

[0055] (A3) The third bottleneck time is calculated based on the first and second transfer sub-times, the second transfer time, the third transfer time, and the preparation time; wherein, the third bottleneck time is used to characterize the theoretical bottleneck time corresponding to the wafer executing the JobIn process and the JobOut process, the JobIn process is used to characterize the process of the wafer being transferred from the material storage area to the wafer transfer area by the second robot, and the JobOut process is used to characterize the process of the wafer being transferred from the wafer transfer area to the material storage area by the second robot; The formula for calculating the third bottleneck time is as follows: (7) in, Indicates the third bottleneck time. The third transfer time refers to the time it takes for the wafer to return to the material storage area after being transferred from the last process chamber to the wafer transfer area by the first robot PTM, and then the JobOut process is performed in the wafer transfer area. In other words, it is the time it takes for the wafer to be transferred from the wafer transfer area to the material storage area by the second robot. The second transfer time refers to the time it takes for the wafer to move from the material storage area to the wafer transfer area during the JobIn process. That is, the time it takes for the wafer to be transferred from the material storage area to the wafer transfer area by the second robot arm, excluding the time it takes for the second robot arm PTM to transfer the wafer from the wafer transfer area to the first process chamber for processing. This indicates the time it takes for the wafer to be transferred from the wafer transfer area to the first process chamber by the first robotic arm, i.e., the time it takes for the wafer to be transferred from the wafer transfer area to the first process chamber by the first robotic arm after JobIn is completed; This indicates the time it takes for the first robotic arm to transfer the wafer from the last process chamber to the wafer transfer area. This represents the preparation time for the first robotic arm to move from the first process chamber to the last process chamber; that is, the preparation time for the first robotic arm to transfer the wafer that is about to complete the process in the last process chamber. This represents the total number of process chambers, thus the above... and This forms the first and second transmission sub-times.

[0056] Furthermore, when calculating the third bottleneck time according to the above formula (7), in addition to considering the time for the wafer to perform the JobIn and JobOut processes, it also includes the transfer time after the JobIn is completed, during which the first robot arm transfers the wafer from the wafer transfer area to the first process chamber. And the transfer time for the wafer to be moved from the last process chamber to the wafer transfer area by the first robotic arm. Preparation time for the first robotic arm This ensures that there is no delay in wafer transport, thereby enabling the target production volume to reach the theoretical optimal level.

[0057] It should be noted that the above steps (A1) to (A3) can be performed simultaneously or in a specific order depending on the actual situation. This embodiment of the invention does not impose any restrictions on this.

[0058] (A4) The maximum value of the first bottleneck time, the second bottleneck time, and the third bottleneck time is taken as the bottleneck time of the semiconductor device; Specifically, after calculating the first bottleneck time corresponding to the process chamber, the second bottleneck time corresponding to the internal transmission module, and the third bottleneck time corresponding to JobIn and JobOut, the maximum value of the first bottleneck time, the second bottleneck time, and the third bottleneck time is taken as the bottleneck time of the semiconductor device.

[0059] The formula for calculating the bottleneck time of semiconductor equipment is as follows: (8) in, Indicates the bottleneck time for semiconductor equipment. Indicates the first bottleneck time. This indicates the second bottleneck time. This indicates the third bottleneck time.

[0060] It should be noted that since the theoretical optimal capacity is achieved under the condition that the bottleneck module of the entire machine operates continuously, once the bottleneck module has idle time during the job operation, the machine's capacity will decrease and will not be able to reach the theoretical optimal capacity. Therefore, through the above formula (8), the maximum bottleneck time of all related modules in the job process of the semiconductor equipment is calculated as the bottleneck time of the semiconductor equipment. Therefore, theoretically, at most every bottleneck time ,from Figure 2 Only when module A in the process starts a new job can the semiconductor equipment potentially reach its theoretically optimal production capacity.

[0061] (A5) The maximum value of the Job running cycle is calculated based on the first transmission time, the second transmission time, the third transmission time, the dwell time, and the process time.

[0062] Specifically, due to the time constraints of the wafer's residence in the process area, the cycle time of a single job is limited. It has a dynamic range, meaning the job execution cycle includes both the maximum and minimum value of the job execution cycle. The formula for calculating the maximum job execution cycle is as follows: (9) in, This indicates the maximum number of job execution cycles. Indicates the second transmission time. Indicates the third transmission time. Indicates the first The next wafer in the process chamber is transferred to the next process chamber by the first robotic arm. The time for each process chamber Indicates the next wafer in the... The process time for each process chamber to perform the processing. This indicates the time it takes for the first robotic arm to transfer the wafer from the last process chamber to the wafer transfer area. Indicates the wafer at the 1st The residence time in each process chamber , This indicates the total number of process chambers. This indicates the time it takes for the wafer to be transferred from the wafer transfer area to the first process chamber by the first robotic arm.

[0063] Furthermore, the minimum job cycle can be calculated based on the first transmission time, the second transmission time, the third transmission time, and the process time. The formula for calculating the minimum job cycle is as follows: (10) in, This represents the minimum execution cycle of the Job. Indicates the second transmission time. Indicates the third transmission time. Indicates the first The next wafer in the process chamber is transferred to the next process chamber by the first robotic arm. The time for each process chamber Indicates the next wafer in the... The process time for each process chamber to perform the processing. This indicates the time it takes for the first robotic arm to transfer the wafer from the last process chamber to the wafer transfer area. , This indicates the total number of process chambers. This indicates the time it takes for the wafer to be transferred from the wafer transfer area to the first process chamber by the first robotic arm.

[0064] It should be noted that the bottleneck time and maximum value of the Job running cycle of the aforementioned semiconductor equipment can be set to be calculated simultaneously, or the order can be set according to the actual situation. This embodiment of the invention does not impose any restrictions on this.

[0065] Example 2 To make it easier to understand, here's an example. Suppose the shortest job execution time is 3600s, the longest is 4000s, the bottleneck time is 1100s, and there are 4 process chambers PM1, PM2, PM3, and PM4.

[0066] When the time interval for starting a new Job is set to the bottleneck time of 1100s, meaning a new Job is started every 1100s during the maximum Job runtime of 4000s, the maximum number of Jobs running simultaneously within 4000s is 4000 / 1100 = 3. Assuming 5 Jobs are started: Job1, Job2, Job3, Job4, and Job5, when Job1 returns to the material storage area, Job2 is located at PM4, Job3 at PM3, Job4 at PM1, and Job5 is in the material storage area awaiting startup. Since the minimum time interval between new job starts is 1100 seconds, the time interval between the current position of each job and the current position of the previous job is approximately 1100 seconds. That is, after about 1100 seconds, Job2 returns to the material storage area, Job3 is located at PM4, Job4 is located at PM3, and Job5 should be located at PM1 to achieve the target production volume. However, Job5 cannot possibly be located where Job4 was 1100 seconds ago because... It takes much longer than 1100 seconds. Job5 needs about 1800-1100=700 seconds to reach the position of Job4 at that time. This results in insufficient wafers, that is, the bottleneck module in the semiconductor equipment has idle time, which leads to the actual production capacity of the semiconductor equipment being lower than the target production volume.

[0067] Based on this, according to the process task control method provided in the embodiment of the present invention, firstly, the minimum number of Jobs can be calculated as 1 + 4000 / 1100 = 4 according to formula (2), and then, the target time interval can be calculated as 4000 / 4 = 1000s according to formula (3). When the Jobs are started at intervals of 1000s, at this time, when Job1 returns to the material storage area, Job2 is located at PM4, Job3 is located at PM3, Job4 is located at PM2, and Job5 is located at PM1. After 1000s, Job2 returns to the material storage area, Job3 is located at PM4, Job4 is located at PM3, Job5 is located at PM2, Job6 is located at PM1, and so on, every 1000s. All can achieve At a position before 1000s, the bottleneck module of the semiconductor equipment will not be idle, and the wafer will not stay in the process area for too long, thus enabling the semiconductor equipment to achieve the target production capacity.

[0068] In summary, the process task control method provided by this invention theoretically analyzes the bottleneck and target production volume of semiconductor equipment under steady-state conditions. Firstly, starting with the semiconductor equipment modules, it decomposes and analyzes the semiconductor equipment model independently. It first calculates the theoretical operating cycle value of each module to determine the bottleneck time of the semiconductor equipment, and then calculates the target production volume based on the bottleneck time. Simultaneously, it calculates the minimum number of jobs by combining the maximum job operating cycle value. Finally, it theoretically analyzes the optimal start time of the jobs based on the minimum number of jobs and the maximum job operating cycle value to achieve the target production volume of the semiconductor equipment. This static analysis method addresses the shortcomings of theoretical capacity assessment for semiconductor equipment, provides a basis for capacity assessment of semiconductor equipment, and improves the control accuracy of process tasks in semiconductor equipment.

[0069] Example 3 exist Figure 3 Based on this, embodiments of the present invention provide another method for controlling process tasks, such as... Figure 5 As shown, the method includes the following steps: (1) Obtain the initialization information of the semiconductor device; that is, obtain multiple preset times in the process recipe. The specific preset times can be referred to the aforementioned embodiments. (2) Calculate the bottleneck time of the associated modules, including calculating the first bottleneck time corresponding to the process chamber, the second bottleneck time corresponding to the first robot arm, and the third bottleneck time corresponding to JobIn and JobOut respectively; (3) Determine the bottleneck time of the semiconductor device based on the first bottleneck time, the second bottleneck time, and the third bottleneck time; that is, take the maximum value of the first bottleneck time, the second bottleneck time, and the third bottleneck time as the bottleneck time of the semiconductor device. (4) Calculate the maximum value of the Job running cycle; that is, calculate the maximum value of the Job running cycle based on the first transmission time, the second transmission time, the third transmission time, the dwell time, and the process time. (5) Calculate the minimum number of jobs based on the bottleneck time and the maximum value of the job running cycle; (6) Calculate the target time interval based on the minimum number of jobs and the maximum value of the job running cycle, and control the start time interval of two adjacent jobs in the minimum number of jobs to be the target time interval so that the output of semiconductor equipment reaches the target production volume.

[0070] Specifically, after the controller calculates the target time interval, it controls the start time interval of two adjacent jobs to be the target time interval. For example, after the previous job starts, when the start time reaches the target time interval, it controls the current job to start running and controls the semiconductor equipment to process the materials of each job running at the same time.

[0071] To facilitate understanding, the current job is used as an example to illustrate the job's operation process. Specifically, after the current job starts, ① the FTR in the control semiconductor equipment moves the Foup carrying the wafer in the current job from the material storage area to the pre-scan port 2 and opens the Foup door; ② the second robotic arm ATM moves the wafer in the Foup on the pre-scan port 2 to the wafer transfer area; ③ the Foup door is closed, and the FTR is used to return the empty Foup on the pre-scan port 2 to the material storage area; ④ the first robotic arm PTM transfers the wafer in the wafer transfer area to the process area. Here, the wafer is first transferred to the first process chamber in the process area and processed in the first process chamber. After completion, the wafer is transferred to the second process chamber, and so on, until the last process chamber completes the wafer processing; ⑦ After the process is completed, the FTR is controlled to move the empty Foup from the material storage area to the pre-scan port 2 and open the Foup door; ⑧ The first robotic arm PTM is controlled to transfer the wafer in the last process chamber from the process area to the wafer transfer area, and the first robotic arm ATM is controlled to move the wafer in the wafer transfer area to the Foup on the pre-scan port 2, and the Foup door is controlled to close; ⑨ The FTR is controlled to put the Foup on the pre-scan port 2 back into the material storage area to complete the current job. For each other job, the execution process of the current job can be referred to, and the embodiments of the present invention will not be described in detail.

[0072] It should be noted that the calculation process of each step above can be referred to the foregoing embodiments, and the embodiments of the present invention will not be described in detail here.

[0073] Therefore, the above-mentioned process task control method, after obtaining the initialization information of the semiconductor equipment, can theoretically assess the capacity bottleneck of the semiconductor equipment and calculate the conditions (including the minimum number of jobs and the target time interval) required to achieve the optimal capacity, so that the capacity of the semiconductor equipment can reach the theoretical optimal capacity (i.e., the target production volume). In addition, this method can also be applied to other semiconductor equipment with different process paths, different process modules, and process residence time constraints. The specific adjustments can be made according to the actual situation, which will not be described in detail in the embodiments of this invention.

[0074] This invention also provides a semiconductor device, including a processor and a memory, wherein the memory stores machine-executable instructions that can be executed by the processor, and the processor executes the machine-executable instructions to implement the control method for the above-mentioned process tasks.

[0075] See Figure 6As shown, the semiconductor device includes a processor 100 and a memory 101. The memory 101 stores machine-executable instructions that can be executed by the processor 100. The processor 100 executes the machine-executable instructions to implement the control method for the above-mentioned process tasks.

[0076] Furthermore, Figure 6 The semiconductor device shown also includes a bus 102 and a communication interface 103, with the processor 100, the communication interface 103 and the memory 101 connected via the bus 102.

[0077] The memory 101 may include high-speed random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage device. Communication between this system network element and at least one other network element is achieved through at least one communication interface 103 (which can be wired or wireless), such as the Internet, wide area network, local area network, metropolitan area network, etc. The bus 102 may be an ISA (Industrial Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Enhanced Industry Standard Architecture) bus, etc. These buses can be categorized as address buses, data buses, control buses, etc. For ease of representation, Figure 6 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus or one type of bus.

[0078] Processor 100 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of processor 100 or by instructions in software form. Processor 100 may be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this invention. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this invention can be directly manifested as execution by a hardware decoding processor, or execution by a combination of hardware and software modules in the decoding processor. The software module can reside in a readily available storage medium in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory 101, and the processor 100 reads the information from memory 101 and, in conjunction with its hardware, completes the steps of the method described in the foregoing embodiments.

[0079] This embodiment also provides a machine-readable storage medium storing machine-executable instructions. When the machine-executable instructions are invoked and executed by a processor, the machine-executable instructions cause the processor to implement the control method for the above-mentioned process tasks.

[0080] The process task control method and semiconductor device computer program product provided in the embodiments of the present invention include a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the methods described in the preceding method embodiments. For specific implementation, please refer to the method embodiments, which will not be repeated here.

[0081] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the system and apparatus described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0082] Furthermore, in the description of the embodiments of the present invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention based on the specific circumstances.

[0083] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0084] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0085] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for controlling a process task, applied to semiconductor equipment, characterized in that, The semiconductor device includes: a material storage area, a wafer transfer area, a first robotic arm, a second robotic arm, and multiple process chambers; the method includes: Obtain a process recipe; wherein the process recipe includes multiple preset times, the preset times including: transfer time, preparation time, dwell time, and process time. The transfer time is used to characterize the time for the wafer to be transferred between the wafer transfer area and the multiple process chambers by the first robot arm, and the time for the wafer to be transferred between the material storage area and the wafer transfer area by the second robot arm. The preparation time is used to characterize the movement time of the first robot arm before transferring the next wafer after the previous wafer transfer is completed. The dwell time is used to characterize the maximum allowable dwell time of the wafer in the process chamber. The process time is used to characterize the time for the wafer to be processed in each of the process chambers. The bottleneck time of the semiconductor device and the maximum job cycle of a single process task are calculated based on multiple preset times. The job process in the entire semiconductor device is divided into multiple bottleneck modules. The bottleneck time of each bottleneck module is calculated based on multiple preset times, and the maximum value of multiple bottleneck times is taken as the bottleneck time of the semiconductor device. The maximum job cycle is calculated based on the transmission time, the dwell time, and the process time. The minimum number of jobs is calculated based on the bottleneck time and the maximum job cycle. The target time interval is calculated based on the minimum number of jobs and the maximum job cycle, and the start time interval between two adjacent jobs in the minimum number of jobs is controlled as the target time interval so that the output of the semiconductor equipment reaches the target production volume; wherein, the target production volume is determined based on the bottleneck time and is used to characterize the maximum number of wafers generated by the semiconductor equipment in continuous operation per unit time.

2. The method according to claim 1, characterized in that, The transmission time includes: a first transmission time, a second transmission time, and a third transmission time; wherein, the first transmission time includes a first first transmission sub-time and a first second transmission sub-time, the first first transmission sub-time including: the time for transferring the current wafer in the current process chamber to the next process chamber via the first robot and the time for transferring the next wafer in the previous process chamber to the current process chamber via the first robot; the first second transmission sub-time including: the time for transferring the wafer from the wafer transfer area to the first process chamber via the first robot, and the time for transferring the wafer from the last process chamber to the wafer transfer area via the first robot; the second transmission time is used to characterize the time for transferring the wafer from the material storage area to the wafer transfer area via the second robot; the third transmission time is used to characterize the time for transferring the wafer from the wafer transfer area to the material storage area via the second robot; The step of calculating the bottleneck time of the semiconductor device and the maximum value of the job run cycle of a single process task based on multiple preset times includes: The theoretical value of the independent operating cycle of each process chamber is calculated based on the first transmission sub-time, the process time, and the preparation time corresponding to each process chamber, and the maximum value of the theoretical values ​​of the independent operating cycles of multiple process chambers is taken as the first bottleneck time; wherein, the first bottleneck time is used to characterize the theoretical bottleneck time corresponding to the process chamber. The second bottleneck time is calculated based on the first transmission sub-time and the preparation time corresponding to the multiple process chambers; wherein, the second bottleneck time is used to characterize the theoretical bottleneck time corresponding to the first robot arm; The third bottleneck time is calculated based on the first and second transmission sub-times, the second transmission time, the third transmission time, and the preparation time; wherein, the third bottleneck time is used to characterize the theoretical bottleneck time corresponding to the wafer performing the JobIn and JobOut processes, the JobIn process is used to characterize the process of the wafer being transferred from the material storage area to the wafer transfer area by the second robot, and the JobOut process is used to characterize the process of the wafer being transferred from the wafer transfer area to the material storage area by the second robot; The maximum value of the first bottleneck time, the second bottleneck time, and the third bottleneck time is taken as the bottleneck time of the semiconductor device. The maximum value of the Job's operating cycle is calculated based on the first transmission time, the second transmission time, the third transmission time, the dwell time, and the process time.

3. The method according to claim 2, characterized in that, The step of calculating the theoretical value of the independent operating cycle of each process chamber based on the first transmission sub-time, the process time, and the preparation time corresponding to each process chamber includes: The formula for calculating the theoretical value of the independent operating cycle is as follows: in, Indicates the first The theoretical value of the independent operating cycle of each process chamber. Indicates the first The wafers processed in the first process chamber are then transported by the first robotic arm from the second process chamber. The process chamber is transferred to the first... The time for each process chamber This indicates that the first robotic arm starts from the... The process chamber moves to the first... Each process chamber is used to transfer the preparation time of the next wafer. Indicates the first The next wafer in the first process chamber is transferred to the second process chamber by the first robotic arm. The time for each process chamber Indicates the next wafer in the... The process time for each process chamber to perform the process. , This indicates the total number of the process chambers. This indicates the time it takes for the wafer to be transferred from the wafer transfer area to the first process chamber by the first robotic arm; This indicates the time it takes for the wafer to be transferred from the last process chamber to the wafer transfer area by the first robotic arm; This refers to the preparation time for the first robotic arm to move from the second process chamber to the wafer transfer area to transfer the next wafer; This indicates that the first robotic arm moves from the Wafer transfer area to the first... Each process chamber is used to transfer the preparation time of the next wafer.

4. The method according to claim 3, characterized in that, The step of calculating the second bottleneck time based on the first transmission sub-time and the preparation time corresponding to the plurality of process chambers includes: The formula for calculating the second bottleneck time is as follows: in, This indicates the second bottleneck time. Indicates the first The wafers processed in the first process chamber are then transported by the first robotic arm from the second process chamber. The process chamber is transferred to the first... The time for each process chamber This indicates that the first robotic arm starts from the... The process chamber moves to the first... Each process chamber is used to transfer the preparation time for the next wafer. , This indicates the total number of the process chambers. This indicates the time it takes for the wafer to be transferred from the wafer transfer area to the first process chamber by the first robotic arm. This indicates the preparation time for the first robotic arm to move from the first process chamber to the last process chamber. This refers to the preparation time for the first robotic arm to move from the second process chamber to the wafer transfer area to transfer the next wafer; This indicates that the first robotic arm moves from the Wafer transfer area to the first... Each process chamber is used to transfer the preparation time of the next wafer; This indicates the time it takes for the wafer to be transferred from the last process chamber to the wafer transfer area by the first robotic arm.

5. The method according to claim 4, characterized in that, The step of calculating the third bottleneck time based on the first and second transmission sub-times, the second transmission time, the third transmission time, and the preparation time includes: The formula for calculating the third bottleneck time is as follows: in, This refers to the third bottleneck time. Indicates the third transmission time, Indicates the second transmission time. This indicates the time it takes for the wafer to be transferred from the wafer transfer area to the first process chamber by the first robotic arm. This indicates the time it takes for the wafer to be transferred from the last process chamber to the wafer transfer area by the first robotic arm. This indicates the preparation time for the first robotic arm to move from the first process chamber to the last process chamber. This indicates the total number of the process chambers.

6. The method according to claim 5, characterized in that, The step of calculating the maximum value of the Job's operating cycle based on the first transmission time, the second transmission time, the third transmission time, the dwell time, and the process time includes: The formula for calculating the maximum value of the Job's execution cycle is as follows: in, This indicates the maximum number of times the job can run. Indicates the second transmission time. Indicates the third transmission time, Indicates the first The next wafer in the first process chamber is transferred to the second process chamber by the first robotic arm. The time for each process chamber Indicates the next wafer in the... The process time for each process chamber to perform the process. This indicates the time it takes for the wafer to be transferred from the last process chamber to the wafer transfer area by the first robotic arm. Indicates the wafer at the 1st The residence time of each process chamber, , This indicates the total number of the process chambers. This indicates the time it takes for the wafer to be transferred from the wafer transfer area to the first process chamber by the first robotic arm.

7. The method according to claim 6, characterized in that, The step of calculating the minimum number of jobs based on the bottleneck time and the maximum value of the job running cycle includes: The formula for calculating the minimum number of jobs is as follows: in, This represents the minimum number of jobs. This indicates the bottleneck time of the semiconductor device. This indicates the maximum number of job execution cycles.

8. The method according to claim 7, characterized in that, The step of calculating the target time interval based on the minimum number of jobs and the maximum job cycle includes: The formula for calculating the target time interval is as follows: in, Indicates the target time interval, This represents the minimum number of jobs. This indicates the maximum number of job execution cycles.

9. A semiconductor device, characterized in that, The semiconductor device includes a controller and an actuator connected to the controller; wherein the actuator includes: a material storage area, a wafer transfer area, a first robotic arm, a second robotic arm, and multiple process chambers; the material storage area and the wafer transfer area are both used to store wafers, and the process chambers are used to perform process processing on the wafers; The first robotic arm is used to transfer the wafer from the wafer transfer area to the process chamber; or, to transfer the wafer from the process chamber to the wafer transfer area; or, to transfer the wafer from one process chamber to another process chamber. The second robotic arm is used to transfer the wafer from the material storage area to the wafer transfer area, or to transfer the wafer from the wafer transfer area to the material storage area; The controller is configured to control the actuator to execute a Job using the process task control method according to any one of claims 1-8, so that the output of the semiconductor equipment reaches the target production volume.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which, when executed by a processor, performs the steps of the control method for the process task as described in any one of claims 1-8.

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