A method, apparatus, and medium for obtaining a temperature of a chip component

Abstract

The application discloses a kind of methods for obtaining chip element temperature, device and medium, applied to chip technical field.The method is monitored to the first change of basic input-output system end start completion signal, and the basic input-output system start completion signal of complex editable logic device end is set to first level;And, after monitoring high-speed serial computer expansion bus standard interface reset signal is low, the basic input-output system start completion signal of complex editable logic device end is set to second level again.If the basic input-output system start completion signal of complex editable logic device end is first level, then after monitoring temperature acquisition instruction, corresponding register is accessed to obtain the temperature of CPU and memory.This scheme is joined high-speed serial computer expansion bus standard interface reset signal as reference, to ensure that BMC can correctly obtain the temperature of CPU and memory.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a method, apparatus, and medium for obtaining the temperature of chip components. Background Technology

[0002] Due to current chip design limitations, if the Baseboard Manager Controller (BMC) needs to read the temperature of components such as the Central Processing Unit (CPU) and memory, the Basic Input Output System (BIOS) must prepare the CPU and memory resources during the boot phase (POST phase) before modifying the BIOS's boot completion signal (FM_BIOS_POST_CMPLT_N signal). The Complex Programmable Logic Device (CPLD) then passes the low level of the FM_BIOS_POST_CMPLT_N signal to the CPLD's BIOS boot completion signal (CPLD_BMC_BIOS_POST_CMPLT_N signal). Only after the CPLD_BMC_BIOS_POST_CMPLT_N signal is synchronously pulled low can the BMC write to the corresponding registers and then access the corresponding registers to obtain the CPU and memory temperatures. In other words, the BMC must read the CPU and memory temperatures after the BIOS has completed the POST phase.

[0003] As can be seen, in the current solution, the CPLD_BMC_BIOS_POST_CMPLT_N signal serves as a flag signal for obtaining chip component temperatures, and its level changes are only related to the FM_BIOS_POST_CMPLT_N signal. However, due to inherent defects in this type of chip, when the system restarts, the CPLD_BMC_BIOS_POST_CMPLT_N signal cannot be pulled high after the system shuts down. That is, after restarting, the CPLD_BMC_BIOS_POST_CMPLT_N signal remains at a low level. At this time, the BIOS may not have prepared the CPU and memory resources, causing driver mounting failure or memory jamming, thus preventing the BMC from correctly obtaining the CPU and memory temperatures.

[0004] Therefore, how to enable the BMC to correctly obtain the temperature of the CPU and memory is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a method, apparatus, and medium for obtaining the temperature of chip components, so as to solve the problem that BMC cannot correctly obtain the temperature of CPU and memory.

[0006] To solve the above-mentioned technical problems, the present invention provides a method for obtaining the temperature of a chip element, comprising:

[0007] Monitor the high-speed serial computer expansion bus standard interface reset signal and the start-up completion signal of the basic input / output system of the target chip;

[0008] After detecting the first changing edge of the startup completion signal at the basic input / output system terminal, the basic input / output system startup completion signal at the complex programmable logic device terminal is set to a first level; wherein, after the basic input / output system startup phase is completed, a first operation is performed on the startup completion signal at the basic input / output system terminal; if the first operation is a pull-down operation, then the first changing edge is a falling edge;

[0009] After detecting that the reset signal of the high-speed serial computer expansion bus standard interface is low, the basic input / output system startup completion signal of the complex programmable logic device is set to the second level; wherein, the first level and the second level are one of low level and high level, respectively;

[0010] If the basic input / output system startup completion signal of the complex programmable logic device is at the first level, then after detecting the temperature acquisition instruction, the corresponding register is accessed to obtain the temperature of the central processing unit and memory.

[0011] On the other hand, if the basic input / output system startup completion signal of the complex programmable logic device is at the first level, then accessing the corresponding register to obtain the temperature of the central processing unit and memory after detecting the temperature acquisition instruction includes:

[0012] Monitor the basic input / output system startup completion signal at the complex programmable logic device terminal of the target chip;

[0013] If the basic input / output system startup completion signal at the complex programmable logic device is at the first level, then monitor the temperature acquisition command;

[0014] If the temperature acquisition command is detected, the corresponding register is accessed to obtain the temperature of the central processing unit and memory.

[0015] On the other hand, prior to the basic input / output system startup completion signal at the complex programmable logic device terminal of the monitoring target chip, the following is also included:

[0016] Monitor the system power-on signal of the target chip;

[0017] If the system power-on signal is detected, a pre-stored monitoring program is selected;

[0018] The monitoring program is executed to monitor the basic input / output system startup completion signal at the complex programmable logic device terminal of the target chip.

[0019] On the other hand, after the basic input / output system startup completion signal at the complex programmable logic device terminal of the monitoring target chip, the following is also included:

[0020] Monitor the system shutdown signal of the target chip;

[0021] If a system shutdown signal is detected, a pre-stored shutdown procedure is selected;

[0022] The cutoff procedure is executed to cut off monitoring of the basic input / output system start-up completion signal at the terminal of the complex programmable logic device.

[0023] On the other hand, after detecting the second changing edge of the basic input / output system start-up completion signal at the complex programmable logic device, the target chip's system generates the temperature acquisition command; wherein, if the first level is low, the second changing edge is a falling edge;

[0024] Correspondingly, if the basic input / output system startup completion signal at the complex programmable logic device is at the first level, then accessing the corresponding register to obtain the temperature of the central processing unit and memory after detecting the temperature acquisition instruction includes:

[0025] After detecting the second changing edge of the basic input / output system start-up completion signal at the complex programmable logic device, the corresponding registers are accessed to obtain the temperature of the central processing unit and memory.

[0026] On the other hand, it also includes:

[0027] After the basic input / output system startup phase is completed, a second operation is performed on the startup completion signal at the basic input / output system terminal; wherein the first operation and the second operation are respectively one of a pull-down operation and a pull-up operation;

[0028] After the startup completion signal at the basic input / output system terminal completes the second operation, the startup completion signal at the basic input / output system terminal is subjected to the first operation.

[0029] After the start-up completion signal at the basic input / output system terminal completes the first operation, the timer is started;

[0030] A second operation is performed on the start-up completion signal of the basic input / output system terminal after a preset time period based on the count value;

[0031] Wherein, after detecting the first changing edge of the start-up completion signal at the basic input / output system terminal, if the high-speed serial computer expansion bus standard interface reset signal is high, then the basic input / output system start-up completion signal at the complex programmable logic device terminal is set to the first level;

[0032] The high-speed serial computer expansion bus standard interface reset signal goes low after the target chip's system is powered off, and goes high after the target chip's system is powered on.

[0033] On the other hand, after accessing the corresponding registers to obtain the temperatures of the central processing unit and memory upon detecting a temperature acquisition instruction, the process also includes:

[0034] Analyze the obtained temperatures of the central processing unit and memory;

[0035] If the obtained temperatures of the central processing unit and memory do not match the actual temperatures, the basic input / output system startup completion signal at the complex programmable logic device terminal is set to the second level.

[0036] To address the aforementioned technical problems, the present invention also provides an apparatus for obtaining the temperature of a chip element, comprising:

[0037] The monitoring module is used to monitor the high-speed serial computer expansion bus standard interface reset signal and the start-up completion signal of the basic input / output system of the target chip.

[0038] The setting module is used to set the basic input / output system startup completion signal at the complex programmable logic device terminal to a first level after detecting the first changing edge of the startup completion signal at the basic input / output system terminal; wherein, after the basic input / output system startup phase is completed, a first operation is performed on the startup completion signal at the basic input / output system terminal; if the first operation is a pull-down operation, the first changing edge is a falling edge;

[0039] The setting module is further configured to set the basic input / output system startup completion signal of the complex programmable logic device to a second level after detecting that the reset signal of the high-speed serial computer expansion bus standard interface is low; wherein the first level and the second level are one of low level and high level, respectively;

[0040] The acquisition module is used to access the corresponding registers to obtain the temperatures of the central processing unit and memory after detecting a temperature acquisition instruction if the basic input / output system startup completion signal of the complex programmable logic device is at the first level.

[0041] On the other hand, the monitoring module of the device for acquiring chip element temperature is also used to monitor the system power-on signal of the target chip before the basic input / output system startup completion signal at the complex programmable logic device terminal of the target chip is monitored;

[0042] The selection module is used to select a pre-stored monitoring program if the system power-on signal is detected.

[0043] The execution module is also used to execute the monitoring program to monitor the basic input / output system start-up completion signal at the complex programmable logic device terminal of the target chip.

[0044] On the other hand, the monitoring module is also used to monitor the system shutdown signal of the target chip after the basic input / output system startup completion signal of the complex programmable logic device terminal of the target chip is monitored;

[0045] The selection module is also used to select a pre-stored shutdown program if a system shutdown signal is detected.

[0046] The execution module is also used to execute the cutoff procedure to cut off the monitoring of the basic input / output system start-up completion signal at the complex programmable logic device.

[0047] On the other hand, the device for acquiring the temperature of the chip components further includes: an operation module, used to perform a second operation on the startup completion signal of the basic input / output system after the startup phase of the basic input / output system is completed; wherein the first operation and the second operation are respectively one of a pull-down operation and a pull-up operation;

[0048] After the startup completion signal at the basic input / output system terminal completes the second operation, the startup completion signal at the basic input / output system terminal is subjected to the first operation.

[0049] After the start-up completion signal at the basic input / output system terminal completes the first operation, the timer is started;

[0050] Based on the count value, a second operation is performed on the start-up completion signal of the basic input / output system after a preset time.

[0051] On the other hand, the analysis module is used to access the corresponding registers after detecting the temperature acquisition instruction to obtain the temperature of the central processing unit and memory, and then analyze the obtained temperature of the central processing unit and memory.

[0052] The setting module is also used to set the basic input / output system startup completion signal of the complex programmable logic device to a second level if the obtained temperature of the central processing unit and memory does not match the actual temperature.

[0053] To solve the above-mentioned technical problems, the present invention also provides an apparatus for obtaining the temperature of a chip element, comprising: a memory for storing a computer program;

[0054] A processor, used to execute a computer program to implement the steps of the method described above for obtaining the temperature of chip components.

[0055] To address the aforementioned technical problems, the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the method for obtaining the temperature of a chip element described above.

[0056] This invention provides a method for acquiring the temperature of chip components, which involves real-time monitoring of the CPU0_PCIE_RST_N and FM_BIOS_POST_CMPLT_N signals of the target chip, and using these two signals to control the level of the CPLD_BMC_BIOS_POST_CMPLT_N signal. Specifically, after detecting the first changing edge of the FM_BIOS_POST_CMPLT_N signal, the CPLD_BMC_BIOS_POST_CMPLT_N signal is set to a first level; and after detecting that the CPU0_PCIE_RST_N signal is low, the CPLD_BMC_BIOS_POST_CMPLT_N signal is set to a second level. If the CPLD_BMC_BIOS_POST_CMPLT_N signal is at the first level, the corresponding register is accessed to obtain the temperature of the CPU and memory after a temperature acquisition instruction is detected. Specifically, after the BIOS POST phase is completed, a first operation is performed on the FM_BIOS_POST_CMPLT_N signal; if the first operation is a pull-low operation, the first changing edge is a falling edge; the first level and the second level are respectively one of a low level and a high level. The beneficial effect of this solution is that it incorporates the CPU0_PCIE_RST_N signal as a reference to control the level of the CPLD_BMC_BIOS_POST_CMPLT_N signal. The CPU0_PCIE_RST_N signal is high when the system powers on and low when the system powers off. Compared to the original solution, this solution can reset the CPLD_BMC_BIOS_POST_CMPLT_N signal to high using the CPU0_PCIE_RST_N signal. After the target chip's system restarts, only after the BIOS POST phase is completed and the FM_BIOS_POST_CMPLT_N signal generates a falling edge will the CPLD_BMC_BIOS_POST_CMPLT_N signal return to low. At this point, the BIOS has prepared the CPU and memory resources, thus ensuring that the BMC can correctly obtain the CPU and memory temperatures.

[0057] Specifically, by monitoring the CPLD_BMC_BIOS_POST_CMPLT_N signal in real time, monitoring for temperature acquisition commands begins when the signal changes to its first level. This means that temperature acquisition is performed only when the command arrives and the temperature data is accurate, ensuring rapid and accurate temperature data acquisition each time. Monitoring the CPLD_BMC_BIOS_POST_CMPLT_N signal after the chip's system boots up ensures timely determination of when the correct temperature can be acquired. Disconnecting the monitoring program after the chip's system shuts down avoids resource waste. Performing a temperature acquisition when the CPLD_BMC_BIOS_POST_CMPLT_N signal changes to its first level ensures timely and accurate CPU and memory temperatures. If the acquired temperature does not match the actual temperature, the CPLD_BMC_BIOS_POST_CMPLT_N signal is changed to its second level to prevent continuous acquisition of incorrect temperatures. Furthermore, after the boot phase is complete, a first operation pulls the FM_BIOS_POST_CMPLT_N signal low, followed by a second operation pulling it high, ensuring that the FM_BIOS_POST_CMPLT_N signal is high after the next restart. Before performing the first operation during the startup phase, a second operation can be performed first. This resolves the issue where the system abnormally restarts when the FM_BIOS_POST_CMPLT_N signal is pulled low during the first operation, preventing the subsequent second operation from being performed. By performing the second operation beforehand, it is ensured that the first changing edge of the FM_BIOS_POST_CMPLT_N signal can be detected.

[0058] The present invention also provides an apparatus for obtaining the temperature of a chip element and a computer-readable storage medium, which correspond to the above-described method and therefore have the same beneficial effects as the above-described method. Attached Figure Description

[0059] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0060] Figure 1 A flowchart of a method for obtaining the temperature of a chip component provided in an embodiment of the present invention;

[0061] Figure 2 A detailed flowchart of a signal level change provided in an embodiment of the present invention;

[0062] Figure 3 This is a structural diagram of the device for obtaining the temperature of a chip element provided in an embodiment of the present invention;

[0063] Figure 4 This is a structural diagram of an apparatus for obtaining the temperature of a chip element, provided in another embodiment of the present invention. Detailed Implementation

[0064] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0065] The core of this invention is to provide a method, apparatus, and medium for obtaining the temperature of chip components, so as to solve the problem that BMC cannot correctly obtain the temperature of CPU and memory.

[0066] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0067] This invention relates to temperature acquisition of components such as the CPU and memory in some chips. The CPU, as the computing and control core of a computer system, is the final execution unit for information processing and program execution. The memory is used to temporarily store the computing data in the CPU and the data exchanged with external storage devices such as hard disks. The temperature of both is very important for the normal operation of the chip, so it is necessary to acquire the temperature data of the components when they are working. In the original scheme, after the chip is powered on by DC power, the FM_BIOS_POST_CMPLT_N signal configured by the CPU is high by default. The hardware implementation logic is that after the CPU completes the BIOS POST phase, it pulls the FM_BIOS_POST_CMPLT_N signal low and sends it to the CPLD. The CPLD then passes the low-level FM_BIOS_POST_CMPLT_N signal through to the CPLD_BMC_BIOS_POST_CMPLT_N signal (a flag signal used to determine whether to acquire temperature). After the CPLD synchronously pulls the CPLD_BMC_BIOS_POST_CMPLT_N signal low, it sends it to the BMC as a signal to indicate the completion of the BIOS POST phase. During this process, the CPLD's operation is to directly pass the low-level FM_BIOS_POST_CMPLT_N signal through to the CPLD_BMC_BIOS_POST_CMPLT_N signal to synchronously pull it low.

[0068] However, since the BMC's logic for obtaining CPU and memory temperatures requires that CPLD_BMC_BIOS_POST_CMPLT_N be consistently low in order to access the CPU temperature register and memory SPD (Serial Presence Detect), the BIOS needs to keep CPLD_BMC_BIOS_POST_CMPLT_N low. Furthermore, after the operating system (OS) is running, the BIOS cannot raise this signal again unless there are other interrupt signals. If the system restarts at this time, before the BIOS completes its boot process and configures the CPU resources to gain control, the FM_BIOS_POST_CMPLT_N and CPLD_BMC_BIOS_POST_CMPLT_N signals will remain low (due to a defect in some CPUs, the CPU will not pull these two signals high when it detects power-off). During this period, after the BMC detects the power-on signal, it will repeatedly try to obtain the CPLD_BMC_BIOS_POST_CMPLT_N signal. At this time, this signal is low, and the BMC considers the BIOSPOST phase to be complete. It will then attempt to mount the driver, access the CPU registers, and switch control of the SPD bus. However, at this time, the BIOS has not prepared the CPU and memory resources, which will cause the driver mounting to fail and memory to get stuck. As a result, the BMC cannot correctly obtain the temperature of the CPU and memory.

[0069] To address the aforementioned technical problems, embodiments of the present invention provide a method for obtaining the temperature of chip components. Figure 1 A flowchart illustrating a method for obtaining the temperature of a chip component according to an embodiment of the present invention; as shown below. Figure 1 As shown, the method includes the following steps:

[0070] S10: The high-speed serial computer expansion bus standard interface reset signal and the start-up completion signal of the basic input / output system terminal of the monitoring target chip.

[0071] S11: After detecting the first changing edge of the start-up completion signal at the basic input / output system terminal, set the basic input / output system start-up completion signal at the complex programmable logic device terminal to the first level; after detecting that the high-speed serial computer extended bus standard interface reset signal is low, set the basic input / output system start-up completion signal at the complex programmable logic device terminal to the second level.

[0072] S12: If the basic input / output system startup completion signal of the complex programmable logic device is at the first level, then after detecting the temperature acquisition instruction, the corresponding register is accessed to obtain the temperature of the central processing unit and memory.

[0073] The reset signal for the Peripheral Component Interconnect Express (PCIE) standard interface is CPU0_PCIE_RST_N. As mentioned above, the boot completion signal for the Basic Input / Output System (BIOS) is FM_BIOS_POST_CMPLT_N, and the BIOS boot completion signal for Complex Programmable Logic Devices (CPLMDs) is CPLD_BMC_BIOS_POST_CMPLT_N. After the chip's BIOS POST phase is complete, the system controller performs a first operation on the FM_BIOS_POST_CMPLT_N signal. If the first operation is a pull-low operation, the first transition edge is a falling edge; conversely, if the first operation is a pull-high operation, the first transition edge is a rising edge. The first and second levels are respectively a low level and a high level. Furthermore, during hot reset / cold reset / OS restart, the CPU pulls the CPU0_PCIE_RST_N signal low. Therefore, the CPU0_PCIE_RST_N signal is high when the system powers on and low when the system powers off; this is an inherent characteristic of the signal. This invention utilizes this characteristic to control the CPLD_BMC_BIOS_POST_CMPLT_N signal.

[0074] This section describes a specific implementation of the above scheme. Specifically, the first level is a low level, the first operation is a pull-low operation, and the first changing edge is a falling edge. After the device is powered on (power plugged in but the power button is not pressed), the FM_BIOS_POST_CMPLT_N signal is configured to be high by default, the CPU0_PCIE_RST_N signal is low by default, and the CPLD will also pull the CPLD_BMC_BIOS_POST_CMPLT_N signal high by default upon power-on. At this time, the BMC, upon reading that the CPLD_BMC_BIOS_POST_CMPLT_N signal is high, will continuously loop, waiting for a low level to appear in order to read the temperature. After the power button is pressed and the computer is turned on, the CPU0_PCIE_RST_N signal will briefly go high. After the BIOSPOST phase is completed, the BIOS first pulls the FM_BIOS_POST_CMPLT_N signal high (for example, if the FM_BIOS_POST_CMPLT_N signal was low during the last abnormal shutdown, it will remain low upon restarting; this high pull resolves that issue). Then, the BIOS pulls the FM_BIOS_POST_CMPLT_N signal low for a preset duration (which can be set to 100ms). At this time, the CPLD detects the falling edge of the FM_BIOS_POST_CMPLT_N signal, and since the CPU0_PCIE_RST_N signal is high, it pulls the CPLD_BMC_BIOS_POST_CMPLT_N signal low. After the BMC detects that the CPLD_BMC_BIOS_POST_CMPLT_N signal is low, it stops looping for signal acquisition and loads the driver to access the CPU registers and switch SPD bus control to read the CPU and memory temperatures. After 100ms, the BIOS pulls the FM_BIOS_POST_CMPLT_N signal high again (this avoids it being low during a reboot), and then keeps it high until the next BIOS POST phase is completed. However, the CPLD and BMC do not perform any processing during this time, so the CPLD_BMC_BIOS_POST_CMPLT_N signal will remain low until the system shuts down. During this period, the CPU temperature and memory temperature obtained by the BMC are unaffected.

[0075] After the device is powered off, the CPU0_PCIE_RST_N signal is pulled low. When the CPLD detects that the CPU0_PCIE_RST_N signal is low, it pulls the CPLD_BMC_BIOS_POST_CMPLT_N signal high. After the BMC detects the power-off signal, it cuts off the CPU and memory temperature acquisition program. The BMC then waits for the power-on signal. After the power-on signal is received, it checks the CPLD_BMC_BIOS_POST_CMPLT_N signal again. If it finds that the signal has been pulled high by the CPLD, it will continuously loop, waiting for a low signal before reading the temperature.

[0076] The above solution is explained below using a flowchart. Figure 2 A detailed flowchart illustrating signal level changes is provided in an embodiment of the present invention; as follows: Figure 2As shown, the specific steps of this scheme are as follows: S20: Power on the chip (plug in the power but do not press the power button), and perform default signal configuration. S21: After the device is powered on, the signal changes from BIOS to CPLD, then from CPLD to BMC, and the BMC obtains the CPU and memory temperatures. S22: After the device is powered off, the state changes, and the BMC cuts off the acquisition of CPU and memory temperatures. Specifically, the process of step S20 is as follows: After the chip is powered on, signal 1 (CPU0_PCIE_RST_N) is set to low level by default; signal 2 (FM_BIOS_POST_CMPLT_N) is set to high level by default; signal 3 (CPLD_BMC_BIOS_POST_CMPLT_N) is set to high level by default. Further, the process of step S21 is as follows: After power-on, process 7 is triggered, signal 1 is pulled high, and process 11 is also triggered. After receiving the power-on signal, the BMC continuously waits for signal 3 to go low to read the temperature. After the BIOS POST phase is completed, it triggers process 1, first pulling signal 2 high (to prevent signal 2 from being low due to the previous abnormal shutdown); the CPLD does not process the high signal 2. Then the BIOS continues process 1, pulling signal 2 low for 100ms. At this time, the CPLD detects the falling edge of signal 2 and triggers process 4, checking signal 1. If signal 1 is high, it immediately triggers process 5, pulling signal 3 low, and then triggers process 10. The BMC detects that signal 3 is low and loads the driver, accesses the CPU registers, switches SPD bus control, and reads the CPU and memory temperatures. Finally, the BIOS continues process 1 to pull signal 2 high (to avoid signal 2 being low during restart), and keeps it high until the next BIOS POST phase is completed. During this time, the CPLD and BMC do not perform any processing. Further, the specific process of step S23 is as follows: after shutdown, process 6 is triggered, pulling signal 1 low. When signal 1 is pulled low, process 12 is triggered. The BMC detects that the system has shut down and will automatically cut off the CPU and memory temperature acquisition processes. When signal 1 is pulled low, process 8 is also triggered. When the CPLD detects that signal 1 has been pulled low, it triggers process 9, which pulls signal 3 high.

[0077] This invention uses the signal changes of BIOS and CPLD as reference information for temperature acquisition. Under various boot conditions such as power-on / off, cold restart, hot restart, booting after unexpected power failure, and normal power-on / off, the BMC can accurately obtain the CPU and memory temperatures. This software approach addresses hardware deficiencies, avoids modifying the hardware platform, and reduces hardware costs.

[0078] This invention provides a method for acquiring the temperature of chip components. It monitors the CPU0_PCIE_RST_N and FM_BIOS_POST_CMPLT_N signals of the target chip in real time, and uses these two signals to control the level of the CPLD_BMC_BIOS_POST_CMPLT_N signal. Specifically, after detecting the first changing edge of the FM_BIOS_POST_CMPLT_N signal, the CPLD_BMC_BIOS_POST_CMPLT_N signal is set to a first level; and after detecting that the CPU0_PCIE_RST_N signal is low, the CPLD_BMC_BIOS_POST_CMPLT_N signal is set to a second level. If the CPLD_BMC_BIOS_POST_CMPLT_N signal is at the first level, the corresponding register is accessed to obtain the temperatures of the CPU and memory after a temperature acquisition instruction is detected. Specifically, after the BIOS POST phase is completed, a first operation is performed on the FM_BIOS_POST_CMPLT_N signal; if the first operation is a pull-low operation, the first changing edge is a falling edge; the first level and the second level are respectively a low level and a high level. The beneficial effect of this solution is that it incorporates the CPU0_PCIE_RST_N signal as a reference to control the level of the CPLD_BMC_BIOS_POST_CMPLT_N signal. The CPU0_PCIE_RST_N signal is high when the system powers on and low when the system powers off. Compared to the original solution, this solution can reset the CPLD_BMC_BIOS_POST_CMPLT_N signal to high using the CPU0_PCIE_RST_N signal. After the target chip's system restarts, only after the BIOS POST phase is completed and the FM_BIOS_POST_CMPLT_N signal generates a falling edge will the CPLD_BMC_BIOS_POST_CMPLT_N signal return to low. At this point, the BIOS has prepared the CPU and memory resources, thus ensuring that the BMC can correctly obtain the CPU and memory temperatures.

[0079] The above embodiment mentions that if the CPLD_BMC_BIOS_POST_CMPLT_N signal is at the first level, the corresponding register is accessed to obtain the CPU and memory temperatures after a temperature acquisition command is detected. In practical applications, the specific implementation scheme is not limited. The CPLD_BMC_BIOS_POST_CMPLT_N signal of the target chip can be monitored in real time. If the signal is at the first level, it indicates that the falling edge of the FM_BIOS_POST_CMPLT_N signal has been detected, that is, the BIOS POST stage of the chip is completed, and the temperature can be obtained normally at this time. Then, the action of monitoring the temperature acquisition command can be performed. If the temperature acquisition command is detected, the corresponding register is accessed to obtain the CPU and memory temperatures. This scheme can obtain the correct CPU and memory temperatures. Moreover, under normal circumstances, after the second changing edge of the CPLD_BMC_BIOS_POST_CMPLT_N signal is detected, the target chip system will directly generate a temperature acquisition command; that is, after the second changing edge of the CPLD_BMC_BIOS_POST_CMPLT_N signal is detected, the BMC directly accesses the corresponding register to obtain the CPU and memory temperatures. Wherein, if the first level is low, the second transition edge is a falling edge; correspondingly, if the first level is high, the second transition edge is a rising edge.

[0080] As mentioned in the above embodiments, the CPLD_BMC_BIOS_POST_CMPLT_N signal is a flag signal used to determine whether the temperature can be correctly acquired. The above scheme determines that the temperature can be acquired after monitoring the CPLD_BMC_BIOS_POST_CMPLT_N signal to change to the first level. However, in practical applications, it is not necessary to continuously monitor the CPLD_BMC_BIOS_POST_CMPLT_N signal. For example, after the system is shut down, the CPLD_BMC_BIOS_POST_CMPLT_N signal will change to the second level, at which point monitoring is meaningless. Therefore, this embodiment provides a solution that, before monitoring the CPLD_BMC_BIOS_POST_CMPLT_N signal of the target chip, further includes: monitoring the system power-on signal of the target chip; if the system power-on signal is detected, selecting a pre-stored monitoring program; and then executing the monitoring program to monitor the CPLD_BMC_BIOS_POST_CMPLT_N signal of the target chip. After monitoring the CPLD_BMC_BIOS_POST_CMPLT_N signal of the target chip, the system shutdown signal of the target chip can also be monitored. If a system shutdown signal is detected, a pre-stored cutoff procedure is selected; then the cutoff procedure is executed to cut off the monitoring of the CPLD_BMC_BIOS_POST_CMPLT_N signal. The solution provided in this embodiment avoids invalid monitoring of the CPLD_BMC_BIOS_POST_CMPLT_N signal, reducing resource waste.

[0081] In practical applications, after the basic input / output system (BIOS) startup phase is completed, a second operation can be performed on the FM_BIOS_POST_CMPLT_N signal. The first and second operations are respectively a pull-low and pull-high operation. As mentioned in the above embodiment, if the first operation is a pull-low operation, the first changing edge is a falling edge; correspondingly, the second operation is a pull-high operation. After the FM_BIOS_POST_CMPLT_N signal completes the second operation, the first operation is performed again, at which point the first changing edge of the FM_BIOS_POST_CMPLT_N signal can be detected. After the FM_BIOS_POST_CMPLT_N signal completes the first operation, a timer is started. Based on the count value, the second operation is performed again on the FM_BIOS_POST_CMPLT_N signal after a preset duration. Performing the second operation at this time avoids the signal being low during a reboot. The first second operation mentioned above is to prevent the system from shutting down abnormally before the second second operation is executed, which would prevent the detection of the first falling edge of the FM_BIOS_POST_CMPLT_N signal. Taking the first operation as a low-level pull as an example, if the FM_BIOS_POST_CMPLT_N signal was low during the previous abnormal shutdown, it will remain low upon restarting. The first second operation pulls it high, thus resolving the issue of not being able to detect the falling edge of the FM_BIOS_POST_CMPLT_N signal. Furthermore, when setting the CPLD_BMC_BIOS_POST_CMPLT_N signal to the first level, the CPU0_PCIE_RST_N signal can be used as a reference. Specifically, after detecting the first falling edge of the FM_BIOS_POST_CMPLT_N signal, if the CPU0_PCIE_RST_N signal is high, then the CPLD_BMC_BIOS_POST_CMPLT_N signal is set to the first level. Because the CPU0_PCIE_RST_N signal goes low after the target chip's system is powered off, and goes high after the target chip's system is powered on, this scheme ensures that the system is powered on when acquiring temperature, thus avoiding some abnormal situations.

[0082] In practice, there may be situations where the acquired temperature differs significantly from the actual temperature, indicating that the correct temperature cannot be obtained. Therefore, after detecting a temperature acquisition command and accessing the corresponding registers to obtain the CPU and memory temperatures, the acquired CPU and memory temperatures can be analyzed. If the acquired CPU and memory temperatures do not match the actual temperatures, the CPLD_BMC_BIOS_POST_CMPLT_N signal is set to the second level. The solution provided by this invention can prevent the BMC from continuously acquiring incorrect temperatures.

[0083] In the above embodiments, the method for obtaining the temperature of chip components has been described in detail. The present invention also provides embodiments corresponding to the apparatus for obtaining the temperature of chip components. It should be noted that the embodiments of the apparatus are described from two perspectives: one based on functional modules, and the other based on hardware.

[0084] From the perspective of functional modules, this embodiment provides a device for acquiring the temperature of chip components. Figure 3 A structural diagram of the device for obtaining the temperature of a chip element provided in an embodiment of the present invention is shown below. Figure 3 As shown, the device includes:

[0085] Monitoring module 10 is used to monitor the CPU0_PCIE_RST_N signal and the FM_BIOS_POST_CMPLT_N signal of the target chip;

[0086] The setting module 11 is further configured to set the CPLD_BMC_BIOS_POST_CMPLT_N signal to a first level after detecting the first changing edge of the FM_BIOS_POST_CMPLT_N signal; wherein, after the basic input / output system startup phase is completed, a first operation is performed on the FM_BIOS_POST_CMPLT_N signal; if the first operation is a pull-low operation, then the first changing edge is a falling edge;

[0087] The setting module 11 is also used to set the CPLD_BMC_BIOS_POST_CMPLT_N signal to a second level after detecting that the CPU0_PCIE_RST_N signal is low; wherein the first level and the second level are one of the low level and the high level, respectively;

[0088] The acquisition module 12 is used to access the corresponding register to obtain the temperature of the central processing unit and memory after detecting a temperature acquisition instruction if the CPLD_BMC_BIOS_POST_CMPLT_N signal is at the first level.

[0089] Since the embodiments of the apparatus and the embodiments of the method correspond to each other, please refer to the description of the embodiments of the method for the embodiments of the apparatus, which will not be repeated here.

[0090] In some embodiments, the monitoring module of the device for acquiring chip component temperature is further configured to monitor the system power-on signal of the target chip before monitoring the CPLD_BMC_BIOS_POST_CMPLT_N signal of the target chip;

[0091] The selection module is used to select a pre-stored monitoring program if a system power-on signal is detected.

[0092] The execution module is also used to execute a monitoring program to monitor the CPLD_BMC_BIOS_POST_CMPLT_N signal of the target chip.

[0093] The monitoring module is also used to monitor the system shutdown signal of the target chip after monitoring the CPLD_BMC_BIOS_POST_CMPLT_N signal of the target chip;

[0094] The selection module is also used to select a pre-stored shutdown procedure if a system shutdown signal is detected.

[0095] The execution module is also used to execute a cutoff procedure to cut off monitoring of the CPLD_BMC_BIOS_POST_CMPLT_N signal.

[0096] The operation module is used to perform a second operation on the FM_BIOS_POST_CMPLT_N signal after the basic input / output system startup phase is completed; wherein the first operation and the second operation are respectively one of the pull-low level operation and the pull-high level operation;

[0097] After the second operation is completed on the FM_BIOS_POST_CMPLT_N signal, the first operation is performed on the FM_BIOS_POST_CMPLT_N signal;

[0098] The timer starts after the FM_BIOS_POST_CMPLT_N signal completes its first operation;

[0099] The second operation is performed on the FM_BIOS_POST_CMPLT_N signal after a preset time based on the count value.

[0100] The analysis module is used to access the corresponding registers after detecting a temperature acquisition command to obtain the temperature of the central processing unit and memory, and then analyze the obtained temperature of the central processing unit and memory.

[0101] The setting module is also used to set the CPLD_BMC_BIOS_POST_CMPLT_N signal to the second level if the obtained temperatures of the central processing unit and memory do not match the actual temperatures.

[0102] The device for obtaining the temperature of chip components provided in this embodiment corresponds to the method described above, and therefore has the same beneficial effects as the method described above.

[0103] From a hardware perspective, this embodiment provides another device for acquiring the temperature of chip components. Figure 4 A structural diagram of a device for obtaining the temperature of a chip element provided in another embodiment of the present invention is shown below. Figure 4 As shown, the device for obtaining the temperature of chip components includes: a memory 20 for storing computer programs;

[0104] The processor 21 is configured to execute a computer program to implement the steps of the method for obtaining the temperature of chip elements as described in the above embodiments.

[0105] The processor 21 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 21 may be implemented using at least one of the following hardware forms: Digital Signal Processor (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 21 may also include a main processor and a coprocessor. The main processor, also known as the CPU, is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 21 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 21 may also include an Artificial Intelligence (AI) processor, which is used to handle computational operations related to machine learning.

[0106] The memory 20 may include one or more computer-readable storage media, which may be non-transitory. The memory 20 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 20 is used to store at least the following computer program 201, which, after being loaded and executed by the processor 21, is capable of implementing the relevant steps of the method for obtaining the temperature of a chip element disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 20 may also include an operating system 202 and data 203, and the storage method may be temporary or permanent storage. The operating system 202 may include Windows, Unix, Linux, etc. The data 203 may include, but is not limited to, data related to the method for obtaining the temperature of a chip element.

[0107] In some embodiments, the device for acquiring the temperature of chip components may further include a display screen 22, an input / output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.

[0108] Those skilled in the art will understand that the structure shown in the figure does not constitute a limitation on the device for obtaining the temperature of chip components, and may include more or fewer components than shown.

[0109] The device for obtaining the temperature of a chip component provided in this embodiment of the invention includes a memory and a processor. When the processor executes a program stored in the memory, it can implement the following method: a method for obtaining the temperature of a chip component.

[0110] The device for obtaining the temperature of chip components provided in this embodiment corresponds to the method described above, and therefore has the same beneficial effects as the method described above.

[0111] Finally, the present invention also provides an embodiment corresponding to a computer-readable storage medium. The computer-readable storage medium stores a computer program, which, when executed by a processor, performs the steps described in the above method embodiments.

[0112] It is understood that if the methods in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0113] The computer-readable storage medium provided in this embodiment corresponds to the method described above, and therefore has the same beneficial effects as the method described above.

[0114] The present invention has provided a detailed description of a method, apparatus, and medium for obtaining the temperature of a chip element. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make various improvements and modifications to the present invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

[0115] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the aforementioned element.

Claims

1. A method for obtaining the temperature of a chip element, characterized in that, include: Monitor the high-speed serial computer expansion bus standard interface reset signal and the start-up completion signal of the basic input / output system of the target chip; After detecting the first changing edge of the startup completion signal at the basic input / output system terminal, the basic input / output system startup completion signal at the complex programmable logic device terminal is set to a first level; wherein, after the basic input / output system startup phase is completed, a first operation is performed on the startup completion signal at the basic input / output system terminal; if the first operation is a pull-down operation, then the first changing edge is a falling edge; After detecting that the reset signal of the high-speed serial computer expansion bus standard interface is low, the basic input / output system startup completion signal of the complex programmable logic device is set to the second level; wherein, the first level and the second level are one of low level and high level, respectively; If the basic input / output system startup completion signal of the complex programmable logic device is at the first level, then after detecting the temperature acquisition instruction, the corresponding register is accessed to obtain the temperature of the central processing unit and memory; Correspondingly, if the basic input / output system startup completion signal at the complex programmable logic device is at the first level, then accessing the corresponding register to obtain the temperature of the central processing unit and memory after detecting the temperature acquisition instruction includes: Monitor the basic input / output system startup completion signal at the complex programmable logic device terminal of the target chip; If the basic input / output system startup completion signal at the complex programmable logic device is at the first level, then monitor the temperature acquisition command; If the temperature acquisition command is detected, the corresponding register is accessed to obtain the temperature of the central processing unit and memory.

2. The method for obtaining the temperature of a chip element according to claim 1, characterized in that, Before the basic input / output system startup completion signal at the complex programmable logic device terminal of the target chip, the following is also included: Monitor the system power-on signal of the target chip; If the system power-on signal is detected, a pre-stored monitoring program is selected; The monitoring program is executed to monitor the basic input / output system startup completion signal at the complex programmable logic device terminal of the target chip.

3. The method for obtaining the temperature of a chip element according to claim 2, characterized in that, After the basic input / output system startup completion signal at the complex programmable logic device terminal of the monitoring target chip, the following is also included: Monitor the system shutdown signal of the target chip; If a system shutdown signal is detected, a pre-stored shutdown procedure is selected; The cutoff procedure is executed to cut off monitoring of the basic input / output system start-up completion signal at the terminal of the complex programmable logic device.

4. The method for obtaining the temperature of a chip element according to claim 1, characterized in that, After detecting the second changing edge of the basic input / output system start-up completion signal at the complex programmable logic device, the target chip's system generates the temperature acquisition command; wherein, if the first level is low, the second changing edge is a falling edge; Correspondingly, if the basic input / output system startup completion signal at the complex programmable logic device is at the first level, then accessing the corresponding register to obtain the temperature of the central processing unit and memory after detecting the temperature acquisition instruction includes: After detecting the second changing edge of the basic input / output system start-up completion signal at the complex programmable logic device, the corresponding registers are accessed to obtain the temperature of the central processing unit and memory.

5. The method for obtaining the temperature of a chip element according to any one of claims 1 to 4, characterized in that, Also includes: After the basic input / output system startup phase is completed, a second operation is performed on the startup completion signal at the basic input / output system terminal; wherein the first operation and the second operation are respectively one of a pull-down operation and a pull-up operation; After the startup completion signal at the basic input / output system terminal completes the second operation, the startup completion signal at the basic input / output system terminal is subjected to the first operation. After the start-up completion signal at the basic input / output system terminal completes the first operation, the timer is started; A second operation is performed on the start-up completion signal of the basic input / output system terminal after a preset time period based on the count value; Wherein, after detecting the first changing edge of the start-up completion signal at the basic input / output system terminal, if the high-speed serial computer expansion bus standard interface reset signal is high, then the basic input / output system start-up completion signal at the complex programmable logic device terminal is set to the first level; The high-speed serial computer expansion bus standard interface reset signal goes low after the target chip's system is powered off, and goes high after the target chip's system is powered on.

6. The method for obtaining the temperature of a chip element according to claim 1, characterized in that, After detecting a temperature acquisition instruction and accessing the corresponding registers to obtain the temperatures of the central processing unit and memory, the process further includes: Analyze the obtained temperatures of the central processing unit and memory; If the obtained temperatures of the central processing unit and memory do not match the actual temperatures, the basic input / output system startup completion signal at the complex programmable logic device terminal is set to the second level.

7. A device for obtaining the temperature of a chip element, characterized in that, include: The monitoring module is used to monitor the high-speed serial computer expansion bus standard interface reset signal and the start-up completion signal of the basic input / output system of the target chip. The setting module is used to set the basic input / output system startup completion signal at the complex programmable logic device terminal to a first level after detecting the first changing edge of the startup completion signal at the basic input / output system terminal; wherein, after the basic input / output system startup phase is completed, a first operation is performed on the startup completion signal at the basic input / output system terminal; if the first operation is a pull-down operation, the first changing edge is a falling edge; The setting module is further configured to set the basic input / output system startup completion signal of the complex programmable logic device to a second level after detecting that the reset signal of the high-speed serial computer expansion bus standard interface is low; wherein the first level and the second level are one of low level and high level, respectively; The acquisition module is used to access the corresponding register to obtain the temperature of the central processing unit and memory after detecting a temperature acquisition instruction if the basic input / output system startup completion signal of the complex programmable logic device is at the first level. Correspondingly, if the basic input / output system startup completion signal at the complex programmable logic device is at the first level, then accessing the corresponding register to obtain the temperature of the central processing unit and memory after detecting the temperature acquisition instruction includes: Monitor the basic input / output system startup completion signal at the complex programmable logic device terminal of the target chip; If the basic input / output system startup completion signal at the complex programmable logic device is at the first level, then monitor the temperature acquisition command; If the temperature acquisition command is detected, the corresponding register is accessed to obtain the temperature of the central processing unit and memory.

8. A device for obtaining the temperature of a chip element, characterized in that, Includes memory used to store computer programs; A processor, configured to implement the steps of the method for obtaining the temperature of a chip element as described in any one of claims 1 to 6 when executing the computer program.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the method for obtaining the temperature of a chip element as described in any one of claims 1 to 6.

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