A method for adaptive SSD prefetchers

Abstract

An adaptive SSD prefetcher method, relating to the field of SSD storage technology, dynamically adjusts the prefetch strategy under different workloads, processes subsequent read commands in advance, reads data from flash memory into DRAM, and when a subsequent read command hits, directly transmits the data to the host. This prefetch method shortens the read latency under small queue depth conditions and greatly improves IOPS.

Description

Technical Field

[0001] This invention relates to the field of SSD storage technology, and more specifically to a method for an adaptive SSD prefetcher. Background Technology

[0002] With the rapid development of artificial intelligence, big data, and cloud computing, solid-state drives (SSDs) are gradually replacing HDDs as an important storage medium. Their high performance and low latency make them the preferred choice for these scenarios. To improve SSD performance and reduce latency, prefetching functionality has been introduced into SSD firmware algorithms. Traditional prefetching algorithms often employ static prefetching strategies for specific scenarios, which cannot adapt to the needs of multiple scenarios. Summary of the Invention

[0003] To overcome the shortcomings of the above technologies, this invention provides a method for an adaptive SSD prefetcher that shortens read latency and greatly improves IOPS under small queue depth conditions.

[0004] The technical solution adopted by this invention to overcome its technical problems is:

[0005] A method for an adaptive SSD prefetcher includes:

[0006] Monitor SSD workload and obtain workload information;

[0007] Analyze the workload based on the obtained workload information;

[0008] Calculate the logical address FPL of the first prefetch during prefetch startup;

[0009] When bad blocks exist in the prefetched physical address multipage, calculate the number of prefetched data frames Df. cnt Send a read command to the NAND FLASH to perform a prefetch operation; the amount of data prefetched is the number of data frames, Df. cnt Perform a prefetch hit check on newly received read requests;

[0010] The prefetch parameters are updated based on workload and prefetch hit rate.

[0011] Furthermore, the method for monitoring SSD workload is to obtain SSD workload information by monitoring the SSD controller's read operations and I / O request patterns, queue depth, and block size.

[0012] Furthermore, the method for analyzing workloads is as follows:

[0013] Based on the obtained workload information, data statistics and analysis are performed by using the logical address and length of the read command to determine whether it is a continuous read or a random read. If it is a random read, no pre-read operation is performed.

[0014] The ratio of continuous reads to random reads is statistically analyzed. Random reads are deleted, and if random reads are not performed, a prefetch operation is performed to reserve backend bandwidth resources for random read operations. When the random read bandwidth in historical data exceeds 120% of the backend bandwidth, the prefetch operation is stopped.

[0015] If the queue depth and block size in the workload information meet the maximum front-end bandwidth without prefetching, then prefetching is canceled.

[0016] Furthermore, the method for determining whether the queue depth and block size in the workload information meet the maximum front-end bandwidth in the absence of prefetching is as follows: when the data transmission time of the queue depth and block size in the workload information is greater than the back-end NAND busy time, it is determined that the maximum front-end bandwidth is met.

[0017] Furthermore, through the formula Calculate the logical address FPL of the first prefetch at the start of prefetch, where CS is the current read rate, Be_bw is the backend bandwidth, BT is the typical busy time of NAND flash read operation, and CL is the current logical address of the command.

[0018] Furthermore, through the formula The number of prefetched data frames, Df, is calculated. cnt In the formula, Fe bw PR is the front-end bandwidth, Bs is the IO pressure value, RR is the random read ratio, and RT is the prefetch coefficient.

[0019] Furthermore, when sending a read command to the NAND FLASH to perform a prefetch operation, if the physical address to be prefetched is on the same LUN as the currently existing random read operation, it is determined whether the logical address to be prefetched is a later logical address or a earlier logical address. If it is a later logical address, the current random read operation is performed, and the prefetch operation is postponed after the random read operation. If it is an earlier logical address, the prefetch operation is not postponed.

[0020] Furthermore, if the prefetched logical address minus the current logical address is greater than the queue depth multiplied by the block size, then the logical address is a later logical address; if the prefetched logical address minus the current logical address is less than or equal to the queue depth multiplied by the block size, then the logical address is a earlier logical address.

[0021] Furthermore, the method for prefetching hit checks on newly received read requests is as follows:

[0022] If the logical address has been prefetched and the required data is in memory, it is considered a hit, and the hit data is transmitted to the host.

[0023] If the logical address has not been prefetched before, or if the data required for a previously prefetched address has not yet been read from the NAND into the memory set, it is considered a miss, and the prefetched data is discarded.

[0024] Furthermore, the method for transmitting the hit data to the host is as follows:

[0025] If the prefetch buffer is full, the data prefetching speed will be reduced to half of the previous prefetch speed.

[0026] If a prefetched logical address is hit, but the data has not yet been read from the NAND to the DRAM, the prefetch speed is slow, and the amount of prefetched data is increased by twice the length of the read command.

[0027] The beneficial effects of this invention are: it can significantly improve IOPS performance under different load pressure scenarios, greatly reduce IO read latency, reduce IO latency jitter, effectively improve SSD QoS, reduce waiting time for upper-layer applications, and improve user experience. Attached Figure Description

[0028] Figure 1 This is a flowchart of the method of the present invention. Detailed Implementation

[0029] The following is in conjunction with the appendix Figure 1 The present invention will be further described below.

[0030] A method for an adaptive SSD prefetcher includes:

[0031] Monitor SSD workload to obtain workload information.

[0032] Analyze the workload based on the obtained workload information.

[0033] Calculate the logical address FPL of the first prefetch during prefetch startup.

[0034] When bad blocks exist in the prefetched physical address multipage, calculate the number of prefetched data frames Df. cnt A read command is sent to the NAND FLASH to perform a prefetch operation, with the prefetch data amount being the number of data frames, Df. cnt .

[0035] Perform a prefetch hit check on newly received read requests.

[0036] The prefetch parameters are updated based on workload and prefetch hit rate.

[0037] By dynamically adjusting the prefetch strategy under different workloads and processing subsequent read commands in advance, data is read from flash memory into DRAM. When a subsequent read command hits, the data is directly transmitted to the host. This prefetching method shortens the read latency under small queue depth and greatly improves IOPS.

[0038] In one embodiment of the present invention, the method for monitoring SSD workload is as follows: SSD workload information is obtained by monitoring the read operations and I / O request patterns, queue depth, and block size of the SSD controller. This information is then used as the basis for predicting future I / O requests based on historical data.

[0039] In one embodiment of the present invention, the method for analyzing workload is as follows:

[0040] Based on the obtained workload information, data statistics and analysis are performed by using the logical address and length of the read command to determine whether it is a continuous read or a random read. Because of the unpredictability of its logical address, random reads do not require pre-reading.

[0041] The ratio of continuous reads to random reads is statistically analyzed. Random reads are deleted, and if random reads are not performed, a prefetch operation is performed to reserve backend bandwidth resources for random read operations. When the random read bandwidth in historical data exceeds 120% of the backend bandwidth, the prefetch operation is stopped.

[0042] The current workload pressure is analyzed. Specifically, if the queue depth and block size in the workload information meet the maximum front-end bandwidth without prefetching, then prefetching is canceled. The method for determining whether the queue depth and block size in the workload information meet the maximum front-end bandwidth without prefetching is: if the data transmission time of the queue depth and block size in the workload information is greater than the back-end NAND busy time, then it is determined that the maximum front-end bandwidth is met.

[0043] Predictive prefetching demand: Based on the analysis of historical workloads, a predictive algorithm is used to predict future I / O requests, determining the logical address and data size to be prefetched. When prefetching begins, the first logical address to be prefetched needs to be calculated. If the calculated logical address is too short, the command may have already finished before prefetching, resulting in prefetching failure. If the prefetched logical address is far from historical data, prefetching may be sluggish, with many commands missing the prefetch hit. Specifically, in one embodiment of this invention, a formula is used... Calculate the logical address FPL of the first prefetch at the start of prefetch, where CS is the current read rate, Be_bw is the backend bandwidth, BT is the typical busy time of NAND flash read operation, and CL is the current logical address of the command.

[0044] Dynamically adjust the prefetch strategy: Adaptively adjust the parameters and strategy of this prefetch based on the predicted prefetch demand and the distribution of physical addresses corresponding to logical addresses, including prefetch distance, prefetch granularity, and prefetch priority. When bad blocks exist in the multi-page of the physical address being prefetched, i.e., prefetching the same amount of data requires sending more backend commands, which can take hundreds of nanoseconds. Therefore, considering the impact on latency, the prefetch quantity is appropriately reduced when bad blocks exist in the physical address. A BR parameter is introduced based on the bad block situation. BR represents the bad block rate (e.g., in a 4-plane NAND granular array, if 2 planes have bad blocks, then BR is 50%). Specifically, in one embodiment of this invention, the formula is used to... The number of prefetched data frames, Df, is calculated. cnt In the formula, Fe bw PR is the front-end bandwidth, Bs is the IO pressure value, RR is the random read ratio, and RT is the prefetch coefficient.

[0045] Perform a prefetch operation: Based on the adjusted prefetch strategy, allocate cache space and send a read command to the NAND FLASH. The amount of data to be prefetched is the number of df values ​​prefetched in step four. To improve bandwidth and latency stability in multi-process operations involving a mix of sequential and random reads, enhance latency consistency, and reduce algorithmic penalties due to prefetch failures, in one embodiment of the invention, when sending a read command to the NAND FLASH for a prefetch operation, if the physical address to be prefetched is on the same LUN as the currently existing random read operation, determine whether the logical address to be prefetched is a later or earlier logical address. If it is a later logical address, perform the current random read operation, and postpone the prefetch operation after the random read operation. If it is an earlier logical address, do not postpone the prefetch operation. In this embodiment, if the prefetch logical address minus the current logical address is greater than the queue depth * block size, the logical address is a later logical address; if the prefetch logical address minus the current logical address is less than or equal to the queue depth * block size, the logical address is an earlier logical address.

[0046] In one embodiment of the present invention, the method for prefetching a newly received read request is as follows: if the logical address has been prefetched previously and the required data is in memory at this moment, it is determined to be a hit, and the hit data is transmitted to the host.

[0047] If the logical address has not been prefetched before, or if the data required for a previously prefetched address has not yet been read from the NAND into the memory set, it is considered a miss, and the prefetched data is discarded.

[0048] In one embodiment of the present invention, the method for transmitting the hit data to the host is as follows:

[0049] If the prefetch buffer is full, the data prefetching speed will be reduced to half of the previous prefetch speed.

[0050] If a prefetched logical address is hit, but the data has not yet been read from the NAND to the DRAM, the prefetch speed is slow, and the amount of prefetched data is increased by twice the length of the read command.

[0051] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for an adaptive SSD prefetcher, characterized in that, include: Monitor SSD workload and obtain workload information; Analyze the workload based on the obtained workload information; Calculate the logical address of the first prefetched during prefetch startup. ; When bad blocks exist in the prefetched physical address multipage, calculate the number of prefetched data frames. ; Send a read command to the NAND FLASH to perform a prefetch operation; the amount of data prefetched is the number of data frames. ; Perform a prefetch hit check on newly received read requests; The prefetch parameters are updated based on workload and prefetch hit rate. Through formula Calculate the logical address of the first prefetched during prefetch startup. In the formula The current read rate, For backend bandwidth, Typical busy time for NAND flash memory read operations The current logical address of the command; Through formula The number of prefetched data frames was calculated. In the formula For front-end bandwidth, This represents the I / O pressure value. For block size, This is the random read ratio. This refers to the pre-read coefficient; The method for prefetching hit checks on newly received read requests is as follows: If the logical address has been prefetched and the required data is in memory, it is considered a hit, and the hit data is transmitted to the host. If the logical address has not been prefetched before, or if the data required by the prefetched data has not yet been read from the NAND into the memory set, it is determined as a miss and the prefetched data is discarded. The method for transmitting the hit data to the host is as follows: If the prefetch buffer is full, the data prefetching speed will be reduced to half of the previous prefetch speed. If a prefetched logical address is hit, but the data has not yet been read from the NAND to the DRAM, the prefetch speed is slow, and the amount of prefetched data is increased by twice the length of the read command.

2. The method for an adaptive SSD prefetcher according to claim 1, characterized in that, The method for monitoring SSD workload is to obtain SSD workload information by monitoring the SSD controller's read operations and I / O request patterns, queue depth, and block size.

3. The method for an adaptive SSD prefetcher according to claim 2, characterized in that, The method for analyzing workload is as follows: Based on the obtained workload information, data statistics and analysis are performed by using the logical address and length of the read command to determine whether it is a continuous read or a random read. If it is a random read, no pre-read operation is performed. The ratio of continuous reads to random reads is statistically analyzed. Random reads are deleted, and if random reads are not performed, a prefetch operation is performed to reserve backend bandwidth resources for random read operations. When the random read bandwidth in historical data exceeds 120% of the backend bandwidth, the prefetch operation is stopped. If the queue depth and block size in the workload information meet the maximum front-end bandwidth without prefetching, then prefetching is canceled.

4. The method for an adaptive SSD prefetcher according to claim 3, characterized in that, The method to determine whether the queue depth and block size in the workload information meet the maximum bandwidth of the front end without prefetching is as follows: when the data transmission time of the queue depth and block size in the workload information is greater than the backend NAND busy time, it is determined that the maximum bandwidth of the front end is met.

5. The method for an adaptive SSD prefetcher according to claim 1, characterized in that: When sending a read command to NAND FLASH for a prefetch operation, if the physical address to be prefetched is on the same LUN as the current random read operation, it is determined whether the logical address to be prefetched is a later logical address or a earlier logical address. If it is a later logical address, the current random read operation is performed, and the prefetch operation is postponed after the random read operation. If it is an earlier logical address, the prefetch operation is not postponed.

6. The method for an adaptive SSD prefetcher according to claim 5, characterized in that: If the prefetched logical address minus the current logical address is greater than the queue depth If the block size is specified, the logical address will be a later logical address. If the prefetched logical address minus the current logical address is less than or equal to the queue depth, then... If the block size is specified, the logical address is the one at the beginning of the block.

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