Ipmi command transmission method, device, system and electronic equipment

Abstract

The application provides an IPMI command transmission method and device, and relates to the field of computer communication.The method comprises the following steps: in the case that a first memory of a BMC is not full, sending a data packet of a first IPMI command in a first memory space of a host where the BIOS is located to the first memory through a PCIe bus; and receiving a data packet of a second IPMI command sent by the BMC to a second memory space of the host through the PCIe bus, wherein the second IPMI command is located in a second memory of the BMC, and the second IPMI command is sent by the BMC in the case that the second memory space is not full. On the one hand, the IPMI command is transmitted between the BIOS and the BMC through the PCIe bus, the transmission speed of the IPMI command is improved, and the hardware cost is reduced. On the other hand, the sending data channel and the receiving data channel of the BIOS are independent of each other, the influence between data sending and receiving is reduced, and the accuracy of data transmission is improved.

Description

Technical Field

[0001] This application relates to the field of computer communication technology, and in particular to an IPMI command transmission method, apparatus, system and electronic device. Background Technology

[0002] The Board Management Controller (BMC) is a controller that provides intelligent services to the main board and operates independently of the CPU (Central Processing Unit). The Basic Input Output System (BIOS) primarily provides the lowest-level hardware settings for the computer, controls and starts the operating system, and provides system parameters to the operating system; it runs on the host side.

[0003] IPMI (Intelligent Platform Management Interface) is a high-layer protocol and an industry standard for managing peripheral devices in enterprise systems with Intel architecture. Currently, the transmission of IPMI commands between the BIOS and BMC primarily uses KCS (Keyboard Controller Style) and BT (Bit Torrent) interfaces.

[0004] Using the KCS or BT interface to transmit IPMI commands is slow, and the hardware needs to have a KCS or BT interface, which is costly. Summary of the Invention

[0005] The purpose of this application is to provide an IPMI command transmission method, apparatus, system, and electronic device to improve IPMI command transmission speed and reduce costs.

[0006] This application provides an IPMI command transmission method for use in BIOS, including: If the first memory of the BMC is not full, the data packet of the first IPMI command in the first memory space of the host where the BIOS is located is sent to the first memory via the PCIe bus; The BMC receives a data packet containing a second IPMI command sent to the host's second memory space via the PCIe bus. The second IPMI command is located in the BMC's second memory and is sent by the BMC when the second memory space is not full.

[0007] Optionally, the step of sending the data packet of the first IPMI command in the first memory space of the host where the BIOS is located to the first memory via the PCIe bus when the first memory of the BMC is not full includes: When the first register corresponding to the first memory is reset and the first memory is not full, the data packet of the first IPMI command is written to the first memory through the PCIe bus. The first register is set after the data packet of the first IPMI command is stored in the first memory to trigger an interrupt in the first memory, which notifies the BMC to receive the data packet of the first IPMI command. The first register is reset after the BMC has received the first IPMI command.

[0008] Optionally, there may be multiple first memories and first memory spaces, with each first memory space corresponding to the first memory space in a one-to-one manner. The step of sending the data packet of the first IPMI command in the first memory space of the host where the BIOS is located to the first memory via the PCIe bus when the first memory of the BMC is not full includes: If the first register of the first memory corresponding to any of the first memory spaces is reset, and the remaining capacity of the first memory is greater than the capacity occupied by the first IPMI command, the first memory corresponding to the first memory space shall be used as the target memory. If the first register of the first memory corresponding to any first memory space is set, or if the remaining capacity of the first memory corresponding to any first memory space is less than or equal to the capacity occupied by the first IPMI command, the first memory with the first register reset and the remaining capacity greater than the capacity occupied by the first IPMI command is selected from other first memories as the target memory. After increasing the priority of the write event to the target memory, the data packet of the first IPMI command is written to the target memory through the PCIe bus, and the priority of the write event to the target memory is restored.

[0009] Optionally, the step of sending the data packet of the first IPMI command in the first memory space of the host where the BIOS is located to the first memory via the PCIe bus when the first memory of the BMC is not full includes: Create a first send queue and a first send event for the first memory space; Store the first IPMI command in the first transmission queue and wake up the first transmission event; If the first IPMI command exists in the first transmission queue and the first memory is not full, the first transmission event is used to store the data packet of the first IPMI command in the first transmission queue into the first memory through the PCIe bus. If the data packet of the first IPMI command is a reply packet, the first sending event enters a sleep state; If the data packet of the first IPMI command is a request packet, wait for the response packet returned by the BMC, and update the status of the first IPMI command according to the command execution result of the first IPMI command in the response packet.

[0010] Optionally, the data packet of the first IPMI command or the data packet of the second IPMI command includes a data header and a data body; The data header includes the length of the first IPMI command or the second IPMI command, a checksum, a command number, and a preset data packet identifier. The request packet and the response packet of the first IPMI command have the same command number, and the request packet and the response packet of the second IPMI command have the same command number. The data body includes the receiving device number, command type, and command characters of the first IPMI command or the second IPMI command; The data body of the response packet also includes the command execution result.

[0011] Optionally, receiving the data packet of the second IPMI command sent by the BMC to the second memory space of the host via the PCIe bus includes: When the host polls the second register corresponding to the second memory and determines that the second register is set, it receives the data packet of the second IPMI command from the second memory space; The second register is set after the data packet of the second IPMI command is written into the second memory space, and is reset after the data packet of the second IPMI command is received from the second memory space.

[0012] Optionally, there are multiple second memories and second memory spaces, and each second memory space corresponds to a different second memory space. When the second register is set, receiving the data packet of the second IPMI command from the second memory space includes: Create a first receive queue, a first receive event, and a first execution event for the second memory space; When the second register corresponding to a single second memory is set, the data packet of the second IPMI command is received from the second memory space corresponding to the single second memory using the first receive event, and the second register corresponding to the single second memory is reset; When the second registers corresponding to multiple second memories are set, the data packets of the second IPMI command are retrieved from the second memory spaces corresponding to multiple second memories using the first receive event, the second registers corresponding to multiple second memories are reset, and the order of the retrieved data packets of the second IPMI command is determined according to the preset data packet identifier in the retrieved data packets of the second IPMI command. Based on the length of the second IPMI command in the data packet of the second IPMI command, determine whether the entire data packet of the second IPMI command has been received; If not all data packets of the second IPMI command are received, continue polling the second registers corresponding to the other second memories; If all data packets of the second IPMI command have been received, all data packets of the second IPMI command are placed in the first receive queue so that the first execution event can execute all data packets of the second IPMI command in the first receive queue.

[0013] This application also provides an IPMI command transmission method, applied to a BMC, including: If the host's second memory space is not full, the data packet of the second IPMI command in the second memory of the BMC is sent to the second memory space through the PCIe bus; After the BIOS on the host writes a data packet of the first IPMI command to the first memory of the BMC through the PCIe bus, it receives the data packet of the first IPMI command. The first IPMI command is located in the first memory space of the host and is written by the BIOS when the first memory is not full.

[0014] Optionally, the step of sending the data packet of the second IPMI command in the second memory of the BMC to the second memory space via the PCIe bus when the second memory space of the host is not full includes: When the second register corresponding to the second memory is reset and the second memory space is not full, the data packet of the second IPMI command is written into the second memory space through the PCIe bus; The second register is set after the data packet of the second IPMI command is stored in the second memory space, and is reset after the BIOS receives the second IPMI command in the second memory space.

[0015] Optionally, there are multiple second memories and second memory spaces, and each second memory space corresponds to a different second memory space. The step of sending the data packet of the second IPMI command in the second memory of the BMC to the second memory space via the PCIe bus when the second memory space of the host is not full includes: If the second register of any second memory is reset, and the remaining capacity of the second memory space corresponding to any second memory is greater than the capacity occupied by the second IPMI command, the second memory space corresponding to any second memory shall be used as the target memory space. If the second register of any second memory is set, or if the remaining capacity of the second memory space corresponding to any second memory is less than or equal to the capacity occupied by the second IPMI command, the second memory space whose second register of the corresponding second memory is reset and whose remaining capacity is greater than the capacity occupied by the second IPMI command is selected from other second memory spaces as the target memory space. After increasing the priority of the write event to the target memory space, the data packet of the second IPMI command is stored in the target memory space through the PCIe bus, and the priority of the write event to the target memory space is restored.

[0016] Optionally, the step of sending the data packet of the second IPMI command in the second memory of the BMC to the second memory space via the PCIe bus when the second memory space of the host is not full includes: Create a second send queue and a second send event for the second memory; The second IPMI command is stored in the second transmission queue, the second transmission event is woken up, and the second transmission event is used to poll the second transmission queue; If the second IPMI command exists in the second transmission queue and the second memory space is not full, the second transmission event is used to store the data packet of the second IPMI command in the second transmission queue into the second memory space through the PCIe bus; If the data packet of the second IPMI command is a reply packet, the second send event enters a sleep state; If the data packet of the second IPMI command is a request packet, wait for the response packet returned by the BIOS, and update the status of the second IPMI command according to the command execution result of the second IPMI command in the response packet.

[0017] Optionally, the data packet of the first IPMI command or the data packet of the second IPMI command includes a data header and a data body; The data header includes the length of the first IPMI command or the second IPMI command, a checksum, a command number, and a preset data packet identifier. The request packet and the response packet of the first IPMI command have the same command number, and the request packet and the response packet of the second IPMI command have the same command number. The data body includes the receiving device number, command type, and command characters of the first IPMI command or the second IPMI command; The data body of the response packet also includes the command execution result.

[0018] Optionally, after the BIOS on the host writes a data packet of the first IPMI command to the first memory of the BMC via the PCIe bus, receiving the data packet of the first IPMI command includes: After the BIOS stores the data packet of the first IPMI command into the first memory, the first register of the first memory is set, triggering the first memory to generate an interrupt; In the event of an interrupt in the first memory, the data packet of the first IPMI command is received, and after receiving the data packet of the first IPMI command, the first register is reset.

[0019] Optionally, there may be multiple first memories and first memory spaces, with each first memory space corresponding to the first memory space in a one-to-one manner. The step of receiving the data packet for the first IPMI command in the event of an interrupt in the first memory includes: Create a second receive queue, a second receive event, and a second execution event for the first memory; In the event of an interrupt in the first memory, the first IPMI command is retrieved from the first memory using the second receive event; Based on the length of the first IPMI command in the data packet of the first IPMI command, determine whether the entire data packet of the first IPMI command has been received; If not all packets of the first IPMI command are received, continue to determine whether other packets of the first memory have been interrupted; If all data packets of the first IPMI command have been received, all data packets of the first IPMI command are placed in the second receive queue so that the second execution event can execute all data packets of the first IPMI command in the second receive queue.

[0020] This application also provides an IPMI command transmission device, comprising: The first sending module is used to send the data packet of the first IPMI command in the first memory space of the host where the BIOS is located to the first memory via the PCIe bus when the first memory of the BMC is not full. The first receiving module is used to receive data packets of the second IPMI command sent by the BMC to the second memory space of the host through the PCIe bus. The second IPMI command is located in the second memory of the BMC and is sent by the BMC when the second memory space is not full.

[0021] This application also provides an IPMI command transmission device, comprising: The second sending module is used to send the data packet of the second IPMI command in the second memory of the BMC to the second memory space via the PCIe bus when the second memory space of the host is not full. The second receiving module is used to receive the data packet of the first IPMI command after the BIOS on the host writes the data packet of the first IPMI command to the first memory of the BMC through the PCIe bus. The first IPMI command is located in the first memory space of the host and is written by the BIOS when the first memory is not full.

[0022] This application also provides an IPMI command transmission system, including the two IPMI command transmission devices mentioned above.

[0023] This application also provides a computer program product, including a computer program / instructions that, when executed by a processor, implement the steps of any of the IPMI command transmission methods described above.

[0024] This application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of any of the above-described IPMI command transmission methods.

[0025] This application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the above-described IPMI command transmission methods.

[0026] The IPMI command transmission method, apparatus, system, and electronic device provided in this application transmit data packets of the first IPMI command in the first memory space of the host where the BIOS is located to the first memory of the BMC via the PCIe bus through the BIOS. The BIOS receives data packets of the second IPMI command in the second memory sent by the BMC to the second memory space of the host via the PCIe bus through the BIOS. On the one hand, the BIOS and BMC transmit IPMI commands via the PCIe bus, which improves the transmission speed of IPMI commands and reduces hardware costs. On the other hand, the BIOS's data transmission channel and data reception channel are independent of each other, which reduces the influence between data transmission and reception and improves the accuracy of data transmission. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of the hardware structure in the IPMI command transmission method provided in this application; Figure 2 This is one of the flowcharts illustrating the IPMI command transmission method provided in this application; Figure 3 This is a schematic diagram of the BIOS sending event processing flow in the IPMI command transmission method provided in this application; Figure 4 This is a flowchart illustrating the BIOS initialization process in the IPMI command transmission method provided in this application; Figure 5 This is a schematic diagram of the BIOS receiving event processing flow in the IPMI command transmission method provided in this application; Figure 6 This is the second flowchart illustrating the IPMI command transmission method provided in this application; Figure 7 This is a schematic diagram of the BMC sending event processing flow in the IPMI command transmission method provided in this application; Figure 8 This is a schematic diagram of the BMC receive event processing flow in the IPMI command transmission method provided in this application; Figure 9 This is one of the structural schematic diagrams of the IPMI command transmission device provided in this application; Figure 10 This is the second schematic diagram of the IPMI command transmission device provided in this application; Figure 11 This is a schematic diagram of the structure of the electronic device provided in this application. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0030] Figure 1 This is a schematic diagram of the hardware structure in the IPMI command transmission method provided by this invention. (See diagram below.) Figure 1 As shown, the BMC acts as the EP (Endpoint) of the PCIe line, connected below the host. The BMC's hardware implements four FIFO (First-In First-Out) memories, which return the first data written to the reader when being read. Then, the registers corresponding to the four FIFO memories are mapped to the host side.

[0031] The BMC hardware requests an address space from the host via the base address register in the PCIe configuration space. This space corresponds to four FIFO memory registers on the BMC side. This space is shared memory on both ends, and the data is identical. That is, if the data in the memory space on one end is modified, the data in the space on the other end will also change.

[0032] The registers of the BMC's FIFO memory provide three important functions: 1. Checking whether the FIFO memory is full of data; 2. Writing to or reading from the FIFO memory; 3. After the firmware sets the register, the hardware will send an interrupt message to the receiving end. After receiving the interrupt message, the receiving end knows that the sending end has put the data into the FIFO memory and is ready to receive it.

[0033] Figure 1 h2bq0 and h2bq1 are FIFO memories used for sending data from the host side to the BMC side, i.e., the first memory; b2hq0 and b2hq1 are FIFO memories used by the BMC side for sending data from the host side, i.e., the second memory.

[0034] The IPMI command transmission method provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0035] like Figure 2As shown in the embodiment of this application, an IPMI command transmission method is provided, which may include the following steps 201 and 202: Step 201: If the first memory of the BMC is not full, send the data packet of the first IPMI command in the first memory space of the host where the BIOS is located to the first memory via the PCIe (Peripheral Component Interconnect Express) bus. The BIOS obtains the first IPMI command to be transmitted from the host's first memory space, and can determine whether the first memory is full by reading the first register of the first memory space corresponding to the first memory space.

[0036] If the first memory is not full, the first IPMI command is packaged and written byte by byte through the PCIe bus into the first memory.

[0037] Transmitting the first IPMI command via the PCIe bus is faster than using KCS and BT, and the KCS and BT interfaces can be optimized in hardware to reduce costs.

[0038] Currently, IPMI format data primarily transmits control commands, and the data volume is generally relatively small. However, if KCS or BT interfaces are used to transmit large amounts of data, the transmission time will be much longer.

[0039] Using the PCIe bus for transmission increases the data volume, allowing commands that are not suitable for transmission using the IPMI protocol to be transmitted using IPMI, such as firmware upgrade packages, thus making IPMI more widely applicable.

[0040] Step 202: Receive a data packet of a second IPMI command sent by the BMC to the second memory space of the host via the PCIe bus. The second IPMI command is located in the second memory of the BMC and is sent by the BMC when the second memory space is not full.

[0041] When the second memory space corresponding to the second memory is not full, the BMC assembles the second IPMI commands in the second memory into packets and writes the second IPMI command data packets byte by byte into the second memory space via the PCIe bus. Transmitting the second IPMI commands via the PCIe bus offers high transmission speed. The BIOS receives the second IPMI commands from the second memory space.

[0042] The IPMI command transmission method provided in this application embodiment transmits a data packet of a first IPMI command in the first memory space of the host where the BIOS is located to the first memory of the BMC via the PCIe bus through the BIOS. The BIOS receives a data packet of a second IPMI command in the second memory sent by the BMC to the second memory space of the host via the PCIe bus through the BIOS. On the one hand, the BIOS and BMC transmit IPMI commands via the PCIe bus, which improves the transmission speed of IPMI commands and reduces hardware costs. On the other hand, the BIOS's data transmission channel and data reception channel are independent of each other, which reduces the influence between data transmission and reception and improves the accuracy of data transmission.

[0043] Based on the above embodiments, this embodiment describes sending the data packet of the first IPMI command in the first memory space of the host where the BIOS is located to the first memory via the PCIe bus when the first memory of the BMC is not full, including: When the first register corresponding to the first memory is reset and the first memory is not full, the data packet of the first IPMI command is written to the first memory through the PCIe bus. The first register is set after the data packet of the first IPMI command is stored in the first memory to trigger an interrupt in the first memory, which notifies the BMC to receive the data packet of the first IPMI command. The first register is reset after the BMC has received the first IPMI command.

[0044] If the first register corresponding to the first memory is reset, it is known that the BMC has completed receiving the data packet of the first IPMI command last written to the first memory.

[0045] If the previous write reception of the first memory is completed and the first memory is not full, the data packet of the first IPMI command is written to the first memory via the PCIe bus.

[0046] The host sends an interrupt message to the BMC by modifying the state of the first register of the first memory, that is, by setting the first register.

[0047] After receiving the interrupt message, the BMC first retrieves the first IPMI command from the first memory; then resets the first register; and finally processes the received first IPMI command.

[0048] The IPMI command transmission method provided in this application resets the first register after the BMC receives the first IPMI command from the first memory; and sets the bit after the data packet of the first IPMI command is stored in the first memory, so that the data packet of the first IPMI command is transmitted in an orderly manner, and the BMC receives the first IPMI command from the first memory in a timely manner.

[0049] Based on the above embodiments, there are multiple first memories and first memory spaces in this embodiment, and the first memories and first memory spaces correspond one-to-one. The step of sending the data packet of the first IPMI command in the first memory space of the host where the BIOS is located to the first memory via the PCIe bus when the first memory of the BMC is not full includes: If the first register of the first memory corresponding to any of the first memory spaces is reset, and the remaining capacity of the first memory is greater than the capacity occupied by the first IPMI command, the first memory corresponding to the first memory space shall be used as the target memory. If the first register of the first memory corresponding to any first memory space is set, or if the remaining capacity of the first memory corresponding to any first memory space is less than or equal to the capacity occupied by the first IPMI command, the first memory with the first register reset and the remaining capacity greater than the capacity occupied by the first IPMI command is selected from other first memories as the target memory. After increasing the priority of the write event to the target memory, the data packet of the first IPMI command is written to the target memory through the PCIe bus, and the priority of the write event to the target memory is restored.

[0050] In the presence of multiple first memories, these multiple first memories can be used interchangeably. Figure 1 The example shows two first memories, h2bq0 and h2bq1.

[0051] If the first memory space corresponding to the first memory space where the first IPMI command to be transmitted is h2bq0, then check whether the first register of h2bq0 has been reset. If the first register of h2bq0 has not been reset, it is known that the BMC terminal did not receive the first IPMI command last written to h2bq0, and the process switches to checking whether the first register of h2bq1 has been reset. If the first register of h2bq1 has not been reset, then the first registers of both first memories are checked again after a period of time.

[0052] Because the capacity of the first memory is limited, it may become insufficient. If the first register of the first memory is reset but the first memory has insufficient capacity, the system switches to another first memory to continue the process until a first memory with a reset first register and sufficient capacity is found. This first memory is then used as the target memory. The data packet of the first IPMI command is then stored in the target memory.

[0053] Before the data packet of the first IPMI command is stored, the event priority of storing data in the target memory is increased to prevent the data packet storage process of the first IPMI command from being interrupted by other events.

[0054] After the first IPMI command data packet is stored in the target memory, the first register of the target memory is set. The hardware sends an interrupt message to the BMC via the PCIe bus to notify the BMC to receive data.

[0055] In this embodiment, the first memory, whose first register is reset and whose remaining capacity is greater than the capacity occupied by the first IPMI command, is used as the target memory to store the data packet of the first IPMI command, thereby improving the utilization rate of the first memory while writing to the first memory in an orderly manner.

[0056] Based on the above embodiments, such as Figure 3 As shown in this embodiment, when the first memory of the BMC is not full, sending the data packet of the first IPMI command in the first memory space of the host where the BIOS is located to the first memory via the PCIe bus includes: Create a first send queue and a first send event for the first memory space; Store the first IPMI command in the first transmission queue and wake up the first transmission event; If the first IPMI command exists in the first transmission queue and the first memory is not full, the first transmission event is used to store the data packet of the first IPMI command in the first transmission queue into the first memory through the PCIe bus. If the data packet of the first IPMI command is a reply packet, the first sending event enters a sleep state; If the data packet of the first IPMI command is a request packet, wait for the response packet returned by the BMC, and update the status of the first IPMI command according to the command execution result of the first IPMI command in the response packet.

[0057] like Figure 4 As shown, the BIOS creates a first send queue for each first memory space to store the first IPMI commands sent by other modules.

[0058] The BIOS creates a first send event for each memory space, which is equivalent to a thread. The first send event polls the first send queue. If there is data in the first send queue, the first send event retrieves the data and sends it to the BMC via the PCIe bus.

[0059] The first transmission event is typically in a sleep state. When other modules need to send the first IPMI command to the BMC, they call the IPMI transmission interface to put the first IPMI command into the first transmission queue, thus waking up the first transmission event.

[0060] Other modules that call the IPMI send interface are producers of the first send queue. The first send event is a consumer of the first send queue. After the first send event is awakened, it mainly performs two processes: organizing data packets to send to the BMC side and receiving and processing the data replied by the BMC.

[0061] The first transmission event checks if there is data in the first transmission queue. If not, it re-enters sleep mode. If there is data, it is retrieved from the first transmission queue, its data length, checksum, and command number are calculated, and the calculation results are placed in the data header to generate a data packet, which is then ready for transmission.

[0062] Determine whether the data packet is a request packet or a response packet. For response packets, there is no need to wait for a reply from the BMC. After all the data packets are put into the first memory, the first send event can enter a sleep state, waiting to be woken up next time.

[0063] If the data packet is a request packet, a response from the BMC is required. This is done by checking if a response packet for the request packet exists in the first receive queue of the second memory space. The data in the first receive queue is the data added by the first receive event in the second memory space.

[0064] If no corresponding reply packet is found in the first receive queue, the system will sleep for a period of time and then check again. If the sleep time has exceeded the preset time, the status of the first IPMI command will be changed to timeout. If a reply packet is found, the BMC reply packet will be analyzed, and the status of the first IPMI command will be changed to the command execution result CompleteCode in the reply packet.

[0065] In this embodiment, the BIOS's transmit data channel and receive data channel are independent of each other, reducing the impact between data transmission and reception and improving the accuracy of data transmission.

[0066] Based on the above embodiments, in this embodiment, the data packet of the first IPMI command or the data packet of the second IPMI command includes a data header and a data body; The data header includes the length of the first IPMI command or the second IPMI command, a checksum, a command number, and a preset data packet identifier. The request packet and the response packet of the first IPMI command have the same command number, and the request packet and the response packet of the second IPMI command have the same command number. The data body includes the receiving device number, command type, and command characters of the first IPMI command or the second IPMI command; The data body of the response packet also includes the command execution result.

[0067] A data packet consists of a header and a body. The body is in IPMI command format, including an IPMI command header and an IPMI command body. IPMI commands include request commands and response commands. Request commands are used to request the peer to perform a certain procedure, while response commands are replies after the procedure is completed.

[0068] The request packet structure is as follows: typedef struct { H2bTransferHeader TransHeader; IpmiReqHeader IpmiHeader; UINT8 IpmiData[0]; ReqPkg The packet structure of the reply packet is as follows: typedef struct { H2bTransferHeader TransHeader; IpmiRespHeader IpmiHeader; UINT8 IpmiData[0]; RespPkg Among them, TransHeader is the data header, IpmiHeader is the IPMI command header, and IpmiData is the IPMI command body.

[0069] The data packet header structure is as follows: typedef structUINT32{ UINT32 Magic; UINT32 BodySize; UINT32 BodyCrc; UINT32 CmdId; H2bTransferHeader Here, `Magic` is a preset packet identifier, a fixed value, indicating the first packet. A packet without a preset packet identifier is not the first packet. `BodySize` indicates the length of the data body, `BodyCrc` represents the data body checksum, and `CmdId` represents the command number. All request packets for an IPMI command correspond to one response packet, unless an exception occurs. The `CmdId` of the request packet and the response packet are the same. After sending a request packet, the response packet can be retrieved from the first receive queue using the command number.

[0070] The structure of the IPMI command header of the request packet is as follows: typedef struct{ UINT8 lun:2; UINT8 NetFn :6; UINT8 Cmd; }IpmiRegHeader The structure of the IPMI command header in the response packet is as follows: typedef struct{ UINT8 lun:2; UINT8 NetFn:6; UINT8 Cmd; INT8 CompleteCode; }IpmiRespHeader Here, Lun represents the logical unit number, i.e., the device number of the receiving end; NetFn represents the command word, which is used to indicate the general category of the process that the receiving end needs to execute; and Cmd is the sub-command word, which is used to indicate the specific process to be executed.

[0071] For example, for a power-on command, NetFn=0x0 indicates a chassis control class, Cmd=0x02 indicates a power control command, and the 0th byte of IpmiData in the IPMI command body is 0x01, indicating power-on. CompleteCode indicates the result of the command execution. 0 indicates success, non-zero indicates failure, and different values ​​represent different error types.

[0072] Based on the above embodiments, the receiving of the data packet of the second IPMI command sent by the BMC to the second memory space of the host through the PCIe bus in this embodiment includes: When the host polls the second register corresponding to the second memory and determines that the second register is set, it receives the data packet of the second IPMI command from the second memory space; The second register is set after the data packet of the second IPMI command is written into the second memory space, and is reset after the data packet of the second IPMI command is received from the second memory space.

[0073] Because the BIOS does not support interrupts, it continuously polls the second register corresponding to the second memory. After the second register is set, it detects that a data packet containing the second IPMI command has been stored in the second memory space corresponding to the second memory, and then retrieves the data packet from that memory space. After retrieving the data packet, the second register is reset.

[0074] The IPMI command transmission method provided in this application stores the data packet of the second IPMI command in the second memory space corresponding to the second memory in the second register and resets it after retrieving the data packet of the second IPMI command in the second memory space, so that the data packet of the first IPMI command is transmitted in an orderly manner and the BIOS receives the second IPMI command in the second memory space in a timely manner.

[0075] Based on the above embodiments, such as Figure 5 As shown, in this embodiment there are multiple second memories and second memory spaces, and each second memory space corresponds to another second memory space. When the second register is set, receiving the data packet of the second IPMI command from the second memory space includes: Create a first receive queue, a first receive event, and a first execution event for the second memory space; When the second register corresponding to a single second memory is set, the data packet of the second IPMI command is received from the second memory space corresponding to the single second memory using the first receive event, and the second register corresponding to the single second memory is reset; When the second registers corresponding to multiple second memories are set, the data packets of the second IPMI command are retrieved from the second memory spaces corresponding to multiple second memories using the first receive event, the second registers corresponding to multiple second memories are reset, and the order of the retrieved data packets of the second IPMI command is determined according to the preset data packet identifier in the retrieved data packets of the second IPMI command. Based on the length of the second IPMI command in the data packet of the second IPMI command, determine whether the entire data packet of the second IPMI command has been received; If not all data packets of the second IPMI command are received, continue polling the second registers corresponding to the other second memories; If all data packets of the second IPMI command have been received, all data packets of the second IPMI command are placed in the first receive queue so that the first execution event can execute all data packets of the second IPMI command in the first receive queue.

[0076] The BIOS creates a first receive queue, a first receive event, and a first execute event for the second memory space. The first receive event receives the data packet of the second IPMI command sent by the BMC and then puts the data packet of the second IPMI command into the first receive queue. The first receive event is the producer of the first receive queue.

[0077] Because the BIOS does not support interrupts, the first receive event continuously polls the second register of the second memory. After the second register is set, the data packet of the second IPMI command is retrieved from the second memory space corresponding to the second memory, combined, and sent to the first receive queue.

[0078] The first execution event retrieves a request packet from the first receive queue and executes it. After execution, it organizes a reply packet and sends it through the IPMI send interface. The first send event retrieves the corresponding reply packet from the first receive queue after sending; both events are consumers of the first receive queue.

[0079] The reason for using the first receive queue, the first receive event, the first send queue, and the first send event is to allow only one event to operate on the first memory and the second memory space, preventing multiple events from operating simultaneously and causing data corruption.

[0080] The BIOS can also send a self-test command to the BMC. If the BMC replies that the self-test is successful, it returns success. If the BMC does not reply or replies with "error", it indicates that there is a problem with the BMC, destroys the previously requested resources, namely the two events and the two queues, and returns failure.

[0081] In the presence of multiple secondary memories, these secondary memories can be used interchangeably. Figure 1 The example shows two secondary memories, b2hq0 and b2hq1.

[0082] The first receive event checks the second registers of the two second memories. If a second register of a certain second memory is found to be set, the data packet of the second IPMI command is received from the second memory space corresponding to that second memory.

[0083] Since it's possible that the second registers of both second memories are set, meaning both second memory spaces contain data, it's impossible to determine which second memory space contains the first data packet of the second IPMI command before reading the data. Therefore, all data from the second memory spaces of both second memories is retrieved, and their Magic fields are verified. The data packet containing the Magic field is taken as the first data packet, and the data packet from the second memory space of the other second memory is placed after the first data packet. Each time a data packet is retrieved from a second memory space, the corresponding second register of the second memory needs to be reset.

[0084] After receiving the data packet, it is determined whether all data packets for the second IPMI command have been received. If not, it checks whether the second register of the other second memory is set. If not set, the first receive event sleeps for a period of time and checks the second register of the second memory again until a timeout occurs. After the second register of the second memory is set, the data packet is read from the corresponding second memory space of the second memory, and this process is repeated until all data packets for the second IPMI command have been received.

[0085] After reading all the data packets of the second IPMI command, these data packets are placed into the first receive queue, and after sleeping for a period of time, the second register of the second memory is checked again to see if it is set.

[0086] Figure 6 This is the second flowchart illustrating the IPMI command transmission method provided by this invention. The process of the BMC sending the second IPMI command to the BIOS can be referenced to the process of the BIOS sending the first IPMI command to the BMC. The process of the BMC receiving the first IPMI command from the BIOS can be referenced to the process of the BIOS receiving the second IPMI command from the BMC. Figure 6 As shown, this method is applied to BMC and includes: Step 601: If the second memory space of the host is not full, send the data packet of the second IPMI command in the second memory of the BMC to the second memory space through the PCIe bus; The BMC retrieves the second IPMI command to be transmitted from its second memory. If the host's second memory space is not full, the second IPMI command is packetized and written byte by byte into the second memory space via the PCIe bus.

[0087] Transmitting the second IPMI command via the PCIe bus is faster than using KCS and BT, and the KCS and BT interfaces can be optimized in hardware to reduce costs.

[0088] Step 602: After the BIOS on the host writes the data packet of the first IPMI command to the first memory of the BMC through the PCIe bus, it receives the data packet of the first IPMI command. The first IPMI command is located in the first memory space of the host and is written by the BIOS when the first memory is not full.

[0089] The BMC typically uses the Linux operating system. This operating system supports interrupts, so the BMC can determine the first memory location being written to based on interrupt messages. Therefore, the BMC's receiving process is simpler than that of the BIOS.

[0090] The IPMI command transmission method provided in this application transmits the data packet of the second IPMI command in the second memory of the BMC to the second memory space of the host via the PCIe bus. The BMC receives the data packet of the first IPMI command written to the first memory of the BMC via the PCIe bus. On the one hand, the transmission of IPMI commands between the BIOS and the BMC via the PCIe bus improves the transmission speed of IPMI commands and reduces hardware costs. On the other hand, the BMC's transmit data channel and receive data channel are independent of each other, reducing the impact between data transmission and reception and improving the accuracy of data transmission.

[0091] Based on the above embodiments, this embodiment describes sending the data packet of the second IPMI command in the second memory of the BMC to the second memory space via the PCIe bus when the second memory space of the host is not full, including: When the second register corresponding to the second memory is reset and the second memory space is not full, the data packet of the second IPMI command is written into the second memory space through the PCIe bus; The second register is set after the data packet of the second IPMI command is stored in the second memory space, and is reset after the BIOS receives the second IPMI command in the second memory space.

[0092] The IPMI command transmission method provided in this application resets the second register after the BIOS has received the second IPMI command in the second memory space; and sets the bit after the data packet of the second IPMI command is stored in the second memory space, so that the data packet of the second IPMI command is transmitted in an orderly manner and the BIOS receives the second IPMI command in the second memory space in a timely manner.

[0093] Based on the above embodiments, such as Figure 7 As shown, in this embodiment there are multiple second memories and second memory spaces, and each second memory space corresponds to another second memory space. The step of sending the data packet of the second IPMI command in the second memory of the BMC to the second memory space via the PCIe bus when the second memory space of the host is not full includes: If the second register of any second memory is reset, and the remaining capacity of the second memory space corresponding to any second memory is greater than the capacity occupied by the second IPMI command, the second memory space corresponding to any second memory shall be used as the target memory space. If the second register of any second memory is set, or if the remaining capacity of the second memory space corresponding to any second memory is less than or equal to the capacity occupied by the second IPMI command, the second memory space whose second register of the corresponding second memory is reset and whose remaining capacity is greater than the capacity occupied by the second IPMI command is selected from other second memory spaces as the target memory space. After increasing the priority of the write event to the target memory space, the data packet of the second IPMI command is stored in the target memory space through the PCIe bus, and the priority of the write event to the target memory space is restored.

[0094] The BMC sending process is almost identical to the BIOS sending process, so it will not be described in detail here.

[0095] In this embodiment, the second memory space with the second register of the corresponding second memory reset and the remaining capacity greater than the capacity occupied by the second IPMI command is used as the target memory space to store the data packet of the second IPMI command, thereby improving the utilization rate of the second memory space while writing to the second memory space in an orderly manner.

[0096] Based on the above embodiments, such as Figure 7 As shown in this embodiment, when the host's second memory space is not full, sending the data packet of the second IPMI command in the second memory of the BMC to the second memory space via the PCIe bus includes: Create a second send queue and a second send event for the second memory; The second IPMI command is stored in the second transmission queue, the second transmission event is woken up, and the second transmission event is used to poll the second transmission queue; If the second IPMI command exists in the second transmission queue and the second memory space is not full, the second transmission event is used to store the data packet of the second IPMI command in the second transmission queue into the second memory space through the PCIe bus; If the data packet of the second IPMI command is a reply packet, the second send event enters a sleep state; If the data packet of the second IPMI command is a request packet, wait for the response packet returned by the BIOS, and update the status of the second IPMI command according to the command execution result of the second IPMI command in the response packet.

[0097] The second transmission event is generally in a sleep state. When other modules need to send a second IPMI command to the BIOS, they put the second IPMI command into the second transmission queue and then wake up the second transmission event. After the second transmission event is woken up, the transmission process on the BMC side is executed. This process is almost the same as the BIOS transmission process, and will not be described in detail here.

[0098] In this embodiment, the BMC's transmit data channel and receive data channel are independent of each other, reducing the impact between data transmission and reception and improving the accuracy of data transmission.

[0099] Based on the above embodiments, in this embodiment, the data packet of the first IPMI command or the data packet of the second IPMI command includes a data header and a data body; The data header includes the length of the first IPMI command or the second IPMI command, a checksum, a command number, and a preset data packet identifier. The request packet and the response packet of the first IPMI command have the same command number, and the request packet and the response packet of the second IPMI command have the same command number. The data body includes the receiving device number, command type, and command characters of the first IPMI command or the second IPMI command; The data body of the response packet also includes the command execution result.

[0100] Based on the above embodiments, in this embodiment, after the BIOS on the host writes a data packet of the first IPMI command to the first memory of the BMC through the PCIe bus, it receives the data packet of the first IPMI command, including: After the BIOS stores the data packet of the first IPMI command into the first memory, the first register of the first memory is set, triggering the first memory to generate an interrupt; In the event of an interrupt in the first memory, the data packet of the first IPMI command is received, and after receiving the data packet of the first IPMI command, the first register is reset.

[0101] The IPMI command transmission method provided in this application sets the first IPMI command data packet after the BIOS stores it in the first memory, and resets it after receiving the first IPMI command data packet, so that the first IPMI command data packet is transmitted in an orderly manner and the BMS receives the first IPMI command in the first memory space in a timely manner.

[0102] Based on the above embodiments, such as Figure 8 As shown, in this embodiment there are multiple first memories and first memory spaces, and each first memory space corresponds to the first memory space. The step of receiving the data packet for the first IPMI command in the event of an interrupt in the first memory includes: Create a second receive queue, a second receive event, and a second execution event for the first memory; In the event of an interrupt in the first memory, the first IPMI command is retrieved from the first memory using the second receive event; Based on the length of the first IPMI command in the data packet of the first IPMI command, determine whether the entire data packet of the first IPMI command has been received; If not all packets of the first IPMI command are received, continue to determine whether other packets of the first memory have been interrupted; If all data packets of the first IPMI command have been received, all data packets of the first IPMI command are placed in the second receive queue so that the second execution event can execute all data packets of the first IPMI command in the second receive queue.

[0103] In the presence of multiple first memories, these multiple first memories can be used interchangeably. Figure 1 The example shows two first memories, h2bq0 and h2bq1.

[0104] The second receive event retrieves the data packet of the first IPMI command from the first memory that first generated the interrupt, and resets the first register of the first memory.

[0105] Check if all packets of the first IPMI command have been received. If not, continue to check if any other first memory has generated an interrupt. If an interrupt occurs, retrieve the packets of the first IPMI command from them, and then reset the first register of that first memory.

[0106] After all the data packets of the first IPMI command are received, all the data packets of the first IPMI command are put into the second receive queue. The second execution time will execute all the data packets of the first IPMI command and put the execution result into the second send queue.

[0107] The IPMI command transmission device provided by the present invention will be described below. The IPMI command transmission device described below can be referred to in correspondence with the IPMI command transmission method described above.

[0108] It should be noted that the IPMI command transmission method provided in this application embodiment can be executed by an IPMI command transmission device or a control module within that IPMI command transmission device for executing the IPMI command transmission method. This application embodiment uses the execution of the IPMI command transmission method by an IPMI command transmission device as an example to illustrate the IPMI command transmission device provided in this application embodiment.

[0109] It should be noted that, in the embodiments of this application, the IPMI command transmission methods shown in the accompanying drawings are all illustrated by way of example with reference to one of the accompanying drawings in the embodiments of this application. In specific implementation, the IPMI command transmission methods shown in the accompanying drawings of the above methods can also be implemented in conjunction with any other accompanying drawings shown in the above embodiments, which will not be elaborated here.

[0110] The IPMI command transmission apparatus provided in this application is described below, and the IPMI command transmission method described below can be referred to in correspondence with the IPMI command transmission method described above.

[0111] Figure 9 This is a schematic diagram of the structure of the IPMI command transmission device provided in the embodiments of this application, as shown below. Figure 9 As shown, it specifically includes a first transmitting module 901 and a first receiving module 902, wherein: The first sending module 901 is used to send the data packet of the first IPMI command in the first memory space of the host where the BIOS is located to the first memory via the PCIe bus when the first memory of the BMC is not full. The first receiving module 902 is used to receive the data packet of the second IPMI command sent by the BMC to the second memory space of the host through the PCIe bus. The second IPMI command is located in the second memory of the BMC and is sent by the BMC when the second memory space is not full.

[0112] The IPMI command transmission device provided in this application transmits data packets of the first IPMI command in the first memory space of the host where the BIOS is located to the first memory of the BMC via the PCIe bus through the BIOS. The BIOS receives data packets of the second IPMI command in the second memory sent by the BMC to the second memory space of the host via the PCIe bus through the BIOS. On the one hand, the BIOS and BMC transmit IPMI commands via the PCIe bus, which improves the transmission speed of IPMI commands and reduces hardware costs. On the other hand, the BIOS's data transmission channel and data reception channel are independent of each other, which reduces the influence between data transmission and reception and improves the accuracy of data transmission.

[0113] Figure 10 This is a schematic diagram of the structure of the IPMI command transmission device provided in the embodiments of this application, as shown below. Figure 10 As shown, it specifically includes a second transmitting module 1001 and a second receiving module 1002, wherein: The second sending module 1001 is used to send the data packet of the second IPMI command in the second memory of the BMC to the second memory space via the PCIe bus when the second memory space of the host is not full. The second receiving module 1002 is used to receive the data packet of the first IPMI command after the BIOS on the host writes the data packet of the first IPMI command to the first memory of the BMC through the PCIe bus. The first IPMI command is located in the first memory space of the host and is written by the BIOS when the first memory is not full.

[0114] The IPMI command transmission device provided in this application transmits data packets of second IPMI commands from the second memory of the BMC to the second memory space of the host via the PCIe bus. The BMC also receives data packets of first IPMI commands written to the first memory of the BMC via the PCIe bus by the BIOS. On the one hand, the transmission of IPMI commands between the BIOS and the BMC via the PCIe bus improves the transmission speed of IPMI commands and reduces hardware costs. On the other hand, the BMC's transmit and receive data channels are independent of each other, reducing the impact between data transmission and reception and improving the accuracy of data transmission.

[0115] This embodiment provides an IPMI command transmission system, including the IPMI command transmission device described in the two embodiments above.

[0116] The IPMI command transmission system provided in this application transmits IPMI commands between the BIOS and BMC via the PCIe bus, thereby improving the transmission speed of IPMI commands and reducing hardware costs. On the other hand, the BMC's transmit data channel and receive data channel are independent of each other, and the BIOS's transmit data channel and receive data channel are also independent of each other, reducing the impact between data transmission and reception and improving the accuracy of data transmission.

[0117] Figure 11 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 11 As shown, the electronic device may include: a processor 1110, a communications interface 1120, a memory 1130, and a communication bus 1140, wherein the processor 1110, the communications interface 1120, and the memory 1130 communicate with each other via the communication bus 1140. The processor 1110 can call logical instructions in the memory 1130 to execute an IPMI command transmission method, which includes: If the first memory of the BMC is not full, the data packet of the first IPMI command in the first memory space of the host where the BIOS is located is sent to the first memory via the PCIe bus; the data packet of the second IPMI command sent by the BMC to the second memory space of the host via the PCIe bus is received. The second IPMI command is located in the second memory of the BMC and is sent by the BMC when the second memory space is not full.

[0118] Furthermore, the logical instructions in the aforementioned memory 1130 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0119] On the other hand, this application also provides a computer program product, which includes a computer program stored on a computer-readable storage medium. The computer program includes program instructions, and when the program instructions are executed by a computer, the computer is able to execute the IPMI command transmission method provided by the above methods, the method including: If the first memory of the BMC is not full, the data packet of the first IPMI command in the first memory space of the host where the BIOS is located is sent to the first memory via the PCIe bus; the data packet of the second IPMI command sent by the BMC to the second memory space of the host via the PCIe bus is received. The second IPMI command is located in the second memory of the BMC and is sent by the BMC when the second memory space is not full.

[0120] In another aspect, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to perform the IPMI command transmission methods provided above, the method comprising: If the first memory of the BMC is not full, the data packet of the first IPMI command in the first memory space of the host where the BIOS is located is sent to the first memory via the PCIe bus; the data packet of the second IPMI command sent by the BMC to the second memory space of the host via the PCIe bus is received. The second IPMI command is located in the second memory of the BMC and is sent by the BMC when the second memory space is not full.

[0121] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0122] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0123] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. An IPMI command transmission method, characterized in that, Applied to BIOS, including: If the first memory of the BMC is not full, the data packet of the first IPMI command in the first memory space of the host where the BIOS is located is sent to the first memory via the PCIe bus; The BMC receives a data packet containing a second IPMI command sent to the host's second memory space via the PCIe bus. The second IPMI command is located in the BMC's second memory and is sent by the BMC when the second memory space is not full. The step of sending the data packet of the first IPMI command in the first memory space of the host where the BIOS is located to the first memory via the PCIe bus when the first memory of the BMC is not full includes: When the first register corresponding to the first memory is reset and the first memory is not full, the data packet of the first IPMI command is written to the first memory through the PCIe bus. The first register is set after the data packet of the first IPMI command is stored in the first memory to trigger an interrupt in the first memory, which notifies the BMC to receive the data packet of the first IPMI command. The first register is reset after the BMC has received the first IPMI command.

2. The method according to claim 1, characterized in that, There are multiple first memories and first memory spaces, and each first memory space and the first memory space corresponds to another one. The step of sending the data packet of the first IPMI command in the first memory space of the host where the BIOS is located to the first memory via the PCIe bus when the first memory of the BMC is not full includes: If the first register of the first memory corresponding to any of the first memory spaces is reset, and the remaining capacity of the first memory is greater than the capacity occupied by the first IPMI command, the first memory corresponding to the first memory space shall be used as the target memory. If the first register of the first memory corresponding to any first memory space is set, or if the remaining capacity of the first memory corresponding to any first memory space is less than or equal to the capacity occupied by the first IPMI command, the first memory with the first register reset and the remaining capacity greater than the capacity occupied by the first IPMI command is selected from other first memories as the target memory. After increasing the priority of the write event to the target memory, the data packet of the first IPMI command is written to the target memory through the PCIe bus, and the priority of the write event to the target memory is restored.

3. The method according to claim 1, characterized in that, The step of sending the data packet of the first IPMI command in the first memory space of the host where the BIOS is located to the first memory via the PCIe bus when the first memory of the BMC is not full includes: Create a first send queue and a first send event for the first memory space; Store the first IPMI command in the first transmission queue and wake up the first transmission event; If the first IPMI command exists in the first transmission queue and the first memory is not full, the first transmission event is used to store the data packet of the first IPMI command in the first transmission queue into the first memory through the PCIe bus. If the data packet of the first IPMI command is a reply packet, the first sending event enters a sleep state; If the data packet of the first IPMI command is a request packet, wait for the response packet returned by the BMC, and update the status of the first IPMI command according to the command execution result of the first IPMI command in the response packet.

4. The method according to claim 1, characterized in that, The data packet of the first IPMI command or the data packet of the second IPMI command includes a data header and a data body; The data header includes the length of the first IPMI command or the second IPMI command, a checksum, a command number, and a preset data packet identifier. The request packet and response packet of the first IPMI command have the same command number, and the request packet and response packet of the second IPMI command have the same command number. The data body includes the receiving device number, command type, and command characters of the first IPMI command or the second IPMI command; The data body of the response packet also includes the command execution result.

5. The method according to any one of claims 1-4, characterized in that, The data packet for receiving the second IPMI command sent by the BMC to the second memory space of the host via the PCIe bus includes: When the host polls the second register corresponding to the second memory and determines that the second register is set, it receives the data packet of the second IPMI command from the second memory space; The second register is set after the data packet of the second IPMI command is written into the second memory space, and is reset after the data packet of the second IPMI command is received from the second memory space.

6. The method according to claim 5, characterized in that, There are multiple second memories and second memory spaces, and each second memory space corresponds to a different second memory space. The step of receiving the data packet for the second IPMI command from the second memory space when the second register is set includes: Create a first receive queue, a first receive event, and a first execution event for the second memory space; When the second register corresponding to a single second memory is set, the data packet of the second IPMI command is received from the second memory space corresponding to the single second memory using the first receive event, and the second register corresponding to the single second memory is reset; When the second registers corresponding to multiple second memories are set, the data packets of the second IPMI command are retrieved from the second memory spaces corresponding to multiple second memories using the first receive event, the second registers corresponding to multiple second memories are reset, and the order of the retrieved data packets of the second IPMI command is determined according to the preset data packet identifier in the retrieved data packets of the second IPMI command. Based on the length of the second IPMI command in the data packet of the second IPMI command, determine whether the entire data packet of the second IPMI command has been received; If not all data packets of the second IPMI command are received, continue polling the second registers corresponding to the other second memories; If all data packets of the second IPMI command have been received, all data packets of the second IPMI command are placed in the first receive queue so that the first execution event can execute all data packets of the second IPMI command in the first receive queue.

7. An IPMI command transmission method, characterized in that, Applied to BMC, including: If the host's second memory space is not full, the data packet of the second IPMI command in the second memory of the BMC is sent to the second memory space through the PCIe bus; After the BIOS on the host writes a data packet of the first IPMI command to the first memory of the BMC through the PCIe bus, it receives the data packet of the first IPMI command. The first IPMI command is located in the first memory space of the host and is written by the BIOS when the first memory is not full. The step of sending the data packet of the second IPMI command in the second memory of the BMC to the second memory space via the PCIe bus when the second memory space of the host is not full includes: When the second register corresponding to the second memory is reset and the second memory space is not full, the data packet of the second IPMI command is written into the second memory space through the PCIe bus; The second register is set after the data packet of the second IPMI command is stored in the second memory space, and is reset after the BIOS receives the second IPMI command in the second memory space.

8. The method according to claim 7, characterized in that, There are multiple second memories and second memory spaces, and each second memory space corresponds to a different second memory space. The step of sending the data packet of the second IPMI command in the second memory of the BMC to the second memory space via the PCIe bus when the second memory space of the host is not full includes: If the second register of any second memory is reset, and the remaining capacity of the second memory space corresponding to any second memory is greater than the capacity occupied by the second IPMI command, the second memory space corresponding to any second memory shall be used as the target memory space. If the second register of any second memory is set, or if the remaining capacity of the second memory space corresponding to any second memory is less than or equal to the capacity occupied by the second IPMI command, the second memory space whose second register of the corresponding second memory is reset and whose remaining capacity is greater than the capacity occupied by the second IPMI command is selected from other second memory spaces as the target memory space. After increasing the priority of the write event to the target memory space, the data packet of the second IPMI command is stored in the target memory space through the PCIe bus, and the priority of the write event to the target memory space is restored.

9. The method according to claim 7, characterized in that, The step of sending the data packet of the second IPMI command in the second memory of the BMC to the second memory space via the PCIe bus when the second memory space of the host is not full includes: Create a second send queue and a second send event for the second memory; The second IPMI command is stored in the second transmission queue, the second transmission event is woken up, and the second transmission event is used to poll the second transmission queue; If the second IPMI command exists in the second transmission queue and the second memory space is not full, the second transmission event is used to store the data packet of the second IPMI command in the second transmission queue into the second memory space through the PCIe bus; If the data packet of the second IPMI command is a reply packet, the second send event enters a sleep state; If the data packet of the second IPMI command is a request packet, wait for the response packet returned by the BIOS, and update the status of the second IPMI command according to the command execution result of the second IPMI command in the response packet.

10. The method according to claim 7, characterized in that, The data packet of the first IPMI command or the data packet of the second IPMI command includes a data header and a data body; The data header includes the length of the first IPMI command or the second IPMI command, a checksum, a command number, and a preset data packet identifier. The request packet and response packet of the first IPMI command have the same command number, and the request packet and response packet of the second IPMI command have the same command number. The data body includes the receiving device number, command type, and command characters of the first IPMI command or the second IPMI command; The data body of the response packet also includes the command execution result.

11. The method according to any one of claims 7-10, characterized in that, After the BIOS on the host writes a data packet of the first IPMI command to the first memory of the BMC via the PCIe bus, it receives the data packet of the first IPMI command, including: After the BIOS stores the data packet of the first IPMI command into the first memory, the first register of the first memory is set, triggering the first memory to generate an interrupt; In the event of an interrupt in the first memory, the data packet of the first IPMI command is received, and after receiving the data packet of the first IPMI command, the first register is reset.

12. The method according to claim 11, characterized in that, There are multiple first memories and first memory spaces, and each first memory space and the first memory space corresponds to another one. The step of receiving the data packet for the first IPMI command in the event of an interrupt in the first memory includes: Create a second receive queue, a second receive event, and a second execution event for the first memory; In the event of an interrupt in the first memory, the first IPMI command is retrieved from the first memory using the second receive event; Based on the length of the first IPMI command in the data packet of the first IPMI command, determine whether the entire data packet of the first IPMI command has been received; If not all packets of the first IPMI command are received, continue to determine whether other packets of the first memory have been interrupted; If all data packets of the first IPMI command have been received, all data packets of the first IPMI command are placed in the second receive queue so that the second execution event can execute all data packets of the first IPMI command in the second receive queue.

13. An IPMI command transmission device, characterized in that, include: The first sending module is used to send the data packet of the first IPMI command in the first memory space of the host where the BIOS is located to the first memory via the PCIe bus when the first memory of the BMC is not full. The first receiving module is used to receive a data packet of a second IPMI command sent by the BMC to the second memory space of the host through the PCIe bus. The second IPMI command is located in the second memory of the BMC and is sent by the BMC when the second memory space is not full. The first sending module is specifically used for: When the first register corresponding to the first memory is reset and the first memory is not full, the data packet of the first IPMI command is written to the first memory through the PCIe bus. The first register is set after the data packet of the first IPMI command is stored in the first memory to trigger an interrupt in the first memory, which notifies the BMC to receive the data packet of the first IPMI command. The first register is reset after the BMC has received the first IPMI command.

14. An IPMI command transmission device, characterized in that, include: The second sending module is used to send the data packet of the second IPMI command in the second memory of the BMC to the second memory space via the PCIe bus when the second memory space of the host is not full. The second receiving module is used to receive the data packet of the first IPMI command after the BIOS on the host writes the data packet of the first IPMI command to the first memory of the BMC through the PCIe bus. The first IPMI command is located in the first memory space of the host and is written by the BIOS when the first memory is not full. The second sending module is specifically used for: When the second register corresponding to the second memory is reset and the second memory space is not full, the data packet of the second IPMI command is written into the second memory space through the PCIe bus; The second register is set after the data packet of the second IPMI command is stored in the second memory space, and is reset after the BIOS receives the second IPMI command in the second memory space.

15. An IPMI command transmission system, characterized in that, It includes the IPMI command transmission device as described in claim 13 and the IPMI command transmission device as described in claim 14.

16. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the steps of the IPMI command transmission method as described in any one of claims 1 to 12.

17. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by a processor, implements the steps of the IPMI command transmission method as described in any one of claims 1 to 12.

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