A cell timing prediction method, device and medium considering multi-input conversion effect

Abstract

The application discloses a unit timing prediction method and device considering multi-input conversion effect and a medium, for a multi-input combination logic unit, characteristic information of a timing arc input mode and a transistor in a standard unit is extracted, a standard unit timing library correction model under MIS effect influence is constructed and trained, and is used for predicting a correction amount of the unit timing library compared with the unit timing library without considering the MIS effect. The unit timing model construction considering the multi-input conversion effect proposed by the application can correct the original timing library timing delay result and can be applied to digital circuit static timing analysis. Compared with a traditional unit timing library modeling mode without considering the MIS effect, the application can accurately and quickly perform timing modeling on the standard unit, reduces optimistic or pessimistic analysis during hold time checking and setup time checking due to the MIS effect, and thus avoids performance loss or causes functional failure.

Description

TECHNICAL FIELD

[0001] The present application relates to a cell timing prediction method, device and medium considering multiple input switching effect, and belongs to the technical field of digital integrated circuit design. BACKGROUND

[0002] Static Timing Analysis (STA) is a complete and detailed method used to verify timing requirements of digital integrated circuit design. Compared with dynamic timing simulation, static timing analysis does not need to use test vectors to activate a path, and the analysis speed is several orders of magnitude faster than timing simulation, which is suitable for large-scale circuit design verification and has become a necessary method for current integrated circuit design timing verification. With the increase of the complexity of digital integrated circuit design, chips often need to use standard cell library for hierarchical design. The timing library of the standard cell defines the timing performance of each timing arc in the cell. The static timing analysis tool calculates the cell delay and line delay on the timing path according to the standard cell timing library information, and then checks whether the path delay meets the timing constraints. Therefore, the standard cell timing library is very important for digital integrated circuit, and has a great influence on the timing convergence and design performance of the circuit. However, the establishment of the standard cell timing library needs to consume a large amount of time and simulation cost, especially under advanced process, the influence of various effects on timing and its characterization are more difficult, how to quickly and accurately establish the standard cell timing library has become a challenge faced by current integrated circuit design.

[0003] The current commonly used static timing analysis method adopts a cell delay model assuming that the gate has only one input switching when the input signal is switched, and other inputs remain at non-controlling values, that is, a Single-Input Switching (SIS) model. The advantage of this model based on single input switching is that the description overhead and the number of inputs are in linear relationship, but it cannot capture the possibility of multiple input switching at the same time in the actual circuit.

[0004] In the signal propagation of actual circuits, different input signals of a multiple-input cell (such as NAND gate, NOR gate, etc.) can be switched at the same time or at a close time, and this case of multiple inputs of a cell being switched at the same time is referred to as multiple-input switching (MIS). The actual MIS delay of a cell in the case of multiple-input switching can have a significant change relative to the SIS delay calculated based on the analysis assumption of single-input switching. If the actual MIS delay of a cell is less than the calculated SIS delay, the early arrival time can be overestimated in the timing analysis, and a setup time violation can occur, causing the circuit to fail. If the actual MIS delay of a cell is greater than the calculated SIS delay, the late arrival time can be underestimated, and a hold time violation can occur, causing the circuit to fail to work normally at the current working frequency.

[0005] With the continuous development of integrated circuits and the continuous progress of process nodes, the working frequency of circuit design is getting higher and higher, and the influence of changes caused by advanced process nodes is getting greater and greater, leading to an increased probability of MIS effect. Therefore, the MIS effect still faces great challenges in characterization. On the one hand, MIS delay is affected by many factors, and the influence of MIS effect on delay is different under different input modes (input mode refers to the state of all inputs of the cell) of different cells. Under a specific input mode, the changes of associated input switching time, output load, side input switching time, and input skew will cause changes in MIS delay, and these parameters and MIS delay present a nonlinear relationship, which brings great challenges in the characterization accuracy of the model. On the other hand, when characterizing the factors affecting MIS delay, different combinations of different cells, different input modes, different associated input switching times, output loads, side input switching times, and input skews need to be simulated. For simulation of different input modes, since each input signal of a cell has four states of rising, falling, always high, and always low, the number of input modes of an N-input cell is 4N, which presents an exponential growth trend with the number of input signals. The cost of modeling all input modes is unacceptable, and the characterization of MIS delay faces great simulation overhead. Therefore, in the static timing analysis process, a cell timing model considering MIS effect needs to be constructed to characterize the influence of MIS effect on delay.

[0006] The field of machine learning is also developing rapidly, and machine learning-based methods have appeared in the application of electronic design automation (EDA), especially in the field of standard cell timing library characterization. For different research problems, different machine learning models can capture the dependence of the research object on the input features of the traditional timing cell model or integrated circuit model, thereby better characterizing various cell timing problems. Moreover, machine learning models can succinctly represent multidimensional data and can be used to handle problems that are difficult to characterize using traditional methods due to excessive input parameters. However, current research mainly uses gate cell features for modeling, lacks node topology information, and cannot meet the high accuracy requirements of prediction.

[0007] In addition, the Graph Neural Network (GNN) learns the information of adjacent nodes based on the graph learning method, thereby extracting cell-level topology information, and is a method that can be effectively applied to establish a cell timing model. However, the existing GNN model for the cell timing library still has deficiencies. First, the existing GNN model only retains the output of the last layer when learning node representation, which can cause the loss of node topology information of adjacent transistors at a first or second order distance. Second, the method of classifying edges only according to the actual existing connection relationship between transistors, power supply nodes, and output nodes in the transistor-level topology structure of the cell does not effectively utilize prior knowledge of the multiple input switching effect.

[0008] In general, most circuit simulations use a margin to model the worst-case change in cell and circuit delay caused by the MIS effect, or fit it as a linear function of the input bias, and ignore the correlation between MIS delay and input switching time, load capacitance, and cell input pattern, which cannot obtain good accuracy, resulting in overly optimistic or pessimistic estimates of the MIS effect. The current machine learning-based multiple input switching effect modeling method cannot reduce simulation overhead while obtaining high-precision delay prediction results.

[0009] Therefore, how to establish a MIS cell delay prediction model that is suitable for MIS cells, reduce optimistic analysis during hold time checking and setup time checking due to the MIS effect, and reduce the simulation overhead of MIS cell timing modeling is a problem that needs to be solved. SUMMARY

[0010] Objective: In order to overcome the deficiencies in the prior art, the present application provides a cell timing prediction method, device and medium considering multiple input switching effects, which can accurately predict the MIS delay of the cell and effectively reduce the simulation overhead of the cell.

[0011] Technical solution: To solve the above technical problems, the technical solution adopted by the present application is:

[0012] In a first aspect, a cell timing prediction method considering multi-input conversion effect, comprising the following steps:

[0013] Step S1: listing cell input modes affected by multi-input cell MIS effect on delay, finding corresponding SIS timing arc and SIS timing arc lookup table in SIS timing library for each cell input mode, generating timing information under single-input effect according to the lookup table in SIS timing library, and taking the timing information under single-input effect as initial sample data.

[0014] Step S2: obtaining an index value list of input skew according to the initial sample data.

[0015] Step S3: taking the initial sample data and the index value list of input skew as input of a timing analysis tool, and outputting MIS delay value of the multi-input cell by the timing analysis tool, and obtaining delay correction amount as real label value by subtracting the delay value under single-input effect from the MIS delay value.

[0016] Step S4: performing static timing simulation on the initial sample data to obtain topology information of the multi-input cell, generating connection relationship between nodes of the multi-input cell according to the topology information of the multi-input cell, generating feature information of the nodes according to the timing information under single-input effect of the multi-input cell, and constructing a heterogeneous graph containing an adjacency matrix and an initial feature matrix according to the connection relationship between the nodes and the feature information of the nodes.

[0017] Step S5: taking the heterogeneous graph and the real label value as training sample of a heterogeneous graph neural network module, training the heterogeneous graph neural network module, updating network parameters of the heterogeneous graph neural network, and obtaining the trained heterogeneous graph neural network module.

[0018] Step S6: obtaining the heterogeneous graph containing the adjacency matrix and the initial feature matrix of the target multi-input cell according to the topology information and the timing information under single-input effect of the target multi-input cell, and inputting the heterogeneous graph of the target multi-input cell into the trained heterogeneous graph neural network module to obtain delay correction amount under each multi-input conversion mode of the target multi-input cell.

[0019] Step S7: obtaining MIS delay prediction value by accumulating the delay correction amount of the target multi-input cell and the delay value under single-input conversion effect of the target multi-input cell.

[0020] As a preferred scheme, the step S2 specifically comprises:

[0021] According to the initial sample data, an input conversion time and output load capacitance associated index value list is obtained, and an inter-input skew index value list is obtained by uniformly taking values within an inter-input skew window under different combinations of the input conversion time, output load capacitance, and input conversion time index value list.

[0022] As a preferred solution, the heterogeneous graph is composed according to the connection relationship among the transistors, power supply, and output node of the multi-input gate unit, different transistor types are represented by nodes of different colors, and different connection relationships are represented by edges of different colors.

[0023] As a preferred solution, the edge types of the heterogeneous graph include a series connection between transistors, a parallel connection between transistors, two transistors on two parallel branches and at least one transistor on at least one parallel branch, a connection between a transistor and a power supply node, and a connection between a transistor and an output pin.

[0024] As a preferred solution, the step S5 specifically includes:

[0025] Step S51: mapping the feature vector corresponding to the transistor level in each gate unit in the feature matrix corresponding to the heterogeneous graph into a fixed-dimension vector through the embedding layer.

[0026] Step S52: connecting the output of the embedding layer to the heterogeneous graph neural network model for learning, the heterogeneous graph neural network layer including multiple aggregation layers and encoding layers, the aggregation layers respectively aggregating the feature information of each transistor unit, the output of the aggregation layer being input to the encoding layer, and the current node embedding vector being obtained after learning of the encoding layer, the current node embedding vector being input to the next aggregation layer and the encoding layer.

[0027] Step S53: repeating the aggregation and encoding process until the node embedding vectors output by the multiple aggregation layers and encoding layers are obtained, and merging the multiple node embedding vectors into node representation.

[0028] Step S54: inputting the node representation into the fully connected layer for training, calculating the error between the predicted value of the heterogeneous graph neural network model and the true value of the sample, optimizing the parameters of the heterogeneous graph neural network model through the adaptive matrix estimation optimizer, so that the loss function is as small as possible, outputting the parameters whose loss function value meets the threshold, and obtaining the trained heterogeneous graph neural network module.

[0029] As a preferred solution, the number of aggregation layers and encoding layers of the heterogeneous graph neural network module is set to 3, the number of hidden layer neurons is 128, the number of output layer neurons is 128, the number of neighbor node samples is 15, the dimension of the embedding layer is 32, and the dimension of the feature matrix is 14.

[0030] As a preferred solution, the full connection layer comprises 3 perceptron layers, the feature matrix dimension is 14, the number of hidden layer neurons is 128, and the number of output layer neurons is 128.

[0031] In a second aspect, a computer readable storage medium has a computer program stored thereon, and the computer program is executed by a processor to implement the method for cell timing prediction considering multi-input switching effect according to any one of the first aspect.

[0032] In a third aspect, a computer device comprises:

[0033] A memory is configured to store instructions.

[0034] A processor is configured to execute the instructions, so that the computer device performs the operations of the method for cell timing prediction considering multi-input switching effect according to any one of the first aspect.

[0035] Beneficial effects: The method for cell timing prediction considering multi-input switching effect, the device and the medium provided by the application can, for a multi-input combination logic cell, extract feature information of a transistor in a timing arc input mode and a standard cell, construct and train a standard cell timing library correction model under MIS effect influence, and be used for predicting a correction amount of a cell timing library compared with a cell timing library without considering MIS effect. The cell timing model considering multi-input switching effect constructed by the application can correct original timing library timing delay results and can be applied in digital circuit static timing analysis. Compared with a traditional cell timing library modeling method without considering MIS effect, the application can accurately and quickly perform timing modeling on a standard cell, reduces optimistic or pessimistic analysis during hold time checking and setup time checking caused by MIS effect, and thus avoids performance loss or causes functional failure.

[0036] The application can be applied in cell static timing analysis, compared with a commercial tool only considering single-input switching model, is more accurate in estimating circuit timing convergence or violation, can more quickly obtain cell or path static delay size, and experimental results are in good agreement with golden SPICE simulation results, and greatly improves timing violation checking speed and efficiency. The application has important significance for improving accuracy of cell timing modeling and reducing cell model simulation overhead. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 FIG. 1 is a flowchart of a method for cell timing prediction considering multi-input effect.

[0038] Figure 2 FIG. 4 is a schematic diagram of input data of a heterogeneous graph neural network module.

[0039] Figure 3This is a schematic diagram of the structure of a graph neural network (GNN) model.

[0040] Figure 4 (a) is a schematic diagram of homogeneous graph neural network processing. Figure 4 (b) is a schematic diagram of heterogeneous graph neural network processing.

[0041] Figure 5 This is a schematic diagram of the classification results for heterogeneous graphs with multiple input units.

[0042] Figure 6 This is a schematic diagram of the structural parameters of a graph neural network (GNN) model.

[0043] Figure 7 This is a schematic diagram of the multilayer perceptron network (MLP) model structure. Detailed Implementation

[0044] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0045] The present invention will be further described below with reference to specific embodiments.

[0046] Example 1:

[0047] like Figure 1 As shown, this embodiment introduces a cell timing prediction method considering multi-input conversion effects, including: for multi-input standard cells (hereinafter referred to as: multi-input cells) in a standard cell timing library, considering the simultaneous conversion of multiple inputs, performing cell timing prediction on the actual cell delay representation, so as to maximize the delay accuracy of the cell timing and reduce the cell timing prediction overhead; the method includes the following steps:

[0048] Step S1: List the cell input modes that affect the delay due to the MIS effect of the multi-input cell. For each cell input mode, find the corresponding SIS timing arc and its lookup table in the SIS timing library. Generate timing information under the single-input effect based on the lookup table in the SIS timing library, and use the timing information under the single-input effect as the initial sample data. Perform static timing simulation on the initial sample data to obtain the topology information of the multi-input cell. The timing information under the single-input effect includes: associated input transition time and output load capacitance, and a list of side input transition time index values.

[0049] The unit input mode refers to combining different input signals of the multi-input cell, and each input signal combination corresponds to a unit input mode. The multi-input cell delay affected by the MIS effect will be reduced or increased.

[0050] Step S2: uniformly taking values in the inter-input skew window under different combinations of the associated input conversion time, the output load capacitance, and the side input conversion time index value list to obtain an inter-input skew index value list.

[0051] Step S3: taking the associated input conversion time, the side input conversion time index value list, the output load capacitance, and the inter-input skew index value list as inputs of the timing analysis tool, obtaining the MIS delay value of the specified multi-input cell through the timing analysis tool, and obtaining the delay correction amount corresponding to each group of multi-input cells under the corresponding unit input mode as the true label value by subtracting the delay value under the single-input effect.

[0052] The timing analysis tool adopts a SPICE simulation tool. By simulating the transistors of the multi-input cell, the transistor-level connection relationship information and the accurate MIS delay value under different unit input modes can be obtained, but the simulation cost is high.

[0053] Step S4: generating the connection relationship between the nodes of the multi-input cell according to the topology information of the multi-input cell, generating the feature information of the nodes according to the timing information of the multi-input cell under the single-input effect, and constructing a heterogeneous graph containing an adjacency matrix and an initial feature matrix according to the connection relationship between the nodes and the feature information of the nodes.

[0054] Step S5: taking the heterogeneous graph and the true label value as a training sample of the heterogeneous graph neural network module, training the heterogeneous graph neural network module, updating the network parameters of the heterogeneous graph neural network, so that the heterogeneous graph neural network model can establish the relationship between the cell topology structure and the MIS delay, and obtaining the trained heterogeneous graph neural network module.

[0055] Step S6: obtaining the heterogeneous graph containing the adjacency matrix and the initial feature matrix of the target multi-input cell according to the topology information and the timing information under the single-input effect of the target multi-input cell. Inputting the heterogeneous graph of the target multi-input cell into the trained heterogeneous graph neural network module to obtain the output embedding vector corresponding to the delay correction amount of each multi-input conversion mode of the target multi-input cell.

[0056] Step S7: obtaining the final MIS delay prediction value through the MIS delay generation module according to the delay correction amount of the target multi-input cell, so as to provide more accurate prediction MIS delay information for the multi-input standard cell timing library.

[0057] The MIS delay generation module is to accumulate the delay correction amount and the delay value under the single input conversion effect of the multi-input unit, thereby calculating the MIS delay prediction value.

[0058] The inter-input skew window refers to that when the inter-input skew is within a certain range, the MIS effect occurs and causes the cell delay to change, and this range of inter-input skew that causes the cell delay to change significantly is referred to as the inter-input skew window; and for each combination of index values of the associated input conversion time, the side input conversion time and the output load capacitance, the range of the inter-input skew of the multi-input conversion effect is calculated.

[0059] The topology information of the multi-input cell is obtained from the report after timing simulation, and the circuit timing information is obtained from the timing report based on the single input conversion analysis by the static timing tool, including the cell type, the cell size, the input conversion type of the associated input and the side input, the conversion time of the associated input and the side input, the output load capacitance and the inter-input skew.

[0060] The topology feature input information of the cell includes: node type, transistor size, conversion type of transistor gate input signal, conversion time of transistor gate input signal, output load capacitance, skew between transistor gate input signal and associated input signal, and associated input node of timing arc of transistor gate.

[0061] After the heterogeneous graph neural network model is trained, the topology information and the timing information at the cell level can be learned, thereby establishing the relationship between the cell topology structure and the multi-input conversion effect. The network predicts the delay correction amount of each group of samples by inputting the adjacency matrix, the feature matrix and the label value of the multi-input cell, and finally obtains the cell timing delay under different multi-input conversion effects, thereby correcting the delay of the original timing library model and improving the timing delay characteristics of the standard cell timing library.

[0062] The input heterogeneous graph information of the MIS cell delay model of the heterogeneous graph neural network includes: Figure 2 As shown in the figure, according to the connection relationship of the multi-input gate cell, the connection relationship is converted into a heterogeneous graph composed of nodes and edges, the adjacency matrix and the node features are taken as the feature input, and the corresponding delay correction value is extracted for each node as the label value for model training. The topology graph information is input into the heterogeneous graph neural network module for graph embedding learning. The heterogeneous graph neural network module includes multiple network layers, and the input topology information is predicted for MIS delay after passing through the multiple network layers of the heterogeneous graph neural network.

[0063] The network layer structure of the heterogeneous graph neural network module is as shown in the figure. Figure 3As shown, first, the feature vector corresponding to each multi-input single unit in the initial feature matrix is mapped into an initial embedding vector of fixed dimension through the embedding layer, and the initial embedding vector is sent into the multi-layer heterogeneous GNN layer for learning. The heterogeneous GNN layer includes an aggregation layer for aggregating the features of the transistor unit and an encoding layer. The aggregated node embedding vector is input into the encoding layer, and the updated node embedding vector of the network layer is obtained through the learning of the encoding layer. The node embedding vector of the current GNN layer is used as the input of the next GNN layer, and the aggregation and encoding process is repeated until the output of the multi-layer heterogeneous GNN layer is obtained. Then, the node embedding vectors output by all network layers are input into the merging layer for merging. The merged embedding vector is input into the fully connected layer for dimension transformation, so as to obtain the MIS delay correction value under each input mode, and finally the node embedding vector containing neighbor node information is obtained, which captures the relationship between the topological feature information of the gate unit and the multi-input conversion effect.

[0064] The heterogeneous graph of the heterogeneous graph neural network is composed according to the connection relationship among the transistors (NMOS / PMOS), power supplies (VDD / VSS) and output nodes of the multi-input gate unit, as shown in Figure 4 (b), the connection relationship between circuits is converted into a heterogeneous graph, in which different color nodes represent different transistor types, and different color edges represent different connection relationships. The network layer includes an aggregation layer and an encoding layer. The aggregation layer aggregates the features of the neighbor nodes in the graph, so as to learn the information of the adjacent nodes. As shown in Figure 4 (a), the homogeneous graph neural network processes the adjacent nodes of these topological connection relationships in the same way, as shown in Figure 4 (b), the heterogeneous graph neural network extracts the neighbor node information of different edge relationships, and then combines them (through the AGG aggregation layer) and inputs them into the fully connected layer of the MLP network to obtain the node embedding vector after aggregating the neighbor node information, so as to represent the influence of different types of neighbor nodes on the MIS delay of the timing arc, and improve the prediction accuracy.

[0065] The heterogeneous graph type is as shown in Figure 5 As shown, whether there is a series and parallel relationship between the transistors has a greater impact on the MIS delay. According to the circuit structure, the edge type of the initial data corresponding to the heterogeneous graph is divided into five categories, as shown in Figure 5As shown, there are five types of connections between transistors, including series connection between transistors, parallel connection between transistors, two transistors on two parallel branches and at least one parallel branch with other transistors, connection between transistors and power nodes, and connection between transistors and output pins. Compared with traditional graph neural networks, the heterogeneous graph considers the MIS effect on the dependency relationship of each specific timing arc, considers the influence of the connection relationship of different transistors on MIS delay, and learns five different weight matrices for five types of edges, so that the model learns different topological information in different types of neighbor nodes, thereby obtaining more accurate MIS prediction delay.

[0066] As shown in Figure 6 The structure and parameters of each layer of the heterogeneous graph neural network model are given, and the structure corresponds to Figure 3 Each aggregation layer and encoding layer. As shown in Figure 7 The structure and parameters of the multi-layer perceptron (MLP) network are given, which corresponds to Figure 3 The fully connected layer of the full connection layer. Finally, the representation result of the multi-input conversion effect of each group of samples is obtained, thereby establishing the relationship between the cell topology structure and the multi-input conversion effect, and realizing the prediction of the cell timing delay under the multi-input conversion effect.

[0067] The step S5 specifically includes the following steps:

[0068] Step S51: According to the connection relationship between the transistors, power and output nodes in the multi-input gate cell, an adjacency matrix is constructed, the timing information and physical information of each node are extracted as the feature vector of the node, and then the initial feature matrix is obtained. According to the adjacency matrix and the initial feature matrix, a heterogeneous graph composed of nodes and edges is converted. The delay correction corresponding to the simulation is extracted for each node as the label value of the model training.

[0069] Step S52: As shown in Figure 3 The heterogeneous graph containing the adjacency matrix and the feature matrix vector is taken as the input of the heterogeneous graph neural network. First, the feature vector corresponding to the transistor level in each gate cell in the feature matrix is mapped to a fixed dimension vector through the embedding layer; then the output of the embedding layer is connected to the heterogeneous graph neural network for learning. The heterogeneous graph neural network layer includes a plurality of aggregation layers and encoding layers for aggregating features. The aggregation layer aggregates the feature information of each transistor cell, and the output of the aggregation layer is taken as the input of the encoding layer composed of the multi-layer perceptron. After learning by the encoding layer, the node embedding vector of the current heterogeneous graph neural network layer is updated, and the output of the current heterogeneous graph neural network layer is taken as the input of the next layer of the heterogeneous graph neural network layer. The aggregation and encoding process is repeated until the output of the multi-layer heterogeneous graph neural network layer is obtained; as shown in Figure 6The number of layers of the graph neural network extracting the transistor-level topological features is 3, the number of hidden layer neurons is 128, the aggregation function uses the mean aggregation function, the number of output layer neurons is 128, the number of neighbor node samples is 15, the embedding layer dimension is 32, and the feature matrix dimension is 14.

[0070] Step S53: input the learned node representation into the multilayer perceptron for training, as shown in the following formula (2). Figure 7 The parameters of the multilayer perceptron of the full connection layer are given, and the parameters of the multilayer perceptron module extracting the transistor-level features are as follows: the number of multilayer perceptron layers is 3, the feature matrix dimension is 14, the number of hidden layer neurons is 128, and the number of output layer neurons is 128. The error between the model prediction value and the sample true value is calculated, the loss function of the model is the mean square error (MSE), which is the average of the square distance between the model prediction value and the sample true value, and the loss function L is defined as shown in formula (1), wherein, y i and p i are the true value and the prediction value of the i-th sample of the model respectively, and n is the number of samples;

[0071]

[0072] Then, the model parameters are optimized by the adaptive moment estimation optimizer to make the loss function L as small as possible. The cross-entropy loss function is minimized by the adaptive moment estimation optimizer Adam to optimize the model parameters. Finally, the unit-level topological information is established to obtain the corresponding delay correction amount, and the multi-input conversion delay value corresponding to the node is obtained based on the single-input conversion timing library, which better represents the multi-input unit timing library.

[0073] Embodiment 2:

[0074] This embodiment introduces a computer readable storage medium, which stores a computer program. When the computer program is executed by a processor, a unit timing prediction method considering multi-input conversion effect is realized as any one of the embodiments 1.

[0075] Embodiment 3:

[0076] This embodiment introduces a computer device, which includes:

[0077] A memory is configured to store instructions.

[0078] A processor is configured to execute the instructions, so that the computer device performs the operations of the unit timing prediction method considering multi-input conversion effect as any one of the embodiments 1.

[0079] Those skilled in the art will appreciate that embodiments of the present application can be readily used as software, hardware, or a combination of software and hardware. In a software embodiment, the methods can be tangibly embodied in a machine-readable storage medium having stored thereon instructions that can be used to program a computer to perform any of the methods. The software implementation can be initialized by loading and executing a set of instructions arranged to perform one of the methods into the computer's memory. Alternatively, hard-wired circuitry can be used in place of, or in combination with, software instructions. Thus, the

[0080] The present application is described in reference to the flowchart and / or block diagrams of the method, apparatus (system) and computer program product according to embodiments of the application. It will be understood that each block of the flowchart and / or block diagrams, and combinations of blocks in the flowchart and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processing machine, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more functions specified in one or more of the flowchart or block diagram block or blocks. Figure 1 means for performing the function specified by the flowchart or block diagram block or blocks.

[0081] These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the flowchart or block diagram block or blocks. Figure 1 one or more functions specified in one or more of the flowchart or block diagram block or blocks. Figure 1 means for performing the function specified by the flowchart or block diagram block or blocks.

[0082] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the flowchart or block diagram block or blocks. Figure 1 one or more functions specified in one or more of the flowchart or block diagram block or blocks. Figure 1 means for performing the function specified by the flowchart or block diagram block or blocks.

[0083] The above description is only preferred embodiments of the present application. It is obvious that those skilled in the art can make some improvements and refinements without departing from the principles of the present application. These improvements and refinements should also be considered as falling within the scope of the present application.

Claims

1. A unit time series prediction method considering multi-input transformation effects, characterized in that: Includes the following steps: Step S1: List the unit input modes that affect the delay due to the multi-input unit MIS effect. For each unit input mode, find the corresponding SIS timing arc and the lookup table of the SIS timing arc in the SIS timing library. Generate timing information under the single-input effect based on the lookup table in the SIS timing library, and use the timing information under the single-input effect as the initial sample data. Step S2: Based on the initial sample data, obtain a list of index values ​​for the input skew; Step S3: Use the initial sample data and the list of index values ​​for input skew as input to the time series analysis tool. The time series analysis tool outputs the MIS delay value of the multi-input unit. Subtract the delay value from the delay value under the single-input effect to obtain the delay correction amount as the true label value. Step S4: Perform static time-series simulation on the initial sample data to obtain the topological information of the multi-input unit. Generate the connection relationship between the nodes of the multi-input unit based on the topological information of the multi-input unit. Generate the feature information of the node based on the time-series information of the single-input effect of the multi-input unit. Construct a heterogeneous graph containing the adjacency matrix and the initial feature matrix based on the connection relationship between the nodes and the feature information of the nodes. Step S5: Use the heterogeneous graph and the real label values ​​as training samples for the heterogeneous graph neural network module, train the heterogeneous graph neural network module, update the network parameters of the heterogeneous graph neural network, and obtain the trained heterogeneous graph neural network module. Step S6: Based on the topological information of the target multi-input unit and the temporal information under the single-input effect, obtain the heterogeneous graph of the target multi-input unit, which includes the adjacency matrix and the initial feature matrix; input the heterogeneous graph of the target multi-input unit into the trained heterogeneous graph neural network module to obtain the delay correction amount for each multi-input conversion mode of the target multi-input unit; Step S7: Based on the delay correction amount of the target multi-input unit, the delay value under the single-input conversion effect of the target multi-input unit is added together to obtain the MIS delay prediction value.

2. The cell time series prediction method considering multi-input transformation effects according to claim 1, characterized in that: Step S2 specifically includes: Based on the initial sample data, obtain the index values ​​of associated input transition time, output load capacitance, and side input transition time. Under different combinations of the index values ​​of associated input transition time, output load capacitance, and side input transition time, obtain the index value list of input skew by uniformly taking values ​​within the input skew window.

3. The cell time series prediction method considering multi-input transformation effects according to claim 1, characterized in that: The heterogeneous graph is composed of the connection relationships between transistors, power supplies and output nodes of a multi-input gate unit. Different transistor types are represented by nodes of different colors, and different connection relationships are represented by edges of different colors.

4. The cell time series prediction method considering multi-input transformation effects according to claim 3, characterized in that: The edge types of the heterogeneous graph include: series connection between transistors, parallel connection between transistors, two transistors on two parallel branches with other transistors on at least one parallel branch, connection between transistors and power nodes, and connection between transistors and output pins.

5. A cell time series prediction method considering multi-input transformation effects according to claim 1, characterized in that: Step S5 specifically includes: Step S51: Map the feature vectors corresponding to the transistor level in each gate unit of the feature matrix corresponding to the heterogeneous map to vectors of fixed dimension through the embedding layer; Step S52: Connect the output of the embedding layer to the heterogeneous graph neural network model for learning. The heterogeneous graph neural network layer includes multiple aggregation layers and encoding layers. The aggregation layer aggregates the feature information of each transistor unit. The output of the aggregation layer is used as the input of the encoding layer. After learning by the encoding layer, the current node embedding vector is updated. The current node embedding vector is used as the input of the next aggregation layer and encoding layer. Step S53: Repeat the aggregation and encoding process until multiple aggregation layers and the node embedding vectors output by the encoding layer are obtained, and merge the multiple node embedding vectors into a node representation; Step S54: Input the node representation into the fully connected layer for training, calculate the error between the predicted value of the heterogeneous graph neural network model and the true value of the sample, optimize the parameters of the heterogeneous graph neural network model through the adaptive moment estimation optimizer to minimize the loss function, output the parameters whose loss function values ​​meet the threshold, and obtain the trained heterogeneous graph neural network module.

6. A cell time series prediction method considering multi-input transformation effects according to claim 5, characterized in that: The heterogeneous graph neural network module has 3 aggregation layers and 3 encoding layers, 128 hidden layer neurons, 128 output layer neurons, 15 neighbor node samples, 32 embedding layer dimensions, and 14 feature matrix dimensions.

7. A cell time series prediction method considering multi-input transformation effects according to claim 5, characterized in that: The fully connected layer consists of three perceptron layers, with a feature matrix dimension of 14, 128 neurons in the hidden layer, and 128 neurons in the output layer.

8. A computer-readable storage medium, characterized in that: It stores a computer program that, when executed by a processor, implements a unit timing prediction method considering multi-input conversion effects as described in any one of claims 1-7.

9. A computer device, characterized in that: include: Memory, used to store instructions; A processor for executing the instructions, causing the computer device to perform the operation of a unit timing prediction method considering multiple input transformation effects as described in any one of claims 1-7.

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