Display device and display driving method

Abstract

This document discloses a display device and a display driving method. The display device includes: a display panel including multiple gate lines, multiple data lines, and multiple sub-pixels, wherein driving transistors are disposed in the multiple sub-pixels; a gate driving circuit configured to apply scan signals to the multiple gate lines; a data driving circuit configured to convert image data into data voltages and apply the data voltages to the multiple data lines; and a timing controller configured to compensate for and control the characteristic values ​​of the driving transistors during a blanking period by using a real-time sensing process to repeatedly apply recovery voltages based on a reference period to reset the driving transistors.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a display device and a display driving method that can reduce image errors that occur when the driving frequency changes and improve image quality. Background Technology

[0002] With the development of the information society, the demand for display devices for displaying images is increasing, and various types of display devices such as liquid crystal displays and organic light-emitting diode displays are being used.

[0003] Among these display devices, OLED displays use self-emissive organic light-emitting diodes, and therefore have advantages in terms of fast response speed, contrast ratio, luminous efficiency, brightness and viewing angle.

[0004] The display device may include a light-emitting element disposed in each of a plurality of sub-pixels disposed in a display panel, and the light-emitting element is controlled to emit light by controlling the voltage applied to the light-emitting element, thereby controlling the brightness represented by each sub-pixel and displaying an image.

[0005] In this configuration, the light-emitting element and the driving transistor used to control the light emission of the light-emitting element are located in each sub-pixel defined in the display panel. Depending on the driving environment of the display panel, deviations may occur in the characteristic values ​​of the driving transistor in each sub-pixel, such as threshold voltage or mobility. Therefore, brightness deviations (brightness non-uniformity) may occur between sub-pixels, which degrades image quality.

[0006] For example, the image data supplied to the display device can be a still image or a moving image that changes at a predetermined speed, and the moving image can also correspond to various types of images, such as motion pictures, movie and game images.

[0007] Since the format of image data can change depending on the type of image data, a variable refresh rate (VRR) mode in which the driving frequency changes according to the type of image data can be used.

[0008] However, when driving subpixels at various refresh rates by applying VRR mode, image errors may occur when the driving frequency changes, resulting in image quality degradation. Summary of the Invention

[0009] Therefore, the inventors of this specification propose a display device and a display driving method that can reduce image errors that occur when the driving frequency changes and improve image quality.

[0010] One aspect of this disclosure is to provide a display device and a display driving method that can reduce image errors that occur when the driving frequency changes and improve image quality by repeatedly applying a recovery voltage during the blanking period.

[0011] Another aspect of this disclosure is to provide a display device and a display driving method that can reduce image errors that occur when the driving frequency changes and improve image quality by determining a reference period for repeatedly applied recovery voltage during the blanking period based on the operating characteristics of the driving transistor.

[0012] Another aspect of this disclosure is to provide a display device and a display driving method that can reduce image errors that occur when the driving frequency changes and improve image quality by applying a recovery voltage that takes into account the delay time when the data enable signal is sent to the display panel.

[0013] In one aspect, embodiments of the present disclosure may provide a display device comprising: a display panel including a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixels in which driving transistors are disposed; a gate driving circuit configured to apply scan signals to the plurality of gate lines; a data driving circuit configured to convert image data into data voltages and apply the data voltages to the plurality of data lines; and a timing controller configured to, during a blanking period, compensate for and control the characteristic values ​​of the driving transistors by using a real-time sensing process to repeatedly apply recovery voltages based on a reference period to reset the driving transistors.

[0014] On the other hand, embodiments of this disclosure can provide a display driving method for a display device, the display device comprising: a display panel including a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixels in which driving transistors are disposed; a gate driving circuit configured to apply scan signals to the plurality of gate lines; and a data driving circuit configured to convert image data into data voltage and apply the data voltage to the plurality of data lines. The display driving method may include: a step of determining a reference time period for resetting a recovery voltage of the driving transistors; a step of displaying an image on the display panel; a step of compensating for characteristic values ​​of the driving transistors during a blanking time period; and a step of repeatedly applying the recovery voltage at intervals of the reference time period during the blanking time period.

[0015] According to embodiments of this disclosure, it is possible to reduce image errors that occur when the driving frequency changes and improve image quality.

[0016] Furthermore, according to embodiments of this disclosure, it is possible to reduce image errors that occur when the drive frequency changes and improve image quality by repeatedly applying a recovery voltage during the blanking period.

[0017] Furthermore, according to embodiments of this disclosure, it is possible to reduce image errors that occur when the drive frequency changes and improve image quality by determining a reference period for repeatedly applying the recovery voltage to the blanking period based on the operating characteristics of the drive transistor.

[0018] Furthermore, according to embodiments of this disclosure, it is possible to reduce image errors that occur when the drive frequency changes and improve image quality by applying a recovery voltage that takes into account the delay time when the data enable signal is transmitted to the display panel. Attached Figure Description

[0019] The above and other aspects, features and advantages of this disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0020] Figure 1 This is a schematic diagram illustrating the configuration of a display device according to an embodiment of the present disclosure;

[0021] Figure 2 This is an exemplary system diagram illustrating a display device according to an embodiment of the present disclosure;

[0022] Figure 3 This is an exemplary diagram illustrating the circuitry of a sub-pixel in a display device according to an embodiment of the present disclosure;

[0023] Figure 4 This is a diagram illustrating an exemplary circuit structure for sensing characteristic values ​​of a driving transistor in a display device according to an embodiment of the present disclosure;

[0024] Figure 5 This is a diagram illustrating a drive timing diagram of threshold voltage sensing among characteristic values ​​of a drive transistor in a display device according to an embodiment of the present disclosure.

[0025] Figure 6 This is a diagram showing a drive timing diagram of mobility sensing among the characteristic values ​​of a drive transistor in a display device according to an embodiment of the present disclosure.

[0026] Figure 7 This is a diagram illustrating an example of a signal timing diagram in a display device where a recovery period is included after the mobility sensing period of the driving transistor according to an embodiment of the present disclosure;

[0027] Figure 8 This is a diagram illustrating an example of the concept of switching between a default mode and a variable refresh rate mode in a display device according to the type of image data, according to an embodiment of the present disclosure;

[0028] Figure 9This is a diagram illustrating an example of a signal waveform in a variable refresh rate mode in a display device according to an embodiment of the present disclosure, where the vertical blanking period changes according to the driving frequency.

[0029] Figure 10 This is a diagram illustrating an example of a recovery voltage applied to the display panel according to a change in driving frequency in a display device according to an embodiment of the present disclosure;

[0030] Figure 11 This is a diagram illustrating the case where a recovery voltage is repeatedly applied to a vertical blanking period in a display device according to an embodiment of the present disclosure;

[0031] Figure 12 This is a diagram showing a reference time period in a display device according to an embodiment of the present disclosure, during which a recovery voltage is repeatedly applied to a vertical blanking period;

[0032] Figure 13 This is an exemplary block diagram of a circuit for generating a source output enable signal in a display device according to an embodiment of the present disclosure.

[0033] Figure 14 This is a diagram illustrating the signal flow in a display device for generating a source output enable signal according to an embodiment of the present disclosure;

[0034] Figure 15 This is a diagram illustrating the signal flow in accordance with an embodiment of the present disclosure, taking into account the delay time of the data enable signal and the source output enable signal in the display device;

[0035] Figure 16 This is a flowchart illustrating a display driving method according to an embodiment of the present disclosure. Detailed Implementation

[0036] In the following description, some embodiments of this disclosure will be described in detail with reference to exemplary accompanying drawings. In the following description of examples or embodiments of this disclosure, reference will be made to the accompanying drawings, in which specific examples or embodiments that may be implemented are illustrated by way of illustration, and the same reference numerals and symbols may be used to refer to the same or similar components, even if these components are shown in different drawings. Furthermore, in the following description of examples or embodiments of this disclosure, detailed descriptions will be omitted where it is determined that descriptions of well-known functions and components incorporated herein may make the subject matter of some embodiments of this disclosure considerably unclear. Terms such as “comprising,” “having,” “containing,” “constituting,” “composed of,” and “formed from” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” As used herein, singular forms are intended to include plural forms unless the context clearly indicates otherwise.

[0037] In this document, terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used to describe elements of this disclosure. Each of these terms is not used to define the nature, order, sequence, or number of elements, but only to distinguish the corresponding element from other elements.

[0038] When referring to a first element being "connected or coupled to" a second element, or "in contact with or overlapping" the second element, it should be understood that the first element can not only be "directly connected or coupled to" the second element or "directly in contact with or overlapping" the second element, but a third element can also be "inserted" between the first and second elements, or the first and second elements can be "connected or coupled," "in contact with or overlapping," etc., via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or coupled," "in contact with or overlapping," etc., to each other.

[0039] When using time-relative terms such as “after,” “following,” “next,” “before,” etc., to describe a process or operation of an element or configuration, or a flow or step in an operating method, processing method, or manufacturing method, these terms may be used to describe discontinuous or non-sequential processes or operations unless used with the terms “directly” or “immediately after.”

[0040] Furthermore, when referring to any size, relative dimensions, etc., even without a specific description, the numerical values ​​or corresponding information of the component or feature (e.g., level, range, etc.) should be considered, including tolerances or error ranges that can be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). Additionally, the term "can" fully encompasses all the meanings of the term "able to".

[0041] Various embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0042] Figure 1 This is a schematic diagram illustrating the configuration of a display device according to an embodiment of the present disclosure.

[0043] Reference Figure 1 The display device 100 according to embodiments of the present disclosure may include: a display panel 110 connected to a plurality of gating lines GL and a plurality of data lines DL, wherein a plurality of sub-pixels SP are arranged in a matrix in the display panel; a gating drive circuit 120 that provides scanning signals to the plurality of gating lines GL; a data drive circuit 130 that supplies data voltage through the plurality of data lines DL; and a timing controller 140 for controlling the gating drive circuit 120 and the data drive circuit 130.

[0044] The display panel 110 displays images based on scan signals sent from the gating drive circuit 120 through multiple gating lines GL and data voltages sent from the data drive circuit 130 through multiple data lines DL.

[0045] In the case of a liquid crystal display device, the display panel 110 includes a liquid crystal layer formed between two substrates and can operate in any known mode such as twisted nematic (TN) mode, vertical alignment (VA) mode, in-plane switching (IPS) mode, or edge field switching (FFS) mode. Furthermore, in the case of an organic light-emitting display device, the display panel 110 can be implemented using a top-emitting method, a bottom-emitting method, or a dual-emitting method.

[0046] In the display panel 110, multiple pixels can be arranged in a matrix. Each pixel can be formed by sub-pixels SP with different colors (e.g., white sub-pixels, red sub-pixels, green sub-pixels, and blue sub-pixels), and each sub-pixel SP can be defined by multiple data lines DL and multiple gate lines GL.

[0047] A sub-pixel SP may include a thin-film transistor (TFT), a light-emitting element that emits light according to a data voltage, and a storage capacitor electrically connected to the light-emitting element to maintain the voltage. The TFT, the light-emitting element, and the storage capacitor are disposed in an area formed by a data line DL and a gate line GL.

[0048] For example, when a display device 100 with a resolution of 2,160 × 3,840 is formed by four sub-pixels SP including white (W) sub-pixels, red (R) sub-pixels, green (G) sub-pixels and blue (B) sub-pixels, a total of 3,840 × 4 = 15,360 data lines DL can be provided because there are 2,160 gating lines GL and 3,840 data lines DL connected to the four sub-pixels (WRGB), and the sub-pixels SP can be set in the area formed by the gating lines GL and the data lines DL.

[0049] The gating drive circuit 120 is controlled by the timing controller 140, and sequentially outputs the scan signal to multiple gating lines GL set in the display panel 110 to control the driving timing of multiple sub-pixels SP.

[0050] In the display device 100 with a resolution of 2,160 × 3,840, the case where the scan signal is output sequentially from the first gate line to the second,160th gate line relative to the 2,160 gate lines GL can be referred to as 2,160-phase drive. Alternatively, when the scan signal is output sequentially from the first gate line to the fourth gate line, and then sequentially from the fifth gate line to the eighth gate line, the case where the scan signal is output sequentially based on four gate lines GL can be referred to as four-phase drive. In other words, the case where the scan signal is output sequentially for every N gate lines GL can be referred to as N-phase drive.

[0051] In this configuration, the gating drive circuit 120 may include one or more gating drive integrated circuits (GDICs), and depending on the driving method, the gating drive circuit 120 may be located on only one side or both sides of the display panel 110. Alternatively, the gating drive circuit 120 may be formed directly in the bezel area of ​​the display panel 110 to implement a gating-in-panel (GIP) configuration.

[0052] The data driving circuit 130 receives digital image data DATA from the timing controller 140 and converts the received digital image data DATA into an analog data voltage. Next, according to the timing when a scan signal is applied through the gate line GL, the data voltage is output to each data line DL, and thus each sub-pixel SP connected to the data line DL displays a light emission signal with a brightness corresponding to the data voltage.

[0053] Similarly, the data driving circuit 130 may include one or more source driver integrated circuits (SDICs), and the source driver integrated circuits (SDICs) may be connected to the bonding pads of the display panel 110, or may be directly disposed on the display panel 110 using the tape auto-bonding (TAB) method or the chip-on-glass (COG) method.

[0054] In some cases, each source driver integrated circuit (SDIC) can be integrated and disposed within the display panel 110. Furthermore, each source driver integrated circuit (SDIC) can be implemented using a chip-on-film (COF) method. In this case, each source driver integrated circuit (SDIC) can be mounted on a circuit film and electrically connected to the data line DL of the display panel 110 via the circuit film.

[0055] The timing controller 140 supplies various control signals to the gating drive circuit 120 and the data drive circuit 130 to control their operation. Specifically, the timing controller 140 controls the gating drive circuit 120 to output a scan signal according to the timing achieved in each frame, and on the other hand, the timing controller 140 sends digital image data (DATA) received from external components to the data drive circuit 130.

[0056] In this configuration, in addition to digital image data DATA, timing controller 140 receives various timing signals from external components (e.g., a host system), including a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a master clock MCLK. Therefore, timing controller 140 uses these various timing signals received from external components to generate control signals and sends them to gating drive circuit 120 and data drive circuit 130.

[0057] For example, to control the gating drive circuit 120, the timing controller 140 outputs various gating control signals, including a gating start pulse GSP, a gating clock GCLK, and a gating output enable signal GOE. Here, the gating start pulse GSP controls the timing of the start of operation of one or more GDICs constituting the gating drive circuit 120. Furthermore, the gating clock GCLK is a clock signal commonly input to one or more gating drive integrated circuits GDICs and controls the shift timing of the scan signal. Additionally, the gating output enable signal GOE specifies the timing information for one or more gating drive integrated circuits GDICs.

[0058] Furthermore, to control the data drive circuit 130, the timing controller 140 outputs various data control signals, including a source start pulse SSP, a source sampling clock SCLK, and a source output enable signal SOE. Here, the source start pulse SSP controls the timing of the start sampling of data by one or more SDICs constituting the data drive circuit 130. The source sampling clock SCLK is a clock signal used to control the timing of SDIC data sampling. The source output enable signal SOE controls the output timing of the data drive circuit 130.

[0059] The display device 100 may also include a power management circuit for supplying various voltages or currents to the display panel 110, the gating drive circuit 120, or the data drive circuit 130, or for controlling the various voltages or currents to be supplied.

[0060] Furthermore, light-emitting elements can be disposed in each sub-pixel SP. For example, an organic light-emitting display device may include a light-emitting element such as a light-emitting diode at each sub-pixel SP, and display an image by controlling the current flowing in the light-emitting elements according to the data voltage.

[0061] Figure 2 This is an exemplary system diagram illustrating a display device according to an embodiment of the present disclosure.

[0062] Figure 2A display device 100 according to an embodiment of the present disclosure is shown, including an SDIC in a data drive circuit 130 implemented using the COF method among various methods (TAB, COG, and COF), and a gate drive circuit 120 implemented in the GIP form among various methods (TAB, COG, COF, and GIP).

[0063] When the gate drive circuit 120 is implemented in GIP form, a plurality of gate drive integrated circuits (GDICs) included in the gate drive circuit 120 can be directly formed in the bezel area of ​​the display panel 110. In this case, the gate drive integrated circuits (GDICs) can receive various signals (clock signal, gate high signal, and gate low signal) required for generating the scan signal through the gate drive related signal lines provided in the bezel area.

[0064] Similarly, one or more source driver integrated circuits (SDICs) included in the data driver circuit 130 can each be mounted on the source film SF, and one side of the source film SF can be electrically connected to the display panel 110. Furthermore, lines for electrically connecting the source driver integrated circuits (SDICs) to the display panel 110 can be provided on the source film SF.

[0065] The display device 100 may include at least one source printed circuit board (SPCB) for connecting multiple source driver integrated circuits (SDIC) to other devices, and a control printed circuit board (CPCB) for mounting control components and various electrical devices.

[0066] In this configuration, one side of the source film SF on which the source driver integrated circuit (SDIC) is mounted can be connected to at least one source printed circuit board (SPCB). That is, one side of the source film SF on which the source driver integrated circuit (SDIC) is mounted can be electrically connected to the display panel 110, while the other side can be electrically connected to the source printed circuit board (SPCB).

[0067] The timing controller 140 and the power management circuit 150 can be mounted on the control printed circuit board (CPCB). The timing controller 140 can control the operation of the data drive circuit 130 and the gating drive circuit 120. The power management circuit 150 can supply drive voltage or current to the display panel 110, the data drive circuit 130, and the gating drive circuit 120, and control the voltage or current to be supplied.

[0068] At least one source printed circuit board (SPCB) and at least one control printed circuit board (CPCB) can be electrically connected via at least one connecting member, and the connecting member can be formed, for example, a flexible printed circuit board (FPC), a flexible flat cable (FFC), etc. Furthermore, at least one source printed circuit board (SPCB) and at least one control printed circuit board (CPCB) can be implemented as an integrated circuit board.

[0069] The display device 100 may also include a setup board 170 electrically connected to a control printed circuit board (CPCB). In this case, the setup board 170 may be referred to as a power board. A main power management circuit 160 for managing the total power supply of the display device 100 may be present in the setup board 170. The main power management circuit 160 may be interconnected with the power management circuit 150.

[0070] In the case of the display device 100 with the above configuration, a driving voltage is generated from the setting board 170 and transmitted to the power management circuit 150 on the control printed circuit board CPCB. The power management circuit 150 transmits the driving voltage required to drive the display or detect characteristic values ​​to the source printed circuit board SPCB via a flexible printed circuit FPC or a flexible flat cable FFC. The driving voltage transmitted to the source printed circuit board SPCB is supplied by the source driver integrated circuit SDIC to drive specific sub-pixels SP in the display panel 110 to emit light or sense specific sub-pixels SP.

[0071] In this case, each sub-pixel SP disposed in the display panel 110 of the display device 100 may include a light-emitting element and circuit elements such as a driving transistor for driving the light-emitting element.

[0072] The type and number of circuit elements constituting each sub-pixel SP can be determined differently depending on the provided functions and design methods.

[0073] Figure 3 This is an exemplary diagram illustrating the circuitry of a sub-pixel in a display device according to an embodiment of the present disclosure.

[0074] Reference Figure 3 In the display device 100 according to an embodiment of the present disclosure, the sub-pixel SP may include one or more transistors and capacitors, and the organic light-emitting diode (OLED) may be configured as a light-emitting element ED.

[0075] For example, a subpixel SP may include a driving transistor DRT, a switching transistor SWT, a sensing transistor SENT, a storage capacitor Cst, and a light-emitting element ED.

[0076] The driving transistor DRT has a first node N1, a second node N2, and a third node N3. The first node N1 of the driving transistor DRT can be the gate node where a data voltage Vdata is applied from the data driving circuit 130 through the data line DL when the switching transistor SWT is turned on. The second node N2 of the driving transistor DRT can be electrically connected to the anode electrode of the light-emitting element ED, and can be either a source node or a drain node. The third node N3 of the driving transistor DRT is electrically connected to the driving voltage line DVL where the driving voltage EVDD is applied, and can be either a drain node or a source node.

[0077] In this case, the driving voltage EVDD required for displaying the image can be supplied to the driving voltage line DVL during the display driving period. For example, the driving voltage EVDD required for displaying the image can be 27V.

[0078] The switching transistor SWT is electrically connected between the first node N1 of the driving transistor DRT and the data line DL, and operates according to the scan signal SCAN supplied via the gating line GL connected to the gate node. Furthermore, when the switching transistor SWT is turned on, it transmits the data voltage Vdata supplied via the data line DL to the gate node of the driving transistor DRT to control the operation of the driving transistor DRT.

[0079] The sensing transistor SENT is electrically connected between the second node N2 of the driving transistor DRT and the reference voltage line RVL. The gate line GL is connected to the gate node, and therefore the sensing transistor SENT operates according to the sensing signal SENSE supplied through the gate line GL. When the sensing transistor SENT is turned on, it transmits the sensing reference voltage Vref supplied through the reference voltage line RVL to the second node N2 of the driving transistor DRT.

[0080] In other words, by controlling the switching transistor SWT and the sensing transistor SENT, the voltage of the first node N1 and the second node N2 of the driving transistor DRT are controlled, so that current can be supplied to drive the light-emitting element ED.

[0081] The gate nodes of the switching transistor SWT and the sensing transistor SENT can be connected to a single gate line GL or to different gate lines GL. Here, an example of a structure is shown where the switching transistor SWT and the sensing transistor SENT are connected to different gate lines GL. In this case, the switching transistor SWT and the sensing transistor SENT can be independently controlled by a scan signal SCAN and a sensing signal SENSE transmitted through different gate lines GL.

[0082] On the other hand, when the switching transistor SWT and the sensing transistor SENT are connected to a gate line GL, the switching transistor SWT and the sensing transistor SENT can be simultaneously controlled by the scan signal SCAN or the sensing signal SENSE transmitted through a gate line GL, and the aperture ratio of the sub-pixel SP can be increased.

[0083] Furthermore, the transistors disposed in the sub-pixel SP can be formed from both p-type and n-type transistors. Here, an example is shown in which the transistors are formed from n-type transistors.

[0084] The storage capacitor Cst is electrically connected between the first node N1 and the second node N2 of the driving transistor DRT, and maintains the data voltage Vdata for one frame.

[0085] Depending on the type of driving transistor DRT, the storage capacitor Cst can be connected between the first node N1 and the third node N3 of the driving transistor DRT. The anode of the light-emitting element ED can be electrically connected to the second node N2 of the driving transistor DRT, and the base voltage EVSS can be applied to the cathode of the light-emitting element ED.

[0086] Here, the base voltage EVSS can be ground voltage or a voltage higher or lower than ground voltage. Furthermore, the base voltage EVSS can change depending on the driving state. For example, the base voltage EVSS can be set differently during display driving and during sensing driving.

[0087] The example above of the structure of a sub-pixel SP is a three-transistor (3T) - one-capacitor (1C) structure. This is merely an example for description, and the structure may additionally include one or more transistors, or in some cases, one or more capacitors. Alternatively, multiple sub-pixel SPs may each have the same structure, or some of the multiple sub-pixel SPs may have different structures.

[0088] In order to effectively detect the characteristic values ​​of the driving transistor DRT, such as threshold voltage or mobility, the display device 100 according to the embodiments of the present disclosure may use a method of measuring the current flowing due to the voltage charged in the storage capacitor Cst during the characteristic value sensing period of the driving transistor DRT, and this is referred to as current sensing.

[0089] In other words, by measuring the current flowing due to the voltage charged into the storage capacitor Cst during the characteristic value sensing period of the driving transistor DRT, the characteristic value or change of the characteristic value of the driving transistor DRT in the sub-pixel SP can be detected.

[0090] In this case, since the reference voltage line RVL is used not only to transmit the reference voltage Vref, but also as a sensing line for sensing the characteristic value of the driving transistor DRT in the sub-pixel SP, the reference voltage line RVL can be called a sensing line.

[0091] Figure 4 This is a diagram illustrating an exemplary circuit structure for sensing characteristic values ​​of a driving transistor in a display device according to an embodiment of the present disclosure.

[0092] Reference Figure 4 The display device 100 according to embodiments of the present disclosure may include components for compensating for deviations in the characteristic values ​​of the driving transistor DRT.

[0093] For example, the characteristic value or change in characteristic value of the driving transistor DRT can be reflected as the voltage (e.g., Vdata - Vth) of the second node N2 of the driving transistor DRT. When the sensing transistor SENT is turned on, the voltage of the second node N2 of the driving transistor DRT can correspond to the voltage of the reference voltage line RVL. Furthermore, the line capacitance Cline of the reference voltage line RVL can be charged using the voltage of the second node N2 of the driving transistor DRT, and the reference voltage line RVL can have a voltage corresponding to the voltage of the second node N2 of the driving transistor DRT due to the sensed voltage Vsen charged into the line capacitance Cline.

[0094] The display device 100 may include: an analog-to-digital converter (ADC) for measuring the voltage of a reference voltage line RVL corresponding to the voltage of the second node N2 of the driving transistor DRT, to convert the measured voltage into a digital value; and switching circuits SAM and SPRE for sensing characteristic values.

[0095] The switching circuits SAM and SPRE used to control the characteristic value sensing drive may include: a sensing reference switch SPRE, which controls the connection between the reference voltage line RVL and the sensing reference voltage supply node Npres, wherein the sensing reference voltage supply node Npres is supplied with a reference voltage Vref; and a sampling switch SAM, which controls the connection between the reference voltage line RVL and the analog-to-digital converter ADC. Here, the sensing reference switch SPRE is a switch used to control the characteristic value sensing drive, and the reference voltage Vref supplied to the reference voltage line RVL by the sensing reference switch SPRE becomes the sensing reference voltage VpreS.

[0096] Furthermore, the switching circuit for sensing the characteristic values ​​of the driving transistor DRT may include a display reference switch RPRE for controlling the display drive. The display reference switch RPRE controls the connection between the reference voltage line RVL and the display reference voltage supply node Nprer, where the display reference voltage supply node Nprer is supplied with a reference voltage Vref. The display reference switch RPRE is a switch for display driving, and the reference voltage Vref supplied by the display reference switch RPRE to the reference voltage line RVL corresponds to the display reference voltage VpreR.

[0097] In this configuration, the sensing reference switch SPRE and the display reference switch RPRE can be provided separately or integrated into a single component. The sensing reference voltage VpreS and the display reference voltage VpreR can have the same voltage value or different voltage values.

[0098] The timing controller 140 of the display device 100 may include: a memory MEM that stores data transmitted from the analog-to-digital converter (ADC) or pre-stored reference values; and a compensation circuit COMP that compensates for deviations in characteristic values ​​by comparing received data with the reference values ​​stored in the memory MEM. In this case, the compensation value calculated by the compensation circuit COMP may be stored in the memory MEM.

[0099] Therefore, the timing controller 140 can use the compensation value calculated by the compensation circuit COMP to compensate the image data DATA to be supplied to the data driving circuit 130, and output the compensated image data DATA_comp to the data driving circuit 130. Thus, the data driving circuit 130 can convert the compensated image data DATA_comp into an analog form compensated data voltage Vdata_comp via a digital-to-analog converter (DAC), and output the compensated data voltage Vdata_comp to the corresponding data line DL via an output buffer BUF. Therefore, the characteristic value deviation (threshold voltage deviation or mobility deviation) of the driving transistor DRT in the corresponding sub-pixel SP can be compensated.

[0100] As described above, the period during which the characteristic values ​​of the driving transistor DRT (such as threshold voltage and / or mobility) are sensed can occur after the power-on signal is generated and before the display driving begins. For example, when the power-on signal is applied to the display device 100, the timing controller 140 loads the parameters required to drive the display panel 110 and then executes the display driving. In this case, the parameters required to drive the display panel 110 may include information about the characteristic value sensing and compensation previously performed in the display panel 110, and the characteristic values ​​of the driving transistor DRT (such as threshold voltage and / or mobility) can be sensed during the parameter loading process. In this way, the process of sensing characteristic values ​​after the power-on signal is generated and before the sub-pixel emits light is called the on-sensing process.

[0101] Alternatively, the period during which the characteristic value of the driving transistor DRT is sensed can occur after a power-off signal is generated in the display device 100. For example, when a power-off signal is generated in the display device 100, the timing controller 140 can cut off the data voltage supplied to the display panel 110 and perform sensing of the characteristic value of the driving transistor DRT for a specific time period. In this way, the process of performing characteristic value sensing in a state where a power-off signal is generated, the data voltage is cut off, and therefore the emission of light from the sub-pixels is terminated, is called an off-sensing process.

[0102] Furthermore, the characteristic value sensing period of the driving transistor DRT can be performed in real time during display driving. This sensing process is called real-time (RT) sensing. During real-time sensing, for each blanking period of the display driving period, the sensing process can be performed for one or more sub-pixel SPs of one or more sub-pixel SP lines.

[0103] In other words, during the display driving period when an image is displayed on the display panel 110, the blanking period during which the data voltage is not supplied to the sub-pixel SP can exist within the first frame or between the nth frame and the n+1th frame, and mobility sensing of one or more sub-pixels SP can be performed during the blanking period.

[0104] In this way, when the sensing process is performed during the blanking period, the sub-pixel SP line that performs the sensing process can be randomly selected. Furthermore, after the sensing process is performed during the blanking period, the compensated data voltage Vdata_comp can be supplied to the sub-pixel SP line that performed the sensing process during the display driving period. Therefore, after the sensing process during the blanking period, anomalies in the sub-pixel SP line that completed the sensing process during the display driving period can be reduced.

[0105] Furthermore, the data drive circuit 130 may include a data voltage output circuit 136, which includes a latch circuit, a digital-to-analog converter (DAC), and an output buffer (BUF). In some cases, the data drive circuit 130 may also include an analog-to-digital converter (ADC) and various switches SAM, SPRE, and RPRE. Alternatively, the ADC and various switches SAM, SPRE, and RPRE may be located external to the data drive circuit 130.

[0106] Additionally, the compensation circuit COMP can exist outside the timing controller 140 or can be included inside the timing controller 140, and the memory MEM can be located outside the timing controller 140 or can be implemented as a register inside the timing controller 140.

[0107] Figure 5 This is a diagram illustrating a drive timing diagram for sensing a threshold voltage among the characteristic values ​​of a drive transistor in a display device according to an embodiment of the present disclosure.

[0108] Reference Figure 5 In the display device 100 according to an embodiment of the present disclosure, the threshold voltage sensing period VthSENSING may include an initialization period INITIAL, a tracking period TRACKING, and a sampling period SAMPLING.

[0109] During the initialization period (INITIAL), the switching transistor SWT is turned on by the on-level scan signal SCAN. Therefore, the first node N1 of the driving transistor DRT is initialized to the sense data voltage Vdata_sen for threshold voltage sensing.

[0110] Additionally, during the initialization period (INITIAL), the sensing transistor SENT is turned on, and the sensing reference switch SPRE is activated by the sensing signal SENSE, which has an on-state voltage. Therefore, the second node N2 of the driving transistor DRT is initialized to the sensing reference voltage VpreS.

[0111] The tracking period is the time period during which the operation of tracking the threshold voltage Vth of the driving transistor DRT is performed. That is, during the tracking period, the voltage of the second node N2 of the tracking driving transistor DRT, which reflects the threshold voltage Vth of the driving transistor DRT, is tracked.

[0112] During the tracking period, the switching transistor SWT and the sensing transistor SENT remain on, while the sensing reference switch SPRE is off. Therefore, the state of the second node N2 of the driving transistor DRT becomes floating, and the voltage at the second node N2 of the driving transistor DRT begins to rise from the sensing reference voltage VpreS.

[0113] In this situation, since the sensing transistor SENT is in the on state, the rise in voltage at the second node N2 of the driving transistor DRT causes a rise in voltage at the reference voltage line RVL.

[0114] The voltage at the second node N2 of the driving transistor DRT rises and then saturates. The saturation voltage at the second node N2 of the driving transistor DRT corresponds to the difference (Vdata_sen-Vth) between the sensed data voltage Vdata_sen used for the threshold voltage and the threshold voltage Vth of the driving transistor DRT.

[0115] Therefore, when the voltage of the second node N2 of the driving transistor DRT is saturated, the voltage of the reference voltage line RVL corresponds to the difference (Vdata_sen-Vth) between the sensing data voltage Vdata_sen used for the threshold voltage and the threshold voltage Vth of the driving transistor DRT.

[0116] When the voltage of the second node N2 of the driving transistor DRT is saturated, the sampling switch SAM is turned on, and the sampling period SAMPLING is performed.

[0117] During the sampling period, the analog-to-digital converter (ADC) can detect the sensed voltage Vsen of the reference voltage line RVL connected by the sampling switch SAM, and convert the sensed voltage Vsen into sensed data corresponding to a digital value. Here, the sensed voltage Vsen transmitted by the ADC corresponds to "Vdata_sen-Vth".

[0118] The compensation circuit COMP can determine the threshold voltage of the driving transistor DRT located in the corresponding sub-pixel SP based on the sensing data output from the analog-to-digital converter ADC, and can compensate the threshold voltage of the driving transistor DRT accordingly.

[0119] In other words, the compensation circuit COMP can determine the threshold voltage Vth of the driving transistor DRT based on the sensing data (digital data corresponding to Vdata_sen-Vth) measured through the threshold voltage sensing operation and the sensing data for the threshold voltage (digital data corresponding to Vdata_sen).

[0120] The compensation circuit COMP compensates for the threshold voltage deviation between driving transistors DRT by comparing the threshold voltage Vth determined for the corresponding driving transistor DRT with a reference threshold voltage or the threshold voltage of another driving transistor DRT. Here, threshold voltage deviation compensation can be a process of transforming the data voltage Vdata into a compensated data voltage Vdata_comp, that is, multiplying the data voltage Vdata by the compensation gain G (e.g., Vdata_comp = G * Vdata).

[0121] Therefore, as the deviation of the threshold voltage increases, the compensation gain G multiplied by the data voltage Vdata can increase.

[0122] Figure 6 This is a diagram illustrating a drive timing diagram for sensing mobility among characteristic values ​​of a drive transistor in a display device according to an embodiment of the present disclosure.

[0123] Reference Figure 6 In the display device 100 according to an embodiment of the present disclosure, similar to threshold voltage sensing operation, the mobility sensing period u SENSING of the driving transistor DRT may include an initialization period INITIAL, a tracking period TRACKING, and a sampling period SAMPLING.

[0124] Since the mobility of the driving transistor DRT is typically sensed by individually turning on or off the switching transistor SWT and the sensing transistor SENT, a sensing operation can be performed by applying the scan signal SCAN and the sensing signal SENSE separately to the switching transistor SWT and the sensing transistor SENT through two gating lines GL.

[0125] During the initialization period (INITIAL), the switching transistor SWT is turned on by the on-level scan signal SCAN, and the first node N1 of the driving transistor DRT is initialized to the sensing data voltage Vdata_sen for mobility sensing.

[0126] Additionally, the sensing transistor SENT is turned on, and the sensing reference switch SPRE is activated by the on-level sensing signal SENSE. In this state, the second node N2 of the driving transistor DRT is initialized to the sensing reference voltage VpreS.

[0127] The tracking period is the time during which the mobility of the driving transistor DRT is tracked. The mobility of the driving transistor DRT represents its current driving capability. During the tracking period, the voltage of the second node N2 of the driving transistor DRT is tracked, and the mobility of the driving transistor DRT can be calculated based on the voltage of the second node N2.

[0128] During the tracking period, the switching transistor SWT is turned off by the cutoff level scan signal SCAN, and the sensing reference switch SPRE transitions to the cutoff level. Therefore, both the first node N1 and the second node N2 of the driving transistor DRT are floating, and consequently, the voltages of both nodes N1 and N2 of the driving transistor DRT rise. Specifically, since the voltage of the second node N2 of the driving transistor DRT is initialized to the sensing reference voltage VpreS, the voltage of the second node N2 begins to rise from the sensing reference voltage VpreS. In this case, since the sensing transistor SENT is in the on state, the rise in the voltage of the second node N2 of the driving transistor DRT causes a rise in the voltage of the reference voltage line RVL.

[0129] During the sampling period, the sampling switch SAM is turned on when a predetermined time Δt has elapsed since the voltage at the second node N2 of the driving transistor DRT began to rise. In this case, the analog-to-digital converter (ADC) can detect the sensed voltage Vsen of the reference voltage line RVL connected by the sampling switch SAM and convert the sensed voltage Vsen into sensed data in the form of a digital signal. Here, the sensed voltage Vsen applied to the ADC corresponds to the voltage level VpreS+ΔV that rises from the sensed reference voltage VpreS by a predetermined voltage ΔV.

[0130] The compensation circuit COMP can determine the mobility of the driving transistor DRT in the corresponding sub-pixel SP based on the sensing data output from the analog-to-digital converter (ADC), and use the determined mobility to compensate for the deviation of the driving transistor DRT. The compensation circuit COMP can determine the mobility of the driving transistor DRT based on the sensing data VpreS+ΔV measured by the mobility sensing operation, the known sensing reference voltage VpreS, and the elapsed time Δt.

[0131] In other words, the mobility of the driving transistor DRT is proportional to the voltage change ΔV / Δt per unit time of the reference voltage line RVL during the tracking period (i.e., the slope of the voltage waveform of the reference voltage line RVL). In this case, compensation for the mobility deviation of the driving transistor DRT can be a process of changing the data voltage Vdata, that is, multiplying the data voltage Vdata by the compensation gain G using arithmetic. For example, the compensated data voltage Vdata_comp can be determined by multiplying the data voltage Vdata by the compensation gain G (Vdata_comp = G * Vdata).

[0132] Furthermore, since the threshold voltage sensing operation of the driving transistor DRT may take a long time to saturate the voltage of the second node N2 of the driving transistor DRT, the threshold voltage sensing operation can be performed as a power-off sensing process that can be performed over a longer period of time. On the other hand, since the mobility sensing operation of the driving transistor DRT may require a relatively short time compared to the threshold voltage sensing operation, the mobility sensing operation can be performed as a power-on sensing process or a real-time sensing process that is performed over a short period of time.

[0133] Furthermore, in order to reset the driving transistor DRT after performing a characteristic value sensing operation for the driving transistor DRT, the display device 100 of this disclosure can apply a recovery voltage during the blanking period.

[0134] Figure 7 This is an example of a signal timing diagram illustrating a case where a recovery period is included after the mobility sensing period of the driving transistor in the display device, according to an embodiment of the present disclosure.

[0135] Reference Figure 7 The display device 100 according to embodiments of the present disclosure may further include a recovery period after the characteristic value sensing operation of the driving transistor DRT (especially the mobility sensing period u SENSING).

[0136] Since the mobility of the driving transistor DRT is typically sensed by individually turning on or off the switching transistor SWT and the sensing transistor SENT, a sensing operation can be performed using a structure in which the scan signal SCAN and the sensing signal SENSE are applied to the switching transistor SWT and the sensing transistor SENT through two gate lines GL.

[0137] The initialization period (INITIAL), tracking period (TRACKING), and sampling period (SAMPLING) have already been described above, and therefore their descriptions will be omitted.

[0138] When the voltage at the second node N2 of the driving transistor DRT is sensed during the sampling period, the recovery period can continue. The recovery period can be performed after the mobility sensing period u for the characteristic value of the driving transistor DRT is completed and during a predetermined period before the start of display driving. In other words, the recovery period can be considered as the period after the characteristic value sensing operation of the driving transistor DRT, during which a recovery voltage REC is applied to reset the voltage applied for display driving. With the display reference switch RPRE on, the recovery voltage REC can be applied through the reference voltage line RVL.

[0139] Furthermore, the display device 100 of this disclosure can operate in a default mode in which the display device 100 operates at a fixed frequency and in a variable refresh rate (VRR) mode in which the display device 100 operates at multiple variable frequencies depending on the type of image data DATA input from an external host system.

[0140] Figure 8 This is an example diagram illustrating the concept of switching between a default mode and a VRR mode in a display device according to the type of image data, according to an embodiment of the present disclosure.

[0141] Reference Figure 8 The display device 100 according to an embodiment of the present disclosure has a default mode and a VRR mode. In the default mode, general image data such as television (TV) images are displayed at a fixed frequency. In the VRR mode, special image data such as game images or movies can be displayed at multiple variable frequencies depending on the selected function.

[0142] However, image data displayed in default mode and image data displayed in VRR mode can be changed in various ways, and the image data described in this article corresponds to some examples. Furthermore, operating modes categorized according to whether the frequency of displaying image data changes can be expressed using various terms other than default mode and VRR mode.

[0143] For example, a TV image can be displayed in a default mode driven by a fixed drive frequency of 120Hz, and special images such as game images or movies can be displayed at a first frequency (e.g., frequency A), and depending on the manipulation, they can be displayed at a variable frequency such as a second frequency (e.g., frequency B) or a third frequency (e.g., frequency C).

[0144] In summary, depending on whether the driving frequency used to display image data DATA on the display panel 110 is fixed or variable, the default mode and the variable refresh rate mode can be regarded as the first operating mode and the second operating mode, respectively.

[0145] When the external host system transmits a TV image to the display device 100, the display device 100 can operate in default mode, in which image data DATA is provided at a fixed default frequency. When providing special images such as game images or movies while providing image data DATA at a fixed default frequency in default mode, the host system can enter VRR mode and provide image data DATA while changing the drive frequency between a first frequency (frequency A), a second frequency (frequency B), and a third frequency (frequency C) according to the selected function.

[0146] Conversely, when a TV image is provided again while operating in VRR mode, the display device 100 can switch to the default mode and provide image data DATA at a fixed default frequency.

[0147] As described above, the operation modes of the display device 100 of this disclosure can be divided into a default mode and a VRR mode. In the default mode, the display device 100 operates at a fixed default frequency. In the VRR mode, the display device 100 operates at multiple variable frequencies depending on the type of image data DATA provided from the host system.

[0148] Furthermore, during the process of changing the default mode to VRR mode or changing VRR mode back to the default mode, the display device 100 of this disclosure can provide image data of a specific brightness to the display panel 110 for a certain period of time to distinguish the mode before the change from the mode after the change.

[0149] For example, when the default mode is changed to VRR mode, image data of brightness A can be applied to display panel 110 for a certain period of time. Alternatively, when VRR mode is changed to the default mode, image data of brightness B can be applied to display panel 110 for a certain period of time.

[0150] Therefore, it can be determined whether to switch between the default mode and the VRR mode by detecting the brightness of the data voltage Vdata supplied to the display panel 110 from the data driving circuit 130 or by detecting the brightness via a brightness detection camera.

[0151] Additionally, when the drive frequency changes from the first frequency to the second frequency in VRR mode, the range of the changed frequency can be determined by counting the number of horizontal synchronization signals during a frame period.

[0152] Figure 9 This is a diagram illustrating an example of a signal waveform in a VRR mode where the vertical blanking period changes according to the driving frequency in a display device according to an embodiment of the present disclosure.

[0153] Here, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the data enable signal DE provided from the host system to the display device 100 are shown.

[0154] Here, a frame can represent the time interval for outputting an image once for the entire portion of the display panel 110, and specifically, a frame includes a display drive period DP for outputting the image and a vertical blanking period Vblank for not outputting the image. Additionally, a horizontal blanking period can be included in the display drive period DP, and the horizontal blanking period can be determined by the horizontal synchronization signal Hsync.

[0155] No image output during the vertical blanking period Vblank can mean that the data enable signal DE remains low, preventing the data voltage Vdata used to generate the image during Vblank from being sent to the data line DL. In other words, a frame can be a time concept.

[0156] The first frame, second frame, and third frame indicate the order of a frame period. That is, the second frame begins after the first frame, and the third frame begins after the second frame. Each frame from the first frame to the third frame lasts for one frame period.

[0157] Here, the time periods of a single frame from the first frame to the third frame can be different from each other. Specifically, within the first frame to the third frame, the display drive time periods DP1, DP2, and DP3 can be the same, while the vertical blanking time periods Vblank1, Vblank2, and Vblank3 can be set differently.

[0158] Reference Figure 9 In the display device 100 according to an embodiment of the present disclosure, the first display driving period DP1 of the first frame, the second display driving period DP2 of the second frame, and the third display driving period DP3 of the third frame are the same.

[0159] On the other hand, the first vertical blanking period Vblank1 of the first frame, the second vertical blanking period Vblank2 of the second frame, and the third vertical blanking period Vblank3 of the third frame can be set differently.

[0160] A frame time period can be defined as the time between the fall time of the vertical synchronization signal Vsync and the fall time of the next vertical synchronization signal Vsync, and a frame time period can be set differently for each frame.

[0161] The display driving period DP can include multiple horizontal periods, and a horizontal period can include a high-level portion of the data enable signal DE for applying image data DATA and a horizontal blanking period (a low-level portion of the data enable signal DE) for not applying image data DATA. In addition, the display driving period DP can include multiple horizontal periods corresponding to the number of gating lines GL constituting the display panel 110, and includes the display driving period DP constituting a frame and the vertical blanking period Vblank.

[0162] For example, when the default frequency is set to 120Hz in the default mode, the image data DATA of one frame can be provided 120 times in one second, and one frame can have a time interval of 8.3ms.

[0163] In this case, when the display panel 110 has a resolution of 2,160×3,840, 2,160 gate lines GL can be set in the vertical direction, so that a data enable signal DE including 2,160 pulses can be applied during the display driving period DP, corresponding to the time during which the 2,160 gate lines GL are turned on in one frame.

[0164] Furthermore, although the data enable signal DE is applied in pulse form during the display drive period DP, the data enable signal DE remains low during the vertical blanking period Vblank.

[0165] On the other hand, the horizontal sync signal Hsync can be applied in pulse form not only during the display drive period (DP) but also during the vertical blanking period (Vblank). When the time interval of the vertical blanking period (Vblank) changes according to the drive frequency in VRR mode, the number of pulses of the horizontal sync signal Hsync included in a frame also changes. Therefore, the drive frequency can be determined by detecting the number of pulses of the horizontal sync signal Hsync included in a frame. For example, the drive frequency can be determined by detecting the number of pulses of the horizontal sync signal Hsync included between the fall time of the vertical sync signal Vsync and the next fall time.

[0166] In this way, because the length of the vertical blanking period Vblank varies with changes in operating mode or drive frequency, the charging time caused by the recovery voltage REC applied after the characteristic value sensing period is different for each drive frequency. Therefore, image errors due to brightness deviations occur when the operating mode or drive frequency changes.

[0167] Figure 10 This is a diagram illustrating an example of a recovery voltage applied to the display panel according to a change in driving frequency in a display device according to an embodiment of the present disclosure.

[0168] Reference Figure 10 According to an embodiment of the present disclosure, the display device 100 can select a sub-pixel SP during the vertical blanking period Vblank, sense and compensate for the mobility in the characteristic value of the driving transistor DRT, and apply a recovery voltage REC.

[0169] Here, the recovery period RECOVERY during which the recovery voltage REC is applied can occur after the mobility sensing period u SENSING of the driving transistor DRT is completed and before the start of display driving. That is, after the mobility sensing and compensation operation of the driving transistor DRT, the recovery voltage REC can be applied to reset the voltage applied for display driving operation within the vertical blanking periods Vblank1 and Vblank2.

[0170] At this time, since the lengths of the vertical blanking periods Vblank1 and Vblank2 change when the driving frequency of the display device 100 changes, the floating time intervals Tf1 and Tf2 between the time when the recovery voltage REC1 and REC2 are applied and the time when the data voltage Vdata is applied are different for each frequency.

[0171] For example, when the display device 100 operates at a drive frequency of 120Hz in the Nth frame and at a drive frequency of 40Hz in the (N+1)th frame, the level of the recovery voltage REC1 applied during the first vertical blanking period Vblank1 at 40Hz can be determined based on the previous drive frequency of 120Hz. Furthermore, the sub-pixel SP that receives the first recovery voltage REC1 during the first vertical blanking period Vblank1 between the Nth and (N+1)th frames can receive the data voltage Vdata after a floating time interval Tf1 has elapsed since the application of the first recovery voltage REC1.

[0172] However, when the driving frequency changes to 120Hz again in the (N+2)th frame, the data voltage Vdata is applied to the corresponding sub-pixel SP after the second floating time interval Tf2 from the time when the second recovery voltage REC2 is applied.

[0173] At this time, since the first floating time interval Tf1 is different from the second floating time interval Tf2 depending on the driving frequency, image errors due to brightness deviation may occur whenever the driving frequency is changed.

[0174] The display device 100 of this disclosure repeatedly applies a recovery voltage REC at regular intervals during the vertical blanking period Vblank, which minimizes the deviation of the floating time interval Tf between the time of applying the recovery voltage REC and the time of applying the data voltage Vdata, and improves image quality by reducing image errors.

[0175] Figure 11 This is a diagram illustrating the case where a recovery voltage is repeatedly applied to a vertical blanking period in a display device according to an embodiment of the present disclosure.

[0176] Reference Figure 11 According to the embodiments of the present disclosure, the display device 100 can sense and compensate the mobility in the characteristic value of the driving transistor DRT by selecting any sub-pixel SP, and then repeatedly apply recovery voltages REC1 and REC2 within the vertical blanking intervals Vblank1 and Vblank2.

[0177] Here, the recovery period RECOVERY during which recovery voltages REC1 and REC2 are repeatedly applied can correspond to a specific time interval between the completion of the mobility sensing period u SENSING of the driving transistor DRT and the time when the data voltage Vdata is applied to the corresponding sub-pixel SP. That is, after the mobility sensing and compensation operation of the driving transistor DRT, recovery voltages REC1 and REC2 can be repeatedly applied according to the reference period Prec in order to reset the voltage applied to the corresponding sub-pixel SP within the vertical blanking intervals Vblank1 and Vblank2.

[0178] At this time, recovery voltages REC1 and REC2 can be repeatedly applied to sub-pixels SP until the endpoints of vertical blanking intervals Vblank1 and Vblank2. Therefore, even if the lengths of the vertical blanking periods Vblank1 and Vblank2 change due to variations in the driving frequency of the display device 100, the floating time intervals Tf1 and Tf2 between the time when the last recovery voltage REC1 and REC2 is applied within the vertical blanking periods Vblank1 and Vblank2 and the time when the data voltage Vdata is applied can remain substantially the same.

[0179] For example, when the operation of the display device 100 changes from a drive frequency of 120Hz in the Nth frame to a drive frequency of 40Hz in the (N+1)th frame, the recovery voltage REC1 during the first vertical blanking period Vblank1 operating at 40Hz can be repeatedly applied based on the reference time period Prec. Therefore, the sub-pixel SP to which the first recovery voltage REC1 is applied during the first vertical blanking period Vblank1 between the Nth frame and the (N+1)th frame receives the data voltage Vdata after a first floating time interval Tf1 from the time the first recovery voltage REC1 was last applied.

[0180] Subsequently, when the driving frequency changes to 120Hz again in the (N+2)th frame, the corresponding sub-pixel SP can repeatedly receive the second recovery voltage REC2 during the second vertical blanking period Vblank2 based on the reference time period Prec. Therefore, the sub-pixel SP that has the second recovery voltage REC2 applied during the second vertical blanking period Vblank2 between the (N+1)th and (N+2)th frames receives the data voltage Vdata after the second floating time interval Tf2 from the time the second recovery voltage REC2 was last applied.

[0181] At this time, the last application of the first recovery voltage REC1 within the first vertical blanking period Vblank1 is close to the end time of the first vertical blanking period Vblank1. Furthermore, the last application of the second recovery voltage REC2 within the second vertical blanking period Vblank2 is close to the end time of the second vertical blanking period Vblank2.

[0182] Therefore, the first floating time interval Tf1 between the time when the first recovery voltage REC1 is last applied and the time when the data voltage Vdata is applied, and the second floating time interval Tf2 between the time when the second recovery voltage REC2 is last applied and the time when the data voltage Vdata is applied, can be kept at the same level. As a result, even if the driving frequency of the display device 100 changes, since the floating time interval Tf of each sub-pixel SP remains constant, image errors caused by brightness deviations can be minimized.

[0183] Figure 12 This is a diagram showing a reference time period in a display device according to an embodiment of the present disclosure, during which a recovery voltage is repeatedly applied to a vertical blanking period.

[0184] Reference Figure 12 In the display device 100 according to an embodiment of the present disclosure, a reference period Prec during which the recovery voltage REC is repeatedly applied during the vertical blanking period Vblank can be determined by reflecting the operating characteristics of the driving transistor DRT.

[0185] For example, in Figure 3 In the circuit of the sub-pixel SP, when the switching transistor SWT is turned on by the scan signal SCAN, the recovery voltage REC can be applied to the gate node of the driving transistor DRT.

[0186] At this time, since the driving transistor DRT is in the off state before the recovery voltage REC is applied to the driving transistor DRT, the source node voltage Vs(DRT) of the driving transistor DRT can be the level of the minimum voltage Vs(min) corresponding to the off state.

[0187] When the recovery voltage REC is applied, the gate node voltage Vg(DRT) of the driving transistor DRT represents the level of the recovery voltage REC, and the driving transistor DRT is turned on.

[0188] When the driving transistor DRT is turned on, the source node voltage Vs(DRT) of the driving transistor DRT rises and enters saturation after a certain period of time from the start of the driving transistor DRT's conduction. In this case, the period from the start of the driving transistor DRT's conduction to the point of reaching saturation can represent the characteristics of the driving transistor DRT.

[0189] Therefore, in order to uniformly reflect the characteristics of the driving transistor DRT, it is preferable to determine the reference period Prec during which the recovery voltage REC is repeatedly applied as the time interval between the time when the driving transistor DRT is turned on and the time when the driving transistor DRT enters saturation.

[0190] For the purposes described above, the reference period Prec of the recovery voltage REC can be stored in memory to reflect the characteristics of the driving transistor DRT disposed on the display panel 110, and the recovery voltage REC can be repeatedly applied during the vertical blanking period Vblank via the reference memory.

[0191] At this time, the reference period Prec for the recovery voltage REC can vary according to the level of the recovery voltage REC applied to the driving transistor DRT during the vertical blanking period Vblank. In this case, the reference period Prec corresponding to the level of the recovery voltage REC can be stored in memory in the form of a lookup table, and the time interval for repeatedly applying the recovery voltage REC can be controlled by retrieving the reference period Prec corresponding to the level of the recovery voltage REC applied during the vertical blanking period Vblank from memory.

[0192] Furthermore, the timing controller 140 of the display device 100 of this disclosure can receive a data enable signal DE supplied from an external host system, and use the received data enable signal DE to generate a source output enable signal SOE for controlling the timing of the data drive circuit 130.

[0193] During this process, a specific delay may occur between the data enable signal DE transmitted to the timing controller 140 and the source output enable signal SOE generated by the timing controller 140. Due to this delay, a deviation may occur in the floating time interval Tf between the time when the recovery voltage REC is applied and the time when the data voltage Vdata is applied.

[0194] The display device 100 of this disclosure can reduce the deviation of the floating time interval Tf between the time of applying the recovery voltage REC and the time of applying the data voltage Vdata, and improve image quality by applying the recovery voltage REC taking into account the delay time between the data enable signal DE and the source output enable signal SOE.

[0195] Figure 13 This is an exemplary block diagram of a circuit for generating a source output enable signal in a display device according to embodiments of the present disclosure, and Figure 14 This is a diagram illustrating the signal flow in a display device for generating a source output enable signal according to an embodiment of the present disclosure.

[0196] Reference Figure 13 and Figure 14 According to an embodiment of the present disclosure, the timing controller 140 of the display device 100 may include a source sampling clock generation circuit 142, a modulation circuit 144, and a source output enable signal generation circuit 146.

[0197] The modulation circuit 144 can receive a data enable signal DE from the host system and generate a modulated data enable signal DEm by modulating the received data enable signal DE. In this case, the modulation process of the data enable signal DE can be performed using the source sampling clock SCLK.

[0198] The source sampling clock SCLK can be generated from the source sampling clock generation circuit 142. For example, the source sampling clock generation circuit 142 can generate the source sampling clock SCLK by spreading the frequency of a clock with a fixed frequency according to a spread spectrum method.

[0199] The source sampling clock SCLK can be formed into various shapes, such as a time-varying triangular wave or a sine wave. Here, a triangular wave source sampling clock SCLK is shown as an example.

[0200] The source sampling clock generation circuit 142 and the modulation circuit 144 can be located inside or outside the timing controller 140. Here, it is assumed that the source sampling clock generation circuit 142 and the modulation circuit 144 are located inside the timing controller 140.

[0201] The source sampling clock SCLK generated by the source sampling clock generation circuit 142 is transmitted to the modulation circuit 144, and the modulation circuit 144 modulates the data enable signal DE by using the source sampling clock SCLK.

[0202] For example, when the source sampling clock SCLK frequency is higher than the reference frequency, the internal clock frequency is increased to advance the falling edge of the data enable signal DE. Conversely, when the source sampling clock SCLK frequency is lower than the reference frequency, the internal clock frequency is decreased to delay the falling edge of the data enable signal DE.

[0203] As described above, the modulation circuit 144 can generate a modulated data enable signal DEm by controlling the timing of the data enable signal DE according to the change in the frequency of the source sampling clock SCLK.

[0204] The modulated data enable signal DEm is transmitted to the source output enable signal generation circuit 146. The source output enable signal generation circuit 146 can generate a source output enable signal SOE that is synchronized with the falling edge of the modulated data enable signal DEm.

[0205] During this process, there is a specific delay time Dde between the source output enable signal SOE generated from the timing controller 140 and the data enable signal DE applied to the timing controller 140.

[0206] Since the delay time Dde can vary depending on the circuit structure and algorithm used to generate the source output enable signal SOE in the timing controller 140, the delay time Dde can have different values ​​depending on the structure of the display device 100 and the timing controller 140.

[0207] However, once the timing controller 140 is installed on the display device 100, the value of the delay time Dde is fixed. Therefore, the timing of the recovery voltage REC to be applied can be controlled by storing information about the delay time Dde of the data enable signal DE in memory and reflecting that information.

[0208] Figure 15 This is a diagram illustrating the signal flow in accordance with an embodiment of the present disclosure, taking into account the delay time of the data enable signal and the source output enable signal in the display device.

[0209] Reference Figure 15 According to the embodiment, the display device 100 can sense and compensate the mobility in the characteristic value of the driving transistor DRT by selecting any sub-pixel SP during the vertical blanking period Vblank, and can repeatedly apply the recovery voltage REC with a reference period Prec.

[0210] Here, the recovery period RECOVERY during which the recovery voltage REC is repeatedly applied can correspond to a specific period after the mobility sensing period u SENSING of the driving transistor DRT is completed and before the data voltage Vdata is applied to the corresponding sub-pixel SP.

[0211] At this time, the recovery voltage REC is repeatedly applied to the corresponding sub-pixel SP until it approaches the end of the vertical blanking period Vblank. Therefore, even if the length of the vertical blanking period Vblank changes due to variations in the driving frequency of the display device 100, the floating time interval Tf between the time when the recovery voltage REC is finally applied and the time when the data voltage Vdata is applied in the vertical blanking period Vblank can remain constant.

[0212] As a result, even if the driving frequency of the display device 100 changes, the image error caused by brightness deviation can be minimized because the floating time interval Tf of each sub-pixel SP remains constant.

[0213] Furthermore, the source output enable signal SOE applied from the timing controller 140 to the data drive circuit 130 may have a certain delay time Dde, depending on the internal circuitry and algorithm of the timing controller 140 used to process the data enable signal DE.

[0214] Therefore, due to the delay time Dde of the data enable signal DE, the vertical blanking period Vblank may increase. Consequently, the floating time interval Tf between the time when the recovery voltage REC is applied and the time when the data voltage Vdata is applied may vary.

[0215] However, when the recovery voltage REC is repeatedly applied according to the reference time period Prec for a period of time within the range of the delay time Dde of the data enable signal DE, the display device 100 of this disclosure may additionally apply the recovery voltage REC within the delay time Dde of the data enable signal DE.

[0216] Therefore, even with the delay time Dde of the data enable signal DE, image errors can be reduced and image quality improved by uniformly maintaining the floating time interval Tf between the time the recovery voltage REC is applied and the time the data voltage Vdata is applied.

[0217] Figure 16 This is a flowchart illustrating a display driving method according to an embodiment of the present disclosure.

[0218] Reference Figure 16The display driving method according to embodiments of the present disclosure may include: step S100 of determining a reference time period Prec for the recovery voltage REC; step S200 of displaying an image on the display panel 110; step S300 of determining a blanking time period; step S400 of compensating the characteristic value of the driving transistor DRT during the blanking time period; step S500 of repeatedly applying the recovery voltage REC at intervals of the reference time period Prec; step S600 of determining whether the time when the recovery voltage REC is applied is within the delay time Dde of the data enable signal DE; step S700 of applying the recovery voltage REC during the delay time Dde of the data enable signal DE; and step S800 of terminating the blanking time period.

[0219] Step S100, which determines the reference period Prec of the recovery voltage REC, is a process of repeatedly applying the recovery voltage REC to the gate node of the drive transistor DRT after the process of compensating the characteristic value of the drive transistor DRT is completed during the blanking period.

[0220] The reference period Prec for the recovery voltage REC can be determined as the time interval between the time when the driving transistor DRT is turned on and the time when the driving transistor DRT enters saturation. The reference period Prec for the recovery voltage REC can be stored in memory at the time of shipment of the display device 100.

[0221] Step S200, which displays an image on display panel 110, is a process of displaying an image by applying image data DATA transmitted from the host system to display panel 110 after power is applied to display device 100.

[0222] Step S300, which determines the blanking period, is the process of determining whether the period during which no image is displayed on the display panel 110 is a horizontal blanking period or a vertical blanking period.

[0223] Step S400, which compensates for the characteristic value of the driving transistor DRT during the blanking period, is a process of sensing and compensating for the threshold voltage or mobility of the driving transistor DRT during the blanking period.

[0224] The step S500, which involves repeatedly applying the recovery voltage REC at intervals equal to the reference time period Prec, is a process of repeatedly applying the recovery voltage REC at intervals equal to the reference time period Prec after the process of compensating the characteristic value of the driving transistor DRT is completed during the blanking period.

[0225] Step S600, which determines whether the time at which the recovery voltage REC is applied is within the delay time Dde of the data enable signal DE, is a process of determining whether the time at which the recovery voltage REC is repeatedly applied based on the reference time Prec corresponds to the extended blanking period caused by the delay time Dde between the data enable signal DE and the source output enable signal SOE.

[0226] Step S700, which applies the recovery voltage REC within the delay time Dde of the data enable signal DE, is a process of applying the recovery voltage REC within the delay time Dde of the data enable signal DE when the time for applying the recovery voltage REC is included within the delay time Dde of the data enable signal DE.

[0227] If the time when the recovery voltage REC is applied is not included in the delay time Dde of the data enable signal DE, the process of applying the recovery voltage REC to the corresponding blanking period can be terminated by applying the recovery voltage REC before the delay time Dde of the data enable signal DE.

[0228] Step S800, which terminates the blanking period, is the process of displaying an image on the display panel 110 after the process of terminating the application of the recovery voltage REC.

[0229] The embodiments described above in this disclosure will now be briefly described.

[0230] The display device disclosed herein may include: a display panel including multiple gate lines, multiple data lines, and multiple sub-pixels, wherein driving transistors are disposed in the multiple sub-pixels; a gate driving circuit configured to apply scan signals to the multiple gate lines; a data driving circuit configured to convert image data into data voltages and apply the data voltages to the multiple data lines; and a timing controller configured to, during a blanking period, compensate and control the characteristic values ​​of the driving transistors by using a real-time sensing process to repeatedly apply recovery voltages based on a reference period to reset the driving transistors.

[0231] The reference period can be defined as the time interval between when the driving transistor is turned on and when the driving transistor enters saturation.

[0232] The reference period can be determined as the level corresponding to the recovery voltage and stored in memory in the form of a lookup table.

[0233] The characteristic value of the driving transistor can be mobility, and the blanking period can be the vertical blanking period.

[0234] The blanking period can have a time interval that varies depending on the driving frequency.

[0235] The timing controller may include: a source sampling clock generation circuit configured to generate a source sampling clock for controlling the timing of data sampling; a modulation circuit configured to modulate a data enable signal using the source sampling clock; and a source output enable signal generation circuit configured to generate a source output enable signal synchronized with the modulated data enable signal to control the output timing of the data drive circuit.

[0236] When the source output enable signal is sent after a predetermined delay from the data enable signal, the blanking period can be extended by the delay time.

[0237] Information about the delay time can be pre-stored in memory.

[0238] The timing controller can be configured to apply the recovery voltage within the delay time when the time for applying the recovery voltage is within the delay time range.

[0239] Furthermore, the present disclosure discloses a display driving method for a display device, the display device comprising: a display panel including a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixels on which driving transistors are disposed; a gate driving circuit configured to apply scan signals to the plurality of gate lines; and a data driving circuit configured to convert image data into data voltage and apply the data voltage to the plurality of data lines. The display driving method may include the following steps: determining a reference time period for resetting the recovery voltage of the driving transistors; displaying an image on the display panel; compensating for the characteristic values ​​of the driving transistors during the blanking time period; and repeatedly applying the recovery voltage at intervals of the reference time period during the blanking time period.

[0240] The display driving method may further include: the step of generating a source sampling clock for controlling data sampling timing; the step of modulating a data enable signal received from an external source using the source sampling clock; and the step of generating a source output enable signal synchronized with the modulated data enable signal to control the output timing of the data driving circuit, wherein the source output enable signal is sent after a delay time from the time the data enable signal is applied, and the blanking period is extended by the delay time.

[0241] The display driving method may further include the step of applying a recovery voltage during the delay time when the time for applying the recovery voltage is included in the delay time.

[0242] The above description has been presented to enable any person skilled in the art to make and use the technical concepts of this disclosure, and has been provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this disclosure. The above description and drawings are provided as examples of the technical concepts of this disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concepts of this disclosure.

[0243] Cross-references to related applications

[0244] This application claims priority to Korean Patent Application No. 10-2022-0072573, filed on June 15, 2022, which is incorporated herein by reference for all purposes as if fully set forth herein.

Claims

1. A display device, the display device comprising: The display panel includes multiple gate lines, multiple data lines, and multiple sub-pixels, each of which is provided with a driving transistor; A gating drive circuit, configured to apply a scan signal to the plurality of gating lines; A data driving circuit configured to convert image data into a data voltage and apply the data voltage to the plurality of data lines; as well as A timing controller is configured to compensate for and control the characteristic values ​​of the driving transistor during a blanking period by using a real-time sensing process to repeatedly apply a recovery voltage for resetting the driving transistor based on a reference period, the blanking period having a time interval that varies according to the driving frequency in the display device. The reference time period corresponds to the interval at which the recovery voltage is repeatedly applied.

2. The display device according to claim 1, wherein, The reference period is defined as the time interval between the time the driving transistor is turned on and the time the driving transistor enters saturation.

3. The display device according to claim 2, wherein, The reference time period is determined to be the level corresponding to the recovery voltage and stored in memory in the form of a lookup table.

4. The display device according to claim 1, wherein, The characteristic value of the driving transistor is mobility, and the blanking period is a vertical blanking period.

5. The display device according to claim 1, wherein, The timing controller includes: A source sampling clock generation circuit is configured to generate a source sampling clock for controlling the timing of data sampling. A modulation circuit, configured to modulate a data enable signal using the source sampling clock; and A source output enable signal generation circuit is configured to generate a source output enable signal synchronized with a modulated data enable signal to control the output timing of the data drive circuit.

6. The display device according to claim 5, wherein, When the source output enable signal is sent after a predetermined delay from the data enable signal, the blanking period is extended by the delay time.

7. The display device according to claim 6, wherein, The delay time information is pre-stored in memory.

8. The display device according to claim 6, wherein, The timing controller is configured to apply the recovery voltage within the delay time when the time at which the recovery voltage is applied is within the range of the delay time.

9. A display driving method for a display device, the display device comprising: The display panel includes multiple gate lines, multiple data lines, and multiple sub-pixels in each of the gate lines, each of which is provided with a driving transistor. A gating drive circuit, configured to apply a scan signal to the plurality of gating lines; The display driving method includes the following steps: and a data driving circuit configured to convert image data into a data voltage and apply the data voltage to the plurality of data lines. Determine a reference time period for resetting the recovery voltage of the drive transistor; The image is displayed on the display panel; The characteristic values ​​of the driving transistor are compensated during the blanking period; and The recovery voltage is repeatedly applied at intervals specified in the reference time period during the blanking period. The blanking period has a time interval that varies according to the driving frequency in the display device, and The reference time period corresponds to the interval at which the recovery voltage is repeatedly applied.

10. The display driving method according to claim 9, wherein, The reference period is defined as the time interval between the time when the driving transistor is turned on and the time when the driving transistor enters saturation.

11. The display driving method according to claim 10, wherein, The reference time period is determined to be the level corresponding to the recovery voltage and stored in memory in the form of a lookup table.

12. The display driving method according to claim 9, further comprising the following steps: Generate a source sampling clock for controlling the timing of data sampling; The data enable signal received from the outside is modulated by using the source sampling clock; as well as A source output enable signal synchronized with the modulated data enable signal is generated to control the output timing of the data drive circuit. The source output enable signal is sent after a delay from the time the data enable signal is applied, and the blanking period is extended by the delay time.

13. The display driving method according to claim 12, further comprising the following steps: Determine whether the time at which the recovery voltage is applied is within the delay time of the data enable signal.

14. The display driving method according to claim 13, further comprising the following steps: The recovery voltage is applied during the delay time when the time for applying the recovery voltage is included in the delay time.

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