A phase adjustment circuit, a delay-locked circuit, and a memory

Abstract

This disclosure provides a phase adjustment circuit, a delay-locked circuit, and a memory. The phase adjustment circuit includes a detection module, a comparison module, a counting module, and an adjustment module connected in sequence. The detection module is configured to detect the phase difference between a first clock signal and a second clock signal to obtain a first detection signal and a second detection signal. The comparison module is configured to perform duty cycle comparison processing on the first and second detection signals to obtain a counting indication signal. The counting module is configured to count the number of pulses of a preset counting clock signal based on the counting indication signal to obtain a count value. The adjustment module is configured to adjust the phase of the second clock signal according to the count value so that the phase difference between the first and second clock signals is a preset value. Thus, by detecting the phase difference between different clock signals and correcting the clock signals, the phase offset of the clock signals can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor memory technology, and more particularly to a phase adjustment circuit, a delay lock circuit, and a memory. Background Technology

[0002] In the delay loop (DLL) of Dynamic Random Access Memory (DRAM), there are four clock paths with phases differing by 90 degrees. However, these four clock paths may cause mismatch and noise problems due to phase offset, thus affecting the performance of the memory. Summary of the Invention

[0003] This disclosure provides a phase adjustment circuit, a delay lock circuit, and a memory that can improve the phase offset of clock signals by detecting the phase difference between different clock signals and correcting the clock signals.

[0004] The technical solution disclosed herein is implemented as follows:

[0005] In a first aspect, embodiments of this disclosure provide a phase adjustment circuit, the phase adjustment circuit comprising a detection module, a comparison module, a counting module, and an adjustment module connected in sequence; wherein...

[0006] The detection module is configured to detect the phase difference between the first clock signal and the second clock signal to obtain a first detection signal and a second detection signal.

[0007] The comparison module is configured to perform a duty cycle comparison process on the first detection signal and the second detection signal to obtain a counting indication signal;

[0008] The counting module is configured to count the number of pulses of a preset counting clock signal based on the counting indication signal to obtain a count value;

[0009] The adjustment module is configured to adjust the phase of the second clock signal according to the count value, so that the phase difference between the first clock signal and the second clock signal is a preset value.

[0010] In some embodiments, the detection module is specifically configured to receive any three of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal, and output the first detection signal and the second detection signal based on the received signals; wherein the third clock signal has a phase difference of 180 degrees with the first clock signal, the fourth clock signal has a phase difference of 180 degrees with the second clock signal, the first detection signal indicates the phase difference between the rising edge of the first clock signal and the rising edge of the second clock signal, and the second detection signal indicates the phase difference between the rising edge of the second clock signal and the falling edge of the first clock signal.

[0011] In some embodiments, the adjustment module is further configured to perform phase adjustment on the fourth clock signal according to the count value, so that the phase difference between the third clock signal and the fourth clock signal is a preset value.

[0012] In some embodiments, the detection module includes a first detection unit and a second detection unit; wherein, the first detection unit is configured to receive a first clock signal and a second clock signal, and perform logical operations on the first clock signal and the second clock signal to obtain a first detection signal; the second detection unit is configured to receive a third clock signal and the second clock signal, and perform logical operations on the third clock signal and the second clock signal to obtain a second detection signal.

[0013] In some embodiments, the first detection unit includes a first inverter, a first transmission gate, and a first NAND gate; the second detection unit includes a second inverter, a second transmission gate, and a second NAND gate; the input terminal of the first inverter receives the second clock signal, the input terminal of the first transmission gate receives the first clock signal, the two input terminals of the first NAND gate are respectively connected to the output terminal of the first inverter and the output terminal of the first transmission gate, and the output terminal of the first NAND gate outputs the first detection signal; the input terminal of the second inverter receives the third clock signal, the input terminal of the second transmission gate receives the second clock signal, the two input terminals of the second NAND gate are respectively connected to the output terminal of the second inverter and the output terminal of the second transmission gate, and the output terminal of the second NAND gate outputs the second detection signal.

[0014] In some embodiments, the phase adjustment circuit is applied to a memory, and the comparison module includes a duty cycle unit, a preprocessing unit, and a sampling unit; wherein, the duty cycle unit is configured to receive the first detection signal and the second detection signal, and perform duty cycle comparison processing on the first detection signal and the second detection signal to obtain a comparison result signal; wherein, when the duty cycle of the first detection signal is higher than that of the second detection signal, the comparison result signal is in a first level state; when the duty cycle of the first detection signal is lower than that of the second detection signal, the comparison result signal is in a second level state; the preprocessing unit is configured to receive the main clock signal of the memory, and perform frequency division processing on the main clock signal to obtain a sampling clock signal; the sampling unit is configured to receive the sampling clock signal and the comparison result signal, and sample the comparison result signal based on the sampling clock signal to obtain the counting indication signal.

[0015] In some embodiments, the duty cycle unit includes a first switch, a second switch, a third switch, a fourth switch, a first current source, a second current source, a third current source, a fourth current source, a first capacitor, a second capacitor, and an operational amplifier; wherein, the control terminal of the first switch and the control terminal of the second switch form a connection point for receiving the first detection signal; the first terminal of the first switch is connected to the output terminal of the first current source, the input terminal of the first current source is connected to a power supply signal, the second terminal of the second switch is connected to the input terminal of the second current source, and the output terminal of the second current source is connected to a ground signal; the second terminal of the first switch and the first terminal of the second switch are both connected to the first terminal of the first capacitor, and the second terminal of the first capacitor is connected to a ground signal. The control terminals of the third and fourth switching transistors form a connection point for receiving the second detection signal. The first terminal of the third switching transistor is connected to the output terminal of the third current source, and the input terminal of the third current source is connected to a power supply signal. The second terminal of the fourth switching transistor is connected to the input terminal of the fourth current source, and the output terminal of the fourth current source is connected to a ground signal. The second terminal of the third switching transistor and the first terminal of the fourth switching transistor are both connected to the first terminal of the second capacitor, and the second terminal of the second capacitor is connected to a ground signal. The first terminal of the first capacitor is also connected to the inverting input terminal of the operational amplifier, and the first terminal of the second capacitor is also connected to the non-inverting input terminal of the operational amplifier. The output terminal of the operational amplifier is used to output the comparison result signal.

[0016] In some embodiments, the preprocessing unit is further configured to delay the sampling clock signal to obtain the preset counting clock signal; the counting module is specifically configured to increment the count value by one for each pulse of the preset counting clock signal detected when the counting indication signal is in a first level state; or, decrement the count value by one for each pulse of the preset counting clock signal detected when the counting indication signal is in a second level state.

[0017] In some embodiments, the adjustment module includes a first adjustment module and a second adjustment module; wherein, the first adjustment module is configured to receive a preset fixed value and a first original clock signal, and perform transmission processing on the first original clock signal based on the preset fixed value to obtain the first clock signal; the second adjustment module is configured to receive the count value and the second original clock signal, and perform transmission processing on the second original clock signal based on the count value to obtain the second clock signal; wherein, when the count value is greater than the preset fixed value, the rising edge of the second clock signal moves in a first direction relative to the rising edge of the first clock signal; when the count value is less than the preset fixed value, the rising edge of the second clock signal moves in a second direction relative to the rising edge of the first clock signal.

[0018] In some embodiments, the adjustment module further includes a third adjustment module and a fourth adjustment module; wherein, the third adjustment module is configured to receive the preset fixed value and a third original clock signal, and perform transmission processing on the third original clock signal based on the preset fixed value to obtain a third clock signal; the phase difference between the third original clock signal and the first original clock signal is 180 degrees; the fourth adjustment module is configured to receive the count value and the fourth original clock signal, and perform transmission processing on the fourth original clock signal based on the count value to obtain a fourth clock signal; the phase difference between the fourth original clock signal and the second original clock signal is 180 degrees; wherein, when the count value is greater than the preset fixed value, the rising edge of the fourth clock signal moves in a first direction relative to the rising edge of the third clock signal; when the count value is less than the preset fixed value, the rising edge of the fourth clock signal moves in a second direction relative to the rising edge of the third clock signal.

[0019] In some embodiments, any one of the first adjustment module, the second adjustment module, the third adjustment module, and the fourth adjustment module includes a preset number of adjustment units, wherein the preset number is an even number; each adjustment unit includes a plurality of inverting units, configured to determine whether each inverting unit is turned on based on either a preset fixed value or a corresponding count value; and to use the turned-on inverting units to perform inversion transmission processing on a corresponding one of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal; wherein at least one inverting unit in each adjustment unit is turned on; the control terminals of the plurality of inverting units together form the control terminal of the adjustment unit, and the control terminal of one inverting unit is used to receive one bit of the count value or one bit of the fixed value; the input terminals of the plurality of inverting units together form the input terminal of the adjustment unit, and the output terminals of the plurality of inverting units together form the output terminal of the adjustment unit.

[0020] In some embodiments, the number of digits in the preset fixed value is the same as the number of digits in the count value, both being n; the adjustment unit includes (n+1) inverting units, and the first inverting unit is fixedly in the on state; if the adjustment unit belongs to the first adjustment module or the third adjustment module, whether the (i+1)th inverting unit is on depends on the i-th digit of the preset fixed value; if the adjustment unit belongs to the second adjustment module or the fourth adjustment module, whether the (i+1)th inverting unit is on depends on the i-th digit of the count value; where n is a positive integer, i is a positive integer, and i is less than or equal to n.

[0021] In some embodiments, each of the inverting units includes a fifth switch, a sixth switch, a seventh switch, and an eighth switch; the first terminal of the fifth switch is connected to a power supply signal, the second terminal of the fifth switch is connected to the first terminal of the sixth switch, the second terminal of the seventh switch is connected to the first terminal of the eighth switch, and the second terminal of the eighth switch is connected to a ground signal; in the first inverting unit, the control terminal of the sixth switch is connected to a ground signal, and the control terminal of the seventh switch is connected to a power supply signal, so that the first inverting unit is fixed in the ON state; in the (i+1)th inverting unit... In the phase unit, the control terminal of the sixth switch is connected to the i-th control signal, the control terminal of the seventh switch is connected to the inverted signal of the i-th control signal, and the level state of the i-th control signal depends on the i-th bit of either the count value or the preset fixed value, so that whether the (i+1)-th inverting unit is turned on depends on the i-th bit of either the count value or the preset fixed value; the control terminal of the fifth switch and the control terminal of the eighth switch together form the input terminal of the inverting unit, and the second terminal of the sixth switch and the first terminal of the seventh switch together form the output terminal of the inverting unit.

[0022] In some embodiments, the preset value is 90 degrees, the first level state is a high level state, and the second level state is a low level state; the first, third, fifth, and sixth switching transistors are all P-type channel field-effect transistors, and the second, fourth, seventh, and eighth switching transistors are all N-type channel field-effect transistors; the control terminal of the P-type channel field-effect transistor is the gate, the first terminal of the P-type channel field-effect transistor is the source, and the second terminal of the P-type channel field-effect transistor is the drain; the control terminal of the N-type channel field-effect transistor is the gate, the first terminal of the N-type channel field-effect transistor is the drain, and the second terminal of the N-type channel field-effect transistor is the source.

[0023] Secondly, embodiments of this disclosure provide a delay-locked circuit for outputting a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal; the delay-locked circuit includes at least the phase adjustment circuit described in the first aspect; wherein the delay-locked circuit is configured to correct the phase difference between the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal through the phase adjustment circuit, so that the phases of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are sequentially 90 degrees apart.

[0024] Thirdly, embodiments of this disclosure provide a memory that includes at least the delay-locking circuit described in the second aspect.

[0025] This disclosure provides a phase adjustment circuit, a delay-locked circuit, and a memory. The phase adjustment circuit includes a detection module, a comparison module, a counting module, and an adjustment module connected in sequence. The detection module is configured to detect the phase difference between a first clock signal and a second clock signal to obtain a first detection signal and a second detection signal. The comparison module is configured to perform duty cycle comparison processing on the first and second detection signals to obtain a counting indication signal. The counting module is configured to count the number of pulses of a preset counting clock signal based on the counting indication signal to obtain a count value. The adjustment module is configured to adjust the phase of the second clock signal according to the count value so that the phase difference between the first and second clock signals is a preset value. Thus, by detecting the phase difference between different clock signals and correcting the clock signals, the phase offset of the clock signals can be improved. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the structure of a phase adjustment circuit provided in an embodiment of the present disclosure;

[0027] Figure 2 A partial structural diagram of a phase adjustment circuit provided in this embodiment of the present disclosure. Figure 1 ;

[0028] Figure 3 A signal timing diagram provided in an embodiment of this disclosure;

[0029] Figure 4 A partial structural diagram of a phase adjustment circuit provided in this embodiment of the present disclosure. Figure 2 ;

[0030] Figure 5 This is another signal timing diagram provided in an embodiment of the present disclosure;

[0031] Figure 6 A partial structural diagram of a phase adjustment circuit provided in this embodiment of the present disclosure. Figure 3 ;

[0032] Figure 7 A partial structural diagram of a phase adjustment circuit provided in this embodiment of the present disclosure. Figure 4 ;

[0033] Figure 8 A partial structural diagram of a phase adjustment circuit provided in this embodiment of the present disclosure. Figure 5 ;

[0034] Figure 9 A partial structural diagram of a phase adjustment circuit provided in this embodiment of the present disclosure. Figure 6 ;

[0035] Figure 10This is yet another signal timing diagram provided in an embodiment of the present disclosure;

[0036] Figure 11 This is a schematic diagram of a delay-locking circuit provided in an embodiment of the present disclosure;

[0037] Figure 12 A schematic diagram of a delay-locking circuit provided in an embodiment of this disclosure;

[0038] Figure 13 This is a schematic diagram of the structure of a memory provided in an embodiment of the present disclosure. Detailed Implementation

[0039] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely for explaining the relevant applications and are not intended to limit the applications. Furthermore, it should be noted that, for ease of description, only the parts relevant to the relevant applications are shown in the accompanying drawings.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0041] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0042] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific order of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0043] In a memory's delay-locked loop (LDL) system, there are four main clock paths. Theoretically, these four clock paths should be sequentially 90 degrees out of phase to facilitate subsequent sampling or data processing. However, phase shifts in the clock paths can occur, leading to mismatch and noise issues that negatively impact memory performance.

[0044] Based on this, embodiments of this disclosure provide a phase adjustment circuit, comprising a detection module configured to detect the phase difference between a first clock signal and a second clock signal to obtain a first detection signal and a second detection signal; a comparison module configured to perform duty cycle comparison processing on the first detection signal and the second detection signal to obtain a counting indication signal; a counting module configured to count the number of pulses of a preset counting clock signal based on the counting indication signal to obtain a count value; and an adjustment module configured to adjust the phase of the second clock signal according to the count value so that the phase difference between the first clock signal and the second clock signal is a preset value. Thus, by detecting the phase difference between different clock signals and correcting the clock signal, the phase offset of the clock signal can be improved.

[0045] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0046] In one embodiment of this disclosure, see Figure 1 This illustrates a schematic diagram of the structure of a phase adjustment circuit 10 provided in an embodiment of this disclosure. Figure 1 As shown, the phase adjustment circuit 10 includes a detection module 11, a comparison module 12, a counting module 13, and an adjustment module 14 connected in sequence; wherein,

[0047] The detection module 11 is configured to detect the phase difference between the first clock signal and the second clock signal to obtain a first detection signal and a second detection signal;

[0048] Comparison module 12 is configured to perform duty cycle comparison processing on the first detection signal and the second detection signal to obtain a counting indication signal;

[0049] The counting module 13 is configured to count the number of pulses of a preset counting clock signal based on a counting indication signal to obtain a count value;

[0050] The adjustment module 14 is configured to adjust the phase of the second clock signal according to the count value so that the phase difference between the first clock signal and the second clock signal is a preset value.

[0051] It should be noted that the phase adjustment circuit 10 of this embodiment can be applied to a memory, such as DRAM or Synchronous Dynamic Random Access Memory (SDRAM), to adjust the phase difference between different clock signals.

[0052] It should be understood that a preset value can be a preset range of allowable error. In memory, the preset value is generally 90 degrees, that is, the phase difference between the first clock signal and the second clock signal is the preset value. This can mean that the phase difference between the second clock signal and the first clock signal after a 90-degree delay is within the allowable error range. When referring to the phase difference of different signals thereafter, it will always refer to being within the allowable error range.

[0053] In this way, when there is a phase shift in the second clock signal, the phase adjustment circuit 10 can adjust the phase of the second clock signal, thereby ensuring that the phase of the second clock signal is delayed by 90 degrees compared with the phase of the first clock signal within the allowable error range, thus improving the accuracy of the clock signal.

[0054] In practical applications, the memory may also involve a third clock signal and a fourth clock signal. The phase difference between the third clock signal and the first clock signal is 180 degrees, and the phase difference between the fourth clock signal and the third clock signal is 180 degrees.

[0055] In some embodiments, the adjustment module 14 is further configured to perform phase adjustment on the fourth clock signal based on the count value, so that the phase difference between the third clock signal and the fourth clock signal is a preset value.

[0056] It should be understood that since the third clock signal and the first clock signal are a pair of inverted signals, the third clock signal can be considered to be fixedly 180 degrees behind the first clock signal, so there is no need to adjust the phase of the third clock signal; similarly, the fourth clock signal can be considered to be fixedly 180 degrees behind the second clock signal, so the fourth clock signal and the second clock signal can be synchronized. Therefore, the fourth clock signal is also phase-adjusted based on the aforementioned count value.

[0057] In this way, the phase adjustment circuit 10 can adjust the phase of a set of four-phase clock signals to eliminate the phase offset between clock signals, thereby ensuring that the phase difference between the first clock signal, the second clock signal, the third clock signal and the fourth clock signal is 90 degrees in sequence within the allowable error range, improving mismatch and noise problems, and improving memory performance.

[0058] In addition, once the phase difference between the first clock signal, the second clock signal (and the third clock signal and the fourth clock signal) is detected to be in accordance with expectations, the count value can be latched to maintain this state.

[0059] It should be noted that the first detection signal is used to indicate the phase difference between the rising edge of the first clock signal and the rising edge of the second clock signal, and the second detection signal is used to indicate the phase difference between the rising edge of the second clock signal and the falling edge of the first clock signal. Specifically, in some embodiments, the detection module 11 is specifically configured to receive any three of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal, and output the first detection signal and the second detection signal based on the received signals.

[0060] The following assumes that the detection module 11 receives a first clock signal CLKOI, a second clock signal CLKOQ, and a third clock signal CLKOIB, and provides a specific structure for the detection module 11. For example... Figure 2 As shown, the detection module 11 may include a first detection unit 111 and a second detection unit 112; wherein,

[0061] The first detection unit 111 is configured to receive a first clock signal CLKOI and a second clock signal CLKOQ, and perform logical operations on the first clock signal CLKOI and the second clock signal CLKOQ to obtain a first detection signal Detection_clkoi_q.

[0062] The second detection unit 112 is configured to receive the third clock signal CLKOIB and the second clock signal CLKOQ, perform logical operations on the third clock signal CLKOIB and the second clock signal CLKOQ to obtain the second detection signal Detection_clkoi_ib.

[0063] In some embodiments, the first detection unit 111 may include a first inverter 201, a first transmission gate 202, and a first NAND gate 203; the second detection unit 112 may include a second inverter 204, a second transmission gate 205, and a second NAND gate 206. The input terminal of the first inverter 201 receives a second clock signal CLKOQ, the input terminal of the first transmission gate 202 receives a first clock signal CLKOI, the two input terminals of the first NAND gate 203 are respectively connected to the output terminals of the first inverter 201 and the first transmission gate 202, and the output terminal of the first NAND gate 203 outputs a first detection signal Detection_clkoi_q. The input terminal of the second inverter 204 receives a third clock signal CLKOIB, the input terminal of the second transmission gate 205 receives the second clock signal CLKOQ, the two input terminals of the second NAND gate 206 are respectively connected to the output terminals of the second inverter 204 and the second transmission gate 205, and the output terminal of the second NAND gate 206 outputs a second detection signal Detection_clkoi_ib.

[0064] It should be noted that both the first inverter 201 and the second inverter 204 can employ conventional inverter structures. For example, the inverter can be composed of an N-channel field-effect transistor (NMOS) and a P-channel field-effect transistor (PMOS). The gates of the NMOS and PMOS are connected to form the input terminal of the inverter. The drain of the NMOS receives the power supply signal VDD, the drain of the PMOS receives the ground signal VSS, and the sources of the NMOS and PMOS are connected to form the output terminal of the inverter.

[0065] It should be understood that in the first detection unit 111, the second clock signal CLKOQ not only undergoes a phase flip when passing through the first inverter 201, but also experiences a certain delay. Therefore, the first transmission gate 202 causes the first clock signal CLKOI to have the same delay, so that the first NAND gate 203 can synchronously perform NAND processing on the inverted signal of the second clock signal CLKOQ and the first clock signal CLKOI to obtain the first detection signal Detection_clkoi_q. The function of the second transmission gate 205 can be understood with reference to this.

[0066] Both the second transmission gate 205 and the second transmission gate 205 can adopt conventional transmission gate structures. For example... Figure 2 As shown, the transmission gate can be composed of an NMOS and a PMOS. The gate of the NMOS is connected to the power supply signal VDD, and the gate of the PMOS is connected to the ground signal VSS, meaning that the NMOS and PMOS are in the ON state. The drains of the NMOS and PMOS are connected to form the input terminal of the transmission gate, and the sources of the NMOS and PMOS are connected to form the output terminal of the transmission gate.

[0067] It should be noted that, in Figure 2 On this basis, Figure 3 A signal timing diagram according to an embodiment of this disclosure is shown. Figure 3 As shown, the first detection signal Detection_clkoi_q is low during the period between the rising edge of the first clock signal CLKOI and the rising edge of the second clock signal CLKOQ; the second detection signal Detection_clkoi_ib is low during the period between the rising edge of the second clock signal CLKOQ and the falling edge of the first clock signal CLKOI. It should be understood that the falling edge of the first clock signal CLKOI coincides with the rising edge of the third clock signal CLKOIB.

[0068] It should be understood that Figure 2The circuit structure shown is only one specific embodiment of the detection module 11. Due to the diversity of circuit components, the detection module 11 can also adopt other circuit structures, provided that phase difference information can be obtained. For example, the detection module 11 may only include a first NAND gate and a second NAND gate. The first NAND gate performs a NAND operation on the first clock signal CLKOI and the fourth clock signal CLKOQB to obtain the first detection signal Detection_clkoi_q, and the second NAND gate performs a NAND operation on the first clock signal CLKOI and the second clock signal CLKOQ to obtain the second detection signal Detection_clkoi_ib.

[0069] In this way, by using the first detection signal Detection_clkoi_q and the second detection signal Detection_clkoi_ib, the phase difference between the first clock signal CLKOI and the second clock signal CLKOQ can be reflected, so that phase adjustment can be performed subsequently.

[0070] In some embodiments, such as Figure 4 As shown, the comparison module 12 includes a duty cycle unit 121, a preprocessing unit 122, and a sampling unit 123; wherein,

[0071] Duty cycle unit 121 is configured to receive a first detection signal Detection_clkoi_q and a second detection signal Detection_clkoi_ib, and perform duty cycle comparison processing on the first detection signal Detection_clkoi_q and the second detection signal Detection_clkoi_ib to obtain a comparison result signal DCD_Com; wherein, when the duty cycle of the first detection signal Detection_clkoi_q is higher than that of the second detection signal Detection_clkoi_ib, the comparison result signal DCD_Com is in a first level state; when the duty cycle of the first detection signal Detection_clkoi_q is lower than that of the second detection signal Detection_clkoi_ib, the comparison result signal DCD_Com is in a second level state.

[0072] Preprocessing unit 122 is configured to receive the main clock signal Main CLK from the memory, and perform frequency division processing on the main clock signal MainCLK to obtain the sampling clock signal DCD_LAT;

[0073] The sampling unit 123 is configured to receive the sampling clock signal DCD_LAT and the comparison result signal DCD_Com, and to sample the comparison result signal DCD_Com based on the sampling clock signal DCD_LAT to obtain the counting indication signal DCD_OUT.

[0074] Here, the first level state and the second level state are different, depending on the actual application scenario.

[0075] It should be noted that if the duty cycle of the first detection signal Detection_clkoi_q is higher than that of the second detection signal Detection_clkoi_ib, the phase difference between the second clock signal CLKOQ and the first clock signal CLKOI is considered to be less than 90 degrees, meaning the phase of the second clock signal CLKOQ needs to be adjusted backward. Conversely, if the duty cycle of the first detection signal Detection_clkoi_q is lower than that of the second detection signal Detection_clkoi_ib, the phase difference between the second clock signal CLKOQ and the first clock signal CLKOI is considered to be greater than 90 degrees, meaning the phase of the second clock signal CLKOQ needs to be adjusted forward. In other words, the comparison result signal DCD_Com indicates the direction of phase adjustment for the second clock signal CLKOQ.

[0076] The sampling clock signal DCD_LAT is obtained by dividing the main clock signal Main CLK. Specifically, the clock period of the sampling clock signal DCD_LAT is greater than the clock period of the main clock signal Main CLK, and the clock period of the sampling clock signal DCD_LAT is an integer multiple of the clock period of the main clock signal Main CLK. This frequency division is performed to provide sufficient response time for the sampling unit 123.

[0077] Taking the first level signal as a high level signal and the second level signal as a low level signal as an example, the specific structure of the duty cycle unit 121 is provided.

[0078] like Figure 4As shown, the duty cycle unit 121 includes a first switch 207, a second switch 208, a third switch 209, a fourth switch 210, a first current source 211, a second current source 212, a third current source 213, a fourth current source 214, a first capacitor 215, a second capacitor 216, and an operational amplifier 217. The control terminal of the first switch 207 and the control terminal of the second switch 208 form a connection point to receive the first detection signal Detection_clkoi_q. The first terminal of the first switch 207 is connected to the output terminal of the first current source 211, and the input terminal of the first current source 211 is connected to the power supply signal VDD. The second terminal of the second switch 208 is connected to the input terminal of the second current source 212, and the output terminal of the second current source 212 is connected to the ground signal VSS. The second terminal of the first switch 207 and the first terminal of the second switch 208 are both connected to the first terminal of the first capacitor 215. The second terminal is connected to the ground signal VSS; the control terminal of the third switch 209 and the control terminal of the fourth switch 210 form a connection point to receive the second detection signal Detection_clkoi_ib; the first terminal of the third switch 209 is connected to the output terminal of the third current source 213, the input terminal of the third current source 213 is connected to the power supply signal, the second terminal of the fourth switch 210 is connected to the input terminal of the fourth current source 214, and the output terminal of the fourth current source 214 is connected to the ground signal; the second terminal of the third switch 209 and the first terminal of the fourth switch 210 are both connected to the first terminal of the second capacitor 216, and the second terminal of the second capacitor 216 is connected to the ground signal VSS; the first terminal of the first capacitor 215 is also connected to the inverting input terminal of the operational amplifier 217, the first terminal of the second capacitor 216 is also connected to the non-inverting input terminal of the operational amplifier 217, and the output terminal of the operational amplifier 217 is used to output the comparison result signal DCD_Com.

[0079] like Figure 4 As shown, if the first detection signal Detection_clkoi_q is high, the first switch 207 is off and the second switch 208 is on. At this time, the first charging node Charge signal A, the second switch 208, the second current source 212, and the ground signal VSS form a current path, meaning the first charging node Charge signal A discharges to ground VSS. If the first detection signal Detection_clkoi_q is low, the first switch 207 is on and the second switch 208 is off. At this time, the power supply signal VDD, the first current source 211, the first switch 207, and the first charging node Charge signal A form a current path, meaning the first charging node Charge signal A is charged by the power supply signal VDD. The remaining parts can be understood by referring to this explanation.

[0080] Thus, if the duty cycle of the first detection signal Detection_clkoi_q is higher than the duty cycle of the second detection signal Detection_clkoi_ib, then the charging speed of the first capacitor 215 is less than the charging speed of the second capacitor 216. At this time, the voltage of the first charging node Charge signal A is less than the voltage of the second charging node Charge signal B, and the operational amplifier 217 outputs a high-level comparison result signal DCD_Com. If the duty cycle of the first detection signal Detection_clkoi_q is lower than the duty cycle of the second detection signal Detection_clkoi_ib, then the charging speed of the first capacitor 215 is greater than the charging speed of the second capacitor 216. At this time, the voltage of the first charging node Charge signal A is greater than the voltage of the second charging node Charge signal B, and the operational amplifier 217 outputs a low-level comparison result signal DCD_Com.

[0081] It should be noted that, as Figure 4 As shown, the preprocessing unit 122 may include a frequency divider 218 for dividing the main clock signal Main CLK to obtain the sampling clock signal DCD_LAT. The frequency divider 218 can refer to a conventional frequency divider circuit. In addition, the sampling unit 123 can be implemented by a D-type flip-flop (DFF).

[0082] In some embodiments, the preprocessing unit 122 is further configured to delay the sampling clock signal DCD_LAT to obtain a preset counting clock signal CLK_CNT. For example, Figure 4 As shown, the preprocessing unit 122 also includes a delay unit 219, used to delay the sampling clock signal DCD_LAT to obtain a preset counting clock signal CLK_CNT. Alternatively, the preset counting clock signal CLK_CNT can also be obtained by directly dividing the main clock signal Main_CLK.

[0083] like Figure 5 As shown, the counting module 13 is specifically configured such that when the counting indication signal DCD_OUT is in the first level state ( Figure 5 In the case of a high-level state (taking the high-level state as an example), for each pulse of the preset counting clock signal CLK_CNT detected, the count value Q is adjusted. <n:0>Increment the count by one; or, when the count indicator signal DCD_OUT is in the second level state ( Figure 5 In the case of a low-level state (taking the low-level state as an example), for each pulse of the preset counting clock signal CLK_CNT detected, the count value Q is adjusted. <n:0>The count is decremented by one. Here, the counting module 13 can adopt a conventional counter structure.

[0084] In other words, the count value Q can be determined by the count indicator signal DCD_OUT. <n:0>The direction of change. With Figures 2-5 Taking the circuit shown as an example, the count value Q <n:0>The larger the value Q, the smaller the phase difference between the first clock signal CLKOI and the second clock signal CLKOQ, indicating that the second clock signal CLKOQ needs to be adjusted backward; <n:0>The smaller the value, the larger the phase difference between the first clock signal CLKOI and the second clock signal CLKOQ. The phase of the second clock signal CLKOQ needs to be adjusted forward so that the first clock signal CLKOI and the second clock signal CLKOQ maintain a 90-degree phase difference.

[0085] In some embodiments, when the count indicator signal DCD_OUT generates a state flip (from a first level state to a second level state, or from a second level state to a first level state), it indicates that the phase difference between the first clock signal and the second clock signal (as well as the third clock signal and the fourth clock signal) has met the requirements, and the count value is latched to maintain the state of the clock signal.

[0086] In one embodiment, only the first clock signal CLKOI and the second clock signal CLKOQ are considered, such as Figure 6 As shown, the adjustment module 14 may include a first adjustment module 141 and a second adjustment module 142.

[0087] The first adjustment module 141 is configured to receive a preset fixed value P. <n:0>And the first original clock signal CLKI, based on a preset fixed value P <n:0>The first original clock signal CLKI is processed for transmission to obtain the first clock signal CLKOI;

[0088] The second adjustment module 142 is configured to receive the count value Q. <n:0>The second original clock signal CLKQ is based on the count value Q. <n:0>The second original clock signal CLKQ is processed to obtain the second clock signal CLKOQ.

[0089] Here, the first original clock signal CLKI and the first clock signal CLKOI have the same shape, but there is a certain transmission delay between them. The second original clock signal CLKQ and the second clock signal CLKOQ have the same shape, but there is a certain transmission delay between them.

[0090] It should be noted that the preset fixed value P <n:0>It should be greater than the count value Q <n:0>The minimum possible value is less than the count value Q. <n:0>The maximum value can be taken to avoid phase adjustment being possible only in a single direction.

[0091] At the count value Q <n:0>Greater than the preset fixed value P <n:0>In this case, the rising edge of the second clock signal CLKOQ moves in the first direction relative to the rising edge of the first clock signal CLKOI; at the count value Q <n:0>Less than a preset fixed value P <n:0>In this case, the rising edge of the second clock signal CLKOQ moves in a second direction relative to the rising edge of the first clock signal CLKOI. Here, the first and second directions are opposite, and the specific direction can be determined according to the actual application scenario.

[0092] In another embodiment, if we consider the first clock signal CLKOI, the second clock signal CLKOQ, the third clock signal CLKOIB, and the fourth clock signal CLKOQB, such as Figure 7 As shown, the adjustment module 14 also includes a third adjustment module 143 and a fourth adjustment module 144;

[0093] The third adjustment module 143 is configured to receive a preset fixed value P. <n:0>And the third original clock signal CLKIB, based on a preset fixed value P <n:0>The third original clock signal CLKIB is processed to obtain the third clock signal CLKOIB; the phase difference between the third original clock signal CLKIB and the first original clock signal CLKI is 180 degrees.

[0094] The fourth adjustment module 144 is configured to receive the count value Q. <n:0>And the fourth original clock signal CLKQB, based on the count value Q <n:0>The fourth original clock signal CLKQB is processed to obtain the fourth clock signal CLKOQB; the phase difference between the fourth original clock signal CLKQB and the second original clock signal CLKIB is 180 degrees.

[0095] Similarly, in the count value Q <n:0>Greater than the preset fixed value P <n:0>In this case, the rising edge of the fourth clock signal CLKOQB moves in the first direction relative to the rising edge of the third clock signal CLKOIB; at the count value Q <n:0>Less than a preset fixed value P <n:0>In this case, the rising edge of the fourth clock signal CLKOQB moves in the second direction relative to the rising edge of the third clock signal CLKOIB.

[0096] In this embodiment, the first adjustment module 141, the second adjustment module 142, the third adjustment module 143, and the fourth adjustment module 144 all adopt the same circuit structure.

[0097] For example, such as Figure 8 As shown, any one of the first adjustment module 141, the second adjustment module 142, the third adjustment module 143, and the fourth adjustment module 144 includes a preset number of adjustment units 220. Figure 8 (Only one is labeled in the text). It should be understood that in... Figure 8 In this system, the adjustment unit is implemented through an adjustable NOT gate, meaning that the output signal of each adjustment unit is phase-flipped relative to the input signal of that adjustment unit. Therefore, the preset number should be even.

[0098] The following is a specific structural example of an adjustment unit 220.

[0099] like Figure 9 As shown, in some embodiments, the adjustment unit 220 includes a plurality of inverting units ( Figure 9 (Taking four inverting units as an example), configured to operate according to a preset fixed value P <n:0>Or the count value Q <n:0>The corresponding one of the following is used to determine whether each inverting unit is turned on; and, using the turned-on inverting unit, the corresponding one of the first clock signal CLKOI, the second clock signal CLKOQ, the third clock signal CLKOIB, and the fourth clock signal CLKOQB is inverted and transmitted.

[0100] It should be noted that for the first adjustment module 141, the second adjustment module 142, the third adjustment module 143, and the fourth adjustment module 144, at least one inverting unit in each adjustment unit is turned on. For each adjustment unit, the control terminals of multiple inverting units together form the control terminal of the adjustment unit, and the control terminal of one inverting unit is used to receive one bit of the count value or one bit of the fixed value; the input terminals of multiple inverting units together form the input terminal of the adjustment unit, used to receive the input signal A; the output terminals of multiple inverting units together form the output terminal of the adjustment unit, used to determine the output signal Y.

[0101] Here, if more inverting units are turned on, the signal transmission speed of the adjustment unit 220 is faster, and the rising edge of its output signal will be adjusted forward; if fewer inverting units are turned on, the signal transmission speed of the adjustment unit 220 is slower, and the rising edge of its output signal will be adjusted backward.

[0102] It should be noted that if the adjustment unit 220 is located in the first adjustment module 141, then the input signal A is the first original clock signal CLKI, and the output signal Y refers to the first clock signal CLKOI; if the adjustment unit 220 is located in the second adjustment module 142, then the input signal A is the second original clock signal CLKQ, and the output signal Y refers to the second clock signal CLKOQ; if the adjustment unit 220 is located in the third adjustment module 143, then the input signal A is the third original clock signal CLKIB, and the output signal Y refers to the third clock signal CLKOIB; if the adjustment unit 220 is located in the fourth adjustment module 144, then the input signal A is the fourth original clock signal CLKQB, and the output signal Y refers to the fourth clock signal CLKOQB.

[0103] In some embodiments, the number of digits in the preset fixed value is the same as the number of digits in the count value, both being n; the adjustment unit includes (n+1) inverting units, and the first inverting unit is fixedly in the on state; if the adjustment unit 220 belongs to the first adjustment module 141 or the third adjustment module 143, whether the (i+1)th inverting unit is on depends on the i-th digit of the preset fixed value; if the adjustment unit 220 belongs to the second adjustment module 142 or the fourth adjustment module 144, whether the (i+1)th inverting unit is on depends on the i-th digit of the count value; where n is a positive integer, i is a positive integer, and i is less than or equal to n.

[0104] Taking n=3 as an example, the count value can be represented as Q<2:0>, with a preset fixed value of P<2:0>. For example... Figure 9 As shown, the adjustment unit 220 includes four inverting units, and the first inverting unit is always on. Specifically, (1) if the adjustment unit 220 is located in the first adjustment module 411 or the third adjustment module 413, whether the second inverting unit is on depends on P. <2> (The first bit in P<2:0>, please refer to the explanation for the others), whether the third inverting unit is turned on depends on P. <1> Whether the fourth inverting unit is turned on depends on P. <0> (2) If the adjustment unit 220 is located in the second adjustment module 412 or the fourth adjustment module 414, whether the second inverting unit is turned on depends on Q. <2> Whether the third inverting unit is turned on depends on Q. <1> Whether the fourth inverting unit is turned on depends on Q. <0> .

[0105] It should also be noted that the signal transmission capabilities of different inverting units can be the same or different, thus providing more delay range to adapt to different situations.

[0106] In some embodiments, such as Figure 9 As shown, each inverting unit ( Figure 9 (Only the devices in one inverting unit are labeled) Each inverting unit includes a fifth switch 221, a sixth switch 222, a seventh switch 223, and an eighth switch 224. The first terminal of the fifth switch 221 is connected to the power supply signal, the second terminal of the fifth switch 221 is connected to the first terminal of the sixth switch 222, the second terminal of the seventh switch 223 is connected to the first terminal of the eighth switch 224, and the second terminal of the eighth switch 224 is connected to the ground signal VSS. In the first inverting unit, the control terminal of the sixth switch 222 is connected to the ground signal VSS, and the control terminal of the seventh switch 223 is connected to the power supply signal, so that the first inverting unit is always in the ON state. In the (i+1)th inverting unit, the control terminal of the sixth switch 222 is connected to the i-th control signal (e.g., Q). <2> Q <1> Q <0> P <2> P <1> P <0> The control terminal of the seventh switch 223 is connected to the inverted signal of the i-th control signal (e.g., QB). <2> QB <1> QB <0> PB <2> PB <1> PB <0> The connection is such that the level of the i-th control signal depends on the i-th bit of either the count value or the preset fixed value, so that whether the (i+1)-th inverting unit is turned on depends on the i-th bit of either the count value or the preset fixed value; the control terminal of the fifth switch 221 and the control terminal of the eighth switch 224 together form the input terminal of the inverting unit, and the second terminal of the sixth switch 222 and the first terminal of the seventh switch 223 together form the output terminal of the inverting unit.

[0107] In one specific embodiment, a preset fixed value P<2:0> = 100 is set. For example... Figure 9 and Figure 10 As shown, in the first adjustment module 141 and the third adjustment module 143, the first inverting unit, the third inverting unit and the fourth inverting unit are fixedly turned on, and the second inverting unit is fixedly turned off. At this time, if Q<2:0>=111, it means that all the inverting units in the second adjustment module 142 and the fourth adjustment module 144 are turned off, that is, the signal transmission speed of the second adjustment module 142 and the fourth adjustment module 144 is slower. At this time, the rising edge of the second clock signal CLKOQ and the fourth clock signal CLKOQB moves backward, that is, the phase difference of CLKOQ between the first clock signal CLKOI and the second clock signal, and the phase difference between the third clock signal CLKOIB and the fourth clock signal CLKOQB increases. If Q<2:0>=000, it means that all the inverting units in the second adjustment module 142 and the fourth adjustment module 144 are turned on, that is, the signal transmission speed of the second adjustment module 142 and the fourth adjustment module 144 is faster. At this time, the rising edge of the second clock signal CLKOQ and the fourth clock signal CLKOQB moves forward, that is, the phase difference of CLKOQ between the first clock signal CLKOI and the second clock signal, and the phase difference between the third clock signal CLKOIB and the fourth clock signal CLKOQB decreases.

[0108] In the foregoing description, the first level state is a high level state, and the second level state is a low level state; the first switch 207, the third switch 209, the fifth switch 221, and the sixth switch 222 are all P-type channel field-effect transistors (FETs), and the second switch 208, the fourth switch 210, the seventh switch 223, and the eighth switch 224 are all N-type channel field-effect transistors (FETs); the control terminal of the P-type channel FET is the gate, the first terminal of the P-type channel FET is the source, and the second terminal of the P-type channel FET is the drain; the control terminal of the N-type channel FET is the gate, the first terminal of the N-type channel FET is the drain, and the second terminal of the N-type channel FET is the source. Furthermore, the actual voltage of the aforementioned power supply signal VDD depends on the specific application scenario.

[0109] besides, Figure 2 , Figure 4 , Figure 8 and Figure 9 These are all feasible examples in the embodiments of this disclosure, and not specific limitations. Other circuit structures may be used provided that the corresponding functions can be achieved.

[0110] In summary, the embodiments of this disclosure provide a phase adjustment circuit that can improve the phase offset of clock signals by detecting the phase difference between different clock signals and correcting the clock signals, thereby improving the performance of semiconductors.

[0111] In another embodiment of this disclosure, a delay-locked circuit is provided, which is used to output a first clock signal, a second clock signal, a third clock signal and a fourth clock signal.

[0112] See Figure 11 This illustrates a schematic diagram of a delay-locking circuit 30 provided in an embodiment of this disclosure. Figure 11 As shown, the delay lock circuit 30 includes at least the phase adjustment circuit 10 as described in any of the preceding claims; the delay lock circuit 30 is configured to correct the phase difference between the first clock signal, the second clock signal, the third clock signal and the fourth clock signal through the phase adjustment circuit 10, so that the phases of the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are sequentially 90 degrees apart.

[0113] It should be noted that the delay-locked circuit 30 can also be called a delay-locked loop, and is applied to memory. In this way, the phase adjustment circuit 10 can eliminate the phase deviation between different clock channels in the delay-locked circuit 30, avoid mismatch problems and noise problems, improve the accuracy of subsequent data sampling or other processing, and thus improve the performance of the memory.

[0114] Please see Figure 12 The following provides a specific structure of a delay-locking circuit 30.

[0115] like Figure 12 As shown, the delay-locked circuit 30 receives four-phase clock input signals (first original clock signal CLKI, second original clock signal CLKQ, third original clock signal CLKIB and fourth original clock signal CLKIB) and outputs four-phase clock output signals (first clock signal CLKOI, second clock signal CLKOQ, third clock signal CLKIOB and fourth clock signal CLKIOB).

[0116] The delay lock circuit 30 includes four DLL delay lines and a phase adjustment circuit 10. The four DLL delay lines are used to transmit CLKI, CLKQ, CLKIB, and CLKIB respectively. The phase adjustment circuit 10 detects and corrects the phase offset between the four-phase clock output signals (CLKOI, CLKOQ, CLKIOB, and CLKIOB) to ensure that the phases between the four-phase clock output signals (CLKOI, CLKOQ, CLKIOB, and CLKIOB) are sequentially 90 degrees.

[0117] Specifically, the phase adjustment circuit 10 includes a detection module 11, a comparison module 12, a counting module 13, and an adjustment module 14.

[0118] (1) Please refer to the above. Figure 2 and Figure 3 The detection module 11 is used to determine the phase difference information between the four-phase clock output signals. Specifically, the detection module 11 compares the rising edge of the first clock signal CLKOI and the rising edge of the second clock signal CLKOQ to obtain the first detection signal Detection_clkoi_q; at the same time, the detection module 11 compares the rising edge of the second clock signal CLKOQ and the falling edge of the first clock signal CLKOI to output the second detection signal Detection_clkoi_ib.

[0119] (2) Please refer to the above. Figure 4 The comparison module 12 is used to determine the duty cycle of the first detection signal Detection_clkoi_q and the second detection signal Detection_clkoi_ib. If the duty cycle of the first detection signal Detection_clkoi_q is greater than the duty cycle of the second detection signal Detection_clkoi_ib, a comparison result signal DCD_Com in a high-level state is output; if the duty cycle of the first detection signal Detection_clkoi_q is less than the duty cycle of the second detection signal Detection_clkoi_ib, a comparison result signal DCD_Com in a low-level state is output. Simultaneously, the memory's main clock signal Main_CLK is divided to obtain a sampling clock signal DCD_LAT, and the comparison result DCD_Com signal is sampled using the sampling clock signal DCD_LAT to obtain the count indication signal DCD_OUT. Here, the sampling clock signal DCD_LAT obtained by frequency division provides sufficient response time for the comparison module 12.

[0120] (3) Please refer to the above. Figure 4 and Figure 5 The counting module 13 is used to count the preset counting clock signal CLK_CNT according to the counting indication signal DCD_OUT to obtain the count value Q<2:0>. Here, the preset counting clock signal CLK_CNT is obtained by delaying the sampling clock signal DCD_LAT, and the counting indication signal DCD_OUT can characterize the direction of change of the count value Q<2:0>. Figure 5 As shown, if the counting indicator signal DCD_OUT is at a high level, the count value Q<2:0> gradually increases; if the counting indicator signal DCD_OUT is at a low level, the count value Q<2:0> gradually decreases.

[0121] (4) Please refer to the above. Figures 7-9 The adjustment module 14 includes a first adjustment module 141, a second adjustment module 142, a third adjustment module 143 and a fourth adjustment module 144, which are respectively set at the output end of the four DLL Delay lines. The control terminal of the first adjustment module 141 receives a preset reference value P<2:0> = 100, and processes the output signal of the first DLL Delay line (corresponding to CLKI) with a fixed delay to obtain the first clock signal CLKOI; the control terminal of the second adjustment module 142 receives a count value Q<2:0>, and processes the output signal of the second DLL Delay line (corresponding to CLKQ) with a corresponding delay to obtain the second clock signal CLKOQ; the control terminal of the third adjustment module 143 receives a preset reference value P<2:0> = 100, and processes the output signal of the third DLL Delay line (corresponding to CLKIB) with a fixed delay to obtain the third clock signal CLKOIB; the control terminal of the fourth adjustment module 144 receives a count value Q<2:0>, and processes the output signal of the fourth DLL Delay line (corresponding to CLKQB) with a corresponding delay to obtain the fourth clock signal CLKOQB. Figure 10 As shown, if the count value Q<2:0> is larger, the signal edges of the second clock signal CLKOQ / the fourth clock signal CLKOQB will move backward; if the count value Q<2:0> is smaller, the signal edges of the second clock signal CLKOQ / the fourth clock signal CLKOQB will move forward.

[0122] In other words, in this embodiment, the preset fixed value is set to P<2:0>=100 as a reference; assuming the phase difference between the first clock signal CLKOI and the second clock signal CLKOQ is less than 90 degrees, and the phase difference between the second clock signal CLKOQ and the third clock signal CLKOIB is greater than 90 degrees, the duty cycle of the first detection signal Detection_clkoi_q is higher than the duty cycle of the second detection signal Detection_clkoi_ib, the counting indicator signal is in a high-level state, the count value increases, thereby increasing the phase difference between the first clock signal CLKOI and the second clock signal CLKOQ, while decreasing the phase difference between the second clock signal CLKOQ and the third clock signal CLKOIB. The phase difference between clock signals CLKOI and CLKOQ is calculated. Conversely, if the phase difference between the first clock signal CLKOI and the second clock signal CLKOQ is greater than 90 degrees, and the phase difference between the second clock signal CLKOQ and the third clock signal CLKOIB is less than 90 degrees, then the duty cycle of the first detection signal Detection_clkoi_q is lower than the duty cycle of the second detection signal Detection_clkoi_ib. The counting indicator signal is low, the count value decreases, thus reducing the phase difference between the first clock signal CLKOI and the second clock signal CLKOQ, while increasing the phase difference between the second clock signal CLKOQ and the third clock signal CLKOIB. Thus, by adding a phase adjustment circuit 10 to the delay-locked loop (DLL), the phase difference between the four clock signals can be adjusted, ensuring that the four clock signals are sequentially 90 degrees apart within the error range. This avoids errors during subsequent sampling processing based on the four clocks, ultimately improving semiconductor performance.

[0123] This disclosure provides a delay-locked circuit, in which the phase adjustment circuit 10 detects the phase difference between different clock signals and corrects the clock signals, thereby improving the phase offset of the clock signals and ensuring that the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are 90 degrees out of phase in sequence within the error range, thereby improving the performance of the semiconductor.

[0124] In yet another embodiment of this disclosure, see [link to relevant documentation]. Figure 13 This illustrates a schematic diagram of the composition structure of a memory 40 provided in an embodiment of this disclosure. For example... Figure 13 As shown, the memory 40 includes at least the aforementioned delay-locking circuit 30.

[0125] Since the delay-locked circuit 30 can detect the phase difference between different clock signals and correct the clock signals through the phase adjustment circuit therein, it can improve the phase offset of the clock signals and ensure that the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are 90 degrees out of phase in turn within the error range, thereby improving the performance of the semiconductor.

[0126] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure. It should be noted that in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. The sequence numbers of the embodiments in this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method or device embodiments without conflict. The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A phase adjustment circuit, characterized by, The phase adjustment circuit includes a detection module, a comparison module, a counting module, and an adjustment module connected in sequence; wherein... The detection module is configured to detect the phase difference between the rising edge of the first clock signal and the rising edge of the second clock signal to obtain a first detection signal, and to detect the phase difference between the rising edge of the second clock signal and the falling edge of the first clock signal to obtain a second detection signal. The comparison module is configured to perform a duty cycle comparison process on the first detection signal and the second detection signal to obtain a counting indication signal; The counting module is configured to count the number of pulses of a preset counting clock signal based on the counting indication signal to obtain a count value; The adjustment module is configured to perform phase adjustment on the second clock signal according to the count value, so that the phase difference between the first clock signal and the second clock signal is a preset value. The phase adjustment circuit is applied to the memory, and the comparison module includes a duty cycle unit, a preprocessing unit, and a sampling unit; wherein... The duty cycle unit is configured to receive the first detection signal and the second detection signal, perform duty cycle comparison processing on the first detection signal and the second detection signal, and obtain a comparison result signal; wherein, when the duty cycle of the first detection signal is higher than that of the second detection signal, the comparison result signal is in a first level state; when the duty cycle of the first detection signal is lower than that of the second detection signal, the comparison result signal is in a second level state. The preprocessing unit is configured to receive the main clock signal of the memory, perform frequency division processing on the main clock signal, and obtain a sampling clock signal; The sampling unit is configured to receive the sampling clock signal and the comparison result signal, and to sample the comparison result signal based on the sampling clock signal to obtain the counting indication signal.

2. The phase adjustment circuit according to claim 1, characterized in that, The detection module is specifically configured to receive any three of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal, and output the first detection signal and the second detection signal based on the received signals. Wherein, the third clock signal has a phase difference of 180 degrees with the first clock signal, the fourth clock signal has a phase difference of 180 degrees with the second clock signal, the first detection signal indicates the phase difference between the rising edge of the first clock signal and the rising edge of the second clock signal, and the second detection signal indicates the phase difference between the rising edge of the second clock signal and the falling edge of the first clock signal.

3. The phase adjustment circuit according to claim 2, characterized in that, The adjustment module is further configured to perform phase adjustment on the fourth clock signal according to the count value, so that the phase difference between the third clock signal and the fourth clock signal is a preset value.

4. The phase adjustment circuit according to claim 2, characterized in that, The detection module includes a first detection unit and a second detection unit; wherein... The first detection unit is configured to receive the first clock signal and the second clock signal, and perform logical operations on the first clock signal and the second clock signal to obtain the first detection signal; The second detection unit is configured to receive the third clock signal and the second clock signal, perform logical operations on the third clock signal and the second clock signal to obtain the second detection signal.

5. The phase adjustment circuit according to claim 4, characterized in that, The first detection unit includes a first inverter, a first transmission gate, and a first NAND gate; the second detection unit includes a second inverter, a second transmission gate, and a second NAND gate. The input terminal of the first inverter receives the second clock signal, the input terminal of the first transmission gate receives the first clock signal, the two input terminals of the first NAND gate are respectively connected to the output terminal of the first inverter and the output terminal of the first transmission gate, and the output terminal of the first NAND gate outputs the first detection signal. The input terminal of the second inverter receives the third clock signal, the input terminal of the second transmission gate receives the second clock signal, the two input terminals of the second NAND gate are respectively connected to the output terminal of the second inverter and the output terminal of the second transmission gate, and the output terminal of the second NAND gate outputs the second detection signal.

6. The phase adjustment circuit according to claim 1, characterized in that, The duty cycle unit includes a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a first current source, a second current source, a third current source, a fourth current source, a first capacitor, a second capacitor, and an operational amplifier; wherein, The control terminal of the first switch and the control terminal of the second switch form a connection point for receiving the first detection signal; the first terminal of the first switch is connected to the output terminal of the first current source, the input terminal of the first current source is connected to the power supply signal, the second terminal of the second switch is connected to the input terminal of the second current source, and the output terminal of the second current source is connected to the ground signal; the second terminal of the first switch and the first terminal of the second switch are both connected to the first terminal of the first capacitor, and the second terminal of the first capacitor is connected to the ground signal. The control terminal of the third switch and the control terminal of the fourth switch form a connection point for receiving the second detection signal; the first terminal of the third switch is connected to the output terminal of the third current source, the input terminal of the third current source is connected to the power supply signal, the second terminal of the fourth switch is connected to the input terminal of the fourth current source, and the output terminal of the fourth current source is connected to the ground signal; the second terminal of the third switch and the first terminal of the fourth switch are both connected to the first terminal of the second capacitor, and the second terminal of the second capacitor is connected to the ground signal. The first terminal of the first capacitor is also connected to the inverting input terminal of the operational amplifier, and the first terminal of the second capacitor is also connected to the non-inverting input terminal of the operational amplifier. The output terminal of the operational amplifier is used to output the comparison result signal.

7. The phase adjustment circuit according to claim 1, characterized in that, The preprocessing unit is further configured to delay the sampling clock signal to obtain the preset counting clock signal; The counting module is specifically configured to increment the count value by one for each pulse of the preset counting clock signal detected when the counting indicator signal is in a first level state; or, decrement the count value by one for each pulse of the preset counting clock signal detected when the counting indicator signal is in a second level state.

8. The phase adjustment circuit according to claim 1, characterized in that, The adjustment module includes a first adjustment module and a second adjustment module; wherein... The first adjustment module is configured to receive a preset fixed value and a first original clock signal, and to perform transmission processing on the first original clock signal based on the preset fixed value to obtain the first clock signal; The second adjustment module is configured to receive the count value and the second original clock signal, and to perform transmission processing on the second original clock signal based on the count value to obtain the second clock signal; Specifically, when the count value is greater than the preset fixed value, the rising edge of the second clock signal moves in a first direction relative to the rising edge of the first clock signal; when the count value is less than the preset fixed value, the rising edge of the second clock signal moves in a second direction relative to the rising edge of the first clock signal.

9. The phase adjustment circuit according to claim 8, characterized in that, The adjustment module further includes a third adjustment module and a fourth adjustment module; wherein... The third adjustment module is configured to receive the preset fixed value and the third original clock signal, and to perform transmission processing on the third original clock signal based on the preset fixed value to obtain a third clock signal; the phase difference between the third original clock signal and the first original clock signal is 180 degrees. The fourth adjustment module is configured to receive the count value and the fourth original clock signal, and perform transmission processing on the fourth original clock signal based on the count value to obtain the fourth clock signal; the phase difference between the fourth original clock signal and the second original clock signal is 180 degrees. Specifically, when the count value is greater than the preset fixed value, the rising edge of the fourth clock signal moves in a first direction relative to the rising edge of the third clock signal; when the count value is less than the preset fixed value, the rising edge of the fourth clock signal moves in a second direction relative to the rising edge of the third clock signal.

10. The phase adjustment circuit according to claim 9, characterized in that, Each of the first adjustment module, the second adjustment module, the third adjustment module, and the fourth adjustment module includes a preset number of adjustment units, wherein the preset number is an even number; The adjustment unit includes multiple inverting units, configured to determine whether each inverting unit is turned on based on either the preset fixed value or the corresponding count value; and to use the turned-on inverting units to perform inverted transmission processing on one of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal. In each of the adjustment units, at least one inverting unit is turned on; the control terminals of multiple inverting units together form the control terminal of the adjustment unit, and the control terminal of one inverting unit is used to receive one bit of the count value or one bit of the fixed value; the input terminals of multiple inverting units together form the input terminal of the adjustment unit, and the output terminals of multiple inverting units together form the output terminal of the adjustment unit.

11. The phase adjustment circuit according to claim 10, characterized in that, The number of digits in the preset fixed value is the same as the number of digits in the count value, both being n; The adjustment unit includes (n+1) inverting units, and the first inverting unit is fixed in the on state; If the adjustment unit belongs to the first adjustment module or the third adjustment module, then whether the (i+1)th inverting unit is turned on depends on the i-th bit of the preset fixed value; If the adjustment unit belongs to the second adjustment module or the fourth adjustment module, then whether the (i+1)th inverting unit is turned on depends on the i-th bit of the count value; Where n is a positive integer, i is a positive integer, and i is less than or equal to n.

12. The phase adjustment circuit according to claim 11, characterized in that, Each of the aforementioned inverting units includes a fifth switch, a sixth switch, a seventh switch, and an eighth switch; The first terminal of the fifth switch is connected to the power signal, the second terminal of the fifth switch is connected to the first terminal of the sixth switch, the second terminal of the seventh switch is connected to the first terminal of the eighth switch, and the second terminal of the eighth switch is connected to the ground signal. In the first inverting unit, the control terminal of the sixth switch is connected to the ground signal, and the control terminal of the seventh switch is connected to the power supply signal, so that the first inverting unit is fixed in the on state. In the (i+1)th inverting unit, the control terminal of the sixth switch is connected to the i-th control signal, the control terminal of the seventh switch is connected to the inverted signal of the i-th control signal, and the level of the i-th control signal depends on the i-th bit of either the count value or the preset fixed value, so that whether the (i+1)th inverting unit is turned on depends on the i-th bit of either the count value or the preset fixed value. The control terminal of the fifth switch and the control terminal of the eighth switch together form the input terminal of the inverting unit, and the second terminal of the sixth switch and the first terminal of the seventh switch together form the output terminal of the inverting unit.

13. The phase adjustment circuit according to claim 1, characterized in that, The preset value is 90 degrees, the first level state is a high level state, and the second level state is a low level state; The first, third, fifth, and sixth switching transistors are all P-channel MOSFETs, while the second, fourth, seventh, and eighth switching transistors are all N-channel MOSFETs. The control terminal of the P-type channel field-effect transistor is the gate, the first terminal of the P-type channel field-effect transistor is the source, and the second terminal of the P-type channel field-effect transistor is the drain. The control terminal of the N-type channel field-effect transistor is the gate, the first terminal of the N-type channel field-effect transistor is the drain, and the second terminal of the N-type channel field-effect transistor is the source.

14. A time-delay locking circuit, characterized in that, The delay-locked circuit is used to output a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal; The delay-locking circuit includes at least the phase adjustment circuit as described in any one of claims 1-13; wherein... The delay-locked circuit is configured to correct the phase difference between the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal through the phase adjustment circuit, so that the phases of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are sequentially 90 degrees apart.

15. A memory, characterized in that, The memory includes at least the delay-locking circuit as described in claim 14.

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