Logic analysis decoding method and apparatus

Abstract

The present disclosure relates to a logic analysis decoding method and device. The logic analysis decoding method comprises the following steps: obtaining a sample file of a memory circuit block, and generating an instruction sequence file of the memory circuit block, the sample file comprising a plurality of sample results, each sample result comprising a sampling point and a pin state of the memory circuit block corresponding to the sampling point, the instruction sequence file comprising a plurality of test instructions applied to the memory circuit block; aligning the plurality of test instructions with the plurality of sample results; judging whether the memory circuit block triggers frequency conversion according to the aligned plurality of test instructions and the plurality of sample results, and if yes, calculating a switching clock frequency of the memory circuit block according to the plurality of sample results; and aligning the plurality of test instructions with the plurality of sample results according to the switching clock frequency. The present disclosure realizes logic analysis decoding on the memory circuit block in a frequency conversion environment.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor testing technology, and in particular to a logic analysis and decoding method and apparatus. Background Technology

[0002] With the rapid development of semiconductor technology and the ever-increasing demands of various industries on circuits, testing circuit performance has become particularly important. Logic analysis, a method for analyzing the behavioral patterns of circuits, is a crucial testing tool for verifying the electrical performance of circuits.

[0003] Logic analysis of circuits is primarily performed using a logic analyzer. This involves sampling the circuit using the analyzer and then decoding the sampling results to determine the circuit's behavior patterns. Logic analyzer decoding is almost always based on the sampling results of the circuit at a fixed clock frequency. Traditional logic analysis decoding methods ensure decoding accuracy by synchronizing the logic analyzer's sampling frequency with the circuit's fixed clock frequency. However, in various application environments, frequency conversion operations are increasingly common in circuits to save power, making traditional logic analysis decoding methods unsuitable for understanding the circuit's behavior in frequency conversion environments.

[0004] Therefore, how to perform logic analysis and decoding on circuits in a frequency conversion environment, thereby expanding the application scope of logic analysis, is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] The present disclosure provides a logic analysis and decoding method and apparatus in some embodiments to solve the problem of being unable to perform logic analysis and decoding on memory circuit blocks in a frequency conversion environment, thereby expanding the application field of logic analysis.

[0006] According to some embodiments, this disclosure provides a logic analysis and decoding method, including the following steps:

[0007] A sampling file of a memory circuit block is obtained, and an instruction sequence file of the memory circuit block is generated. The sampling file includes multiple sampling results, each of which includes a sampling point and the pin status of the memory circuit block corresponding to the sampling point. The instruction sequence file includes multiple test instructions applied to the memory circuit block.

[0008] Align multiple test commands with multiple sampling results;

[0009] Based on the aligned test instructions and the sampling results, it is determined whether the memory circuit block triggers frequency conversion. If so, the switching clock frequency of the memory circuit block is calculated based on the sampling results.

[0010] Align multiple test commands with multiple sampling results according to the switching clock frequency.

[0011] In some embodiments, the specific steps for obtaining the sampling file of the memory circuit block include:

[0012] A logic analyzer is used to obtain the sampling file of the memory circuit block at a fixed sampling frequency.

[0013] In some embodiments, the specific steps of determining whether the memory circuit block triggers frequency conversion based on the aligned plurality of test instructions and the plurality of sampling results further include:

[0014] The multiple sampling results are arranged sequentially according to the sampling time order, and the following first loop step is performed at least once until the first current clock frequency of the memory circuit block is greater than the trigger threshold. The first loop step includes:

[0015] Starting from the sampling result at the first initial position, a preset number of sampling results are extracted sequentially;

[0016] Calculate the first current clock frequency of the memory circuit block based on the preset number of sampling results;

[0017] Determine whether the first current frequency is greater than the trigger threshold. If not, use the sampling result of the next position adjacent to the first initial position as the sampling result of the first initial position for the next first loop step.

[0018] In some embodiments, the pin state includes a first state and a second state; the specific steps for calculating the first current clock frequency of the memory circuit block based on the preset number of sampling results include:

[0019] The preset number of sampling results arranged in chronological order are divided into multiple groups of first sub-sampling results. Each group of first sub-sampling results includes several first states that are continuously distributed, and several second states that are continuously distributed and adjacent to the several first states.

[0020] Calculate the frequency of the first sub-sampling result in each group, and use it as the first sub-clock frequency;

[0021] Calculate the average of multiple first sub-clock frequencies as the first current clock frequency.

[0022] In some embodiments, the trigger threshold is 300MHz.

[0023] In some embodiments, the specific steps for calculating the switching clock frequency of the memory circuit block based on multiple sampling results include:

[0024] Using the first initial position corresponding to the first current clock frequency greater than the trigger threshold as the second initial position, perform at least one second loop step as follows, until the second current clock frequency calculated in at least two adjacent second loop steps is the same, and use the same second current clock frequency as the switching clock frequency of the memory circuit block; the second loop step includes:

[0025] Starting from the sampling result at the second initial position, a preset number of sampling results are extracted sequentially;

[0026] Calculate the second current clock frequency of the memory circuit block based on the preset number of sampling results;

[0027] Determine whether the second current clock frequency is the same as the second current clock frequency calculated in the previous second loop step. If not, use the sampling result of the next position adjacent to the second initial position as the sampling result of the second initial position for the next second loop step.

[0028] In some embodiments, the test command includes a chip select signal and an address signal; the specific steps of aligning multiple test commands with multiple sampling results according to the switching clock frequency include:

[0029] Align the chip select signal with the pin state in the sampling result according to the switching clock frequency;

[0030] Align the address signal with the pin state in the sampling result according to the switching clock frequency.

[0031] In some embodiments, the sampling file includes multiple record lines arranged in chronological order, each record line recording one sampling result; the specific steps of aligning the chip select signal with the pin state in the sampling result according to the switching clock frequency include:

[0032] Based on the switching clock frequency, the record line in which the pin state changes from the first state to the second state after the chip select signal is applied to the memory circuit block is selected as the current chip select line;

[0033] The time interval between the two record rows adjacent to the current row of the slice selection is obtained as the first slice selection time;

[0034] The time interval between the record line in the sampling results before the current chip selection line where the pin state changes from the first state to the second state and the current chip selection line is obtained, is used as the second chip selection time;

[0035] The difference between the first chip select time and the second chip select time is calculated and used as the configuration time of the chip select signal.

[0036] In some embodiments, the specific steps of aligning the address signal with the pin state in the sampling result according to the switching clock frequency include:

[0037] Based on the switching clock frequency, the record line in which the pin state changes from the first state to the second state after the address signal is applied to the memory circuit block is selected as the current address line;

[0038] Obtain the time interval between the two record rows adjacent to the current row of the address, and use it as the first address time;

[0039] The difference between the first address time and the second address time is calculated and used as the configuration time of the address signal.

[0040] In some embodiments, after aligning the plurality of test commands and the plurality of sampling results according to the switching clock frequency, the method further includes the following steps:

[0041] The configuration time of the chip select signal and the configuration time of the address signal are used as decoding instructions, and the sampling results are further decoded using the configuration of the decoding instructions aligned with the fixed sampling frequency.

[0042] According to other embodiments, this disclosure also provides a logic analysis and decoding apparatus, including a processor, and further comprising:

[0043] A memory, connected to the processor, is used to store sampling files of memory circuit blocks and generate instruction sequence files of the memory circuit blocks. The sampling files include multiple sampling results, each of which includes a sampling point and the pin status of the memory circuit block corresponding to the sampling point. The instruction sequence files include multiple test instructions applied to the memory circuit blocks.

[0044] A first alignment circuit, connected to the processor, is used to align the plurality of test instructions and the plurality of sampling results according to the initial clock frequency;

[0045] A judgment circuit, connected to the processor, is used to determine whether the memory circuit block triggers frequency conversion based on the aligned test instructions and the sampling results. If so, the switching clock frequency of the memory circuit block is calculated based on the sampling results.

[0046] A second alignment circuit, connected to the processor, is used to align multiple test instructions with multiple sampling results according to the switching clock frequency.

[0047] In some embodiments, it also includes:

[0048] The access port is connected to the memory and is used to receive the sampling file of the memory circuit block obtained by the logic analyzer at a fixed sampling frequency.

[0049] In some embodiments, the plurality of sampling results in the memory are arranged sequentially according to the sampling time order; the determination circuit includes a first loop circuit, which is configured to perform at least one first loop step as follows until the first current clock frequency of the memory circuit block is greater than a trigger threshold, the first loop step including:

[0050] Starting from the sampling result at the first initial position, a preset number of sampling results are extracted sequentially;

[0051] Calculate the first current clock frequency of the memory circuit block based on the preset number of sampling results;

[0052] Determine whether the first current frequency is greater than the trigger threshold. If not, use the sampling result of the next position adjacent to the first initial position as the sampling result of the first initial position for the next first loop step.

[0053] In some embodiments, the pin state includes a first state and a second state;

[0054] The first loop circuit is further configured to separate the preset number of sampling results arranged in chronological order into multiple groups of first sub-sampling results, each group of first sub-sampling results including a plurality of continuously distributed first states and a plurality of continuously distributed second states adjacent to the plurality of continuously distributed first states; the first loop circuit is further configured to calculate the frequency of each group of first sub-sampling results as a first sub-clock frequency; the first loop circuit is further configured to calculate the average value of multiple first sub-clock frequencies as the first current clock frequency.

[0055] In some embodiments, the trigger threshold is 300MHz.

[0056] In some embodiments, the determining circuit further includes a second loop circuit, which is configured to perform at least one second loop step using the first initial position corresponding to the first current clock frequency greater than the trigger threshold as the second initial position, until the second current clock frequency calculated in at least two adjacent second loop steps is the same, and the same second current clock frequency is used as the switching clock frequency of the memory circuit block; the second loop step includes:

[0057] Starting from the sampling result at the second initial position, a preset number of sampling results are extracted sequentially;

[0058] Calculate the second current clock frequency of the memory circuit block based on the preset number of sampling results;

[0059] Determine whether the second current clock frequency is the same as the second current clock frequency calculated in the previous second loop step. If not, use the sampling result of the next position adjacent to the second initial position as the sampling result of the second initial position for the next second loop step.

[0060] In some embodiments, the test command includes a chip select signal and an address signal; the second alignment circuit is further configured to align the chip select signal with the pin state in the sampling result according to the switching clock frequency, and to align the address signal with the pin state in the sampling result according to the switching clock frequency.

[0061] In some embodiments, the sampling file includes multiple record lines arranged in chronological order, with each record line recording one sampling result;

[0062] The second alignment circuit includes a chip select signal alignment circuit, which is used to select, according to the switching clock frequency, the record line in which the pin state changes from the first state to the second state after the chip select signal is applied to the memory circuit block, as the current chip select line; the chip select signal alignment circuit is also used to obtain the time interval between two adjacent record lines, as the first chip select time, and to obtain the time interval between the record line in the sampling results before the current chip select line where the pin state changes from the first state to the second state and the current chip select line, as the second chip select time; the chip select signal alignment circuit is also used to calculate the difference between the first chip select time and the second chip select time, as the configuration time of the chip select signal.

[0063] In some embodiments, the second alignment circuit further includes an address signal alignment circuit, which is used to select, according to the switching clock frequency, the record row whose pin state changes from the first state to the second state after the address signal is applied to the memory circuit block, as the current address row, and to obtain the time interval between two adjacent record rows as the first address time; the address signal alignment circuit is also used to calculate the difference between the first address time and the second address time as the configuration time of the address signal.

[0064] In some embodiments, the processor is configured to use the configuration time of the chip select signal and the configuration time of the address signal as decoding instructions, and to continue decoding the sampling results using the decoding instructions aligned with the fixed sampling frequency.

[0065] The logic analysis and decoding method and apparatus provided in some embodiments of this disclosure, after confirming that the memory circuit block to be tested has triggered frequency conversion, calculates the switching clock frequency of the memory circuit block based on the sampling results of logic analysis, and aligns multiple test instructions with multiple sampling results based on the switching clock frequency, thereby enabling the alignment of the test instructions of the memory circuit block in the frequency conversion environment with the sampling results of logic analysis, realizing logic analysis and decoding of memory circuit blocks in the frequency conversion environment, thereby expanding the application scope of logic analysis. Attached Figure Description

[0066] Appendix Figure 1 This is a flowchart of the logic analysis and decoding method in a specific embodiment of this disclosure;

[0067] Appendix Figure 2 This is a structural block diagram of the logic analysis and decoding device in a specific embodiment of this disclosure. Detailed Implementation

[0068] The specific implementation methods of the logic analysis and decoding method and apparatus provided in this disclosure will be described in detail below with reference to the accompanying drawings.

[0069] This specific implementation provides a logic analysis and decoding method, with appendix... Figure 1 This is a flowchart of the logic analysis and decoding method in a specific embodiment of this disclosure. For example... Figure 1 As shown, the logic analysis and decoding method includes the following steps:

[0070] Step S11: Obtain the sampling file of the memory circuit block and generate the instruction sequence file of the memory circuit block. The sampling file includes multiple sampling results. Each sampling result includes a sampling point and the pin status of the memory circuit block corresponding to the sampling point. The instruction sequence file includes multiple test instructions applied to the memory circuit block.

[0071] In some embodiments, the specific steps for obtaining the sampling file of the memory circuit block include:

[0072] A logic analyzer is used to obtain the sampling file of the memory circuit block at a fixed sampling frequency.

[0073] The memory circuit block described in this specific embodiment may be, but is not limited to, DRAM. This specific embodiment obtains the sampling file of the memory circuit block using the logic analyzer. For example, the logic analyzer samples the memory circuit block in a fixed sampling frequency sampling mode to obtain the sampling file. During the sampling of the memory circuit block using the logic analyzer at a fixed sampling frequency, the sampling frequency of the logic analyzer is at least four times the sampling frequency to ensure that the pins of the memory circuit block can switch between a first state and a second state, and that both the first and second states have two sampling points for state verification. For example, when the sampling frequency of the logic analyzer is four times the sampling frequency, the logic analyzer can acquire four sampling points in each sampling cycle. The first state can be a low-voltage state below a threshold voltage (e.g., state 0), and the second state can be a high-voltage state above a threshold voltage (e.g., state 1). The sampling depth of the logic analyzer can be set according to actual needs, and this specific embodiment does not limit this. The greater the sampling depth of the logic analyzer, the longer the acquired sequence.

[0074] In one embodiment, the sampling file can be a CSV format sampling file. The CSV format sampling file is a plain text file. The sampling file describes multiple sampling results, each sampling result including multiple sampling points and multiple pin states of the memory circuit block corresponding to each sampling point. The sampling point is a sampling time point. The pin state is the state of the pins in the memory circuit block that have been collected. The pin state includes a first state and a second state.

[0075] Step S12: Align the multiple test instructions with the multiple sampling results.

[0076] The test instruction refers to the control instruction sent by the controller of the memory circuit block. In one embodiment, the control instruction includes one or more combinations of write, read, precharge, and activation instructions (ACT). Aligning multiple test instructions with multiple sampling results means aligning the pin state of the sampling point in the sampling result with the edge of the clock of the memory circuit block from the first state to the second state. For example, in a sampling cycle at 4 times the sampling frequency, if the pin state sampled by the logic analyzer at the second sampling point is the first state and the pin state sampled by the third sampling point is the second state, then the pin state sampled by the third sampling point is considered to be the aligned result.

[0077] Step S13: Determine whether the memory circuit block triggers frequency conversion based on the multiple aligned test instructions and multiple sampling results. If so, calculate the switching clock frequency of the memory circuit block based on the multiple sampling results.

[0078] In some embodiments, the specific steps of determining whether the memory circuit block triggers frequency conversion based on the aligned plurality of test instructions and the plurality of sampling results further include:

[0079] The multiple sampling results are arranged sequentially according to the sampling time order, and the following first loop step is performed at least once until the first current clock frequency of the memory circuit block is greater than the trigger threshold. The first loop step includes:

[0080] Starting from the sampling result at the first initial position, a preset number of sampling results are extracted sequentially;

[0081] Calculate the first current clock frequency of the memory circuit block based on the preset number of sampling results;

[0082] Determine whether the first current frequency is greater than the trigger threshold. If not, use the sampling result of the next position adjacent to the first initial position as the sampling result of the first initial position for the next first loop step.

[0083] In some embodiments, the trigger threshold is 300MHz.

[0084] For example, a list containing the preset number of elements can be declared, the list being used to dynamically store the preset number of sampling results. In this specific embodiment, the elements are variables. In one embodiment, the elements are storage spaces used to store the sampling results.

[0085] The sampling results in the sampling file are arranged sequentially according to their sampling time, and then the first loop step is performed multiple times. The following explanation uses a preset quantity of 160 and a trigger threshold of 300MHz as an example; those skilled in the art can choose other preset quantities and trigger thresholds according to actual needs. In the first loop step, the 160 elements in the list store the sampling results from the 1st to the 160th position, respectively. The first current clock frequency of the memory circuit block (i.e., the initial clock frequency of the memory circuit block) is calculated based on the 160 sampling results stored in the list, and it is determined whether the calculated first current clock frequency is greater than 300MHz. If not, the first loop step is performed a second time. In the second loop step, the 160 elements in the list store the sampling results from the 2nd to the 161st position, respectively. The first current clock frequency of the memory circuit block is calculated based on the 160 sampling results stored in the list, and it is determined whether the calculated first current clock frequency is greater than 300MHz. If not, the first loop step is performed a third time. In the first loop step of the third iteration, the 160 elements in the list store the sampling results from the 3rd to the 162nd bit, respectively. The first current clock frequency of the memory circuit block is calculated based on the 160 sampling results stored in the list, and it is determined whether the calculated first current clock frequency is greater than 300MHz. If not, the first loop step is repeated for the fourth iteration. This process continues until the first current clock frequency is greater than or equal to 300MHz, at which point the memory circuit block is considered to have triggered a frequency conversion. By monitoring the frequency conversion point of the memory circuit block, the sampling point that triggers the frequency conversion operation and the corresponding sampling result can be obtained in a timely and accurate manner. Determining whether the memory circuit block triggers a frequency conversion determines whether a frequency conversion decoding operation should be performed, thereby improving the flexibility of decoding the sampled file.

[0086] To simplify the calculation of the first current clock frequency, in some embodiments, the pin state includes a first state and a second state; the specific steps for calculating the first current clock frequency of the memory circuit block based on the preset number of sampling results include:

[0087] The preset number of sampling results arranged in chronological order are divided into multiple groups of first sub-sampling results. Each group of first sub-sampling results includes several first states that are continuously distributed, and several second states that are continuously distributed and adjacent to the several first states.

[0088] Calculate the frequency of the first sub-sampling result in each group, and use it as the first sub-clock frequency;

[0089] Calculate the average of multiple first sub-clock frequencies as the first current clock frequency.

[0090] Specifically, within one clock cycle of the memory circuit block, the pin states of the memory circuit block include a continuous second state (e.g., state 1) and a continuous first state (e.g., state 0) adjacent to the continuous second state. The reciprocal of the clock cycle of the memory circuit block is the clock frequency of the memory circuit block. Therefore, by dividing and calculating the preset number of sampling results in the list, multiple first sub-clock frequencies of the memory circuit block can be obtained, and the average value of the multiple first sub-clock frequencies can be calculated as the first current clock frequency.

[0091] In some embodiments, the specific steps for calculating the switching clock frequency of the memory circuit block based on multiple sampling results include:

[0092] Using the first initial position corresponding to the first current clock frequency greater than the trigger threshold as the second initial position, perform at least one second loop step as follows, until the second current clock frequency calculated in at least two adjacent second loop steps is the same, and use the same second current clock frequency as the switching clock frequency of the memory circuit block; the second loop step includes:

[0093] Starting from the sampling result at the second initial position, a preset number of sampling results are extracted sequentially;

[0094] Calculate the second current clock frequency of the memory circuit block based on the preset number of sampling results;

[0095] Determine whether the second current clock frequency is the same as the second current clock frequency calculated in the previous second loop step. If not, use the sampling result of the next position adjacent to the second initial position as the sampling result of the second initial position for the next second loop step.

[0096] Specifically, the first initial position in the last first loop step is used as the second initial position in the first second loop step, that is, the first initial position corresponding to the first current clock frequency that triggers the frequency conversion is used as the second initial position in the first second loop step. For example, in the first second loop step, the 160 elements in the list store the sampling results from the nth bit to the 159+nth bit, and the second current clock frequency of the memory circuit block is calculated based on the 160 sampling results stored in the list. In the second second loop step, the 160 elements in the list store the sampling results from the (n+1th)th bit to the 160+nth bit, and the second current clock frequency of the memory circuit block is calculated based on the 160 sampling results stored in the list. It is then determined whether the second current clock frequency calculated in the second second loop step is the same as the second current clock frequency calculated in the first second loop step. If not, the third second loop step is performed. In the second loop step of the third iteration, the 160 elements in the list store the sampling results from the (n+2)th bit to the (161+n)th bit. The second current clock frequency of the memory circuit block is calculated based on the 160 sampling results stored in the list. It is then determined whether the second current clock frequency calculated in the third loop step is the same as the second current clock frequency calculated in the second loop step. If not, the fourth loop step is performed. This process continues until the second current clock frequencies calculated in two consecutive loop steps are the same. At this point, it is confirmed that the clock frequency change of the memory circuit block has stabilized, and the stable second current clock frequency is used as the switching clock frequency of the memory circuit block.

[0097] Step S14: Align the multiple test commands with the multiple sampling results according to the switching clock frequency.

[0098] Specifically, by aligning multiple test instructions and multiple sampling results according to the switching clock frequency, the correspondence between, for example, the sampling results collected by the logic analyzer and the clock of the memory circuit block is determined, thereby ensuring the accuracy of logic analysis and decoding.

[0099] In some embodiments, the test command includes a chip select signal (i.e., a CS signal) and an address signal (i.e., a CA signal); the specific steps for aligning multiple test commands with multiple sampling results according to the switching clock frequency include:

[0100] Align the chip select signal with the pin state in the sampling result according to the switching clock frequency;

[0101] Align the address signal with the pin state in the sampling result according to the switching clock frequency.

[0102] In some embodiments, the sampling file includes multiple record lines arranged in chronological order, each record line recording one sampling result; the specific steps of aligning the chip select signal with the pin state in the sampling result according to the switching clock frequency include:

[0103] Based on the switching clock frequency, the record line in which the pin state changes from the first state to the second state after the chip select signal is applied to the memory circuit block is selected as the current chip select line;

[0104] The time interval between the two record rows adjacent to the current row of the slice selection is obtained as the first slice selection time;

[0105] The time interval between the record line in the sampling results before the current chip selection line where the pin state changes from the first state to the second state and the current chip selection line is obtained, is used as the second chip selection time;

[0106] The difference between the first chip select time and the second chip select time is calculated and used as the configuration time of the chip select signal.

[0107] For example, the sampling file is a CSV format sampling file, which includes multiple record rows arranged in chronological order, with each record row recording one sampling result. When aligning the chip select signal with the pin state in the sampling results according to the switching clock frequency, the record row in the sampling file where the pin state changes from the first state to the second state after the chip select signal is applied to the memory circuit block is found and designated as the current chip select row. Obtaining the time interval between two adjacent record rows of the current chip select row refers to obtaining the time interval between the row preceding the current chip select row and the row following the current chip select row.

[0108] In some embodiments, the specific steps of aligning the address signal with the pin state in the sampling result according to the switching clock frequency include:

[0109] Based on the switching clock frequency, the record line in which the pin state changes from the first state to the second state after the address signal is applied to the memory circuit block is selected as the current address line;

[0110] Obtain the time interval between the two record rows adjacent to the current row of the address, and use it as the first address time;

[0111] The difference between the first address time and the second address time is calculated and used as the configuration time of the address signal.

[0112] Specifically, the chip select signal is always issued synchronously with the test command of the memory circuit block. If the chip select signal is detected, it is determined that the memory circuit block is receiving the test command. The address signal is a specific combination of instructions that is received by the memory circuit block synchronously with the chip select signal. The chip select signal and the address signal are the main signals for logic analysis and decoding. By aligning the chip select signal with the sampling result and the address signal with the sampling result, the accuracy of logic analysis and decoding can be further ensured.

[0113] In some embodiments, after aligning the plurality of test commands and the plurality of sampling results according to the switching clock frequency, the method further includes the following steps:

[0114] The configuration time of the chip select signal and the configuration time of the address signal are used as decoding instructions, and the sampling results are further decoded using the configuration of the decoding instructions aligned with the fixed sampling frequency.

[0115] This specific embodiment also provides a logic analysis and decoding device, with attachment Figure 2 This is a structural block diagram of the logic analysis and decoding device in a specific embodiment of this disclosure. The logic analysis and decoding device provided in this specific embodiment can employ, for example... Figure 1 The logical analysis and decoding method shown is used for decoding. For example... Figure 2 As shown, the logic analysis and decoding device includes a processor 21, and further includes:

[0116] The memory 20, connected to the processor 21, is used to store sampling files of memory circuit blocks and generate instruction sequence files of the memory circuit blocks. The sampling files include multiple sampling results, each sampling result including a sampling point and the pin status of the memory circuit block corresponding to the sampling point. The instruction sequence files include multiple test instructions applied to the memory circuit blocks.

[0117] The first alignment circuit 22 is connected to the processor 21 and is used to align the multiple test instructions and the multiple sampling results according to the initial clock frequency.

[0118] The judgment circuit 23, connected to the processor 21, is used to determine whether the memory circuit block triggers frequency conversion based on the multiple aligned test instructions and multiple sampling results. If so, the switching clock frequency of the memory circuit block is calculated based on the multiple sampling results.

[0119] The second alignment circuit 24, connected to the processor 21, is used to align multiple test instructions and multiple sampling results according to the switching clock frequency.

[0120] In some embodiments, the logic analysis and decoding apparatus further includes:

[0121] Access port 25 is connected to the memory 20 and is used to receive the sampling file of the memory circuit block obtained by the logic analyzer at a fixed sampling frequency.

[0122] In some embodiments, the plurality of sampling results in the memory 20 are arranged sequentially according to the sampling time order; the judgment circuit 23 includes a first loop circuit 231, which is configured to perform at least one first loop step until the first current clock frequency of the memory circuit block is greater than a trigger threshold, the first loop step including:

[0123] Starting from the sampling result at the first initial position, a preset number of sampling results are extracted sequentially;

[0124] Calculate the first current clock frequency of the memory circuit block based on the preset number of sampling results;

[0125] Determine whether the first current frequency is greater than the trigger threshold. If not, use the sampling result of the next position adjacent to the first initial position as the sampling result of the first initial position for the next first loop step.

[0126] In some embodiments, the pin state includes a first state and a second state;

[0127] The first loop circuit 231 is further configured to separate the preset number of sampling results arranged in chronological order into multiple groups of first sub-sampling results, each group of first sub-sampling results including a plurality of continuously distributed first states and a plurality of continuously distributed second states adjacent to the plurality of continuously distributed first states; the first loop circuit 231 is further configured to calculate the frequency of each group of first sub-sampling results as a first sub-clock frequency; the first loop circuit 231 is further configured to calculate the average value of multiple first sub-clock frequencies as the first current clock frequency.

[0128] In some embodiments, the trigger threshold is 300MHz.

[0129] In some embodiments, the determination circuit 23 further includes a second loop circuit 232, which is configured to perform at least one second loop step, using the first initial position corresponding to the first current clock frequency greater than the trigger threshold as the second initial position, until the second current clock frequency calculated in at least two adjacent second loop steps is the same, and using the same second current clock frequency as the switching clock frequency of the memory circuit block; the second loop step includes:

[0130] Starting from the sampling result at the second initial position, a preset number of sampling results are extracted sequentially;

[0131] Calculate the second current clock frequency of the memory circuit block based on the preset number of sampling results;

[0132] Determine whether the second current clock frequency is the same as the second current clock frequency calculated in the previous second loop step. If not, use the sampling result of the next position adjacent to the second initial position as the sampling result of the second initial position for the next second loop step.

[0133] In some embodiments, the test command includes a chip select signal and an address signal; the second alignment circuit 24 is further configured to align the chip select signal with the pin state in the sampling result according to the switching clock frequency, and to align the address signal with the pin state in the sampling result according to the switching clock frequency.

[0134] In some embodiments, the sampling file includes multiple record lines arranged in chronological order, with each record line recording one sampling result;

[0135] The second alignment circuit 24 includes a chip select signal alignment circuit 241. The chip select signal alignment circuit 241 is used to select, according to the switching clock frequency, the record line in which the pin state changes from the first state to the second state after the chip select signal is applied to the memory circuit block, as the current chip select line. The chip select signal alignment circuit 241 is also used to obtain the time interval between two adjacent record lines, as the first chip select time, and to obtain the time interval between the record line in the sampling results before the current chip select line where the pin state changes from the first state to the second state and the current chip select line, as the second chip select time. The chip select signal alignment circuit 241 is also used to calculate the difference between the first chip select time and the second chip select time, as the configuration time of the chip select signal.

[0136] In some embodiments, the second alignment circuit 24 further includes an address signal alignment circuit 242, which is used to select, according to the switching clock frequency, the record row whose pin state changes from the first state to the second state after the address signal is applied to the memory circuit block, as the current address row, and to obtain the time interval between two adjacent record rows as the first address time; the address signal alignment circuit 242 is also used to calculate the difference between the first address time and the second address time as the configuration time of the address signal.

[0137] In some embodiments, the processor 21 is configured to use the configuration time of the chip select signal and the configuration time of the address signal as decoding instructions, and to continue decoding the sampling results using the decoding instructions aligned with the fixed sampling frequency.

[0138] The logic analysis and decoding method and apparatus provided in some embodiments of this specific implementation, after confirming that the memory circuit block to be tested has triggered frequency conversion, calculates the switching clock frequency of the memory circuit block based on the sampling results of logic analysis, and aligns multiple test instructions with multiple sampling results based on the switching clock frequency, thereby enabling the alignment of the test instructions of the memory circuit block in the frequency conversion environment with the sampling results of logic analysis, realizing logic analysis and decoding of memory circuit blocks in the frequency conversion environment, thereby expanding the application scope of logic analysis.

[0139] The above description is only a preferred embodiment of this disclosure. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of this disclosure, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A logic analysis and decoding method, characterized in that, Includes the following steps: A sampling file of a memory circuit block is obtained, and an instruction sequence file of the memory circuit block is generated. The sampling file includes multiple sampling results, each of which includes a sampling point and the pin status of the memory circuit block corresponding to the sampling point. The instruction sequence file includes multiple test instructions applied to the memory circuit block. Align multiple test commands with multiple sampling results; Based on the aligned test instructions and the sampling results, it is determined whether the memory circuit block triggers frequency conversion. If so, the switching clock frequency of the memory circuit block is calculated based on the sampling results. Align multiple test commands with multiple sampling results according to the switching clock frequency.

2. The logic analysis and decoding method according to claim 1, characterized in that, The specific steps for obtaining the sampling file of the memory circuit block include: A logic analyzer is used to obtain the sampling file of the memory circuit block at a fixed sampling frequency.

3. The logic analysis and decoding method according to claim 2, characterized in that, The specific steps for determining whether the memory circuit block triggers frequency conversion based on the aligned test commands and sampling results also include: The multiple sampling results are arranged sequentially according to the sampling time order, and the following first loop step is performed at least once until the first current clock frequency of the memory circuit block is greater than the trigger threshold. The first loop step includes: Starting from the sampling result at the first initial position, a preset number of sampling results are extracted sequentially; the first current clock frequency of the memory circuit block is calculated based on the preset number of sampling results; Determine whether the first current clock frequency is greater than the trigger threshold. If not, use the sampling result of the next position adjacent to the first initial position as the sampling result of the first initial position for the next first loop step.

4. The logic analysis and decoding method according to claim 3, characterized in that, The pin states include a first state and a second state; the specific steps for calculating the first current clock frequency of the memory circuit block based on the preset number of sampling results include: The preset number of sampling results arranged in chronological order are divided into multiple groups of first sub-sampling results. Each group of first sub-sampling results includes several first states that are continuously distributed, and several second states that are continuously distributed and adjacent to the several first states. Calculate the frequency of the first sub-sampling result in each group, and use it as the first sub-clock frequency; Calculate the average of multiple first sub-clock frequencies as the first current clock frequency.

5. The logic analysis and decoding method according to claim 3, characterized in that, The trigger threshold is 300MHz.

6. The logic analysis and decoding method according to claim 3, characterized in that, The specific steps for calculating the switching clock frequency of the memory circuit block based on multiple sampling results include: Using the first initial position corresponding to the first current clock frequency greater than the trigger threshold as the second initial position, perform at least one second loop step as follows, until the second current clock frequency calculated in at least two adjacent second loop steps is the same, and use the same second current clock frequency as the switching clock frequency of the memory circuit block; the second loop step includes: Starting from the sampling result at the second initial position, a preset number of sampling results are extracted sequentially; the second current clock frequency of the memory circuit block is calculated based on the preset number of sampling results; Determine whether the second current clock frequency is the same as the second current clock frequency calculated in the previous second loop step. If not, use the sampling result of the next position adjacent to the second initial position as the sampling result of the second initial position for the next second loop step.

7. The logic analysis and decoding method according to claim 4, characterized in that, The test commands include a chip select signal and an address signal; the specific steps for aligning multiple test commands with multiple sampling results according to the switching clock frequency include: Align the chip select signal with the pin state in the sampling result according to the switching clock frequency; Align the address signal with the pin state in the sampling result according to the switching clock frequency.

8. The logic analysis and decoding method according to claim 7, characterized in that, The sampling file includes multiple record lines arranged in chronological order, with each record line recording one sampling result; the specific steps for aligning the chip select signal with the pin status in the sampling result according to the switching clock frequency include: Based on the switching clock frequency, the record line in which the pin state changes from the first state to the second state after the chip select signal is applied to the memory circuit block is selected as the current chip select line; The time interval between the two record rows adjacent to the current row of the slice selection is obtained as the first slice selection time; The time interval between the record line in the sampling results before the current chip selection line where the pin state changes from the first state to the second state and the current chip selection line is obtained, is used as the second chip selection time; The difference between the first chip select time and the second chip select time is calculated and used as the configuration time of the chip select signal.

9. A logic analysis and decoding device, characterized in that, Including the processor, it also includes: A memory, connected to the processor, is used to store sampling files of memory circuit blocks and generate instruction sequence files of the memory circuit blocks. The sampling files include multiple sampling results, each of which includes a sampling point and the pin status of the memory circuit block corresponding to the sampling point. The instruction sequence files include multiple test instructions applied to the memory circuit blocks. A first alignment circuit, connected to the processor, is used to align the multiple test instructions and the multiple sampling results according to an initial clock frequency. A judgment circuit, connected to the processor, is used to determine whether the memory circuit block triggers frequency conversion based on the aligned test instructions and the sampling results. If so, the switching clock frequency of the memory circuit block is calculated based on the sampling results. A second alignment circuit, connected to the processor, is used to align multiple test instructions with multiple sampling results according to the switching clock frequency.

10. The logic analysis and decoding device according to claim 9, characterized in that, Also includes: The access port is connected to the memory and is used to receive the sampling file of the memory circuit block obtained by the logic analyzer at a fixed sampling frequency.

11. The logic analysis and decoding apparatus according to claim 10, characterized in that, The multiple sampling results in the memory are arranged sequentially according to the sampling time order; the judgment circuit includes a first loop circuit, which performs at least one first loop step as follows until the first current clock frequency of the memory circuit block is greater than a trigger threshold, the first loop step including: Starting from the sampling result at the first initial position, a preset number of sampling results are extracted sequentially; the first current clock frequency of the memory circuit block is calculated based on the preset number of sampling results; Determine whether the first current clock frequency is greater than the trigger threshold. If not, use the sampling result of the next position adjacent to the first initial position as the sampling result of the first initial position for the next first loop step.

12. The logic analysis and decoding device according to claim 11, characterized in that, The pin states include a first state and a second state; The first loop circuit is further configured to separate the preset number of sampling results arranged in chronological order into multiple groups of first sub-sampling results, each group of first sub-sampling results including a plurality of continuously distributed first states and a plurality of continuously distributed second states adjacent to the plurality of continuously distributed first states; the first loop circuit is further configured to calculate the frequency of each group of first sub-sampling results as a first sub-clock frequency; the first loop circuit is further configured to calculate the average value of multiple first sub-clock frequencies as the first current clock frequency.

13. The logic analysis and decoding apparatus according to claim 11, characterized in that, The trigger threshold is 300MHz.

14. The logic analysis and decoding device according to claim 11, characterized in that, The judgment circuit further includes a second loop circuit, which is used to perform at least one second loop step with the first initial position corresponding to the first current clock frequency greater than the trigger threshold as the second initial position, until the second current clock frequency calculated by at least two adjacent second loop steps is the same, and the same second current clock frequency is used as the switching clock frequency of the memory circuit block. The second loop step includes: Starting from the sampling result at the second initial position, a preset number of sampling results are extracted sequentially; the second current clock frequency of the memory circuit block is calculated based on the preset number of sampling results; Determine whether the second current clock frequency is the same as the second current clock frequency calculated in the previous second loop step. If not, use the sampling result of the next position adjacent to the second initial position as the sampling result of the second initial position for the next second loop step.

15. The logic analysis and decoding apparatus according to claim 12, characterized in that, The test command includes a chip select signal and an address signal; the second alignment circuit is further configured to align the chip select signal with the pin state in the sampling result according to the switching clock frequency, and to align the address signal with the pin state in the sampling result according to the switching clock frequency.

16. The logic analysis and decoding apparatus according to claim 15, characterized in that, The sampling file includes multiple record lines arranged in chronological order, each record line recording one sampling result; the second alignment circuit includes a chip select signal alignment circuit, which is used to select, according to the switching clock frequency, the record line in which the pin state changes from the first state to the second state after the chip select signal is applied to the memory circuit block, as the current chip select line; the chip select signal alignment circuit is also used to obtain the time interval between two adjacent record lines, as the first chip select time, and to obtain the time interval between the record line in the sampling results before the current chip select line where the pin state changes from the first state to the second state and the current chip select line, as the second chip select time; the chip select signal alignment circuit is also used to calculate the difference between the first chip select time and the second chip select time, as the configuration time of the chip select signal.

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