A CMOS logic circuit based on GaN and carbon nanotubes and a preparation method thereof

Abstract

The application discloses a CMOS logic circuit based on GaN and carbon nanotubes and a preparation method thereof. The CMOS logic circuit is composed of a GaN n-type transistor and a carbon nanotube p-type transistor prepared on the same chip. A buffer layer, an electron conductive channel layer and a barrier layer are sequentially laminated on a substrate. The source, the drain and the gate structure of the GaN n-type transistor are located on the barrier layer, the gate is located on the gate structure, and the GaN n-type transistor is covered by a passivation layer. The carbon nanotube p-type transistor comprises a carbon nanotube channel and the drain and the source at both ends of the carbon nanotube channel. The gate dielectric layer and the gate are sequentially located on the carbon nanotube channel. The carbon nanotube p-type transistor is located on the passivation layer on the side or above the GaN n-type transistor. The CMOS logic circuit has a large saturated current density and a high working speed, can be used as a peripheral circuit of a GaN power device, realizes monolithic integration, effectively solves the inter-chip parasitic inductance problem caused by the Si circuit, and fully plays the performance advantages of the GaN power device.

Description

Technical Field

[0001] This invention relates to a CMOS logic circuit and its fabrication method, specifically to a CMOS logic circuit based on GaN and carbon nanotubes and its fabrication method, belonging to the field of microelectronic device technology. Background Technology

[0002] GaN power devices offer excellent performance and are widely used in power electronic circuits, having already achieved commercial applications. Currently, silicon-based CMOS logic circuits are needed as peripheral circuits for GaN power devices, such as gate drive circuits, detection circuits, and control circuits. This multi-chip approach increases system size and design complexity, with inter-chip parasitic inductance effects reducing overall system stability. Therefore, researching CMOS peripheral circuits that can be monolithically integrated with GaN power devices is of great significance, as it facilitates the miniaturization of power electronic systems and more effectively utilizes the performance of GaN power devices.

[0003] CMOS logic circuits require both n-type and p-type transistors. While GaN n-type transistors are readily fabricated, high-performance GaN p-type transistors are difficult to fabricate due to the high ionization energy and low hole mobility of the acceptor doped atoms in GaN.

[0004] The Hong Kong University of Science and Technology has fabricated an enhancement-type GaN p-type transistor using a grooved gate structure. This device can be monolithically integrated with a GaN n-type transistor via its gate. [1][2] The carrier mobility of this device is approximately 10 cm⁻¹. 2 / Vs, therefore the saturation current is low, less than 10mA / mm.

[0005] The Swiss Federal Institute of Technology in Lausanne (EPFL) has fabricated a polycrystalline diamond-based p-type transistor on a GaN chip, enabling monolithic integration with GaN n-type transistors. However, polycrystalline diamond p-type transistors are depletion-mode devices with low saturation current density, making them difficult to apply practically. [3] .

[0006] There is an urgent need for a technical solution that can simultaneously fabricate high current density n-type transistors and high current density p-type transistors on GaN chips in order to achieve the goal of fabricating CMOS logic circuits on GaN chips.

[0007] References:

[0008] [1] Zheyang Zheng, Wenjie Song, Li Zhang, Song Yang, Han Xu, Roy K.-Y. Wong, Jin Wei and Kevin J. Chen, “Enhancement-Mode GaN p-Channel MOSFETs for Power Integration,” 2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2020, pp. 525-528, doi:10.1109 / ISPSD46842.2020.9170081.

[0009] [2] Li Zhang, Zheyang Zheng, Yan Cheng, Yat Hon Ng, Sirui Feng, Wenjie Song, Tao Chen, and Kevin J. Chen, “SiN / in-situ-GaON Staggered Gate Stack on p-GaN for Enhanced Stability in Buried-Channel GaN p-FETs,” 2021 IEEE International Electron Devices Meeting (IEDM), 2021, pp. 5.3.1-5.3.4, doi:10.1109 / IEDM19574.2021.9720653.

[0010] [3] R. Soleimanzadeh, M. Naamoun, R. A. Khadar, R. van Erp and E. Matioli, “H-Terminated Polycrystalline Diamond p-Channel Transistors on GaN-on-Silicon,” in IEEE Electron Device Letters, vol. 41, no. 1, pp. 119-122, Jan. 2020, doi:10.1109 / LED.2019.2953245. Summary of the Invention

[0011] The purpose of this invention is to provide a technique for fabricating CMOS logic circuits on GaN chips, in order to solve the problem of low speed of GaN CMOS logic circuits caused by the low saturation current density of GaN p-type transistors in the prior art.

[0012] To achieve the above technical objectives, the present invention adopts the following technical solution:

[0013] A CMOS logic circuit based on GaN and carbon nanotubes comprises an enhancement-mode GaN n-type transistor and an enhancement-mode carbon nanotube p-type transistor fabricated on the same chip. It includes a substrate and, from bottom to top, a buffer layer, an electronic conduction channel layer, and a barrier layer stacked on the substrate. The source, drain, and gate structures of the GaN n-type transistor are located on the barrier layer, wherein the space between the source and gate structures, between the gate structure and the drain, and the periphery of the source, drain, and gate structures are covered by a first passivation layer. The gate of the GaN n-type transistor is located above the gate structure. A second passivation layer covers the GaN n-type transistor. The carbon nanotube p-type transistor includes a carbon nanotube channel located on the second passivation layer and its drain and source at both ends. The gate dielectric layer and gate of the carbon nanotube p-type transistor are sequentially arranged on the carbon nanotube channel. The carbon nanotube p-type transistor is located on the second passivation layer to the side of the GaN n-type transistor, or on the second passivation layer above the GaN n-type transistor. When the carbon nanotube p-type transistor is located on the GaN n-type transistor... When the second passivation layer is on the side of an n-type transistor, ion implantation or etching is required to isolate the GaN n-type transistor from the carbon nanotube p-type transistor.

[0014] In the aforementioned CMOS logic circuit based on GaN and carbon nanotubes, the substrate can be a Si substrate, a SiC substrate, a sapphire substrate, a GaN substrate, etc.

[0015] In the aforementioned CMOS logic circuit based on GaN and carbon nanotubes, the buffer layer can be selected from one or more of the following materials: GaN, AlN, InGaN, AlGaN, InAlGaN, etc.

[0016] In the aforementioned CMOS logic circuit based on GaN and carbon nanotubes, the electronic conductive channel layer can be made of materials such as GaN, InGaN, AlGaN, and InAlGaN.

[0017] In the aforementioned CMOS logic circuit based on GaN and carbon nanotubes, the barrier layer can be selected from one or more of GaN, AlN, AlGaN, InGaN, InAlGaN, etc., and generate a two-dimensional electron gas through polarization effect.

[0018] In the aforementioned CMOS logic circuit based on GaN and carbon nanotubes, the gate structure can be a gate p-GaN cap layer, a MIS structure, etc., to realize an enhancement-mode GaN n-type transistor.

[0019] In the aforementioned CMOS logic circuit based on GaN and carbon nanotubes, the first passivation layer can be made of materials such as SiO2, Si3N4, and AlN; the second passivation layer can be made of materials such as SiO2 and SOG.

[0020] In the aforementioned CMOS logic circuit based on GaN and carbon nanotubes, the carbon nanotube channel of the carbon nanotube p-type transistor can be a network-like carbon nanotube thin film or an array of carbon nanotube thin films.

[0021] In the aforementioned CMOS logic circuit based on GaN and carbon nanotubes, the gate dielectric layer of the carbon nanotube p-type transistor can be made of insulating dielectric materials with high dielectric constant (high k), such as HfO2 and ZrO2.

[0022] Through-holes can be formed in the second passivation layer by etching, and metal can be deposited to form a metal interconnect structure connecting the gate, source, and drain of the device, realizing CMOS circuits with various logic functions. For example, the gate of a GaN n-type transistor can be connected to the gate of a carbon nanotube p-type transistor, with an external input signal V. in Connect the drain of the GaN n-type transistor to the drain of the carbon nanotube p-type transistor, and connect an external output signal V. out The source of the carbon nanotube p-type transistor is connected to an external power supply voltage V. dd Connect the source of the GaN n-type transistor to GND; thereby realizing a CMOS logic circuit with inverter function.

[0023] This invention also provides a method for fabricating the above-mentioned CMOS logic circuit based on GaN and carbon nanotubes, comprising the following steps:

[0024] 1) A buffer layer, an electronic conductive channel layer, and a barrier layer are sequentially grown on the substrate;

[0025] 2) Forming the gate structure of an enhancement-mode GaN n-type transistor;

[0026] 3) A first passivation layer is grown on the barrier layer and the gate structure, and then the first passivation layer is etched to form grooves for depositing the source, drain and gate of the GaNn transistor.

[0027] 4) Electrode metal is deposited in the corresponding grooves formed in step 3) to form the source and drain electrodes;

[0028] 5) If the designed carbon nanotube p-type transistor is located to the side of the GaN n-type transistor, proceed to step 6); if the designed carbon nanotube p-type transistor is located above the GaN n-type transistor, skip step 6) and proceed directly to step 7).

[0029] 6) Forming device isolation between GaN n-type transistors and carbon nanotube p-type transistors;

[0030] 7) Grow gate metal on the gate structure to form the gate of a GaN n-type transistor;

[0031] 8) Deposit a second passivation layer on the overall structure and perform planarization treatment;

[0032] 9) Carbon nanotube channels are fabricated on the second passivation layer;

[0033] 10) Electrode metals are deposited at both ends of the carbon nanotube channel to form the drain and source of the carbon nanotube p-type transistor;

[0034] 11) A high-k insulating dielectric material is grown on the carbon nanotube channel between the drain and source of a carbon nanotube p-type transistor to form the gate dielectric layer of the carbon nanotube p-type transistor.

[0035] 12) A gate metal is grown on the gate dielectric layer of a carbon nanotube p-type transistor to form the gate of the carbon nanotube p-type transistor.

[0036] 13) Etch the second passivation layer to form vias above the source, drain and gate of the GaN n-type transistor, and deposit metal to form a metal interconnect structure.

[0037] Step 6) above can be performed to form device isolation using the following methods: Ion implantation is performed on the first passivation layer region on the side of the GaN n-type transistor. One or more combinations of F, N, B, Ar, and Fe ions can be used to form a device isolation region by the first passivation layer and the barrier layer and electron conduction channel layer below it; or, the first passivation layer region on the side of the GaN n-type transistor is etched away to remove the first passivation layer and the barrier layer and electron conduction channel layer below it, so that the two-dimensional electron gas (2DEG) disappears.

[0038] Since carbon nanotube p-type transistors have a higher saturation current density than GaN p-type transistors, the CMOS logic circuit based on GaN and carbon nanotubes in this invention can have a faster switching speed.

[0039] Furthermore, variations in parameters such as length, thickness, and doping concentration of different regions in the aforementioned CMOS logic circuits fall within the scope of this invention, depending on different design requirements and fabrication processes. It is worth noting that the focus of this invention is on combining carbon nanotube p-type transistors with high saturation current densities and GaN n-type transistors to construct CMOS logic circuits. It is understood that other structures and variations are possible without departing from the essence and spirit of this invention; for example, the gate of the GaN n-type transistor can have structures other than those shown in the embodiments of this invention. Moreover, different examples, structures, and processes can be combined to achieve the same purpose.

[0040] The beneficial effects of this invention are:

[0041] This invention provides a CMOS logic circuit based on GaN and carbon nanotubes and its fabrication method. The GaN n-type transistors and carbon nanotube p-type transistors formed by this method exhibit high saturation current densities, resulting in a CMOS logic circuit with higher operating speed. This GaN and carbon nanotube-based CMOS logic circuit can replace the Si-based CMOS logic circuits currently used in power electronic circuits as peripheral circuits for GaN power devices, achieving monolithic integration and effectively solving the inter-chip parasitic inductance problem caused by Si circuits, thereby fully leveraging the performance advantages of GaN power devices. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of the structure completed in step 1 of embodiment 1.

[0043] Figure 2 This is a schematic diagram of the structure completed in step 2 of embodiment 1.

[0044] Figure 3 This is a schematic diagram of the structure completed in step 3 of embodiment 1.

[0045] Figure 4 This is a schematic diagram of the structure completed in step 4 of Example 1.

[0046] Figure 5 This is a schematic diagram of the structure completed in step 5 of embodiment 1.

[0047] Figure 6 This is a schematic diagram of the structure completed in step 6 of Example 1.

[0048] Figure 7 This is a schematic diagram of the structure completed in step 7 of Example 1.

[0049] Figure 8 This is a schematic diagram of the structure completed in step 8 of Example 1.

[0050] Figure 9This is a schematic diagram of the structure completed in step 9 of Example 1.

[0051] Figure 10 This is a schematic diagram of the structure completed in step 10 of Example 1.

[0052] Figure 11 This is a schematic diagram of the structure completed in step 11 of embodiment one.

[0053] Figure 12 This is a schematic diagram of the structure completed in step 12 of Example 1.

[0054] Figure 13 This is a schematic diagram of the structure completed in step 13 of Example 1.

[0055] Figure 14 This is a cross-sectional view of the GaN and carbon nanotube-based CMOS device fabricated in Example 1.

[0056] Figure 15 This is a cross-sectional view of the structure of a CMOS device based on GaN and carbon nanotubes provided in Embodiment 2 of the present invention. Detailed Implementation

[0057] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0058] Example 1

[0059] This embodiment fabricates a CMOS device based on GaN and carbon nanotubes, the structure of which is as follows: Figure 14As shown, it includes: a substrate 1, which can be a Si substrate, SiC substrate, sapphire substrate, GaN substrate, etc.; a buffer layer 2 that can reduce device leakage current and increase breakdown voltage, which can be one or more of GaN, AlN, InGaN, AlGaN, InAlGaN, etc.; an electronic conductive channel layer 3 that provides an electronic conductive channel, which can be GaN, InGaN, AlGaN, InAlGaN, etc.; a barrier layer 4 that generates a two-dimensional electron gas through polarization effect, which can be one or more of GaN, AlN, AlGaN, InGaN, InAlGaN, etc.; a gate p-GaN cap layer 5a that depletes the two-dimensional electron gas; first passivation layers 6a, 6b, 6c and 6d used as passivation layers on the surface of GaN n-type transistors, which can be made of SiO2, Si3N4, AlN, etc.; a GaN n-type transistor source 7; a GaN n-type transistor drain 8; a device isolation region 9 used to isolate the GaN n-type transistor from the carbon nanotube p-type transistor; GaN The n-type transistor gate 10; the second passivation layer 11, which can be made of materials such as SiO2 or SOG, is used to provide a substrate for the fabrication of the carbon nanotube p-type transistor; the carbon nanotube channel 12 of the carbon nanotube p-type transistor, which can be made of a network of carbon nanotube films or an array of carbon nanotube films; the carbon nanotube p-type transistor drain 13; the carbon nanotube p-type transistor source 14; the carbon nanotube p-type transistor gate dielectric layer 15, which can be made of materials with high dielectric constant (high k) such as HfO2 or ZrO2; the carbon nanotube p-type transistor gate 16; and interconnecting or connecting metals 17a, 17b, 17c, and 17d.

[0060] The preparation steps are as follows:

[0061] 1. A buffer layer 2, a channel layer 3, a barrier layer 4, and a p-GaN cap layer 5 are sequentially epitaxially grown on substrate 1, as follows: Figure 1 As shown;

[0062] 2. Etch the p-GaN cap layer 5 to form the gate p-GaN cap layer 5a of the GaN n-type transistor, as shown below. Figure 2 As shown;

[0063] 3. A first passivation layer 6 is grown on the barrier layer 4 and the gate p-GaN cap layer 5a, such as... Figure 3 As shown;

[0064] 4. Etch the first passivation layer 6 to form four separate parts 6a, 6b, 6c, and 6d, as shown. Figure 4 As shown;

[0065] 5. Electrode metal is deposited on the barrier layer 4 to form the source 7 and drain 8 of the GaN n-type transistor, such as... Figure 5 As shown, the source 7 of the GaN n-type transistor is embedded in the groove formed between the two parts of the first passivation layer 6a and 6b, and the drain 8 of the GaN n-type transistor is embedded in the groove formed between the two parts of the first passivation layer 6c and 6d.

[0066] 6. A device isolation region 9 is formed between the GaN n-type transistor and the carbon nanotube p-type transistor by fluorine ion implantation, such as... Figure 6 As shown, the isolation region 9 is located in the first passivation layer 6d and in the barrier layer 4 and the channel layer 3 below it, and is used for device isolation between GaN n-type transistors and carbon nanotube p-type transistors.

[0067] 7. A gate metal is grown on the gate p-GaN cap layer 5a to form the gate 10 of the GaN n-type transistor, as shown below. Figure 7 As shown;

[0068] 8. A second passivation layer 11 is deposited on the above-described overall structure and planarized to form the substrate required for fabricating carbon nanotube p-type transistors, such as... Figure 8 As shown;

[0069] 9. Carbon nanotubes are fabricated on the second passivation layer 11 to form the carbon nanotube channel 12 of the carbon nanotube p-type transistor, such as... Figure 9 As shown;

[0070] 10. Electrode metals are deposited at both ends of the carbon nanotube channel 12 to form the drain 13 and source 14 of the carbon nanotube p-type transistor, as shown below. Figure 10 As shown;

[0071] 11. A high-k insulating dielectric material is grown on the carbon nanotube channel 12 between the drain 13 and source 14 of the carbon nanotube p-type transistor to form the gate dielectric layer 15 of the carbon nanotube p-type transistor, such as... Figure 11 As shown;

[0072] 12. A gate metal is grown on the gate dielectric layer 15 of the carbon nanotube p-type transistor to form the gate 16 of the carbon nanotube p-type transistor, as shown below. Figure 12 As shown;

[0073] 13. Etch the second passivation layer 11 to form a via above the source 7, drain 8, and gate 10 of the GaN n-type transistor, such as... Figure 13 As shown;

[0074] 14. Deposit metals to form the source interconnect metal 17a and gate interconnect metal 17b of the GaN n-type transistor, the interconnect metal 17c between the drain of the GaN n-type transistor and the drain of the carbon nanotube p-type transistor, and the source interconnect metal 17d of the carbon nanotube p-type transistor, thus obtaining a CMOS device based on GaN and carbon nanotubes, such as... Figure 14 As shown.

[0075] If the gate interconnect metal 17b is connected to the gate 16 of the carbon nanotube p-type transistor via other connections, and an external input signal V is connected... in The interconnect metal 17c connects the drain 8 of the GaN n-type transistor to the drain 13 of the carbon nanotube p-type transistor, and externally outputs a signal V. out The source electrode is connected to an external power supply voltage V via a metal 17d. dd The source electrode is connected to the external GND via metal 17a. The CMOS logic circuit thus constructed can implement the function of a CMOS inverter.

[0076] Example 2

[0077] This embodiment fabricates a second CMOS device based on GaN and carbon nanotubes, with the structure as follows: Figure 15 As shown. The CMOS device structure in this embodiment differs from that in Embodiment 1. In this embodiment, the carbon nanotube p-type transistor is positioned above the GaN n-type transistor, and no additional device isolation is required between them. Other structures and effects are consistent with the embodiment.

[0078] Etching is performed on the periphery of the carbon nanotube p-type transistor to form vias above the source 7, drain 8, and gate 10 of the GaN n-type transistor. Then, connecting metal is deposited to form a CMOS logic circuit.

Claims

1. A CMOS logic circuit based on GaN and carbon nanotubes, comprising GaN n-type transistors and carbon nanotube p-type transistors fabricated on the same chip, including a substrate and a buffer layer, an electronic conduction channel layer, and a barrier layer stacked sequentially from bottom to top on the substrate; the source, drain, and gate structures of the GaN n-type transistor are located on the barrier layer, wherein the space between the source and gate structures, between the gate structure and the drain, and the periphery of the source, drain, and gate structures are covered by a first passivation layer; the gate of the GaN n-type transistor is located above the gate structure; a second passivation layer covers the GaN n-type transistor; the carbon nanotube p-type transistor includes a carbon nanotube channel located on the second passivation layer and its drain and source at both ends, wherein the gate dielectric layer and the gate of the carbon nanotube p-type transistor are sequentially arranged on the carbon nanotube channel; the carbon nanotube p-type transistor is located on the second passivation layer on the side of the GaN n-type transistor, or on the second passivation layer above the GaN n-type transistor; when the carbon nanotube p-type transistor is located on the GaN n-type transistor, the second passivation layer is used to further define the structure. When the second passivation layer is applied to the side of the n-type transistor, the GaN n-type transistor and the carbon nanotube p-type transistor are isolated by ion implantation or etching.

2. The CMOS logic circuit as described in claim 1, characterized in that, The substrate is a Si substrate, a SiC substrate, a sapphire substrate, or a GaN substrate.

3. The CMOS logic circuit as described in claim 1, characterized in that, The buffer layer is selected from one or more of the following materials: GaN, AlN, InGaN, AlGaN, and InAlGaN.

4. The CMOS logic circuit as described in claim 1, characterized in that, The material of the electronically conductive channel layer is GaN, InGaN, AlGaN, or InAlGaN.

5. The CMOS logic circuit as described in claim 1, characterized in that, The barrier layer is selected from one or more of the following materials: GaN, AlN, AlGaN, InGaN, InAlGaN, which generate a two-dimensional electron gas through polarization effect.

6. The CMOS logic circuit as described in claim 1, characterized in that, The first passivation layer is made of SiO2, Si3N4 or AlN, and the second passivation layer is made of SiO2 or SOG.

7. The CMOS logic circuit as described in claim 1, characterized in that, The carbon nanotube channel of the carbon nanotube p-type transistor is made of a network of carbon nanotube thin films or an array of carbon nanotube thin films.

8. The CMOS logic circuit as described in claim 1, characterized in that, The gate dielectric layer of the carbon nanotube p-type transistor is made of a high-k insulating dielectric material.

9. The CMOS logic circuit as described in claim 1, characterized in that, The CMOS logic circuit implements an inverter function, wherein the gate of the GaN n-type transistor is connected to the gate of the carbon nanotube p-type transistor, and an external input signal V is connected. in The drain of the GaN n-type transistor is connected to the drain of the carbon nanotube p-type transistor, and the external output signal V is connected. out The source external power supply voltage V of the carbon nanotube p-type transistor dd The source of a GaN n-type transistor is externally connected to GND.

10. The method for fabricating a CMOS logic circuit based on GaN and carbon nanotubes according to any one of claims 1 to 9, comprising the following steps: 1) A buffer layer, an electronic conductive channel layer, and a barrier layer are sequentially grown on the substrate; 2) Forming the gate structure of an enhancement-mode GaN n-type transistor; 3) A first passivation layer is grown on the barrier layer and the gate structure, and then the first passivation layer is etched to form grooves for depositing the source, drain and gate of the GaN n-type transistor. 4) Electrode metal is deposited in the corresponding grooves formed in step 3) to form the source and drain electrodes; 5) If the designed carbon nanotube p-type transistor is located to the side of the GaN n-type transistor, proceed to step 6); if the designed carbon nanotube p-type transistor is located above the GaN n-type transistor, skip step 6) and proceed directly to step 7). 6) Forming device isolation between GaN n-type transistors and carbon nanotube p-type transistors; 7) Grow gate metal on the gate structure to form the gate of a GaN n-type transistor; 8) Deposit a second passivation layer on the overall structure and perform planarization treatment; 9) Carbon nanotube channels are fabricated on the second passivation layer; 10) Electrode metals are deposited at both ends of the carbon nanotube channel to form the drain and source of the carbon nanotube p-type transistor; 11) A high-k insulating dielectric material is grown on the carbon nanotube channel between the drain and source of a carbon nanotube p-type transistor to form the gate dielectric layer of the carbon nanotube p-type transistor. 12) A gate metal is grown on the gate dielectric layer of a carbon nanotube p-type transistor to form the gate of the carbon nanotube p-type transistor. 13) Etch the second passivation layer to form vias above the source, drain and gate of the GaN n-type transistor, and deposit metal to form a metal interconnect structure.

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