A peak current control method for a switching power supply

Abstract

The application relates to the technical field of power supplies, and discloses a peak current control method of a switching power supply. When a load mutation sharply increases to cause an output voltage to drop, the output voltage is sampled, a voltage loop reference is dynamically adjusted to limit a driving pulse width of the switching power supply, the peak current is effectively limited, the current stress of a semiconductor device in a power circuit and the saturation risk of a magnetic core device are reduced, and the reliability of the switching power supply is improved.

Description

Technical Field

[0001] This invention relates to the field of power supply technology, and more specifically to a peak current control method for a switching power supply. Background Technology

[0002] In switching power supply applications, regulated switching power supplies typically employ voltage loop control to ensure system stability and dynamic response. To meet the product specification requirement of 25% dynamic load switching performance, the voltage loop response speed is often required to be relatively fast.

[0003] However, this can also lead to a sharp drop in output voltage when the load changes drastically, especially during the switching between no-load and full-load and the switching between full-load and short-circuit. The sudden increase in load causes the output voltage to drop significantly, and the driving pulse width of the switching power supply is controlled by the rapid response of the voltage loop, which in turn leads to a sharp increase in the peak current in the power circuit. This increases the difficulty of designing the magnetic core devices and selecting the semiconductor devices in the power circuit, and at the same time reduces the reliability of the switching power supply. Summary of the Invention

[0004] In view of this, the technical problem to be solved by the present invention is to propose a peak current control method that effectively limits the peak current in the power circuit when the load undergoes large dynamic changes, reduces the saturation risk of magnetic core devices and the current stress of semiconductor devices, and improves the reliability of the switching power supply.

[0005] The technical solution adopted in this invention is as follows:

[0006] A peak current control method for a switching power supply, the switching power supply including a control chip, the control chip having a preset voltage loop reference value, the peak current control method including:

[0007] Step S1: After the soft start of the switching power supply is completed, the output voltage of the switching power supply is sampled and compared with the first voltage protection threshold. If the output voltage is lower than the first voltage protection threshold, the control chip enters the first timing cycle. During the first timing cycle, the control chip outputs a control signal to adjust the output voltage so that the output voltage rises.

[0008] If the output voltage rises above the second voltage protection threshold during the first timing cycle, the timing is canceled, wherein the second voltage protection threshold is greater than the first voltage protection threshold; if the output voltage is still below the second voltage protection threshold at the end of the first timing cycle, then the following step S2 is executed.

[0009] Step S2: Modify the preset voltage loop reference value to the current output voltage so that the speed at which the drive pulse width of the switching power supply increases is reduced, and at the same time the control chip enters the second timing cycle.

[0010] During the second timing cycle, the voltage loop reference value is adjusted by the control chip to increase the voltage loop reference value at a preset slope, thereby increasing the output voltage. If the output voltage is lower than the second voltage protection threshold during a third timing cycle, the voltage loop reference value is modified to the current output voltage after the third timing cycle ends, until the second timing cycle ends. If the output voltage recovers to above the second voltage protection threshold during the second timing cycle, the timing is canceled. If the output voltage is still lower than the second voltage protection threshold after the second timing cycle ends, the control chip controls the switching power supply to stop working and soft-starts again after a fourth timing cycle, wherein the second timing cycle is longer than the third timing cycle.

[0011] Furthermore, during soft start-up of the switching power supply, peak current control is not performed.

[0012] Furthermore, after the switching power supply is soft-started, the output voltage of the switching power supply is controlled by the voltage loop, and the switching power supply outputs at the rated output voltage.

[0013] Furthermore, the voltage loop reference value corresponds one-to-one with the output voltage and has a linear relationship.

[0014] Furthermore, the third timing cycle is set to one or more switching cycles.

[0015] Furthermore, both the first voltage protection threshold and the second voltage protection threshold are less than the rated output voltage.

[0016] Based on the above technical solution, compared with the prior art, the effective effects of the present invention are as follows:

[0017] (1) By sampling the output voltage, the voltage loop reference value is dynamically adjusted to limit the drive pulse width of the switching power supply, thereby effectively limiting the peak current, avoiding large dynamic false triggering circuit protection such as no-load and full-load switching, and having no effect on small dynamics, effectively ensuring the overall dynamic performance.

[0018] (2) The peak current is reduced, and the maximum working magnetic flux density of the magnetic devices in the power circuit is reduced, which is beneficial to the optimal design of the magnetic core device.

[0019] (3) The peak current is reduced, the current stress on the semiconductor devices in the power circuit is reduced, which is beneficial for the selection of semiconductor devices. Attached Figure Description

[0020] Figure 1 This is a control logic diagram for implementing a peak current control method proposed in this invention;

[0021] Figure 2 The waveform diagram shows the no-load to full-load test process under existing technology control.

[0022] Figure 3The waveform diagram shows the no-load to full-load experimental process obtained using the control method of this invention. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0024] This invention provides a peak current control method applied to a switching power supply. The switching power supply includes an output voltage sampling circuit and a digital control chip. The digital control chip has a preset voltage loop reference value Vref, a first timing period T1, a second timing period T2, a third timing period T3, a first voltage protection threshold Vf1 (hereinafter referred to as threshold Vf1), and a second voltage protection threshold Vf2 (hereinafter referred to as threshold Vf2), wherein threshold Vf2 > threshold Vf1.

[0025] refer to Figure 1 , Figure 1 The above is a control logic diagram for implementing the peak current control method proposed in this invention. The peak current control method of this invention includes the following steps:

[0026] Step S1: After the soft start of the switching power supply is completed, the output voltage Vo is controlled by the voltage loop to output the rated output voltage Vonom (hereinafter referred to as rated voltage Voonom). At this time, the voltage loop reference value Vref of the reference control module inside the digital control chip (hereinafter referred to as the chip) is the rated voltage Voonom. Subsequently, the output voltage sampling circuit starts to sample the output voltage Vo and outputs the sampled output voltage Vo to the ADC port (analog-to-digital conversion port) of the chip. The chip compares the output voltage Vo with the threshold Vf1 set inside the chip. When the output voltage Vo is lower than the threshold Vf1, the chip starts to enter the first timing cycle T1. During the first timing cycle T1, the output voltage Vo is automatically controlled by the loop to make the output voltage Vo gradually rise.

[0027] If the output voltage Vo recovers to the threshold Vf2 set internally by the chip within the first timing cycle T1, the timing is canceled and reset. If the output voltage Vo is still below the threshold Vf2 at the end of the first timing cycle T1, then the following step S2 is executed.

[0028] Step S2: The reference control module in the chip reduces the voltage loop reference value Vref to the current output voltage Vo, so as to reduce the rate at which the drive pulse width of the switching power supply increases, thereby reducing the peak current, and at the same time enters the second timing cycle T2.

[0029] During the second timing cycle T2, the voltage loop reference value Vref rises at a preset slope until it reaches the rated voltage reference K, at which point the second timing cycle T2 ends, where Vf2 ≤ K ≤ Vo. During the second timing cycle T2, the output voltage sampling circuit continuously monitors the output voltage Vo. If the output voltage Vo remains below the threshold Vf2 for a third timing cycle T3, the following step S3 is executed.

[0030] Step S3: After the third timing cycle T3, the reference control module will modify the voltage loop reference value Vref to the current output voltage Vo, until the second timing cycle T2 ends. If the output voltage Vo recovers to above the threshold Vf2 within the second timing cycle T2, the timing is canceled and reset; if the output voltage Vo is still below the threshold Vf2 at the end of the second timing cycle T2, the switching power supply stops working and soft-starts again after the fourth timing cycle T4.

[0031] refer to Figure 2 , Figure 3 , Figure 2 The waveform diagram shows the no-load to full-load test process under existing technology control. Figure 3 The waveform diagram of the no-load to full-load test process obtained by the control method of this invention is shown below. Figure 3 It is evident that the control method of this invention can effectively reduce the peak current of the power stage under large dynamic loads.

[0032] The above embodiments are merely preferred embodiments of the present invention. It should be noted that the above preferred embodiments should not be considered as limitations on the present invention. For those skilled in the art, the control methods of the above embodiments can achieve the functions through other solutions such as logic gate circuits and operational amplifiers. Without departing from the spirit and scope of the present invention, several improvements and modifications can be made, which are obvious from existing known technologies. These improvements and modifications should also be considered within the protection scope of the present invention, and will not be elaborated further here using embodiments.

Claims

1. A peak current control method for a switching power supply, the switching power supply including a control chip, the control chip having a preset voltage loop reference value, characterized in that, The peak current control method includes: Step S1: After the soft start of the switching power supply is completed, the output voltage of the switching power supply is sampled and the sampled output voltage is compared with the first voltage protection threshold. If the output voltage is lower than the first voltage protection threshold, the control chip enters the first timing cycle. During the first timing cycle, the control chip outputs a control signal to adjust the output voltage so that the output voltage increases. If the output voltage rises above the second voltage protection threshold during the first timing period, the timing is canceled, wherein the second voltage protection threshold is greater than the first voltage protection threshold; if the output voltage is still below the second voltage protection threshold at the end of the first timing period, then the following step S2 is executed. Step S2: Modify the preset voltage loop reference value to the current output voltage so that the speed at which the drive pulse width of the switching power supply increases is reduced, and the control chip enters the second timing cycle. During the second timing cycle, the control chip adjusts the voltage loop reference value to increase it at a preset slope, thereby increasing the output voltage. If the output voltage is lower than the second voltage protection threshold during a third timing cycle, the voltage loop reference value is modified to the current output voltage after the third timing cycle ends, until the second timing cycle ends. If the output voltage recovers to above the second voltage protection threshold during the second timing cycle, the timing is canceled. If the output voltage is still lower than the second voltage protection threshold after the second timing cycle ends, the control chip controls the switching power supply to stop working and soft-starts it again after a fourth timing cycle, wherein the second timing cycle is longer than the third timing cycle.

2. The peak current control method for a switching power supply according to claim 1, characterized in that: When the switching power supply is soft-started, the switching power supply does not perform peak current control.

3. The peak current control method for a switching power supply according to claim 1, characterized in that: After the switching power supply is soft-started, the output voltage of the switching power supply is controlled by a voltage loop, and the switching power supply outputs at the rated output voltage.

4. The peak current control method for a switching power supply according to claim 1, characterized in that: The voltage loop reference value corresponds one-to-one with the output voltage and has a linear relationship.

5. The peak current control method for a switching power supply according to claim 1, characterized in that: The third timing cycle is set to one or more switching cycles.

6. The peak current control method for a switching power supply according to claim 3, characterized in that: Both the first voltage protection threshold and the second voltage protection threshold are less than the rated output voltage.

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