A gate voltage bootstrap switch using nonlinear capacitance compensation

Abstract

The application discloses a gate voltage self-boosting switch using nonlinear capacitor compensation, which comprises a gate voltage self-boosting unit, a MOS sampling switch tube and a nonlinear capacitor compensation circuit. P The nonlinear error caused by the parasitic capacitor C P The nonlinear error caused by the parasitic capacitor C P The nonlinear error caused by the parasitic capacitor C

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design, and specifically relates to a gate voltage bootstrap switch that uses nonlinear capacitance compensation. Background Technology

[0002] With the rapid development of semiconductor integrated circuits, the digitization level of signal processing chips is constantly improving, and the requirements for converting analog signals into digital signals are constantly increasing. This requires analog-to-digital converters to have a higher sampling rate when sampling analog signals, which necessitates the use of gate voltage bootstrap switching circuits.

[0003] Traditional gate-voltage bootstrap switching circuits mainly consist of a main NMOS switch and a gate-voltage bootstrap circuit. While this structure can solve the nonlinear error problem caused by the variation of on-resistance with the input signal, the introduction of on-capacitance, which is also related to the input signal during sampling, can also cause nonlinear errors. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a gate voltage bootstrap switch employing nonlinear capacitance compensation. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] A gate voltage bootstrap switch employing nonlinear capacitance compensation includes:

[0006] The circuit includes a gate voltage bootstrap unit, a MOS sampling switch, and a nonlinear capacitor compensation circuit; among which...

[0007] The gate voltage bootstrap unit is used to control the MOS sampling switch to complete sampling during the sampling phase, thereby achieving the purpose of gate voltage bootstrap; during the hold phase, the gate voltage bootstrap unit is controlled by the hold clock signal CLKN to turn off the MOS sampling switch.

[0008] The MOS sampling switch is used to process the input signal V. in Perform sampling and preservation;

[0009] By selecting the parameters of the devices in the nonlinear capacitance compensation circuit, the parasitic capacitance C generated by the gate voltage bootstrap unit and the MOS sampling switch during the sampling phase is eliminated. P The resulting nonlinear error.

[0010] In one embodiment of the present invention, the gate voltage bootstrap unit includes:

[0011] The transistors consist of a first PMOS transistor M1, a first NMOS transistor M2, a second PMOS transistor M3, a second NMOS transistor M4, a third PMOS transistor M5, a third NMOS transistor M6, a fourth NMOS transistor M7, a fifth NMOS transistor M8, a sixth NMOS transistor M9, and a first capacitor C1; wherein,

[0012] The source of the first PMOS transistor M1 is connected to VDD, the gate of the first PMOS transistor M1 is connected to the drain of the third PMOS transistor M5 at a first node, and the drain of the first PMOS transistor M1 is connected to the first terminal of the first capacitor C1 at a second node.

[0013] The source of the first NMOS transistor M2 is grounded, the gate of the first NMOS transistor M2 is connected to the hold clock signal CLKN, and the drain of the first NMOS transistor M2 is connected to the second terminal of the first capacitor C1 at the third node.

[0014] The source of the second PMOS transistor M3 is connected to VDD, the gate of the second PMOS transistor M3 is connected to the sampling clock signal CLK, and the drain of the second PMOS transistor M3 is connected to the drain of the second NMOS transistor M4 at the fourth node.

[0015] The source of the second NMOS transistor M4 is connected to the third node, and the gate of the second NMOS transistor M4 is connected to the sampling clock signal CLK;

[0016] The source and substrate of the third PMOS transistor M5 are connected to the second node, and the gate of the third PMOS transistor M5 is connected to the fourth node.

[0017] The source of the third NMOS transistor M6 is connected to the third node, the gate of the third NMOS transistor M6 is connected to the first node, and the drain of the third NMOS transistor M6 is connected to the gate of the third PMOS transistor M5.

[0018] The source of the fourth NMOS transistor M7 is connected to the first node, the gate of the fourth NMOS transistor M7 is connected to VDD, and the drain of the fourth NMOS transistor M7 is connected to the source of the fifth NMOS transistor M8.

[0019] The gate of the fifth NMOS transistor M8 is connected to the hold clock signal CLKN, and the drain of the fifth NMOS transistor M8 is grounded.

[0020] The source of the sixth NMOS transistor M9 is connected to the input signal V. in The gate of the sixth NMOS transistor M9 is connected to the first node, and the drain of the sixth NMOS transistor M9 is connected to the source of the third NMOS transistor M6.

[0021] In one embodiment of the present invention, the MOS sampling switch includes: a switching NMOS transistor M10; wherein,

[0022] The source of the NMOS transistor M10 is connected to the input signal V. in The gate of the switching NMOS transistor M10 is connected to the first node, and the drain of the switching NMOS transistor M10 serves as the output terminal VOUT.

[0023] In one embodiment of the present invention, the nonlinear capacitance compensation circuit includes:

[0024] The seventh NMOS transistor NM1, the eighth NMOS transistor NM2, the ninth NMOS transistor NM3, the tenth NMOS transistor NM4, the eleventh NMOS transistor NM5, the twelfth NMOS transistor NM6, the thirteenth NMOS transistor NM7, and the fourteenth NMOS transistor NM8; the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, and the seventh resistor R7; among which,

[0025] The first end of the first resistor R1 is connected to an external fixed voltage V1, and the second end of the first resistor R1 is connected to the first end of the second resistor R2.

[0026] The second end of the second resistor R2 is connected to the first end of the third resistor R3;

[0027] The second end of the third resistor R3 is connected to the first end of the fourth resistor R4;

[0028] The second end of the fourth resistor R4 is connected to the first end of the fifth resistor R5;

[0029] The second end of the fifth resistor R5 is connected to the first end of the sixth resistor R6;

[0030] The second end of the sixth resistor R6 is connected to the first end of the seventh resistor R7;

[0031] The second terminal of the seventh resistor R7 is connected to an external fixed voltage V2;

[0032] The gates of the seventh NMOS transistor NM1, the eighth NMOS transistor NM2, the ninth NMOS transistor NM3, the tenth NMOS transistor NM4, the eleventh NMOS transistor NM5, the twelfth NMOS transistor NM6, the thirteenth NMOS transistor NM7, and the fourteenth NMOS transistor NM8 are interconnected and then connected to the third node.

[0033] The source and drain of the seventh NMOS transistor NM1 are connected to the first terminal of the first resistor R1;

[0034] The source and drain of the eighth NMOS transistor NM2 are connected to the first end of the second resistor R2;

[0035] The source and drain of the ninth NMOS transistor NM3 are connected to the first terminal of the third resistor R3;

[0036] The source and drain of the tenth NMOS transistor NM4 are connected to the first terminal of the fourth resistor R4;

[0037] The source and drain of the eleventh NMOS transistor NM5 are connected to the first terminal of the fifth resistor R5.

[0038] The source and drain of the twelfth NMOS transistor NM6 are connected to the first terminal of the sixth resistor R6;

[0039] The source and drain of the thirteenth NMOS transistor NM7 are connected to the first terminal of the seventh resistor R7;

[0040] The source and drain of the fourteenth NMOS transistor NM8 are connected to the second terminal of the seventh resistor R7.

[0041] In one embodiment of the present invention, during the sampling phase, the gate voltage bootstrap unit is controlled by the sampling clock signal CLK, which controls the MOS sampling switch to complete sampling, thereby achieving the purpose of gate voltage bootstrap. The corresponding working process includes:

[0042] When the hold clock signal CLKN is 0 and the sampling clock signal CLK is 1, the sampling phase begins. The third PMOS transistor M5 is turned on, while the first NMOS transistor M2 and the fifth NMOS transistor M8 are turned off. The voltage across the upper plate of the first capacitor C1 is transmitted through the third PMOS transistor M5 to the gate of the sixth NMOS transistor M9 and the gate of the switching NMOS transistor M10, causing the sixth NMOS transistor M9 and the switching NMOS transistor M10 to turn on. The input signal V... in The voltage is transmitted to the lower plate of the first capacitor C1 through the sixth NMOS transistor M9, causing the voltage on the upper plate of the first capacitor C1 to change. The changed voltage is then transmitted to the gate of the switching NMOS transistor M10 through the third PMOS transistor M5, thereby achieving gate voltage bootstrapping.

[0043] In one embodiment of the present invention, the voltage is changed to the VDD and the input signal V. in sum.

[0044] In one embodiment of the present invention, during the hold phase, the gate voltage bootstrap unit is controlled by the hold clock signal CLKN, causing the MOS sampling switch to be turned off. The corresponding working process includes:

[0045] When the hold clock signal CLKN is 1 and the sampling clock signal CLK is 0, the hold phase begins. The fourth NMOS transistor M7 and the fifth NMOS transistor M8 are turned on. The gate of the MOS sampling switch M10 is grounded through the fourth NMOS transistor M7 and the fifth NMOS transistor M8, thus turning off the MOS sampling switch M10.

[0046] In one embodiment of the present invention, the parasitic capacitance C P This includes: the sum of parasitic capacitances generated between the drain and substrate, and between the source and substrate, in the third NMOS transistor M6 and the MOS sampling switch M10; C P The expression is: Among them, C P0 Initially, the input signal V in Irrelevant capacitor, K r is the ratio coefficient of the capacitor to the input voltage corresponding to the rth order, and n is the order of the gate voltage bootstrap switch using nonlinear capacitor compensation.

[0047] In one embodiment of the present invention, by selecting the parameters of the devices in the nonlinear capacitance compensation circuit, the parasitic capacitance C generated by the gate voltage bootstrap unit and the MOS sampling switch during the sampling phase is eliminated. P The resulting nonlinear error and the corresponding working principle include:

[0048] The input signal V in The capacitance value from the input terminal to the AC ground in the nonlinear capacitor compensation circuit is C. n C n The expression is: Wherein, K′ r is the compensation coefficient of the nonlinear capacitor compensation circuit corresponding to the rth order, and n is the order of the gate voltage bootstrap switch using nonlinear capacitor compensation;

[0049] During the sampling phase, the parasitic capacitance C P The total capacitance of the nonlinear capacitor compensation circuit is C. a C a The expression is:

[0050]

[0051] By selecting the dimensions of the seventh NMOS transistor NM1 to the fourteenth NMOS transistor NM8 and the resistance values ​​of the first resistor R1 to the seventh resistor R7, K′ is made... r With the K r Equal to eliminate the parasitic capacitance C P With the input signal V in The relevant terms enable the elimination of nonlinear errors.

[0052] The beneficial effects of this invention are:

[0053] In the solution provided by this invention embodiment, a nonlinear capacitance compensation circuit is introduced to compensate for the parasitic capacitance C generated in the gate voltage bootstrap unit and the MOS sampling switch. P The resulting nonlinear error is compensated. In this embodiment of the invention, the parameters of the components in the nonlinear capacitance compensation circuit are selected such that the compensation coefficients of each order are equal to the proportional coefficients of the capacitance and input voltage corresponding to each order, thereby eliminating the corresponding terms and reducing the parasitic capacitance C. P The resulting nonlinear error can be eliminated. Attached Figure Description

[0054] Figure 1 This is a circuit schematic of a traditional gate voltage bootstrap switching circuit.

[0055] Figure 2 This is a circuit diagram of a gate voltage bootstrap switch using nonlinear capacitance compensation, provided as an embodiment of the present invention. Detailed Implementation

[0056] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0057] To facilitate understanding, a brief introduction to the traditional gate voltage bootstrap switching circuit will be given below.

[0058] For traditional gate-voltage bootstrap switching circuits, see Figure 1 It consists of a MOS sampling switch M10 and a gate voltage bootstrap unit; wherein, the gate voltage bootstrap unit includes: a first PMOS transistor M1, a first NMOS transistor M2, a second PMOS transistor M3, a second NMOS transistor M4, a third PMOS transistor M5, a third NMOS transistor M6, a fourth NMOS transistor M7, a fifth NMOS transistor M8, a sixth NMOS transistor M9 and a first capacitor C1.

[0059] Its working principle is as follows:

[0060] (1) When the circuit is in the sampling phase, CLK is high and CLKN is low. M4 is turned on, and the gate of M5 is grounded. When M5 is turned on, the gate voltages of M9 and M10 are raised. M8 and M2 are turned off, and M9 is turned on. The MOS sampling switch M10 is closed. The charge stored in the first capacitor C1 remains unchanged. C1 is connected to the gate-source terminal of the sampling switch M10, and the gate of the sampling switch M10 is raised to VDD+V. in The gate-source voltage of the MOS sampling switch M10 is VDD.

[0061] (2) When the circuit is in the holding phase, CLK is low, CLKN is high, M5 and M6 are turned on, and the gate of M4 is V. DD When M4 is off, M2 and sampling transistor M1 are off, MOS sampling switch M10 is off, the gate of M7 is grounded, M7 is on, and M10 is on. The first capacitor C1 is charged to V through M7 and M10. DD The first capacitor C1 stores a charge C1*V. DD The amount of electricity.

[0062] The on-resistance of the sampling switch in the sampling phase is shown in the following formula:

[0063]

[0064] Where, μ n C represents the carrier mobility. ox V is the gate capacitance per unit area of ​​the MOS sampling switch, W / L is the width-to-length ratio of the MOS sampling switch, and V is the gate capacitance per unit area of ​​the MOS sampling switch. GS V is the gate-source voltage of the sampling switch. TH This is the turn-on threshold voltage of the switching transistor.

[0065] Traditional gate-voltage bootstrap switching circuits, compared to general sampling switches, solve the problem of nonlinear errors introduced by the change in on-resistance with the input signal. However, sample-and-hold circuits contain not only on-resistance but also on-capacitance. The capacitance is also related to the input signal during sampling, which can also cause nonlinear errors.

[0066] To compensate for nonlinear errors caused by capacitance during sampling, this invention provides a gate-voltage bootstrap switch employing nonlinear capacitance compensation, building upon existing technologies. A nonlinear capacitance compensation circuit is added to the traditional gate-voltage bootstrap switch circuit to eliminate the parasitic capacitance C generated by the gate-voltage bootstrap unit and the MOS sampling switch during the sampling phase. P The purpose of addressing the resulting nonlinear error.

[0067] A gate voltage bootstrap switch employing nonlinear capacitance compensation includes:

[0068] The circuit includes a gate voltage bootstrap unit, a MOS sampling switch, and a nonlinear capacitor compensation circuit; among which...

[0069] The gate voltage bootstrap unit is used to control the MOS sampling switch to complete sampling during the sampling phase, thereby achieving the purpose of gate voltage bootstrap; during the hold phase, the gate voltage bootstrap unit is controlled by the hold clock signal CLKN to turn off the MOS sampling switch.

[0070] The MOS sampling switch is used to sample the input signal V. in Perform sampling and preservation;

[0071] By selecting the parameters of the devices in the nonlinear capacitance compensation circuit, the parasitic capacitance C generated by the gate voltage bootstrap unit and the MOS sampling switch during the sampling phase is eliminated. P The resulting nonlinear error.

[0072] This invention eliminates parasitic capacitance C by selecting parameters for the components in the nonlinear capacitance compensation circuit such that the compensation coefficients of each order are equal to the proportionality coefficients of the capacitance to the input voltage for each order. P The resulting nonlinear error can be eliminated.

[0073] For ease of understanding, the various modules of the embodiments of the present invention will be described below.

[0074] Gate-type bootstrap unit

[0075] Optionally, the gate voltage bootstrap unit includes:

[0076] The transistors consist of a first PMOS transistor M1, a first NMOS transistor M2, a second PMOS transistor M3, a second NMOS transistor M4, a third PMOS transistor M5, a third NMOS transistor M6, a fourth NMOS transistor M7, a fifth NMOS transistor M8, a sixth NMOS transistor M9, and a first capacitor C1; wherein,

[0077] The source of the first PMOS transistor M1 is connected to VDD, the gate of the first PMOS transistor M1 is connected to the drain of the third PMOS transistor M5 at the first node, and the drain of the first PMOS transistor M1 is connected to the first terminal of the first capacitor C1 at the second node.

[0078] The source of the first NMOS transistor M2 is grounded, the gate of the first NMOS transistor M2 is connected to the hold clock signal CLKN, and the drain of the first NMOS transistor M2 is connected to the second terminal of the first capacitor C1 at the third node.

[0079] The source of the second PMOS transistor M3 is connected to VDD, the gate of the second PMOS transistor M3 is connected to the sampling clock signal CLK, and the drain of the second PMOS transistor M3 is connected to the drain of the second NMOS transistor M4 at the fourth node.

[0080] The source of the second NMOS transistor M4 is connected to the third node, and the gate of the second NMOS transistor M4 is connected to the sampling clock signal CLK.

[0081] The source and substrate of the third PMOS transistor M5 are connected to the second node, and the gate of the third PMOS transistor M5 is connected to the fourth node.

[0082] The source of the third NMOS transistor M6 is connected to the third node, the gate of the third NMOS transistor M6 is connected to the first node, and the drain of the third NMOS transistor M6 is connected to the gate of the third PMOS transistor M5.

[0083] The source of the fourth NMOS transistor M7 is connected to the first node, the gate of the fourth NMOS transistor M7 is connected to VDD, and the drain of the fourth NMOS transistor M7 is connected to the source of the fifth NMOS transistor M8.

[0084] The gate of the fifth NMOS transistor M8 is connected to the hold clock signal CLKN, and the drain of the fifth NMOS transistor M8 is grounded;

[0085] The source of the sixth NMOS transistor M9 is connected to the input signal V. in The gate of the sixth NMOS transistor M9 is connected to the first node, and the drain of the sixth NMOS transistor M9 is connected to the source of the third NMOS transistor M6.

[0086] The gate voltage bootstrap unit functions as follows in the circuit: During the sampling phase, it is controlled by the sampling clock signal CLK, which controls the MOS sampling switch to complete the sampling, thus achieving gate voltage bootstrapping; during the hold phase, it is controlled by the hold clock signal CLKN, which turns off the MOS sampling switch. During the sampling phase, the gate voltage bootstrap unit ensures that the on-resistance is independent of the input signal, reducing the nonlinear error introduced by the on-resistance.

[0087] MOS sampling switch

[0088] Optionally, the MOS sampling switch includes: a switching NMOS transistor M10; wherein,

[0089] The source of the switching NMOS transistor M10 is connected to the input signal V. in The gate of the switching NMOS transistor M10 is connected to the first node, and the drain of the switching NMOS transistor M10 serves as the output terminal VOUT.

[0090] Optionally, during the sampling phase, the gate voltage bootstrap unit is controlled by the sampling clock signal CLK, which controls the MOS sampling switch to complete sampling, thereby achieving the purpose of gate voltage bootstrap. The corresponding working process includes:

[0091] When the holding clock signal CLKN is 0 and the sampling clock signal CLK is 1, the sampling phase begins. The third PMOS transistor M5 is turned on, while the first NMOS transistor M2 and the fifth NMOS transistor M8 are turned off. The voltage across the upper plate of the first capacitor C1 is transmitted through the third PMOS transistor M5 to the gate of the sixth NMOS transistor M9 and the gate of the switching NMOS transistor M10, causing the sixth NMOS transistor M9 and the switching NMOS transistor M10 to turn on. The input signal V... in The voltage is transmitted to the lower plate of the first capacitor C1 through the sixth NMOS transistor M9, causing the voltage on the upper plate of the first capacitor C1 to change. The changed voltage is then transmitted to the gate of the switching NMOS transistor M10 through the third PMOS transistor M5, thus achieving the purpose of gate voltage bootstrapping.

[0092] Optionally, the voltage can be changed to VDD and the input signal V. in sum.

[0093] Optionally, during the hold phase, the gate voltage bootstrap unit is controlled by the hold clock signal CLKN, causing the MOS sampling switch to be turned off. The corresponding operating process includes:

[0094] When the holding clock signal CLKN is 1 and the sampling clock signal CLK is 0, the holding phase begins. The fourth NMOS transistor M7 and the fifth NMOS transistor M8 are turned on. The gate of the MOS sampling switch M10 is grounded through the fourth NMOS transistor M7 and the fifth NMOS transistor M8, thus turning off the MOS sampling switch M10.

[0095] Reference Figure 2 The input signal comes from V in The input is at the terminal, and the output is from the VOUT terminal during the sampling phase. During this process, the gate voltage bootstrap unit and the MOS sampling switch will generate parasitic capacitance, which will introduce nonlinear errors.

[0096] Optional, parasitic capacitance C P This includes the sum of parasitic capacitances generated between the drain and substrate, and between the source and substrate, in the third NMOS transistor M6 and the MOS sampling switch M10; C P The expression is: Among them, C P0 Initially, the input signal V in Irrelevant capacitor, K r is the ratio coefficient of the capacitor to the input voltage corresponding to the r-th order, and n is the order of the gate voltage bootstrap switch using nonlinear capacitor compensation.

[0097] To make it easier to understand, let's take n=1 and n=2 as examples.

[0098] When n=1, parasitic capacitance

[0099] When n=2, parasitic capacitance

[0100] To eliminate the nonlinear error caused by parasitic capacitance, this invention introduces a nonlinear capacitance compensation circuit to eliminate the term in the parasitic capacitance that is related to the input signal. The nonlinear capacitance compensation circuit and its specific compensation principle are described below.

[0101] Nonlinear capacitor compensation circuit

[0102] The nonlinear capacitor compensation circuit includes:

[0103] The seventh NMOS transistor NM1, the eighth NMOS transistor NM2, the ninth NMOS transistor NM3, the tenth NMOS transistor NM4, the eleventh NMOS transistor NM5, the twelfth NMOS transistor NM6, the thirteenth NMOS transistor NM7, and the fourteenth NMOS transistor NM8; the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, and the seventh resistor R7; among which,

[0104] The first end of the first resistor R1 is connected to an external fixed voltage V1, and the second end of the first resistor R1 is connected to the first end of the second resistor R2.

[0105] The second end of the second resistor R2 is connected to the first end of the third resistor R3;

[0106] The second end of the third resistor R3 is connected to the first end of the fourth resistor R4;

[0107] The second terminal of the fourth resistor R4 is connected to the first terminal of the fifth resistor R5;

[0108] The second terminal of the fifth resistor R5 is connected to the first terminal of the sixth resistor R6;

[0109] The second terminal of the sixth resistor R6 is connected to the first terminal of the seventh resistor R7;

[0110] The second terminal of the seventh resistor R7 is connected to an external fixed voltage V2;

[0111] The gates of the seventh NMOS transistor NM1, the eighth NMOS transistor NM2, the ninth NMOS transistor NM3, the tenth NMOS transistor NM4, the eleventh NMOS transistor NM5, the twelfth NMOS transistor NM6, the thirteenth NMOS transistor NM7, and the fourteenth NMOS transistor NM8 are interconnected and then connected to the third node.

[0112] The source and drain of the seventh NMOS transistor NM1 are connected to the first terminal of the first resistor R1;

[0113] The source and drain of the eighth NMOS transistor NM2 are connected to the first terminal of the second resistor R2;

[0114] The source and drain of the ninth NMOS transistor NM3 are connected to the first terminal of the third resistor R3;

[0115] The source and drain of the tenth NMOS transistor NM4 are connected to the first terminal of the fourth resistor R4;

[0116] The source and drain of the eleventh NMOS transistor NM5 are connected to the first terminal of the fifth resistor R5;

[0117] The source and drain of the twelfth NMOS transistor NM6 are connected to the first terminal of the sixth resistor R6;

[0118] The source and drain of the thirteenth NMOS transistor NM7 are connected to the first terminal of the seventh resistor R7;

[0119] The source and drain of the fourteenth NMOS transistor NM8 are connected to the second terminal of the seventh resistor R7.

[0120] Optionally, by selecting the parameters of the devices in the nonlinear capacitance compensation circuit, the parasitic capacitance C generated by the gate voltage bootstrap unit and the MOS sampling switch during the sampling phase can be eliminated. P The resulting nonlinear error and the corresponding working principle include:

[0121] Input signal V in The capacitance value from the input terminal to the AC ground in the nonlinear capacitor compensation circuit is C. n C n The expression is: Wherein, K′ r is the compensation coefficient of the nonlinear capacitor compensation circuit corresponding to the rth order, and n is the order of the gate voltage bootstrap switch using nonlinear capacitor compensation.

[0122] During the sampling phase, the parasitic capacitance C P The total capacitance of the nonlinear capacitor compensation circuit is C. a C a The expression is:

[0123]

[0124] By selecting the dimensions of the seventh NMOS transistor NM1 to the fourteenth NMOS transistor NM8 and the resistance values ​​of the first resistor R1 to the seventh resistor R7, K′ is made possible. r With K r Equal, eliminating parasitic capacitance C P With input signal V in The relevant terms enable the elimination of nonlinear errors.

[0125] A nonlinear capacitor compensation circuit can be viewed as a pulse width modulation circuit. If the input terminal V in If grounded, all NMOS transistors from the seventh NMOS transistor NM1 to the fourteenth NMOS transistor NM8 will be turned off, and the voltage will change with the input voltage V. in Starting from zero, the voltage increases until it exceeds the threshold voltage of the NMOS transistor, at which point NM8 turns on, and V... in Then, NM7 turns on, followed by NM6, V in As the capacitance increases, eventually all NMOS transistors will turn on. When each NMOS transistor is turned on, its gate-to-AC ground capacitance is approximately WLC. OX Where W is the width of the NMOS transistor, L is the length of the NMOS transistor, and C is the width of the NMOS transistor. OX This is the gate capacitance per unit area of ​​the NMOS transistor. As the input voltage increases, the input signal V... in The capacitance C from the input terminal to the AC ground in the nonlinear capacitor compensation circuit. n The expression is:

[0126] Wherein, K′ r is the compensation coefficient of the nonlinear capacitor compensation circuit corresponding to the rth order, and n is the order of the gate voltage bootstrap switch using nonlinear capacitor compensation.

[0127] During the sampling phase, the parasitic capacitance C P The total capacitance C of the nonlinear capacitor compensation circuit a The expression is:

[0128]

[0129] As can be seen from the above, the best way to eliminate the parasitic capacitance terms related to the input signal is to make K′ r With the K r Equal. Therefore, by selecting the dimensions of the seventh NMOS transistor NM1 to the fourteenth NMOS transistor NM8 and the resistance values ​​of the first resistor R1 to the seventh resistor R7, K′ is made equal to... r With the K r Equal values ​​can eliminate parasitic capacitance C. P With input signal Vin The purpose of related items.

[0130] Let's continue with the example of n=1.

[0131] When n=1, C n =K′1V in .

[0132] C a =C p +C n =C P0 -K1V in +K′1V in .

[0133] To eliminate the parasitic capacitance C in the above equation P With input signal V in In the relevant section, when selecting the parameters of the components in the nonlinear capacitor compensation circuit, ensure that the specifications and dimensions of the seventh NMOS transistor NM1, the eighth NMOS transistor NM2, the ninth NMOS transistor NM3, the tenth NMOS transistor NM4, the eleventh NMOS transistor NM5, the twelfth NMOS transistor NM6, the thirteenth NMOS transistor NM7, and the fourteenth NMOS transistor NM8 are exactly the same; and that the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, and the seventh resistor R7 are the same. Then, select appropriate specifications and resistance values ​​so that K′1 is equal to K1, and set K′1V... in and This cancels out the nonlinear error caused by parasitic capacitance.

[0134] Let's take n=2 as an example to illustrate.

[0135] When n = 2, C n =K'1V in +K'2V in 2 .

[0136]

[0137] To eliminate the parasitic capacitance C in the above equation p With input signal V in Related items in V inEight uniform points are selected within the range to obtain the required compensation capacitance for these eight points. By adjusting the dimensions of the seventh NMOS transistor NM1, the eighth NMOS transistor NM2, the ninth NMOS transistor NM3, the tenth NMOS transistor NM4, the eleventh NMOS transistor NM5, the twelfth NMOS transistor NM6, the thirteenth NMOS transistor NM7, and the fourteenth NMOS transistor NM8, as well as the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, and the seventh resistor R7, the compensation capacitance for each point is made the same as the required compensation capacitance. Then, a linear fitting method can be used to obtain the relationship between the compensation capacitance and V. in Approximate second-order relation, i.e., C n =K'1V in +K'2V in 2 This eliminates the second-order nonlinear error caused by parasitic capacitance.

[0138] In the solution provided by this invention embodiment, a nonlinear capacitance compensation circuit is introduced to compensate for the parasitic capacitance C generated in the gate voltage bootstrap unit and the MOS sampling switch. P The resulting nonlinear error is compensated. In this embodiment of the invention, the parameters of the components in the nonlinear capacitance compensation circuit are selected such that the compensation coefficients of each order are equal to the proportional coefficients of the capacitance and input voltage corresponding to each order, thereby eliminating the corresponding terms and reducing the parasitic capacitance C. P The resulting nonlinear error can be eliminated.

[0139] It should be noted that, in the description of this invention, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0140] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0141] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A gate voltage bootstrap switch employing nonlinear capacitance compensation, characterized in that, include: The circuit includes a gate voltage bootstrap unit, a MOS sampling switch, and a nonlinear capacitor compensation circuit; among which... The gate voltage bootstrap unit is used to control the MOS sampling switch to complete sampling during the sampling phase, thereby achieving the purpose of gate voltage bootstrap; during the hold phase, the gate voltage bootstrap unit is controlled by the hold clock signal CLKN to turn off the MOS sampling switch. The MOS sampling switch is used to process the input signal V. in Perform sampling and preservation; By selecting the parameters of the devices in the nonlinear capacitance compensation circuit, the parasitic capacitance C generated by the gate voltage bootstrap unit and the MOS sampling switch during the sampling phase is eliminated. P The resulting nonlinear error; The gate voltage bootstrap unit includes: The transistors consist of a first PMOS transistor M1, a first NMOS transistor M2, a second PMOS transistor M3, a second NMOS transistor M4, a third PMOS transistor M5, a third NMOS transistor M6, a fourth NMOS transistor M7, a fifth NMOS transistor M8, a sixth NMOS transistor M9, and a first capacitor C1; wherein, The source of the first PMOS transistor M1 is connected to VDD, the gate of the first PMOS transistor M1 is connected to the drain of the third PMOS transistor M5 at a first node, and the drain of the first PMOS transistor M1 is connected to the first terminal of the first capacitor C1 at a second node. The source of the first NMOS transistor M2 is grounded, the gate of the first NMOS transistor M2 is connected to the hold clock signal CLKN, and the drain of the first NMOS transistor M2 is connected to the second terminal of the first capacitor C1 at the third node. The source of the second PMOS transistor M3 is connected to VDD, the gate of the second PMOS transistor M3 is connected to the sampling clock signal CLK, and the drain of the second PMOS transistor M3 is connected to the drain of the second NMOS transistor M4 at the fourth node. The source of the second NMOS transistor M4 is connected to the third node, and the gate of the second NMOS transistor M4 is connected to the sampling clock signal CLK; The source and substrate of the third PMOS transistor M5 are connected to the second node, and the gate of the third PMOS transistor M5 is connected to the fourth node. The source of the third NMOS transistor M6 is connected to the third node, the gate of the third NMOS transistor M6 is connected to the first node, and the drain of the third NMOS transistor M6 is connected to the gate of the third PMOS transistor M5. The source of the fourth NMOS transistor M7 is connected to the first node, the gate of the fourth NMOS transistor M7 is connected to VDD, and the drain of the fourth NMOS transistor M7 is connected to the source of the fifth NMOS transistor M8. The gate of the fifth NMOS transistor M8 is connected to the hold clock signal CLKN, and the drain of the fifth NMOS transistor M8 is grounded. The source of the sixth NMOS transistor M9 is connected to the input signal V. in The gate of the sixth NMOS transistor M9 is connected to the first node, and the drain of the sixth NMOS transistor M9 is connected to the source of the third NMOS transistor M6. The MOS sampling switch includes: a switching NMOS transistor M10; wherein... The source of the NMOS transistor M10 is connected to the input signal V. in The gate of the switching NMOS transistor M10 is connected to the first node, and the drain of the switching NMOS transistor M10 serves as the output terminal VOUT. The nonlinear capacitance compensation circuit includes: The seventh NMOS transistor NM1, the eighth NMOS transistor NM2, the ninth NMOS transistor NM3, the tenth NMOS transistor NM4, the eleventh NMOS transistor NM5, the twelfth NMOS transistor NM6, the thirteenth NMOS transistor NM7, and the fourteenth NMOS transistor NM8; the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, and the seventh resistor R7; among which, The first end of the first resistor R1 is connected to an external fixed voltage V1, and the second end of the first resistor R1 is connected to the first end of the second resistor R2. The second end of the second resistor R2 is connected to the first end of the third resistor R3; The second end of the third resistor R3 is connected to the first end of the fourth resistor R4; The second end of the fourth resistor R4 is connected to the first end of the fifth resistor R5; The second end of the fifth resistor R5 is connected to the first end of the sixth resistor R6; The second end of the sixth resistor R6 is connected to the first end of the seventh resistor R7; The second terminal of the seventh resistor R7 is connected to an external fixed voltage V2; The gates of the seventh NMOS transistor NM1, the eighth NMOS transistor NM2, the ninth NMOS transistor NM3, the tenth NMOS transistor NM4, the eleventh NMOS transistor NM5, the twelfth NMOS transistor NM6, the thirteenth NMOS transistor NM7, and the fourteenth NMOS transistor NM8 are interconnected and then connected to the third node. The source and drain of the seventh NMOS transistor NM1 are connected to the first terminal of the first resistor R1; The source and drain of the eighth NMOS transistor NM2 are connected to the first end of the second resistor R2; The source and drain of the ninth NMOS transistor NM3 are connected to the first terminal of the third resistor R3; The source and drain of the tenth NMOS transistor NM4 are connected to the first terminal of the fourth resistor R4; The source and drain of the eleventh NMOS transistor NM5 are connected to the first terminal of the fifth resistor R5. The source and drain of the twelfth NMOS transistor NM6 are connected to the first terminal of the sixth resistor R6; The source and drain of the thirteenth NMOS transistor NM7 are connected to the first terminal of the seventh resistor R7; The source and drain of the fourteenth NMOS transistor NM8 are connected to the second terminal of the seventh resistor R7.

2. A gate voltage bootstrap switch employing nonlinear capacitance compensation according to claim 1, characterized in that, During the sampling phase, the gate voltage bootstrap unit is controlled by the sampling clock signal CLK, which controls the MOS sampling switch to complete sampling, thereby achieving the purpose of gate voltage bootstrap. The corresponding working process includes: When the hold clock signal CLKN is 0 and the sampling clock signal CLK is 1, the sampling phase begins. The third PMOS transistor M5 is turned on, while the first NMOS transistor M2 and the fifth NMOS transistor M8 are turned off. The voltage across the upper plate of the first capacitor C1 is transmitted through the third PMOS transistor M5 to the gate of the sixth NMOS transistor M9 and the gate of the switching NMOS transistor M10, causing the sixth NMOS transistor M9 and the switching NMOS transistor M10 to turn on. The input signal V... in The voltage is transmitted to the lower plate of the first capacitor C1 through the sixth NMOS transistor M9, causing the voltage on the upper plate of the first capacitor C1 to change. The changed voltage is then transmitted to the gate of the switching NMOS transistor M10 through the third PMOS transistor M5, thereby achieving gate voltage bootstrapping.

3. A gate voltage bootstrap switch employing nonlinear capacitance compensation according to claim 2, characterized in that, The voltage change is VDD and the input signal V in sum.

4. A gate voltage bootstrap switch employing nonlinear capacitance compensation according to claim 1, characterized in that, During the hold phase, the gate voltage bootstrap unit is controlled by the hold clock signal CLKN, causing the MOS sampling switch to be turned off. The corresponding working process includes: When the hold clock signal CLKN is 1 and the sampling clock signal CLK is 0, the hold phase begins. The fourth NMOS transistor M7 and the fifth NMOS transistor M8 are turned on. The gate of the MOS sampling switch M10 is grounded through the fourth NMOS transistor M7 and the fifth NMOS transistor M8, thus turning off the MOS sampling switch M10.

5. A gate voltage bootstrap switch employing nonlinear capacitance compensation according to claim 1, characterized in that, The parasitic capacitance C P This includes: the sum of parasitic capacitances generated between the drain and substrate, and between the source and substrate, in the third NMOS transistor M6 and the MOS sampling switch M10; C P The expression is: Where CP0 is the capacitor initially independent of the input signal Vin, and K r is the ratio coefficient of the capacitor to the input voltage corresponding to the rth order, and n is the order of the gate voltage bootstrap switch using nonlinear capacitor compensation.

6. A gate voltage bootstrap switch employing nonlinear capacitance compensation according to claim 5, characterized in that, The parasitic capacitance C generated by the gate voltage bootstrap unit and the MOS sampling switch during the sampling phase is eliminated by selecting the parameters of the devices in the nonlinear capacitance compensation circuit. P The resulting nonlinear error and the corresponding working principle include: The input signal V in The capacitance value from the input terminal to the AC ground in the nonlinear capacitor compensation circuit is Cn, and the expression for Cn is: ;in, is the compensation coefficient of the nonlinear capacitor compensation circuit corresponding to the rth order, and n is the order of the gate voltage bootstrap switch using nonlinear capacitor compensation; During the sampling phase, the parasitic capacitance C P The total capacitance of the nonlinear capacitor compensation circuit is C. a C a The expression is: ； By selecting the dimensions of the seventh NMOS transistor NM1 to the fourteenth NMOS transistor NM8 and the resistance values ​​of the first resistor R1 to the seventh resistor R7, the... With the Equal to eliminate the parasitic capacitance C P With the input signal V in The relevant terms enable the elimination of nonlinear errors.

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