A level shifting circuit

Abstract

The application discloses a level shift circuit, and relates to the technical field of microelectronics, and comprises a pulse generating circuit, a level shift circuit electrically connected with the pulse generating circuit and comprising a plurality of transistors, and an output signal acquisition unit which is responsive to a first pulse signal and a second pulse signal. The application has the characteristics of low delay, low static power consumption and anti-noise.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology, and specifically relates to a level shifting circuit. Background Technology

[0002] Switching power supply chips are widely used in the industry due to their high power density, high efficiency, high reliability and low cost. In order to further reduce costs and chip size, switching power supply chips are constantly developing towards higher switching frequencies.

[0003] Level shifting circuits are crucial in switching power supply chips, connecting different voltage domains. Their conversion of signals from low to high voltage domains introduces additional delay. Furthermore, when switching power supply chips operate at high switching frequencies, the rate of change of the switching node VSW can reach tens of V / ns. Such high dVSW / dt noise can couple to the high-side floating power rail through external bootstrap capacitors, easily causing the level shifting circuit to output incorrect logic signals.

[0004] Therefore, the transmission speed and reliability of level shifting circuits are among the main challenges in achieving high-frequency switching power supply chips. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a level shifting circuit. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] In a first aspect, the present invention provides a level shifting circuit, comprising:

[0007] A pulse generation circuit is used to generate a first pulse signal and a second pulse signal.

[0008] The level shifting circuit, electrically connected to the pulse generation circuit, includes multiple transistors and acquires an output signal in response to a first pulse signal and a second pulse signal.

[0009] The beneficial effects of this invention are:

[0010] The present invention provides a level shifting circuit, comprising a pulse generating circuit and a level shifting circuit. The pulse generating circuit is used to generate a first pulse signal and a second pulse signal. The level shifting circuit is electrically connected to the pulse generating circuit and includes multiple transistors. In response to the first pulse signal and the second pulse signal, it acquires an output signal. It features low delay, low static power consumption, and noise immunity.

[0011] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0012] Figure 1This is a schematic diagram of a pulse generation circuit provided in an embodiment of the present invention;

[0013] Figure 2 This is a schematic diagram of a level shifting circuit provided in an embodiment of the present invention;

[0014] Figure 3 This is a simulation waveform diagram of the rise delay of the level shifting circuit provided in the embodiment of the present invention;

[0015] Figure 4 This is a simulation waveform diagram of the fall delay of the level shifting circuit provided in the embodiment of the present invention;

[0016] Figure 5 This is a simulation waveform diagram of the level shifting circuit provided in the embodiment of the present invention under the condition that the floating power rail switching speed is 100V / ns. Detailed Implementation

[0017] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0018] Please see Figures 1-2 As shown, Figure 1 This is a schematic diagram of a pulse generation circuit provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of a level shifting circuit provided in an embodiment of the present invention. The level shifting circuit provided by the present invention includes:

[0019] A pulse generation circuit is used to generate a first pulse signal and a second pulse signal.

[0020] The level shifting circuit, electrically connected to the pulse generation circuit, includes multiple transistors and acquires an output signal in response to a first pulse signal and a second pulse signal.

[0021] In an optional embodiment of the present invention, please continue to refer to Figure 1 As shown, the pulse generation circuit includes the pulse generation circuit input terminal IN, the first branch, and the second branch.

[0022] The first branch includes a first NAND gate INV1, a first branch transistor MP1, a first branch transistor MN1, a first capacitor C1, a first branch NOR gate NOR1, and the first output terminal PR of the pulse generation circuit.

[0023] The pulse generation circuit input terminal IN is electrically connected to the input terminal of the first NAND gate INV1, and the output terminal of the first NAND gate INV1 is electrically connected to the first node N1; the first terminal of the first branch transistor MP1 is electrically connected to the first node N1, the second terminal of the first branch transistor MP1 is electrically connected to the first fixed voltage signal terminal VDDL, and the third terminal of the first branch transistor MP1 is electrically connected to the second node N2; the first terminal of the first branch transistor MN1 is electrically connected to the first node N1, the second terminal of the first branch transistor MN1 is electrically connected to ground, and the third terminal of the first branch transistor MN1 is electrically connected to the second node N2; the first terminal of the first capacitor C1 is electrically connected to the second node N2, and the second terminal of the first capacitor C1 is electrically connected to ground; the input terminal of the first branch NOR gate NOR1 is electrically connected to the first node N1, and the input terminal of the first branch NOR gate NOR1 is also electrically connected to the second node N2; the output terminal of the first branch NOR gate NOR1 is electrically connected to the first output terminal PR of the pulse generation circuit, used to generate the first pulse signal;

[0024] The first branch includes the second branch transistor MP2, the second branch transistor MN2, the second capacitor C2, the second branch NOR gate NOR2, and the second output terminal PL of the pulse generation circuit;

[0025] The pulse generation circuit input terminal IN is electrically connected to the third node N3. The first terminal of the second branch transistor MP2 is electrically connected to the third node N3, the second terminal of the second branch transistor MP2 is electrically connected to the first fixed voltage signal terminal VDDL, and the third terminal of the second branch transistor MP2 is electrically connected to the fourth node N4. The first terminal of the second branch transistor MN2 is electrically connected to the third node N3, the second terminal of the second branch transistor MN2 is electrically connected to ground, and the third terminal of the second branch transistor MN2 is electrically connected to the fourth node N4. The first terminal of the second capacitor C2 is electrically connected to the fourth node N4, and the second terminal of the second capacitor C2 is electrically connected to ground. The input terminal of the second branch NOR gate NOR2 is electrically connected to the third node N3, and the input terminal of the second branch NOR gate NOR2 is also electrically connected to the fourth node N4. The output terminal of the second branch NOR gate NOR2 is electrically connected to the second output terminal PL of the pulse generation circuit to generate the second pulse signal.

[0026] In an optional embodiment of the present invention, please continue to refer to Figure 2 As shown, the level shifting circuit includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, and an output terminal OUT; wherein,

[0027] The first terminal of the first transistor M1 is electrically connected to the second output terminal PL of the pulse generation circuit, the second terminal of the first transistor M1 is electrically connected to the second fixed voltage signal terminal VSSL, and the third terminal of the first transistor M1 is electrically connected to the fifth node N5. The first terminal of the fifth transistor M5 is electrically connected to the first fixed voltage signal terminal VDDL, the second terminal of the fifth transistor M5 is electrically connected to the fifth node N5, and the second terminal of the fifth transistor M5 is electrically connected to the sixth node N6. The first terminal of the third transistor M3 receives the inverted signal INN of the input signal, the second terminal of the third transistor M3 is electrically connected to the fifth node N5, and the third terminal of the third transistor M3 is electrically connected to the seventh node N7.

[0028] The first terminal of the ninth transistor M9 is electrically connected to the eighth node N8, the second terminal of the ninth transistor M9 is electrically connected to the sixth node N6, the sixth node N6 is electrically connected to the eighth node N8, and the third terminal of the ninth transistor M9 is electrically connected to the third fixed voltage signal terminal VDDH; the first terminal of the tenth transistor M10 is electrically connected to the eighth node N8, the second terminal of the tenth transistor M10 is electrically connected to the third fixed voltage signal terminal VDDH, and the third terminal of the tenth transistor M10 is electrically connected to the ninth node N9; the first terminal of the seventh transistor M7 is electrically connected to the tenth node N10, the first terminal of the seventh transistor M7 is also electrically connected to the first terminal of the ninth node N9, the second terminal of the seventh transistor M7 is electrically connected to the ninth node N9, and the third terminal of the seventh transistor M7 is electrically connected to the fourth fixed voltage signal terminal VSSH;

[0029] The first terminal of the eleventh transistor M11 is electrically connected to the twelfth node N12, the second terminal of the eleventh transistor M11 is electrically connected to the sixth node N6, and the third terminal of the eleventh transistor M11 is electrically connected to the third fixed voltage signal terminal VDDH; the first terminal of the twelfth transistor M12 is electrically connected to the sixth node N6, the second terminal of the twelfth transistor M12 is electrically connected to the twelfth node N12, and the third terminal of the twelfth transistor M12 is electrically connected to the third fixed voltage signal terminal VDDH; the first terminal of the thirteenth transistor M13 is electrically connected to the thirteenth node N13, the second terminal of the thirteenth transistor M13 is electrically connected to the eleventh node N11, and the third terminal of the thirteenth transistor M13 is electrically connected to the third fixed voltage signal terminal VDDH; the first terminal of the fourteenth transistor M14 is electrically connected to the thirteenth node N13, the second terminal of the fourteenth transistor M14 is electrically connected to the twelfth node N12, and the third terminal of the fourteenth transistor M14 is electrically connected to the third fixed voltage signal terminal VDDH.

[0030] The first terminal of the eighth transistor M8 is electrically connected to the tenth node N10, the second terminal of the eighth transistor M8 is electrically connected to the eleventh node N11, the third terminal of the eighth transistor M8 is electrically connected to the fourth fixed voltage signal terminal VSSH; the output terminal OUT is electrically connected to the eleventh node N11.

[0031] The first terminal of the sixth transistor M6 is electrically connected to the first fixed voltage signal terminal VDDL, the second terminal of the sixth transistor M6 is electrically connected to the twelfth node N12, and the third terminal of the sixth transistor M6 is electrically connected to the fourteenth node N14; the first terminal of the fourth transistor M4 receives the input signal, the second terminal of the fourth transistor M4 is electrically connected to the fourteenth node N14, and the third terminal of the fourth transistor M4 is electrically connected to the seventh node N7; the first terminal of the second transistor M2 is electrically connected to the second output terminal PL of the pulse generation circuit, the second terminal of the second transistor M2 is electrically connected to the fourteenth node N14, and the third terminal of the second transistor M2 is electrically connected to the second fixed voltage signal terminal VSSL;

[0032] The seventh node N7 is electrically connected to the second fixed voltage signal terminal VSSL.

[0033] In an optional embodiment of the present invention, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, and the fourteenth transistor M14 are all low-voltage MOSFETs.

[0034] In an optional embodiment of the present invention, both the fifth transistor M5 and the sixth transistor M6 are LDMOS transistors.

[0035] In an optional embodiment of the present invention, the eleventh transistor M11 and the twelfth transistor M12 constitute a latch structure.

[0036] In an optional embodiment of the present invention, the seventh transistor M7 and the eighth transistor M8 constitute a current mirror.

[0037] In an optional embodiment of the present invention, the ninth transistor M9 and the tenth transistor M10 constitute a current mirror.

[0038] In an optional embodiment of the present invention, please continue to refer to Figure 1As shown, the pulse generation circuit in this embodiment has a voltage domain between VSSL and VDDL. INV1 inverts the input signal IN to generate the signal INN. MP1, MN1, and C1 invert and delay the signal INN to generate the signal IN_Delay. NOR1 performs a NOR operation on the signal INN and the signal IN_Delay. When the input signal IN transitions from logic low to logic high, PR generates a logic high-level pulse signal; when the input signal IN transitions from logic high to logic low, PR remains at a logic low level. MP2, MN2, and C2 invert and delay the input signal IN to generate the signal INN_Delay. NOR2 performs a NOR operation on the signal IN and the signal INN_Delay. When the input signal IN transitions from logic low to logic high, PL remains at a logic low level; when the input signal IN transitions from logic high to logic low, PL generates a logic high-level pulse signal. The width of the rising edge pulse signal is determined by MN1, MP1, and C1, while the width of the falling edge pulse signal is determined by MN2, MP2, and C2.

[0039] In an optional embodiment of the present invention, please continue to refer to Figure 2 As shown, in the main part of the level shifting circuit provided in this embodiment, M1-M4 and M7-M14 use low-voltage MOSFETs to accelerate the switching speed, while M5 and M6, which need to withstand voltage, use LDMOS. The input signals IN, INN, PL, and PR are logic levels in the low voltage domain, and the output signal OUT is a logic level in the high voltage domain. The following is the working principle of the level shifting circuit.

[0040] When IN is logic low, INN is logic high. M1, M2, and M4 are all off, M3 is on and in the deep linear region, and the gate voltage of M5, VDDL, is greater than its source voltage, which is approximately VDS of IBIAS. Therefore, M5 is on. All the bias current IBIAS flows through M3, M5, current mirrors M9-M10, and current mirrors M7-M8 to OUT, pulling OUT down to VSSH. At this time, the output OUT of the level shifting circuit is logic low.

[0041] When IN transitions from logic low to logic high, INN transitions from logic high to logic low. M1 and M3 are turned off, and M4 is turned on. All the bias current IBIAS flows to OUT through M4, M6, and current mirrors M13-M14. Additionally, the output PR of the pulse generation circuit generates a high-level pulse input to the gate of M2, causing M2 to generate a pulse current of several hundred μA or even mA. This pulse current flows to OUT through M2, M6, and current mirrors M13-14, pulling OUT to VDDH along with IBIAS. At this time, the output OUT of the level shifting circuit transitions from logic low to logic high.

[0042] When IN is logic high, INN is logic low. M1, M2, and M3 are all off, and M4 is on. Therefore, all the bias current IBIAS flows to OUT through M4, M6, and current mirrors M13 to M14, keeping the output OUT of the level shifting circuit at logic high.

[0043] When IN transitions from logic high to logic low, INN transitions from logic low to logic high. M2 and M4 are turned off, and M3 is turned on. All the bias current IBIAS flows to OUT through M3, M5, current mirrors M9-M10, and current mirrors M7-M8. Additionally, the output PL of the pulse generation circuit generates a high-level pulse input to the gate of M1, causing M1 to generate a pulse current of several hundred μA or even mA. This pulse, along with IBIAS, pulls OUT down to VSSH. At this time, the output OUT of the level shifting circuit transitions from logic high to logic low.

[0044] When the input signal IN of the level shifting circuit flips, the output signal OUT is pulled up to VDDH or down to VSSH by a current of several hundred uA or even mA. Therefore, the rise and fall delays are very small, around 1 ns, which greatly reduces the additional delay caused by the conversion of the signal from the low voltage domain to the high voltage domain in the switching power supply chip. When the input signal IN remains at a high or low level, the output signal OUT only needs a bias current of a few uA IBIAS to maintain its output, which greatly reduces static power consumption and improves efficiency.

[0045] The latch structure composed of M11 and M12 can improve the noise immunity of this level shifting circuit and ensure the correctness of the output results. If IN is a logic high level, all the bias current flows to OUT through M4, M6, and current mirrors M13-M14, while no current flows through M3, M5, current mirrors M9-M10, and current mirrors M7-M8. Therefore, the voltage at point B is lower than the voltage at point A, M11 is in the linear region, and M12 is in the cutoff region. When VDDH and VSSH rise synchronously, since M5 and M6 are LDMOS, their parasitic capacitance CDS is relatively large. Therefore, a charging current I = CDS * dV / dt will be generated from top to bottom in the paths where points A and B are located, where dV / dt is the rise rate of VDDH and VSSH. The charging current in the path at point A is provided by M9 and M11. Because the VGS of M11 is greater than that of M9, most of the charging current is provided by M11, while the charging current provided by M9 is very small. The pull-down current replicated to OUT through current mirrors M9-M10 and M7-M8 is also very small. The charging current in the path at point B is provided by M12 and M14. Because the VGS of M14 is greater than that of M12, most of the charging current is provided by M14, while the charging current provided by M12 is very small. The pull-up current replicated to OUT through current mirrors M13-M14 is very large. Therefore, when VDDH and VSSH rise synchronously, the pull-up current capability at OUT is much greater than the pull-down current capability, and OUT maintains a logic high level. Similarly, if IN is a logic low level, when VDDH and VSSH fall synchronously, OUT maintains a logic low level. The latch structure composed of M11 and M12 ensures the correctness of the output result, greatly improves the noise immunity of the level shifting circuit, and thus greatly improves the reliability of the switching power supply chip at high frequencies.

[0046] Please see Figure 3 and Figure 4 As shown, Figure 3 This is a simulation waveform diagram of the rise delay of the level shifting circuit provided in the embodiment of the present invention. Figure 4 This is a simulation waveform diagram of the fall delay of the level shifting circuit provided in the embodiment of the present invention. As can be seen from the figure, the rise delay is about 1.1ns and the fall delay is about 1.6ns.

[0047] Please see Figure 5 As shown, Figure 5This is a simulation waveform diagram of the level shifting circuit provided in this embodiment of the invention when the floating power rail switching speed is 100V / ns. When the floating power rail rises at a switching speed of 100V / ns, the undershoot of the output voltage is 0.75V, and the output of the level shifting circuit does not experience a logical state erroneous flip. When the floating power rail falls at a switching speed of 100V / ns, the overshoot of the output voltage is 0.35V, and the output also does not experience a logical state erroneous flip.

[0048] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device comprising said element. Terms such as "connected" or "linked" are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect. The orientations or positional relationships indicated by terms such as "upper," "lower," "left," and "right" are based on the orientations or positional relationships shown in the accompanying drawings and are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0049] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0050] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A level shifting circuit, characterized in that, include: A pulse generation circuit is used to generate a first pulse signal and a second pulse signal based on the input signal. A level shifting circuit, electrically connected to the pulse generation circuit, includes multiple transistors and acquires an output signal in response to the first pulse signal and the second pulse signal; The level shifting circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and an output terminal; wherein, The gate of the first transistor is electrically connected to the second output terminal of the pulse generation circuit, the source of the first transistor is electrically connected to the second fixed voltage signal terminal, and the drain of the first transistor is electrically connected to the fifth node; the gate of the fifth transistor is electrically connected to the first fixed voltage signal terminal, the source of the fifth transistor is electrically connected to the fifth node, and the drain of the fifth transistor is electrically connected to the sixth node; the gate of the third transistor receives the inverted signal of the input signal, the drain of the third transistor is electrically connected to the fifth node, and the source of the third transistor is electrically connected to the seventh node; The gate of the ninth transistor is electrically connected to the eighth node, the drain of the ninth transistor is electrically connected to the sixth node, the sixth node is electrically connected to the eighth node, and the source of the ninth transistor is electrically connected to the third fixed voltage signal terminal; the gate of the tenth transistor is electrically connected to the eighth node, the source of the tenth transistor is electrically connected to the third fixed voltage signal terminal, and the drain of the tenth transistor is electrically connected to the ninth node; the gate of the seventh transistor is electrically connected to the tenth node, the drain of the seventh transistor is electrically connected to the ninth node, the source of the seventh transistor is electrically connected to the fourth fixed voltage signal terminal, and the ninth node is electrically connected to the tenth node; The gate of the eleventh transistor is electrically connected to the twelfth node, the drain of the eleventh transistor is electrically connected to the sixth node, and the source of the eleventh transistor is electrically connected to the third fixed voltage signal terminal; the gate of the twelfth transistor is electrically connected to the sixth node, the drain of the twelfth transistor is electrically connected to the twelfth node, and the source of the twelfth transistor is electrically connected to the third fixed voltage signal terminal; the gate of the thirteenth transistor is electrically connected to the thirteenth node, the drain of the thirteenth transistor is electrically connected to the eleventh node, and the source of the thirteenth transistor is electrically connected to the third fixed voltage signal terminal; the gate of the fourteenth transistor is electrically connected to the thirteenth node, the drain of the fourteenth transistor is electrically connected to the twelfth node, and the source of the fourteenth transistor is electrically connected to the third fixed voltage signal terminal. The gate of the eighth transistor is electrically connected to the tenth node, the drain of the eighth transistor is electrically connected to the eleventh node, and the source of the eighth transistor is electrically connected to the fourth fixed voltage signal terminal; the output terminal is electrically connected to the eleventh node. The gate of the sixth transistor is connected to the first fixed voltage signal terminal, the drain of the sixth transistor is electrically connected to the twelfth node, and the source of the sixth transistor is electrically connected to the fourteenth node; the gate of the fourth transistor receives the input signal, the drain of the fourth transistor is electrically connected to the fourteenth node, and the source of the fourth transistor is electrically connected to the seventh node; the gate of the second transistor is electrically connected to the second output terminal of the pulse generation circuit, the drain of the second transistor is electrically connected to the fourteenth node, and the source of the second transistor is electrically connected to the second fixed voltage signal terminal. The seventh node is electrically connected to the second fixed voltage signal terminal via a bias current source.

2. The level shifting circuit according to claim 1, characterized in that, The pulse generation circuit includes a pulse generation circuit input terminal, a first branch, and a second branch. The first branch includes a first NOT gate, a first branch transistor one, a first branch transistor two, a first capacitor, a first branch NOR gate, and a first output terminal of the pulse generation circuit; The input terminal of the pulse generation circuit is electrically connected to the input terminal of the first NOT gate, and the output terminal of the first NOT gate is electrically connected to the first node; the gate of the first branch transistor is electrically connected to the first node, the source of the first branch transistor is electrically connected to the first fixed voltage signal terminal, and the drain of the first branch transistor is electrically connected to the second node; the gate of the first branch transistor is electrically connected to the first node, the source of the first branch transistor is electrically connected to ground, and the drain of the first branch transistor is electrically connected to the second node; the first terminal of the first capacitor is electrically connected to the second node, and the second terminal of the first capacitor is electrically connected to ground; the input terminal of the first branch NOR gate is electrically connected to the first node, and the input terminal of the first branch NOR gate is also electrically connected to the second node; the output terminal of the first branch NOR gate is electrically connected to the first output terminal of the pulse generation circuit, for generating the first pulse signal; The second branch includes a second branch transistor one, a second branch transistor two, a second capacitor, a second branch NOR gate, and a second output terminal of the pulse generation circuit; The input terminal of the pulse generation circuit is electrically connected to the third node; the gate of the second branch transistor one is electrically connected to the third node; the source of the second branch transistor one is electrically connected to the first fixed voltage signal terminal; and the drain of the second branch transistor one is electrically connected to the fourth node. The gate of the second branch transistor two is electrically connected to the third node; the source of the second branch transistor two is electrically connected to ground; and the drain of the second branch transistor two is electrically connected to the fourth node. The first terminal of the second capacitor is electrically connected to the fourth node; and the second terminal of the second capacitor is electrically connected to ground. The input terminal of the second branch NOR gate is electrically connected to the third node and also electrically connected to the fourth node. The output terminal of the second branch NOR gate is electrically connected to the second output terminal of the pulse generation circuit, for generating the second pulse signal.

3. The level shifting circuit according to claim 1, characterized in that, The first transistor, the second transistor, the third transistor, the fourth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, and the fourteenth transistor are all low-voltage MOSFETs.

4. The level shifting circuit according to claim 1, characterized in that, Both the fifth transistor and the sixth transistor are LDMOS transistors.

5. The level shifting circuit according to claim 1, characterized in that, The eleventh transistor and the twelfth transistor constitute a latch structure.

6. The level shifting circuit according to claim 1, characterized in that, The seventh transistor and the eighth transistor constitute a current mirror.

7. The level shifting circuit according to claim 1, characterized in that, The ninth transistor and the tenth transistor constitute a current mirror.

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