Power consumption pull method and device, computer device and storage medium

Abstract

The present application relates to the technical field of computer, and discloses a power consumption pull loading method, device, equipment and medium, comprising: acquiring a power consumption pull loading instruction of a to-be-tested interface, and a preset pull loading delay time corresponding to each power consumption circuit; analyzing the power consumption pull loading instruction to acquire a pull loading power of a target optical port test fixture, the target optical port test fixture comprising a plurality of power consumption circuits; determining a target power of each power consumption circuit according to the pull loading power and the corresponding relationship between the pull loading power and each power consumption circuit in the target optical port test fixture; sorting all the power consumption circuits according to the target power of each power consumption circuit to determine a pull loading sequence of each power consumption circuit; and controlling each power consumption circuit to be pulled to the target power corresponding to the power consumption circuit in turn according to the pull loading sequence of each power consumption circuit and the preset pull loading delay time. The present application can avoid voltage fluctuation superposition when the optical port test fixture is pulled to consume power, and avoid test timeout.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and more specifically to power consumption reduction methods, apparatus, computer equipment, and storage media. Background Technology

[0002] The power consumption load simulation test module is a functional module in the optical port test fixture. It is used to simulate and test the power consumption generated by the high-volume data communication of the optical module during normal communication.

[0003] Because there are many types of optical communication ports, and their power consumption varies, optical port test fixtures need to support different load power consumption in order to meet the testing requirements of different optical communication ports. Currently, when optical port test fixtures load power consumption, if the target power is loaded at once, it will cause excessive voltage fluctuations, affecting the test results and impacting the circuit. If a stepped load is used, it will cause a large delay when the target power to be loaded is large, which cannot meet the testing requirements. Summary of the Invention

[0004] In view of this, the present invention provides a power consumption load method, apparatus, computer equipment and storage medium to solve the problems of excessive voltage fluctuation and delay caused by power consumption load during optical port test fixture.

[0005] In a first aspect, the present invention provides a power consumption load method, comprising:

[0006] Obtain the power load command of the interface to be tested, as well as the preset load delay time corresponding to each power circuit;

[0007] The power consumption load command is parsed to obtain the load power of the target optical port test fixture. The target optical port test fixture is used to perform power consumption testing on the interface under test and includes multiple power consumption circuits.

[0008] Based on the load power and the correspondence between the load power and each power consumption circuit in the target optical port test fixture, the target power of each power consumption circuit is determined.

[0009] Based on the target power of each power consumption circuit, all power consumption circuits are sorted to determine the load-bearing sequence of each power consumption circuit.

[0010] Based on the load-pull sequence of each power consumption circuit and the preset load-pull delay time, each power consumption circuit is sequentially controlled to be loaded to the target power corresponding to that power consumption circuit.

[0011] Using the above method, the power consumption load command of the interface under test and the preset load delay time corresponding to each power consumption circuit are obtained; the power consumption load command is parsed to obtain the load power of the target optical port test fixture, which is used to perform power consumption testing on the interface under test and includes multiple power consumption circuits; based on the load power and the correspondence between the load power and each power consumption circuit in the target optical port test fixture, the target power of each power consumption circuit is determined; based on the target power of each power consumption circuit, all power consumption circuits are sorted to determine the load order of each power consumption circuit; based on the load order of each power consumption circuit and the preset load delay time, each power consumption circuit is sequentially controlled to be loaded to the target power corresponding to that power consumption circuit. When performing power consumption load testing, the target power of each power consumption circuit in the optical port test fixture can be determined first based on the load power of the target optical port test fixture. Then, each power consumption circuit is loaded to the target power in sequence, and a preset load delay time is set as the load interval time. This avoids the problem of excessive voltage fluctuation when the optical port test fixture is loaded to the load power at once. Moreover, since the optical port test fixture generally has a small number of power consumption circuits (usually 4 to 6), the time interval required when using this method for load testing is not large. Furthermore, the time required for any load power of the same optical port test fixture is the same, that is, each power consumption circuit needs to be loaded in sequence. Therefore, it also solves the delay problem caused by progressive load testing to a certain extent when the target power is too large.

[0012] In one optional implementation, parsing the power consumption load command to obtain the load power of the target optical port test fixture includes:

[0013] Parse the power load command to obtain the load power number;

[0014] Based on the load power consumption number and the correspondence between the load power consumption number and the load power, the load power of the target optical port test fixture is determined.

[0015] The above method allows for the establishment of a correspondence between load power consumption number and load power, determining the load power of the target optical port test fixture. This eliminates the need to directly transmit the load power, thus providing a certain degree of confidentiality.

[0016] In one optional implementation, before obtaining the power load command of the interface to be tested and the preset load delay time corresponding to each power circuit, the method further includes:

[0017] Obtain the voltage fluctuation time when each power consumption circuit is subjected to power consumption load.

[0018] The voltage fluctuation time after power consumption load is applied to each power consumption circuit is used as the preset load delay time.

[0019] By using the above method, the voltage fluctuation time after power consumption load is applied to each power consumption circuit as the preset load delay time. Loading can be performed immediately after the voltage fluctuation ends, which can avoid voltage fluctuation and save the load time of the entire target optical port test fixture, effectively reducing delay.

[0020] In one optional implementation, before obtaining the power load command of the interface to be tested and the preset load delay time corresponding to each power circuit, the method further includes:

[0021] Obtain the voltage fluctuation time when each power consumption circuit is subjected to power consumption load.

[0022] The voltage fluctuation time corresponding to each power consumption circuit is compared to determine the maximum voltage fluctuation time.

[0023] The maximum voltage fluctuation time is used as the preset load delay time.

[0024] By using the above method, determining the maximum voltage fluctuation time as the preset load delay time can better avoid voltage fluctuations, minimize the impact on test results, and better protect the circuit.

[0025] In one optional implementation, based on the load-pull sequence of each power consumption circuit and a preset load-pull delay time, each power consumption circuit is sequentially controlled to be loaded to the target power corresponding to that power consumption circuit, including:

[0026] The current power consumption circuit to be pulled is determined according to the pull-up sequence of each power consumption circuit;

[0027] The current power consumption circuit generates an enable signal;

[0028] The target state is determined by controlling the switching state of the preset switch in the current power consumption circuit according to the enable signal. The target state is used to indicate that the current power consumption circuit is pulled to the target power corresponding to the current power consumption circuit.

[0029] After waiting for the first preset load delay time, the next power consumption circuit is selected according to the load order of each power consumption circuit.

[0030] Control the power load of the next power consumption circuit to the target power corresponding to the next power consumption circuit, wherein the first preset load delay time is the preset load delay time between the current power consumption circuit and the next power consumption circuit.

[0031] By using the above method, the current power consumption circuit to be loaded is determined according to the loading sequence of each power consumption circuit. The power consumption circuit is controlled to generate an enable signal. The enable signal controls the state of the preset switch of the current power consumption circuit, so that the current power consumption circuit is loaded to the target power. Then, after waiting for a preset loading delay time, the power consumption of the next power consumption circuit is loaded, until all power consumption circuits are loaded to the target power. Adding a preset loading delay time interval between the loading of each power consumption circuit can effectively avoid voltage fluctuations and shorten the delay time.

[0032] In one optional implementation, after parsing the power consumption load command and obtaining the load power of the target optical port test fixture, the method further includes:

[0033] Obtain the circuit layout information for each power consumption circuit;

[0034] Based on the circuit distribution information of each power consumption circuit and the preset load delay time, each power consumption circuit is sequentially controlled to be loaded to the target power corresponding to each power consumption circuit.

[0035] In one optional implementation, the circuit distribution information includes the grouping of each power consumption circuit and the arrangement position of each power consumption circuit in each group; according to the circuit distribution information of each power consumption circuit and a preset load delay time, each power consumption circuit is sequentially controlled to be loaded to the target power corresponding to each power consumption circuit, including:

[0036] Determine the group order of each group of power consumption circuits based on the grouping of each power consumption circuit.

[0037] Based on the arrangement of the first power consumption circuit in the first group of power consumption circuits, the circuit order of the first power consumption circuit in the first group of power consumption circuits is determined, wherein the first group of power consumption circuits is any group of power consumption circuits in all groups of power consumption circuits, and the first power consumption circuit is any one of the power consumption circuits in the first group of power consumption circuits.

[0038] The current power consumption circuit group to be loaded is determined according to the group order of each power consumption circuit group.

[0039] The current power consumption circuit to be loaded is determined based on the circuit sequence of each power consumption circuit in the current power consumption circuit group.

[0040] Pull the current power consumption circuit to the target power corresponding to the current power consumption circuit;

[0041] After waiting for the preset load delay time corresponding to the current power consumption circuit, determine the next power consumption circuit group according to the group order;

[0042] The next power consumption circuit to be loaded in the next power consumption circuit group is determined according to the circuit sequence in the next power consumption circuit group.

[0043] Continue until it is confirmed that every power consumption circuit in all groups has been fully loaded.

[0044] In a second aspect, the present invention provides a power consumption load-bearing device, comprising:

[0045] The acquisition module is used to acquire the power consumption load command of the interface to be tested, as well as the preset load delay time corresponding to each power consumption circuit.

[0046] The parsing module is used to parse the power load command and obtain the load power of the target optical port test fixture. The target optical port test fixture is used to perform power consumption testing on the interface to be tested and includes multiple power consumption circuits.

[0047] The determination module is used to determine the target power of each power consumption circuit based on the load power and the correspondence between the load power and each power consumption circuit in the target optical port test fixture.

[0048] The sorting module is used to sort all power consumption circuits according to the target power of each power consumption circuit and determine the load order of each power consumption circuit.

[0049] The control module is used to sequentially control each power consumption circuit to be loaded to the target power corresponding to that power consumption circuit according to the loading sequence of each power consumption circuit and the preset loading delay time.

[0050] In one optional implementation, the parsing module specifically includes:

[0051] The parsing unit is used to parse the power load command and obtain the load power number;

[0052] The first determining unit is used to determine the load power of the target optical port test fixture based on the load power consumption number and the correspondence between the load power consumption number and the load power.

[0053] In one alternative embodiment, the apparatus further includes:

[0054] The first processing module is used to obtain the voltage fluctuation time when each power consumption circuit is subjected to power consumption load; and to use the voltage fluctuation time after each power consumption circuit is subjected to power consumption load as the preset load delay time.

[0055] In one alternative embodiment, the apparatus further includes:

[0056] The second processing module is used to acquire the voltage fluctuation time of each power consumption circuit when it is subjected to power consumption load; compare the voltage fluctuation time corresponding to each power consumption circuit to determine the maximum voltage fluctuation time; and use the maximum voltage fluctuation time as the preset load delay time.

[0057] In one alternative implementation, the control module includes:

[0058] The second determining unit is used to determine the current power consumption circuit to be loaded according to the loading sequence of each power consumption circuit;

[0059] The first control unit is used to control the current power consumption circuit to generate an enable signal; according to the enable signal, it controls the switching state of the preset switch in the current power consumption circuit to the target state, and the target state is used to indicate that the current power consumption circuit is pulled to the target power corresponding to the current power consumption circuit.

[0060] The waiting unit is used to wait for the first preset load delay time and then select the next power consumption circuit according to the load order of each power consumption circuit.

[0061] The second control unit is used to control the power load of the next power consumption circuit to the target power corresponding to the next power consumption circuit, wherein the first preset load delay time is the preset load delay time between the current power consumption circuit and the next power consumption circuit.

[0062] In one alternative embodiment, the apparatus further includes:

[0063] The acquisition module is also used to acquire circuit distribution information for each power consumption circuit;

[0064] The control module is also used to sequentially control each power consumption circuit to be loaded to the target power corresponding to each power consumption circuit according to the circuit distribution information of each power consumption circuit and the preset load delay time.

[0065] In one optional implementation, the circuit distribution information includes the grouping of each power consumption circuit and the arrangement position of each power consumption circuit in each group. The control module is further used for:

[0066] Determine the group order of each group of power consumption circuits based on the grouping of each power consumption circuit.

[0067] Based on the arrangement of the first power consumption circuit in the first group of power consumption circuits, the circuit order of the first power consumption circuit in the first group of power consumption circuits is determined, wherein the first group of power consumption circuits is any group of power consumption circuits in all groups of power consumption circuits, and the first power consumption circuit is any one of the power consumption circuits in the first group of power consumption circuits.

[0068] The current power consumption circuit group to be loaded is determined according to the group order of each power consumption circuit group.

[0069] The current power consumption circuit to be loaded is determined based on the circuit sequence of each power consumption circuit in the current power consumption circuit group.

[0070] Pull the current power consumption circuit to the target power corresponding to the current power consumption circuit;

[0071] After waiting for the preset load delay time corresponding to the current power consumption circuit, determine the next power consumption circuit group according to the group order;

[0072] The next power consumption circuit to be loaded in the next power consumption circuit group is determined according to the circuit sequence in the next power consumption circuit group.

[0073] Continue until it is confirmed that every power consumption circuit in all groups has been fully loaded.

[0074] Thirdly, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the computer instructions to perform the power consumption reduction method of the first aspect or any corresponding embodiment described above.

[0075] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to perform the power consumption loading method of the first aspect or any corresponding embodiment thereof. Attached Figure Description

[0076] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0077] Figure 1 This is a flowchart illustrating the power consumption loading method according to an embodiment of the present invention;

[0078] Figure 2 This is a circuit diagram of a QSFP-DD type optical port test fixture according to an embodiment of the present invention;

[0079] Figure 3 This is a schematic diagram of voltage fluctuation when P30 and P31 are simultaneously loaded in the QSFP-DD type optical port test fixture according to an embodiment of the present invention;

[0080] Figure 4 This is a schematic diagram of the voltage fluctuation during power consumption load when P30 is written to 0 in the QSFP-DD type optical port test fixture according to an embodiment of the present invention;

[0081] Figure 5This is a schematic diagram of voltage fluctuation during power consumption loading when writing 1 to P30 in the QSFP-DD type optical port test fixture according to an embodiment of the present invention;

[0082] Figure 6 This is a schematic diagram of voltage fluctuation during power consumption under load when writing 0 on P31 in the QSFP-DD type optical port test fixture according to an embodiment of the present invention;

[0083] Figure 7 This is a schematic diagram of voltage fluctuation during power consumption loading when writing 1 to P31 in the QSFP-DD type optical port test fixture according to an embodiment of the present invention;

[0084] Figure 8 This is a flowchart illustrating another power consumption loading method according to an embodiment of the present invention.

[0085] Figure 9 This is a structural block diagram of a power consumption load-bearing device according to an embodiment of the present invention;

[0086] Figure 10 This is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. Detailed Implementation

[0087] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0088] An optical port test fixture is a tool used to test the optical communication ports of a switch by simulating the communication function of an optical module. The difference between an optical module and a switch optical port test fixture is that an optical module has an optical cable connecting it to other optical modules, allowing communication between hosts A and B. The optical cable inside the test fixture is self-looping, not communicating with the outside world, and only transmitting and receiving signals. It is mainly used to simulate the communication state of a switch's optical communication port, thereby determining the port's qualification. Optical port test fixtures are available in different models depending on the optical module. For example, the optical communication port of a Small Form-factor Pluggable (SFP) optical module requires an SFP-type test fixture for simulation testing, while the optical communication port of a Quad Small Form-factor Pluggable-Double Density (QSFP-DD) optical module requires a QSFP-DD-type test fixture for simulation testing. The power consumption load simulation test module is a functional module in the optical port test fixture. It is used to simulate and test the power consumption generated by the high-volume data communication of the optical module during normal communication.

[0089] In intelligent switch products, various network service ports are used for data transmission and reception. Before leaving the factory, these service ports need to be tested, including monitoring high-speed link signals, low-speed link signals, power consumption, temperature, and voltage. Directly testing with optical modules and cables would be extremely costly and difficult to operate. Therefore, optical port test fixtures have emerged. These fixtures are responsible for loop-through testing of the aforementioned signals and states of the switch's optical communication ports, quantifying the functional indicators of the optical communication ports before the switch leaves the factory, and improving the product's testing specifications.

[0090] The main function of the power consumption load simulation test module on the optical port test fixture is to simulate the power consumption generated by the optical module during normal communication with large amounts of data, thereby testing the performance of the switch's optical communication port. Four to six power consumption control lines control different combinations of MOS transistors through general-purpose input / output (GPIO) to generate different power consumption simulations and different power consumption levels, verifying the qualification of the relevant characteristics of power consumption change when the optical communication port of the switch product carries large amounts of data.

[0091] For example, the SFP type optical port test fixture can perform power consumption load simulation tests at 8 levels: 0W, 0.5W, 1W, 1.5W, 2W, 2.5W, 3W, and 3.5W; the QSF-DD type optical port test fixture can perform power consumption load simulation tests at 16 levels: 0W, 1.5W, 2W, 3.5W, 4.5W, 6W, 6.5W, 7.5W, 8W, 10W, 12W, 14W, 16W, 18W, 20W, and 22W.

[0092] In one related technology, a load-pull method is called "direct," which means that according to the power load-pull table definition, when the host issues a power load simulation test command, the relevant power control circuits are directly enabled. This method directly enables the corresponding load control circuits according to the load table after receiving the host's power load simulation test command, and the corresponding MOSFETs are turned on. Since all load control circuits operate simultaneously, voltage fluctuations will occur, resulting in momentary voltage dips. When the MOSFETs causing voltage fluctuations share power with the MCU, there is a risk of interfering with the normal operation of the MCU in the optical port test fixture.

[0093] In another related technology, a load-pull method is called "stepped load-pull," also known as stepped load-pull. According to the power consumption load-pull table definition, when the host issues a power consumption load simulation test command, it starts from the lowest power consumption level and gradually increases the load step by step, adding a small delay between each level. For example, to load to 2W, it first loads to 0.5W with a 50ms delay, then to 1W with a 50ms delay, then to 1.5W with a 50ms delay, and finally to 2W. This method, after receiving the host's power consumption load simulation test command, steadily increases the load to the corresponding power consumption, avoiding sudden voltage spikes and protecting the normal operation of the MCU. However, the stepped load-pull method is time-consuming. The power consumption load simulation test function needs to provide feedback to the host within a specified time after the load is completed. The higher the power consumption, the longer the time required, and the greater the chance of timeout.

[0094] According to an embodiment of the present invention, a power consumption load method embodiment is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0095] This embodiment provides a power consumption load method, which can be used for the various optical port test fixtures mentioned above. Figure 1 This is a flowchart of a power consumption load method according to an embodiment of the present invention, such as... Figure 1 As shown, the process includes the following steps:

[0096] Step S101: Obtain the power load command of the interface to be tested, and the preset load delay time corresponding to each power circuit.

[0097] Specifically, the power load command is a power load command sent by the control end, such as a microprocessor or computer, to the optical port test fixture to instruct the target optical port test fixture to perform power load testing on the target object (such as the optical switching port under test of a switch). The preset load delay time corresponding to each power circuit refers to the interval between two power circuits after the first power circuit has been loaded and the next power circuit has been loaded.

[0098] Step S102: Parse the power consumption load command to obtain the load power of the target optical port test fixture.

[0099] Specifically, the target optical port test fixture is used to perform power consumption testing on the interface under test. The target optical port test fixture includes multiple power consumption circuits. It can parse the power consumption load command, extract the parameters corresponding to the load power from the command, and determine the load power of the target optical port test fixture based on the parameter values.

[0100] Step S103: Determine the target power of each power consumption circuit based on the load power and the correspondence between the load power and each power consumption circuit in the target optical port test fixture.

[0101] Specifically, the correspondence between the load power in the optical port test fixture and each power consumption circuit in the target optical port test fixture can be preset. Then, based on the load power and the correspondence between the load power and each power consumption circuit in the target optical port test fixture, the target power of each power consumption circuit can be determined.

[0102] In an optional example, such as the power load simulation test module of an SFP optical port test fixture, there are four power control circuits. Each circuit uses GPIOs P30-P33 to control one 0.5W and three 1W MOSFETs, respectively. Different combinations of writing '1' and '0' to P30-P33 complete eight power load simulation tests: 0W, 0.5W, 1W, 1.5W, 2W, 2.5W, 3W, and 3.5W, as shown in Table 1. Writing '1' to different GPIOs indicates MOSFET conduction and increases power consumption by the amount shown in the table; writing '0' does not increase the corresponding power consumption. By combining the four GPIOs, different total power consumption values ​​can be obtained, thus achieving different power consumption test objectives. The correspondence between the load power and each power circuit in the SFP optical port test fixture is shown in Table 1 below.

[0103] Table 1

[0104] Load power consumption P33 P32 P31 P30 0W 0 0 0 0 0.5W 0 0 0 1 1W 0 0 1 0 1.5W 0 1 0 1 2W 0 1 1 0 2.5W 0 1 1 1 3W 1 1 1 0 3.5W 1 1 1 1

[0105] As can be seen from Table 1, for example, if the SFP type optical port test fixture needs to be loaded to 2.5W, then the target power of the four power consumption circuits is 0W for P33 power consumption circuit, 1W for P32 power consumption circuit, 1W for P31 power consumption circuit, and 1W for P30 power consumption circuit.

[0106] In another optional example, such as the QSFP-DD type optical port test fixture, there are 6 power consumption control lines, two more than the SFP type optical port test fixture. These are implemented by 6 GPIOs controlling the MOSFETs. The power consumption increase per line is increased from 0.5W-1W in the SFP type to 1.5W-6W. Through combination, 16 power consumption load simulation tests can be performed at levels of 1.5W, 3.5W, 4.5W, 6W, 6.5W, 7.5W, 8W, 10W, 12W, 14W, 16W, 18W, 20W, and 22W, as shown in Table 2 below.

[0107] Table 2

[0108] Load power consumption P42 P43 P33 P32 P31 P30 0W 0 0 0 0 0 0 1.5W 0 0 0 0 0 1 2W 1 0 0 0 0 0 3.5W 1 0 0 0 0 1 4.5W 0 0 0 0 1 0 6W 1 0 1 0 0 0 6.5W 1 0 0 0 1 0 7.5W 1 0 1 0 0 1 8W 0 0 1 1 0 0 10W 0 1 1 0 0 0 12W 1 1 1 0 0 0 14W 0 1 1 1 0 0 16W 1 1 1 1 0 0 18W 1 1 1 0 1 1 20W 0 1 1 1 1 1

[0109] As can be seen from Table 2, for example, if the QSFP-DD type optical port test fixture needs to be loaded to 14W, then the target power of the four power consumption circuits is 0W for P42, 1W for P43, 1W for P33, 1W for P32, 0W for P31, and 0W for P30.

[0110] Step S104: Sort all power consumption circuits according to the target power of each power consumption circuit, and determine the load order of each power consumption circuit.

[0111] Specifically, for example, the target power of the power consumption circuit can be sorted from small to large or from large to small, so that the voltage fluctuation is smaller when the power consumption is under load, which can better protect the circuit.

[0112] Figure 2 The power consumption circuit power supply table for the QSFP-DD type optical port test fixture is shown in Table 3:

[0113] Table 3

[0114] P3V3 P30 QDD_P1W5SET P3V3 powers the MCU P3V3 P31 QDD_P4W5SET P3V3 powers the MCU PVCCT P32 QDD_P4WSET_1 PVCCT P33 QDD_P4WSET_0 PVCCR P42 QDD_P2WSET PVCCR P43 QDD_P6WSET

[0115] Step S105: Based on the load-pull sequence of each power consumption circuit and the preset load-pull delay time, control each power consumption circuit to be loaded to the target power corresponding to that power consumption circuit in sequence.

[0116] Specifically, each power consumption circuit is sequentially loaded to the target power corresponding to it according to the loading sequence of each power consumption circuit. After the previous power consumption circuit is loaded, a delay is performed according to the preset loading delay time corresponding to the previous power consumption circuit, and then the power consumption loading operation of the next power consumption circuit is performed.

[0117] The power load method provided in this embodiment obtains the power load command of the interface under test and the preset load delay time corresponding to each power circuit; parses the power load command to obtain the load power of the target optical port test fixture, wherein the target optical port test fixture is used to perform power consumption testing on the interface under test and includes multiple power circuits; determines the target power of each power circuit based on the load power and the correspondence between the load power and each power circuit in the target optical port test fixture; sorts all power circuits according to the target power of each power circuit to determine the load order of each power circuit; and controls each power circuit to be loaded to the target power corresponding to it in sequence according to the load order of each power circuit and the preset load delay time. When performing power consumption load testing, the target power of each power consumption circuit in the optical port test fixture can be determined first based on the load power of the target optical port test fixture. Then, each power consumption circuit is loaded to the target power in sequence, and a preset load delay time is set as the load interval time. This avoids the problem of excessive voltage fluctuation when the optical port test fixture is loaded to the load power at once. Moreover, since the optical port test fixture generally has a small number of power consumption circuits (usually 4 to 6), the time interval required when using this method for load testing is not large. Furthermore, the time required for any load power of the same optical port test fixture is the same. Therefore, it also solves the delay problem caused by progressive load testing to a certain extent when the target power is too large.

[0118] In one optional implementation, parsing the power consumption load command to obtain the load power of the target optical port test fixture includes:

[0119] Step a1: Parse the power consumption load command and obtain the load power consumption number.

[0120] Step a2: Determine the load power of the target optical port test fixture based on the load power consumption number and the correspondence between the load power consumption number and the load power.

[0121] Specifically, the power consumption load command can be a load request, which includes multiple fields. The multiple fields in the request are parsed to obtain power consumption-related information in the load command, such as the load power consumption number. Then, based on the load power consumption number and the correspondence between the load power consumption number and the load power, the load power of the target optical port test fixture is determined.

[0122] The above method allows for the establishment of a correspondence between load power consumption number and load power, determining the load power of the target optical port test fixture. This eliminates the need to directly transmit the load power, thus providing a certain degree of confidentiality.

[0123] In one optional implementation, all power consumption circuits are sorted according to the target power of each power consumption circuit to determine the load order of each power consumption circuit, including:

[0124] Based on the target power of each power consumption circuit, the target power of each power consumption circuit is sorted from smallest to largest to determine the load order of each power consumption circuit.

[0125] By using the above method, the circuits can be sorted according to their target power to determine the load order of each power consumption circuit, which can better reduce voltage fluctuations than random sorting.

[0126] In one optional implementation, before obtaining the power load command of the interface to be tested and the preset load delay time corresponding to each power circuit, the method further includes:

[0127] Step b1: Obtain the voltage fluctuation time when each power consumption circuit is subjected to power consumption load.

[0128] Step b2: The voltage fluctuation time after power consumption load is applied to each power consumption circuit is used as the preset load delay time.

[0129] Specifically, for example, an oscilloscope can be used to obtain the voltage fluctuation time of each power consumption circuit during power consumption load, for example, in... Figure 3 The oscilloscope diagram shows the voltage fluctuations measured after the power control lines corresponding to P30 and P31 are simultaneously written to 0. The fluctuations occur at approximately 7.8µs and 2.43ms respectively (image stitching is used due to the limited waveform length displayed on the oscilloscope), with a maximum fluctuation time of 151µs. Setting a delay greater than 151µs between each power control line can stagger the fluctuations from two power setting changes.

[0130] By using the above method, the voltage fluctuation time after power consumption load is applied to each power consumption circuit as the preset load delay time. Loading can be performed immediately after the voltage fluctuation ends, which can avoid voltage fluctuation and save the load time of the entire target optical port test fixture, effectively reducing delay.

[0131] In an optional example, an RC circuit can be added to each power control line to reduce the amplitude of voltage fluctuations.

[0132] In one optional implementation, before obtaining the power load command of the interface to be tested and the preset load delay time corresponding to each power circuit, the method further includes:

[0133] Step c1: Obtain the voltage fluctuation time when each power consumption circuit is subjected to power consumption load.

[0134] Step c2: Compare the voltage fluctuation time corresponding to each power consumption circuit to determine the maximum voltage fluctuation time.

[0135] Step c3: Use the maximum voltage fluctuation time as the preset load delay time.

[0136] Specifically, the voltage fluctuation time corresponding to each power consumption circuit can be obtained, and then the maximum voltage fluctuation time can be obtained by comparison. The maximum voltage fluctuation time is used as the preset load delay time, which can reduce the impact of voltage fluctuation to a greater extent.

[0137] In an optional example, the impact of the two power control lines containing P30 and P31 of the QSFP-DD optical port test fixture on the P3V3 circuit is illustrated below:

[0138] (1) When P30 is written to 0, the MOS is not turned on and does not provide effective power consumption. The voltage jitter of the P3V3 circuit is as follows: Figure 4 As shown, observations indicate that the jitter time is approximately 111.87 μs.

[0139] (2) When P30 is written to 1, the MOSFET is turned on, providing 1.5W of power consumption. The jitter of P3V3 is as follows: Figure 5 As shown, observations indicate that the jitter time is approximately 68.125 µs.

[0140] (3) When P31 is written to 0, the MOS is not turned on and no effective power consumption is provided. P3V3 still exhibits jitter, such as Figure 6 As shown, the jitter time is approximately 152.11 µs.

[0141] (4) When P31 is written to 1, the MOSFET is turned on, providing 4.5W of power consumption. The jitter of P3V3 is as follows: Figure 7 As shown, observations indicate that the jitter time is approximately 67.734 μs.

[0142] Using the same method, the jitter time of each of the six power consumption circuits can be obtained.

[0143] From above Figures 4 to 7It can be seen that when the optical port test fixture performs power load simulation testing, regardless of the power load level used, each power control line will cause corresponding voltage fluctuations. When the direct one-step load to the target power is used, the power control lines of P30 and P31 will be enabled at the same time. The voltage fluctuations caused by the enable will be superimposed at almost the same time point. For the QSFP-DD type optical port test fixture, the superposition effect of P30 and P31 on P3V3 will affect the normal operation of the MCU. When the load time is sufficient, the maximum jitter time can be selected as the preset load delay time, which can largely avoid the superposition effect of voltage jitter.

[0144] In one optional implementation, based on the load-pull sequence of each power consumption circuit and a preset load-pull delay time, each power consumption circuit is sequentially controlled to be loaded to the target power corresponding to that power consumption circuit, including as follows: Figure 8 The steps shown are as follows:

[0145] Step S801: Determine the current power consumption circuit to be loaded according to the loading sequence of each power consumption circuit.

[0146] Step S802: Control the current power consumption circuit to generate an enable signal.

[0147] Specifically, the current power consumption circuit to be pulled is determined according to the pull-up sequence of each power consumption circuit, and the current power consumption circuit is controlled to generate an enable signal. For example, the enable signal can be a high level or a low level, or it can be a value, such as 0 or 1.

[0148] Step S803: Control the switching state of the preset switch in the current power consumption circuit to the target state according to the enable signal.

[0149] Specifically, the target state is used to indicate that the current power consumption circuit is being pulled to the target power corresponding to the current power consumption circuit.

[0150] In an optional example, for example Figure 2 The QSFP-DD type optical port test fixture shown uses a MOSFET as the circuit switch. When the enable signal is "0", the MOSFET is turned off, and when the enable signal is "1", the MOSFET is turned on.

[0151] Step S804: After waiting for the first preset load delay time, select the next power consumption circuit according to the load order of each power consumption circuit.

[0152] Step S805: Control the power load of the next power consumption circuit to the target power corresponding to the next power consumption circuit.

[0153] Specifically, the first preset load delay time is the preset load delay time between the current power consumption circuit and the next power consumption circuit. Each power consumption circuit is loaded to the target power in sequence according to the load order. The preset load delay time corresponding to each power consumption circuit is added to the load time at each time. For example, after loading the first power consumption circuit, wait for the preset load delay time corresponding to the first power consumption circuit before loading the next power consumption circuit to the target power.

[0154] By using the above method, the current power consumption circuit to be loaded is determined according to the loading sequence of each power consumption circuit. The power consumption circuit is controlled to generate an enable signal, which controls the state of the preset switch of the current power consumption circuit, so that the current power consumption circuit is loaded to the target power. Then, after waiting for the preset loading delay time, the power consumption of the next power consumption circuit is loaded, until all power consumption circuits are loaded to the target power. Adding the preset loading delay time interval between the loading of each power consumption circuit can effectively avoid voltage fluctuations and shorten the delay time. Since the power consumption circuits of an optical port test fixture are generally few (4 to 6 channels), an appropriate delay time will not cause timeout.

[0155] In one alternative implementation, the preset load delay time for each power consumption circuit is the same.

[0156] Specifically, the same preset load delay time is set between each power consumption circuit load, which makes it convenient to set and count the entire test time, and has certain convenience.

[0157] In one optional implementation, after parsing the power consumption load command and obtaining the load power of the target optical port test fixture, the method further includes:

[0158] Obtain the circuit layout information for each power consumption circuit;

[0159] Based on the circuit distribution information of each power consumption circuit and the preset load delay time, each power consumption circuit is sequentially controlled to be loaded to the target power corresponding to each power consumption circuit.

[0160] Specifically, the circuit distribution information of each power consumption circuit can be obtained. The circuit distribution information may include, for example, the grouping of power consumption circuits and the arrangement of power consumption circuits.

[0161] In one optional implementation, the circuit distribution information includes the grouping of each power consumption circuit and the arrangement position of each power consumption circuit in each group; according to the circuit distribution information of each power consumption circuit and the preset load delay time, each power consumption circuit is sequentially controlled to be loaded to the target power corresponding to each power consumption circuit, including the following method steps:

[0162] Step d1: Determine the group order of each group of power consumption circuits based on the grouping of each power consumption circuit.

[0163] Step d2: Determine the circuit sequence of the first power consumption circuit in the first group of power consumption circuits based on the arrangement position of the first power consumption circuit in the first group of power consumption circuits.

[0164] Specifically, the first group of power consumption circuits is any one of the power consumption circuits in all groups of power consumption circuits, and the first power consumption circuit is any one of the power consumption circuits in the first group of power consumption circuits.

[0165] In an optional example, for example in Figure 2 The QSFP-DD type optical port test fixture shown contains a total of P3V3 ( Figure 2 Vcc), PVCCT ( Figure 2 VccT) and PVCCR ( Figure 2 The circuit is powered by three circuits (P3V3, PVCCT, and PVCCR). The circuit can be divided into three groups: P3V3, PVCCT, and PVCCR. Each group has two power consumption circuits. The circuit sequence of the first power consumption circuit in P3V3 is 1, and the circuit sequence of the second power consumption circuit is 2. Other circuits can be set in the same way.

[0166] Step d3: Determine the current power consumption circuit group to be loaded based on the group order of each power consumption circuit group.

[0167] Step d4: Determine the current power consumption circuit to be loaded based on the circuit sequence of each power consumption circuit in the current power consumption circuit group.

[0168] Specifically, in an optional example, for instance... Figure 2 The three groups of circuits are arranged as follows: P3V3 is arranged first, PVCCT is arranged second, and PVCCR is arranged third. For example, during the first load, the current power consumption circuit group to be loaded is P3V3, and the current power consumption circuit to be loaded is the first circuit in P3V3.

[0169] Step d5: Pull the current power consumption circuit to the target power corresponding to the current power consumption circuit.

[0170] Specifically, the current power consumption circuit is pulled to the target power corresponding to the current power consumption circuit.

[0171] Step d6: After waiting for the preset load delay time corresponding to the current power consumption circuit, determine the next power consumption circuit group according to the group order.

[0172] Step d7: Determine the next power consumption circuit to be loaded in the next power consumption circuit group according to the circuit sequence in the next power consumption circuit group.

[0173] Step d8 continues until it is confirmed that every power consumption circuit in all groups of power consumption circuits has been fully loaded.

[0174] In an optional example, for example in Figure 2 The QSFP-DD type optical port test fixture shown contains a total of P3V3 ( Figure 2 Vcc), PVCCT ( Figure 2 VccT) and PVCCR ( Figure 2 The P3V3 is powered by three power supplies (VccR), using a "gold finger" connector. In addition to powering the 1.5W and 4.5W power supply lines, the P3V3 also powers the microcontroller unit (MCU). AN12 is the data acquisition circuit for P3V3, AN15 is the data acquisition circuit for PVCCT, and AN2 is the data acquisition circuit for PVCCR. The three power supplies power the six power consumption circuits. Vcc1 powers the P31 power consumption circuit, VccT powers the P32 and P33 power consumption circuits, and VccR powers the P34 and P35 power consumption circuits. In other words, each power supply is responsible for powering two power consumption circuits. The first power consumption circuit powered by the first power supply can be connected first, then the first power consumption circuit powered by the second power supply, then the first power consumption circuit powered by the third power supply, and so on, starting from the second power consumption circuit of the first power supply. This alternating connection can effectively reduce the superposition of voltage fluctuations caused by the power consumption circuits, which can reduce voltage fluctuations to a certain extent or appropriately reduce the delay time and improve test efficiency.

[0175] This embodiment also provides a power consumption load-bearing device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, hardware implementations, or a combination of software and hardware, are also possible and contemplated.

[0176] This embodiment provides a power consumption load-bearing device, such as... Figure 9 As shown, it includes:

[0177] The acquisition module 901 is used to acquire the power consumption load command of the interface to be tested, as well as the preset load delay time corresponding to each power consumption circuit.

[0178] The parsing module 902 is used to parse the power consumption load command and obtain the load power of the target optical port test fixture. The target optical port test fixture is used to perform power consumption testing on the interface to be tested and includes multiple power consumption circuits.

[0179] The determination module 903 is used to determine the target power of each power consumption circuit based on the load power and the correspondence between the load power and each power consumption circuit in the target optical port test fixture.

[0180] The sorting module 904 is used to sort all power consumption circuits according to the target power of each power consumption circuit and determine the load order of each power consumption circuit.

[0181] The control module 905 is used to sequentially control each power consumption circuit to be loaded to the target power corresponding to that power consumption circuit according to the loading sequence of each power consumption circuit and the preset loading delay time.

[0182] In one optional implementation, the parsing module 902 specifically includes:

[0183] The parsing unit is used to parse the power load command and obtain the load power number;

[0184] The first determining unit is used to determine the load power of the target optical port test fixture based on the load power consumption number and the correspondence between the load power consumption number and the load power.

[0185] In one alternative embodiment, the apparatus further includes:

[0186] The first processing module 906 is used to obtain the voltage fluctuation time when each power consumption circuit is subjected to power consumption load; and to use the voltage fluctuation time after each power consumption circuit is subjected to power consumption load as the preset load delay time.

[0187] In one alternative embodiment, the apparatus further includes:

[0188] The second processing module 907 is used to acquire the voltage fluctuation time when each power consumption circuit is subjected to power consumption load; compare the voltage fluctuation time corresponding to each power consumption circuit to determine the maximum voltage fluctuation time; and use the maximum voltage fluctuation time as the preset load delay time.

[0189] In one alternative implementation, the control module 905 includes:

[0190] The second determining unit is used to determine the current power consumption circuit to be loaded according to the loading sequence of each power consumption circuit;

[0191] The first control unit is used to control the current power consumption circuit to generate an enable signal; according to the enable signal, it controls the switching state of the preset switch in the current power consumption circuit to the target state, and the target state is used to indicate that the current power consumption circuit is pulled to the target power corresponding to the current power consumption circuit.

[0192] The waiting unit is used to wait for the first preset load delay time and then select the next power consumption circuit according to the load order of each power consumption circuit.

[0193] The second control unit is used to control the power load of the next power consumption circuit to the target power corresponding to the next power consumption circuit, wherein the first preset load delay time is the preset load delay time between the current power consumption circuit and the next power consumption circuit.

[0194] In one alternative embodiment, the apparatus further includes:

[0195] The acquisition module 901 is also used to acquire the circuit distribution information of each power consumption circuit;

[0196] The control module 905 is also used to control each power consumption circuit to be loaded to the target power corresponding to each power consumption circuit in sequence according to the circuit distribution information of each power consumption circuit and the preset load delay time.

[0197] In one optional implementation, the circuit distribution information includes the grouping of each power consumption circuit and the arrangement position of each power consumption circuit in each group. The control module 905 is further used for:

[0198] Determine the group order of each group of power consumption circuits based on the grouping of each power consumption circuit.

[0199] Based on the arrangement of the first power consumption circuit in the first group of power consumption circuits, the circuit order of the first power consumption circuit in the first group of power consumption circuits is determined, wherein the first group of power consumption circuits is any group of power consumption circuits in all groups of power consumption circuits, and the first power consumption circuit is any one of the power consumption circuits in the first group of power consumption circuits.

[0200] The current power consumption circuit group to be loaded is determined according to the group order of each power consumption circuit group.

[0201] The current power consumption circuit to be loaded is determined based on the circuit sequence of each power consumption circuit in the current power consumption circuit group.

[0202] Pull the current power consumption circuit to the target power corresponding to the current power consumption circuit;

[0203] After waiting for the preset load delay time corresponding to the current power consumption circuit, determine the next power consumption circuit group according to the group order;

[0204] The next power consumption circuit to be loaded in the next power consumption circuit group is determined according to the circuit sequence in the next power consumption circuit group.

[0205] Continue until it is confirmed that every power consumption circuit in all groups has been fully loaded.

[0206] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0207] In this embodiment, the power consumption load device is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0208] This invention also provides a computer device having the above-described features. Figure 9 The power consumption load device shown.

[0209] Please see Figure 10 , Figure 10 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 10 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 10 Take a processor 10 as an example.

[0210] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0211] The memory 20 stores instructions executable by at least one processor 10 to cause at least one processor 10 to perform the method shown in the above embodiments.

[0212] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0213] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0214] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0215] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0216] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A power consumption load method, characterized in that, The method includes: Obtain the power load command of the interface to be tested, as well as the preset load delay time corresponding to each power circuit; The power consumption load command is parsed to obtain the load power of the target optical port test fixture, wherein the target optical port test fixture is used to perform power consumption testing on the interface to be tested, and the target optical port test fixture includes multiple power consumption circuits. Based on the load power and the correspondence between the load power and each power consumption circuit in the target optical port test fixture, the target power of each power consumption circuit is determined. Based on the target power of each power consumption circuit, all power consumption circuits are sorted to determine the load order of each power consumption circuit. According to the loading sequence of each power consumption circuit and the preset loading delay time, each power consumption circuit is sequentially controlled to be loaded to the target power corresponding to that power consumption circuit; The step of sequentially controlling each power consumption circuit to be loaded to the target power corresponding to that power consumption circuit according to the loading sequence of each power consumption circuit and the preset loading delay time includes: The current power consumption circuit to be pulled is determined according to the pull-up sequence of each of the power consumption circuits; The current power consumption circuit is controlled to generate an enable signal; The enable signal controls the switching state of the preset switch in the current power consumption circuit to the target state, and the target state is used to indicate that the current power consumption circuit is pulled to the target power corresponding to the current power consumption circuit. After waiting for the first preset load delay time, the next power consumption circuit is selected according to the load order of each power consumption circuit. The power load of the next power consumption circuit is controlled to be pulled up to the target power corresponding to the next power consumption circuit, until it is determined that each power consumption circuit has been fully loaded. The first preset load delay time is the preset load delay time between the current power consumption circuit and the next power consumption circuit.

2. The method according to claim 1, characterized in that, The step of parsing the power consumption load command to obtain the load power of the target optical port test fixture includes: The power consumption load command is parsed to obtain the load power consumption number; The load power of the target optical port test fixture is determined based on the load power number and the correspondence between the load power number and the load power.

3. The method according to claim 2, characterized in that, Before obtaining the power load command of the interface to be tested and the preset load delay time corresponding to each power circuit, the method further includes: Obtain the voltage fluctuation time of each of the power consumption circuits when it is subjected to power consumption load; The voltage fluctuation time after power consumption load is applied to each of the power consumption circuits is taken as the preset load delay time.

4. The method according to claim 3, characterized in that, Before obtaining the power load command of the interface to be tested and the preset load delay time corresponding to each power circuit, the method further includes: Obtain the voltage fluctuation time of each of the power consumption circuits when it is subjected to power consumption load; The voltage fluctuation time corresponding to each of the power consumption circuits is compared to determine the maximum voltage fluctuation time. The maximum voltage fluctuation time is used as the preset load delay time.

5. The method according to any one of claims 1 to 4, characterized in that, After parsing the power consumption load command to obtain the load power of the target optical port test fixture, the method further includes: Obtain the circuit distribution information for each of the power consumption circuits; Based on the circuit distribution information of each power consumption circuit and the preset load delay time, each power consumption circuit is sequentially controlled to be loaded to the target power corresponding to each power consumption circuit.

6. The method according to claim 5, characterized in that, The circuit distribution information includes the grouping of each power consumption circuit and the arrangement position of each power consumption circuit in each group; the step of sequentially controlling each power consumption circuit to be loaded to the target power corresponding to each power consumption circuit according to the circuit distribution information of each power consumption circuit and the preset load delay time includes: The group order of each group of power consumption circuits is determined according to the grouping of each power consumption circuit. Based on the arrangement of the first power consumption circuit in the first group of power consumption circuits, the circuit order of the first power consumption circuit in the first group of power consumption circuits is determined, wherein the first group of power consumption circuits is any group of power consumption circuits in all groups of power consumption circuits, and the first power consumption circuit is any power consumption circuit in the first group of power consumption circuits. The current power consumption circuit group to be loaded is determined according to the group order of each group of power consumption circuits. The current power consumption circuit to be loaded is determined according to the circuit sequence of each power consumption circuit in the current power consumption circuit group. The current power consumption circuit is loaded to the target power corresponding to the current power consumption circuit; After waiting for the preset load delay time corresponding to the current power consumption circuit, the next power consumption circuit group is determined according to the group order. The next power consumption circuit to be loaded in the next power consumption circuit group is determined according to the circuit sequence in the next power consumption circuit group. This continues until it is confirmed that each of the power consumption circuits in all groups has been fully loaded.

7. A power consumption load-bearing device, characterized in that, The device includes: The acquisition module is used to acquire the power consumption load command of the interface to be tested, as well as the preset load delay time corresponding to each power consumption circuit. The parsing module is used to parse the power load command and obtain the load power of the target optical port test fixture. The target optical port test fixture is used to perform power consumption testing on the interface to be tested. The target optical port test fixture includes multiple power consumption circuits. The determination module is used to determine the target power of each power consumption circuit based on the load power and the correspondence between the load power and each power consumption circuit in the target optical port test fixture. The sorting module is used to sort all the power consumption circuits according to the target power of each power consumption circuit, and determine the loading order of each power consumption circuit. The control module is used to sequentially control each power consumption circuit to be loaded to the target power corresponding to that power consumption circuit according to the loading order of each power consumption circuit and the preset loading delay time. The control module includes: The second determining unit is used to determine the current power consumption circuit to be loaded according to the loading sequence of each power consumption circuit; The first control unit is used to control the current power consumption circuit to generate an enable signal; according to the enable signal, it controls the switching state of the preset switch in the current power consumption circuit to the target state, and the target state is used to indicate that the current power consumption circuit is pulled to the target power corresponding to the current power consumption circuit. The waiting unit is used to wait for the first preset load delay time and then select the next power consumption circuit according to the load order of each power consumption circuit. The second control unit is used to control the power load of the next power consumption circuit to the target power corresponding to the next power consumption circuit, until it is determined that each power consumption circuit has been fully loaded. The first preset load delay time is the preset load delay time between the current power consumption circuit and the next power consumption circuit.

8. A test fixture, characterized in that, The test fixture includes multiple power consumption circuits and a controller. Each power consumption circuit is connected to the controller. At least two of the multiple power consumption circuits are target power consumption circuits that power the controller. Each target power consumption circuit is connected to a delay circuit. The controller in the test fixture is used to execute the power consumption loading method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to perform the power consumption loading method according to any one of claims 1 to 6.

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