Methods, apparatus, equipment and media for determining the number of multi-channel error symbol flags

Abstract

This application discloses a method, apparatus, device, and medium for determining the number of multi-channel error symbol flags, relating to the field of computer communication. It converts the serial input of each code block into p-channel parallel inputs, allowing calculation of the p-channel parallel inputs of each code block using a preset parallelism degree p. Based on a parallel search method, it determines the error symbol flags of the target channel corresponding to each code block within the preset parallelism degree p. It distributes all symbol flags of each code block into a preset number of channels according to a preset interleaving distribution rule, generating first-channel data which is sent to the optical module receiving channel, and receives the returned second-channel data. Based on the second-channel data, it alternately accumulates and calculates the error symbol flags corresponding to each channel in the preset number of channels for each code block in each decoding cycle, determining the total number of error symbol flags for all code blocks in these channels during the current decoding process. This achieves the calculation of the number of multi-channel error symbols.

Description

[0001] This application is a divisional application of Chinese Patent Application No. 202310460591.X, filed with the Chinese Patent Office on April 26, 2023, entitled "A method, apparatus, device and medium for determining the number of error symbol flags". Technical Field

[0002] This invention relates to the field of computer communication, and in particular to a method, apparatus, device, and medium for determining the number of multi-channel error symbol flags. Background Technology

[0003] Reed-Solomon (RS) decoding is a type of Forward Error Correction (FEC) decoding technology. It is widely used in communication systems to ensure data accuracy. Its basic idea is to re-encode the information to be transmitted at the transmitting end, adding redundant check information to form a longer codeword (code block). Upon reaching the receiving end, if the error is within correctable limits, it is corrected through decoding, thereby reducing the bit error rate and improving the reliability of the communication system. In optical communication systems, FEC processing can effectively reduce the system's bit error rate and extend transmission distance with minimal redundancy overhead, thus reducing system costs.

[0004] Although parallel RS decoding is widely used, most applications are in RS(255,239) and similar modes. While some applications exist in RS(544,514), or RS decoder implementations have been proposed, direct decoding only restores the data without providing a method for calculating multi-channel error symbols. Currently, only hard-core RS decoder IPs integrated within FPGA (Field Programmable Gate Array) chips exist, but licenses are required. Some hard-core IPs provide the number of multi-channel error symbols, and some organizations or companies have implemented these methods, but these implementations are kept confidential. Although some papers or patents propose 100G RS decoders, few provide methods for calculating the number of multi-channel error symbols. A method for calculating multi-channel error symbols in a 400G RS decoder is particularly important for evaluating single-channel signal quality, jitter, and performance, and plays a crucial guiding role in the research, design, and optimization of module channels.

[0005] As can be seen from the above, how to provide a method for calculating the number of multi-channel error symbols during RS parallel decoding is a problem that needs to be solved in this field. Summary of the Invention

[0006] In view of this, the purpose of this invention is to provide a method, apparatus, device, and medium for determining the number of multi-channel error symbol flags, capable of calculating the number of multi-channel error symbols. The specific solution is as follows:

[0007] Firstly, this application discloses a method for determining the number of multi-channel error symbol flags, including:

[0008] The serial input of each code block is converted into p parallel inputs, with each input having the same bit width, so that the p parallel inputs of each code block can be calculated using a preset parallelism degree p.

[0009] The error symbol flag of each code block in the target path of the preset parallelism p is determined based on the parallel search method; wherein, the error symbol flag of each code block in the target path of the p path is determined in advance according to the preset error position determination rule, and the target path is the path in the p path that contains the error symbol flag;

[0010] The first channel data generated by distributing all symbol flags corresponding to each code block into a preset number of channels according to a preset interleaving distribution rule is sent to the optical module receiving channel, and the second channel data returned by the optical module receiving channel is used to determine the channel to which each erroneous symbol flag in the first channel data belongs.

[0011] Based on the second channel data, the error symbol flags corresponding to each channel in each decoding cycle corresponding to each code block are cumulatively calculated in an alternating cumulative manner to determine the total number of error symbol flags corresponding to all code blocks in the preset number of channels during the current decoding process.

[0012] Optionally, the determination of the error symbol flag of the target path corresponding to each code block in a preset parallelism p based on the parallel Qian search method includes:

[0013] The error position polynomial coefficients are determined based on a preset parallelism p in each decoding cycle during the current decoding process using a parallel search method, and the error position polynomial is determined based on the error position polynomial coefficients corresponding to each decoding cycle.

[0014] The path corresponding to the sum of the even-numbered terms and the sum of the odd-numbered terms in the error position polynomial in the preset parallelism p is determined as the target path containing the error symbol flag.

[0015] Optionally, the step of distributing all symbol flags corresponding to each code block to a preset number of channels according to a preset interleaving distribution rule to generate first channel data and sending it to the optical module receiving channel includes:

[0016] The first channel data generated by distributing all symbol flags corresponding to each code block into a preset number of channels according to a preset interleaving distribution rule through the transmitting end of the high-speed optical transceiver is sent to the receiving channel of the optical module.

[0017] Accordingly, the second channel data returned by the optical module receiving channel for determining the channel to which each error symbol flag in the first channel data belongs includes:

[0018] The receiver of the high-speed optical transceiver receives the second channel data returned by the optical module's receiving channel, which is used to determine the channel to which each error symbol flag in the first channel data belongs.

[0019] Optionally, the determination of the error symbol flag of the target path corresponding to each code block in a preset parallelism p based on the parallel Qian search method includes:

[0020] Using a p-bit register, the error symbol flag of the target path corresponding to each code block in a preset parallelism p is determined based on the parallel search method.

[0021] Optionally, the step of cumulatively calculating the error symbol flags corresponding to each channel in the preset number of channels in each decoding cycle corresponding to each code block based on the second channel data in an alternating cumulative calculation manner, to determine the total number of error symbol flags corresponding to all code blocks in the preset number of channels during the current decoding process, includes:

[0022] Define a first calculation group and a second calculation group for calculating the error symbol flag value of each channel in a preset number of channels for each code block;

[0023] The target flag bit for controlling level toggling is determined based on the start input signal of each code block;

[0024] Using the error flag alternation accumulation method determined based on the second channel data, the first calculation group, the second calculation group, and the target flag bit, the error symbol flags corresponding to each channel in the preset number of channels in each decoding cycle corresponding to each code block are accumulated and calculated to determine the total number of error symbol flags in the preset number of channels corresponding to all code blocks in the current decoding process.

[0025] Optionally, the process of accumulating the error symbol flags corresponding to each channel in the preset number of channels in each decoding cycle corresponding to each code block using the error flag alternating accumulation method determined based on the second channel data, the first calculation group, the second calculation group, and the target flag bit includes:

[0026] When the target flag is the first flag, the second channel data is used to assign a value to the first calculation group, and the second calculation group is assigned a value of 0;

[0027] When the target flag is the second flag, the second calculation group is assigned a value using the second channel data, and the first calculation group is assigned a value of 0.

[0028] Optionally, the process of cumulatively calculating the error symbol flags corresponding to each channel in the preset number of channels in each decoding cycle corresponding to each code block based on the second channel data in an alternating cumulative calculation manner, to determine the total number of error symbol flags corresponding to all code blocks in the preset number of channels during the current decoding process, includes:

[0029] A counter is generated to count the input signal of the code block, so that when the count value in the counter is the target number of cycles corresponding to the current code block, the count in the counter is updated, and the flag bit of the target signal used to record the code block processing process is switched to a flag bit indicating that the current code block processing is completed.

[0030] When the flag bit of the target signal is a flag bit indicating that the current code block processing is complete, the error symbol flag is cumulatively calculated using the calculated values ​​in the current first calculation group and the second calculation group.

[0031] Secondly, this application discloses a device for determining the number of multi-channel error symbol flags, comprising:

[0032] The input conversion module is used to convert the serial input of each code block into p-path parallel inputs, with each path having the same bit width, so as to perform calculations on the p-path parallel inputs of each code block using a preset parallelism degree p.

[0033] The parallel money search module is used to determine the error symbol flag of the target path corresponding to each code block in a preset parallelism p based on the parallel money search method; wherein, the error symbol flag of each code block corresponding to the p path is determined in advance according to the preset error position determination rule, and the target path is the path containing the error symbol flag in the p path;

[0034] The data processing module is used to distribute all the symbol flags corresponding to each code block to a preset number of channels according to a preset interleaving distribution rule to generate first channel data, which is then sent to the optical module receiving channel, and to receive second channel data returned by the optical module receiving channel for determining the channel to which each erroneous symbol flag in the first channel data belongs.

[0035] The data accumulation module is used to accumulate the error symbol flags corresponding to each channel in the preset number of channels in each decoding cycle corresponding to each code block based on the second channel data in an alternating accumulation calculation manner, so as to determine the total number of error symbol flags corresponding to all code blocks in the preset number of channels during the current decoding process.

[0036] Thirdly, this application discloses an electronic device, including:

[0037] Memory, used to store computer programs;

[0038] A processor is used to execute the computer program to implement the aforementioned method for determining the number of multi-channel error symbol flags.

[0039] Fourthly, this application discloses a computer storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the steps of the aforementioned disclosed method for determining the number of multi-channel error symbol flags.

[0040] The beneficial effect of this invention is that it provides a method, apparatus, device, and medium for determining the number of multi-channel error symbol flags: First, the serial input of each code block is converted into p-path parallel inputs, so that the p-path parallel inputs of each code block can be calculated using a preset parallelism degree p; the error symbol flags of the target path corresponding to each code block in the preset parallelism degree p are determined based on a parallel search method; wherein the target path is a path in the p-paths that contains error symbol flags; the first channel data generated by distributing all symbol flags corresponding to each code block to a preset number of channels according to a preset interleaving distribution rule is sent to the optical module receiving channel, and the second channel data returned by the optical module receiving channel is received to determine the channel to which each error symbol flag in the first channel data belongs; based on the second channel data, the error symbol flags corresponding to each channel in the preset number of channels in each decoding cycle corresponding to each code block are cumulatively calculated in an alternating cumulative calculation manner to determine the total number of error symbol flags of all code blocks in the preset number of channels during the current decoding process. In this way, the present invention uses a parallel search method to determine the error symbol flag of the target path corresponding to each code block in a preset parallelism p. After determining the channel to which each error symbol flag belongs, the error symbol flags corresponding to each channel in the preset number of channels in each decoding cycle corresponding to each code block are accumulated by an alternating cumulative calculation method to determine the total number of error symbol flags of all code blocks in the preset number of channels during the current decoding process. This ultimately solves the problem of calculating the number of error symbols in multiple channels and realizes the calculation of the number of error symbols in multiple channels. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0042] Figure 1 A flowchart of a method for determining the number of multi-channel error symbol flags provided in this application;

[0043] Figure 2 This application provides a schematic diagram of a multi-channel codeword distribution.

[0044] Figure 3 A schematic diagram of a 64-channel parallel distribution per cycle is provided for this application;

[0045] Figure 4 A flowchart illustrating a specific method for determining the number of multi-channel error symbol flags provided in this application;

[0046] Figure 5 A schematic diagram of a device for determining the number of multi-channel error symbol flags provided in this application;

[0047] Figure 6 This application provides a structural diagram of an electronic device. Detailed Implementation

[0048] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0049] In the existing technology, there are currently only hard-core RS decoder IPs integrated inside FPGA chips, but licenses are required. Some hard-core decoders also specify the number of multi-channel error symbols, and some foreign organizations or companies have implemented them, but the implementation methods are kept confidential. Although some papers or patents have proposed 100GRS decoders, few provide methods for calculating the number of multi-channel error symbols. This application provides a method, apparatus, device, and medium for determining the number of multi-channel error symbol flags, which can realize the calculation of the number of multi-channel error symbols.

[0050] This invention discloses a method for determining the number of multi-channel error symbol flags, see [link to relevant documentation]. Figure 1 The method includes:

[0051] Step S11: Convert the serial input of each code block into p parallel inputs, with each input having the same bit width, so that the p parallel inputs of each code block can be calculated using a preset parallelism p.

[0052] Step S12: Determine the error symbol flag of the target path corresponding to each code block in the preset parallelism p based on the parallel search method; wherein, the error symbol flag of the target path corresponding to each code block in the p path is determined in advance according to the preset error position determination rule, and the target path is the path in the p path that contains the error symbol flag.

[0053] In this embodiment, assuming that the number of information symbols input to the RS high-speed decoding circuit is k and the bit width of the symbol is m, then the total bit width of each codeword input to the RS high-speed decoding circuit is k·m; the total bit width serial input is converted into p-way parallel input, and the bit width of each way is symbol_size bits.

[0054] FEC decoding is usually represented in the form RS(n,k,t,m), where:

[0055] n: frame size[symbol], indicating that there are n symbols in one code block;

[0056] k: message size[symbol], representing the number of information symbols out of n code elements;

[0057] t: correctable symbol error per frame, representing the correctable symbol data, and nk = 2t;

[0058] m: symbol size [bit], indicating that a single symbol consists of m bits, i.e., the bit width.

[0059] Additionally, p represents the parallelism of the parallel decoding, which is the preset parallelism p in this invention. Since 400G has high requirements for the parallelism of p, it is generally taken to be greater than 32. In specific implementation, if p is divisible by n, the decoding cycle c is c = n / p; if p is not divisible by n, the decoding cycle c = n / p is rounded down and incremented by 1. For cases where p is not divisible by n, we use a leading zero-padding method, that is, we add u zero symbols to the front of a codeword, where u is n mod p, thus forming a total of c × p symbols, which are calculated in c cycles. For example, in RS(544,514) n = 544, k = 514, and the parallelism p is 64, then u = 32, that is, 32 zero symbols need to be added; C = 544 / 64 + 1 = 9, and the calculation of 9 × 64 = 576 symbols of the codeword is completed in 9 cycles.

[0060] In this step, the error symbol flag for each code block in the target path within a preset parallelism p is determined using a parallel search method. It is understood that during the actual decoding process of the code block, the symbols corresponding to the code block are computed in parallel across p paths. In this step, the error symbol flag for each code block in the p paths can be determined by pre-setting error location determination rules.

[0061] In this embodiment, determining the error symbol flag of the target path corresponding to each code block in a preset parallelism p based on the parallel Qian search method may include: using a register with a bit width of p bits to determine the error symbol flag of the target path corresponding to each code block in a preset parallelism p based on the parallel Qian search method. It can be understood that in this embodiment, a register with a bit width of p bits can be used to perform simultaneous calculations on p parallel circuits.

[0062] Step S13: Distribute all symbol flags corresponding to each code block into a preset number of channels according to a preset interleaving distribution rule to generate first channel data, send it to the optical module receiving channel, and receive second channel data returned by the optical module receiving channel to determine the channel to which each erroneous symbol flag in the first channel data belongs.

[0063] Specifically, different Ethernet protocols define different interleaving distribution rules, but the principle is the same. This method is applicable to different protocols, and the preset interleaving distribution rule mentioned in this step is preferably the interleaving distribution rule in section 119.2.4.8 of IEEE 802.3bs-2017.

[0064] In this step, data from each channel is sent to the corresponding optical module receiving channel, and the data is received back. Based on the received data, the specific channel corresponding to each error symbol is determined, which makes it easier to accumulate the number of error symbols for that channel later.

[0065] Step S14: Based on the second channel data, the error symbol flags corresponding to each channel in the preset number of channels in each decoding cycle corresponding to each code block are cumulatively calculated in an alternating cumulative calculation manner to determine the total number of error symbol flags in the preset number of channels corresponding to all code blocks in the current decoding process.

[0066] In this embodiment, the received second channel data can be used to accumulate the error symbol flags corresponding to each channel in each predetermined number of channels within each decoding cycle corresponding to each code block using an alternating cumulative calculation method. In a specific implementation, when decoding each code block, the calculation of c×p symbol flags is completed within c cycles. Each of the c cycles is interleaved and distributed across a predetermined number of channels with a parallelism of p, such as... Figure 2 The figure shows a schematic diagram of a multi-channel codeword distribution using RS(544, 514) as an example in this embodiment. The 544 codeword markers (i.e., CA_0 to CA_543 in the figure) are distributed in an interleaved manner in the 16 channels. Figure 3 This is a schematic diagram of a multi-channel distribution of p symbols per cycle proposed in this invention. Taking p as an example, the diagram shows 64 symbol flags (sym_0 to sym_63 in the diagram) distributed in an interleaved manner across 16 channels. In this embodiment, after the symbol flags are interleaved, the second channel data of the channel to which each erroneous symbol flag belongs can be used to accumulate the erroneous symbol flags corresponding to each channel in each predetermined number of channels in each decoding cycle corresponding to each code block in an alternating cumulative calculation method. In a specific implementation, it can be understood that the erroneous symbol flags of the even-numbered codewords and the erroneous symbol flags of the odd-numbered codewords are calculated using two different sets of calculation groups. This alternating counting method ensures the continuity of counting due to the continuity of data. Specifically, for each codeword, after completing the calculation in c cycles, we can obtain the number of erroneous symbols in the 16 channels corresponding to the current codeword in c cycles. After performing the corresponding calculation for each codeword, we can obtain the number of erroneous symbols in all channels across all cycles corresponding to all codewords in the current decoding process.

[0067] In this embodiment, the serial input of each code block is first converted into p-path parallel input; the error symbol flags of the target path corresponding to each code block in the preset parallelism p are determined based on the parallel Qian search method; wherein the target path is a path in the p-path that contains error symbol flags; the first channel data generated by distributing all symbol flags corresponding to each code block to a preset number of channels according to a preset interleaving distribution rule is sent to the optical module receiving channel, and the second channel data returned by the optical module receiving channel is received to determine the channel to which each error symbol flag in the first channel data belongs; based on the second channel data, the error symbol flags corresponding to each channel in the preset number of channels in each decoding cycle corresponding to each code block are cumulatively calculated in an alternating cumulative calculation manner to determine the total number of error symbol flags of all code blocks in the preset number of channels in the current decoding process. In this way, the parallel search method is used to determine the error symbol flag of the target path corresponding to each code block in the preset parallelism p. After determining the channel to which each error symbol flag belongs, the error symbol flags corresponding to each channel in the preset number of channels in each decoding cycle corresponding to each code block are accumulated by alternating cumulative calculation to determine the total number of error symbol flags of all code blocks in the preset number of channels in the current decoding process. This solves the problem of calculating the number of error symbols in multiple channels and realizes the calculation of the number of error symbols in multiple channels.

[0068] Figure 4 A flowchart illustrating a specific method for determining the number of multi-channel error symbol flags provided in this application embodiment. See also... Figure 4 As shown, the method includes:

[0069] Step S21: Determine the error position polynomial coefficients in each decoding cycle during the current decoding process based on the parallel Qian search method, using a preset parallelism p as the basis, and determine the error position polynomial based on the error position polynomial coefficients corresponding to each decoding cycle.

[0070] In this embodiment, in the serial case, r (n-1) r (n -2), ..., r0 need to be calculated sequentially to satisfy the serial money search. Since the serial approach is inefficient, a parallel money search circuit of p times is needed to meet the 400G speed requirement. The parallel money search circuit proposed in this step is as follows:

[0071]

[0072] In the above formula, matrix A is a p-row, i-column matrix. Each coefficient in the matrix can be calculated using pre-defined calculation software, and each coefficient is a constant-coefficient multiplier over the Galois field. The pre-defined calculation software includes, but is not limited to, MATLAB.

[0073] In the above formula This represents the value of each path in the p-path parallel Qian search, with a total of p paths, where p is the degree of parallelism, i is the number of polynomial coefficients at error locations after solving the key equation in the RS decoding, and the matrix lambda is used to calculate the coefficients of the Qian search. This represents the coefficients of the error position polynomial calculated in each cycle; after solving the RS decoding key equation, i initial position polynomial coefficients are obtained, which are the initial input coefficients of the money search in this invention; let the i initial error position polynomial coefficients obtained from solving the RS decoding key equation be...

[0074] In the first cycle, in the above formula These are the polynomial coefficients at the i initial error positions obtained by solving the key equation for RS decoding, which are...

[0075] The second period is used to calculate the polynomial coefficients at the error locations. That is, the coefficients of the erroneous polynomial are α p Increasing;

[0076] The third period is used to calculate the polynomial coefficients at the error locations.

[0077]

[0078] …

[0079] In the c-th period, the polynomial coefficients at the error location are calculated.

[0080] Step S22: Determine the path corresponding to the sum of even-numbered terms and the sum of odd-numbered terms in the error position polynomial of the preset parallelism p as the target path containing the error symbol flag.

[0081] In the specific implementation of this embodiment, it is necessary to calculate the error position polynomial at error position α. -i The value on, specifically, the error position polynomial λ(α) -i )=λ(α n-i )=λ even (α n-i )+λ odd (α n-i ), i=0, 1,...,n-1. If λ(α -i If ) = 0, then r i The position is incorrect. In the incorrectly positioned polynomial, It is the value obtained by adding the even-numbered terms of the i-th path in path p. The value is obtained by adding the odd-numbered terms of the i-th path in path p. There is an error at this position in this embodiment. When , we can determine that symi is 1, i = 0, 1, 2…p-1; when Given that sym_i is 0, the target path in this embodiment is the i-th path when sym_i is 1.

[0082] Step S23: The transmitting end of the high-speed optical transceiver distributes all the symbol flags corresponding to each code block into a preset number of channels according to a preset interleaving distribution rule to generate the first channel data, which is then sent to the receiving channel of the optical module. The receiving end of the high-speed optical transceiver receives the second channel data returned by the receiving channel of the optical module, which is used to determine the channel to which each erroneous symbol flag in the first channel data belongs.

[0083] Specifically, after each codeword is encoded, it is distributed to multiple channels according to its interleaving rules. The data of each channel is sent to the corresponding optical module receiving channel through the PHY. The PHY receiving channel receives the data sent by the optical module and receives the data back. Therefore, the specific channel corresponding to each symbol can be determined according to the position of each symbol.

[0084] Step S24: Define a first calculation group and a second calculation group for calculating the error symbol flag value of each channel in a preset number of channels for each code block, and determine the target flag bit for controlling level flipping based on the start input signal of each code block.

[0085] Specifically, in this embodiment, the number of error symbols for each codeword in lanes 0 to 1516 can be defined. The first calculation group consists of eA_sym_ln0<5:0>, eA_sym_ln1<5:0>, eA_sym_ln2<5:0>, eA_sym_ln3<5:0>, eA_sym_ln4<5:0>, eA_sym_ln5<5:0>, eA_sym_ln6<5:0>, eA_sym_ln7<5:0>, eA_sym_ln8<5:0>, eA_sym_ln9<5:0>, eA_sym_ln10<5:0>, and eA_sym_ln1 1<5:0>, eA_sym_ln12<5:0>, eA_sym_ln13<5:0>, eA_sym_ln14<5:0>, eA_sym_ln15<5:0>;

[0086] The second calculation group is eB_sym_ln0<5:0>, eB_sym_ln1<5:0>, eB_sym_ln2<5:0>, eB_sym_ln3<5:0>, eB_sym_ln4<5:0>, eB_sym_ln 5<5:0>, eB_sym_ln6<5:0>, eB_sym_ln7<5:0>, eB_sym_ln8<5:0>, eB_sym_ln9<5:0>, eB_sym_ln10<5:0>, eB_sym_ln1 1<5:0>, eB_sym_ln12<5:0>, eB_sym_ln13<5:0>, eB_sym_ln14<5:0>, eB_sym_ln15<5:0>.

[0087] Step S25: Using the error flag alternation accumulation method determined based on the second channel data, the first calculation group, the second calculation group, and the target flag bit, the error symbol flags corresponding to each channel in the preset number of channels in each decoding cycle corresponding to each code block are accumulated and calculated to determine the total number of error symbol flags in the preset number of channels corresponding to all code blocks in the current decoding process.

[0088] In this embodiment, the error flag alternating accumulation method can be a method of generating a ping-pong flag (i.e., target flag bit) sym_pp_flag (initialized to 0) based on the initial input in_pluse of each codeword, and performing accumulation calculations based on sym_pp_flag. Specifically, in_pluse is an input signal that is high in the first cycle of each codeword and low in other cycles. When in_pluse is 1, the level of sym_pp_flag toggles; when in_pluse is otherwise, the level of sym_pp_flag remains unchanged.

[0089] In this embodiment, the method of alternating accumulation of error flags based on the second channel data, the first calculation group, the second calculation group, and the target flag bit to accumulate the error symbol flags corresponding to each channel in the preset number of channels in each decoding cycle corresponding to each code block may include: when the target flag bit is the first flag bit, assigning a value to the first calculation group using the second channel data and assigning the value of the second calculation group to 0; when the target flag bit is the second flag bit, assigning a value to the second calculation group using the second channel data and assigning the value of the first calculation group to 0.

[0090] Specifically, when sym_pp_flag is 1, in the first calculation group

[0091] eA_sym_ln0=eA_sym_ln0+sym_0+sym_16+sym_32+sym_48;

[0092] eA_sym_ln1=eA_sym_ln1+sym_8+sym_24+sym_40+sym_56;

[0093] eA_sym_ln2=eA_sym_ln2+sym_1+sym_17+sym_33+sym_49;

[0094] eA_sym_ln3=eA_sym_ln3+sym_9+sym_25+sym_41+sym_57;

[0095] eA_sym_ln4=eA_sym_ln4+sym_2+sym_18+sym_34+sym_50;

[0096] eA_sym_ln5=eA_sym_ln5+sym_10+sym_26+sym_42+sym_58;

[0097] eA_sym_ln6=eA_sym_ln6+sym_3+sym_19+sym_35+sym_51;

[0098] eA_sym_ln7=eA_sym_ln7+sym_11+sym_27+sym_43+sym_59;

[0099] eA_sym_ln8=eA_sym_ln8+sym_4+sym_20+sym_36+sym_52;

[0100] eA_sym_ln9=eA_sym_ln9+sym_12+sym_28+sym_44+sym_60;

[0101] eA_sym_ln10=eA_sym_ln10+sym_5+sym_21+sym_37+sym_53;

[0102] eA_sym_ln11=eA_sym_ln11+sym_13+sym_29+sym_45+sym_61;

[0103] eA_sym_ln12=eA_sym_ln12+sym_6+sym_22+sym_38+sym_54;

[0104] eA_sym_ln13 = eA_sym_ln13 + sym_14 + sym_30 + sym_46 + sym_62;

[0105] eA_sym_ln14 = eA_sym_ln14 + sym_7 + sym_23 + sym_39 + sym_55;

[0106] eA_sym_ln15 = eA_sym_ln15 + sym_15 + sym_31 + sym_47 + sym_63;

[0107] All of eB_sym_ln0 to eB_sym_ln15 in the second calculation group are 0;

[0108] When sym_pp_flag is 0, in the second calculation group

[0109] eB_sym_ln0 = eB_sym_ln0 + sym_0 + sym_16 + sym_32 + sym_48;

[0110] eB_sym_ln1 = eB_sym_ln1 + sym_8 + sym_24 + sym_40 + sym_56;

[0111] eB_sym_ln2 = eB_sym_ln2 + sym_1 + sym_17 + sym_33 + sym_49;

[0112] eB_sym_ln3 = eB_sym_ln3 + sym_9 + sym_25 + sym_41 + sym_57;

[0113] eB_sym_ln4 = eB_sym_ln4 + sym_2 + sym_18 + sym_34 + sym_50;

[0114] eB_sym_ln5 = eB_sym_ln5 + sym_10 + sym_26 + sym_42 + sym_58;

[0115] eB_sym_ln6 = eB_sym_ln6 + sym_3 + sym_19 + sym_35 + sym_51;

[0116] eB_sym_ln7 = eB_sym_ln7 + sym_11 + sym_27 + sym_43 + sym_59;

[0117] eB_sym_ln8 = eB_sym_ln8 + sym_4 + sym_20 + sym_36 + sym_52;

[0118] eB_sym_ln9=eB_sym_ln9+sym_12+sym_28+sym_44+sym_60;

[0119] eB_sym_ln10=eB_sym_ln10+sym_5+sym_21+sym_37+sym_53;

[0120] eB_sym_ln11=eB_sym_ln11+sym_13+sym_29+sym_45+sym_61;

[0121] eB_sym_ln12=eB_sym_ln12+sym_6+sym_22+sym_38+sym_54;

[0122] eB_sym_ln13=eB_sym_ln13+sym_14+sym_30+sym_46+sym_62;

[0123] eB_sym_ln14=eB_sym_ln14+sym_7+sym_23+sym_39+sym_55;

[0124] eB_sym_ln15=eB_sym_ln15+sym_15+sym_31+sym_47+sym_63;

[0125] The first calculation group's eA_sym_ln0 to eA_sym_ln15 are all 0;

[0126] The method described above, which alternately accumulates the number of multi-channel error symbols for each codeword, involves resetting the multi-channel error symbol counts for the first codeword to zero in the ranges of eA_sym_ln0 to eA_sym_ln15 and eB_sym_ln0 to eB_sym_ln15, respectively. The same applies to the second codeword and the third and fourth codewords. This alternating counting ensures the continuity of the count, given the continuous nature of the data.

[0127] After the codeword calculation is completed in c cycles, we can define the number of error symbols for the 16 channels from lane0 to lane15, e_sym0<5:0> to e_sym15<5:0>.

[0128] When sym_pp_flag is 1:

[0129] e_sym0<5:0>~e_sym15<5:0> are respectively equal to eA_sym_ln0~eAsym_ln15;

[0130] When sym_pp_flag is 0:

[0131] e_sym0<5:0>~e_sym15<5:0> are respectively equal to eB_sym_ln0~eB_sym_ln15.

[0132] In this embodiment, the process of cumulatively calculating the error symbol flags corresponding to each channel in each decoding cycle corresponding to each code block in an alternating cumulative calculation manner based on the second channel data to determine the total number of error symbol flags corresponding to all code blocks in the preset number of channels during the current decoding process may include: generating a counter for counting the input signal of the code block, so that when the count value in the counter is the target cycle number corresponding to the current code block, the count in the counter is updated, and the flag bit of the target signal used to record the code block processing process is switched to a flag bit indicating the completion of the current code block processing; when the flag bit of the target signal is a flag bit indicating the completion of the current code block processing, the error symbol flags are cumulatively calculated using the calculated values ​​in the first calculation group and the second calculation group.

[0133] That is, in this embodiment, a counter cw_cnt is generated based on the initial input in_pluse of each codeword. cw_cnt is incremented by 1 in each cycle. When the counter equals c cycles, it indicates that a codeword has been calculated and a high-level 1 signal sym_adden is generated. When the counter is not equal to c, sym_adden is low-level 0; at the same time, the value of cw_cnt is 0. The count is based on the in_pluse of the next codeword, and so on.

[0134] In a specific implementation, this embodiment can define 16 accumulator circuits, symbol_add0 to symbol_add15. When symbol_add0 to symbol_add15 is 1, e_sym0 to e_sym15 are added respectively. When symbol_adden is 0, it remains unchanged, and the accumulation calculation is completed in one step.

[0135] In this embodiment, after determining the coefficients of the error polynomial, the location of the error symbol is determined based on the error polynomial. After the symbols are interleaved and distributed, the number of error symbols is cumulatively calculated based on the second channel data using the first and second calculation groups and the target flag. This realizes the calculation of the number of error symbols for each channel, solving the problem of multi-channel error symbol calculation, which is crucial for evaluating the signal quality of each channel of the module. The use of a parallel search method to determine the error symbol location improves computational efficiency and solves the problem of low efficiency in serial and low-parallel search methods.

[0136] See Figure 5 As shown in the figure, this application discloses a device for determining the number of multi-channel error symbol flags, which may specifically include:

[0137] The input conversion module 11 is used to convert the serial input of each code block into p-way parallel input, with each way having the same bit width, so as to perform calculations on the p-way parallel input of each code block by means of a preset parallelism p.

[0138] The parallel money search module 12 is used to determine the error symbol flag of the target path corresponding to each code block in the preset parallelism p based on the parallel money search method; wherein, the error symbol flag of each code block corresponding to the p path is determined in advance according to the preset error position determination rule, and the target path is the path containing the error symbol flag in the p path;

[0139] Data processing module 13 is used to send the first channel data generated by distributing all symbol flags corresponding to each code block to a preset number of channels according to a preset interleaving distribution rule to the optical module receiving channel, and to receive the second channel data returned by the optical module receiving channel for determining the channel to which each erroneous symbol flag in the first channel data belongs.

[0140] The data accumulation module 14 is used to accumulate the error symbol flags corresponding to each channel in the preset number of channels in each decoding cycle corresponding to each code block based on the second channel data in an alternating accumulation calculation manner, so as to determine the total number of error symbol flags corresponding to all code blocks in the preset number of channels during the current decoding process.

[0141] This invention first determines the error symbol flags of the target path corresponding to each code block in a preset parallelism p based on a parallel search method; wherein the target path is a path containing error symbol flags in p paths; the first channel data generated by distributing all symbol flags corresponding to each code block to a preset number of channels according to a preset interleaving distribution rule is sent to the optical module receiving channel, and the second channel data returned by the optical module receiving channel is received to determine the channel to which each error symbol flag in the first channel data belongs; based on the second channel data, the error symbol flags corresponding to each channel in the preset number of channels in each decoding cycle corresponding to each code block are cumulatively calculated in an alternating cumulative calculation manner to determine the total number of error symbol flags of all code blocks corresponding to the preset number of channels in the current decoding process. In this invention, the error symbol flags of the target path corresponding to each code block are determined by a parallel Qian search method within a preset parallelism p. After determining the channel to which each error symbol flag belongs, the error symbol flags corresponding to each channel in each preset number of channels in each decoding cycle corresponding to each code block are cumulatively calculated using an alternating cumulative calculation method. This determines the total number of error symbol flags corresponding to all code blocks in the preset number of channels during the current decoding process, ultimately solving the problem of multi-channel error symbol count calculation and realizing the calculation of multi-channel error symbol count. In specific implementation, a parallelism of 64 Qian search calculation can be used, which can ensure that the maximum clock frequency of the circuit is greater than 390MHz. With a data interface width of 1280 bits, a data throughput of over 425G / bits can be achieved, and the number of multi-channel error symbols can be continuously counted to measure the signal quality of each channel of the module.

[0142] Furthermore, embodiments of this application also disclose an electronic device, Figure 6 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content of the diagram should not be construed as limiting the scope of use of this application.

[0143] Figure 6 This is a schematic diagram of the structure of an electronic device 20 provided in an embodiment of this application. Specifically, the electronic device 20 may include: at least one processor 21, at least one memory 22, a power supply 23, a display screen 24, an input / output interface 25, a communication interface 26, and a communication bus 27. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the method for determining the number of multi-channel error symbol flags disclosed in any of the foregoing embodiments. Alternatively, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0144] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the electronic device 20; the communication interface 26 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0145] Furthermore, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk, or optical disk, etc. The resources stored on it can include an operating system 221, computer programs 222, and virtual machine data 223, etc. The virtual machine data 223 can include various types of data. The storage method can be temporary storage or permanent storage.

[0146] The operating system 221 is used to manage and control the various hardware devices on the electronic device 20 and the computer program 222, which may be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program capable of performing the method for determining the number of multi-channel error symbol flags executed by the electronic device 20 as disclosed in any of the foregoing embodiments, the computer program 222 may further include a computer program capable of performing other specific tasks.

[0147] Furthermore, this application also discloses a computer-readable storage medium, which includes random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, magnetic disks, optical disks, or any other form of storage medium known in the art. The computer program, when executed by a processor, implements the aforementioned method for determining the number of multi-channel error symbol flags. Specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.

[0148] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatuses disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple; relevant parts can be referred to the method section. Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0149] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0150] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0151] The above provides a detailed description of the method, apparatus, device, and storage medium for determining the number of multi-channel error symbol flags provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for determining the number of multi-channel error symbol flags, characterized in that, include: The serial input of each code block is converted into p parallel inputs, with each input having the same bit width, so that the p parallel inputs of each code block can be calculated using a preset parallelism degree p. The error symbol flag of each code block in the target path of the preset parallelism p is determined based on the parallel search method; wherein, the error symbol flag of each code block in the target path of the p path is determined in advance according to the preset error position determination rule, and the target path is the path in the p path that contains the error symbol flag; The first channel data generated by distributing all symbol flags corresponding to each code block into a preset number of channels according to a preset interleaving distribution rule is sent to the optical module receiving channel, and the second channel data returned by the optical module receiving channel is used to determine the channel to which each erroneous symbol flag in the first channel data belongs. Based on the second channel data, the error symbol flags corresponding to each channel in each decoding cycle corresponding to each code block are cumulatively calculated in an alternating cumulative manner to determine the total number of error symbol flags corresponding to all code blocks in the preset number of channels during the current decoding process.

2. The method for determining the number of multi-channel error symbol flags according to claim 1, characterized in that, The method based on parallel Qian search determines the error symbol flag of the target path corresponding to each code block in a preset parallelism p, including: The error position polynomial coefficients are determined based on a preset parallelism p in each decoding cycle during the current decoding process using a parallel search method, and the error position polynomial is determined based on the error position polynomial coefficients corresponding to each decoding cycle. The path corresponding to the sum of the even-numbered terms and the sum of the odd-numbered terms in the error position polynomial in the preset parallelism p is determined as the target path containing the error symbol flag.

3. The method for determining the number of multi-channel error symbol flags according to claim 1, characterized in that, The step of distributing all symbol flags corresponding to each code block to a preset number of channels according to a preset interleaving distribution rule to generate first channel data and sending it to the optical module receiving channel includes: The first channel data generated by distributing all symbol flags corresponding to each code block into a preset number of channels according to a preset interleaving distribution rule through the transmitting end of the high-speed optical transceiver is sent to the receiving channel of the optical module. Accordingly, the second channel data returned by the optical module receiving channel for determining the channel to which each error symbol flag in the first channel data belongs includes: The receiver of the high-speed optical transceiver receives the second channel data returned by the optical module's receiving channel, which is used to determine the channel to which each error symbol flag in the first channel data belongs.

4. The method for determining the number of multi-channel error symbol flags according to claim 1, characterized in that, The method based on parallel Qian search determines the error symbol flag of the target path corresponding to each code block in a preset parallelism p, including: Using a p-bit register, the error symbol flag of the target path corresponding to each code block in a preset parallelism p is determined based on the parallel search method.

5. The method for determining the number of multi-channel error symbol flags according to any one of claims 1 to 4, characterized in that, The step of cumulatively calculating the error symbol flags corresponding to each channel in the preset number of channels in each decoding cycle corresponding to each code block using an alternating cumulative calculation method based on the second channel data, to determine the total number of error symbol flags corresponding to all code blocks in the preset number of channels during the current decoding process, includes: Define a first calculation group and a second calculation group for calculating the error symbol flag value of each channel in a preset number of channels for each code block; The target flag bit for controlling level toggling is determined based on the start input signal of each code block; Using the error flag alternation accumulation method determined based on the second channel data, the first calculation group, the second calculation group, and the target flag bit, the error symbol flags corresponding to each channel in the preset number of channels in each decoding cycle corresponding to each code block are accumulated and calculated to determine the total number of error symbol flags in the preset number of channels corresponding to all code blocks in the current decoding process.

6. The method for determining the number of multi-channel error symbol flags according to claim 5, characterized in that, The method of alternating accumulation of error flags based on the second channel data, the first calculation group, the second calculation group, and the target flag bit, in the process of accumulating the error symbol flags corresponding to each channel in the preset number of channels in each decoding cycle corresponding to each code block, includes: When the target flag is the first flag, the second channel data is used to assign a value to the first calculation group, and the second calculation group is assigned a value of 0; When the target flag is the second flag, the second calculation group is assigned a value using the second channel data, and the first calculation group is assigned a value of 0.

7. The method for determining the number of multi-channel error symbol flags according to claim 6, characterized in that, The process of cumulatively calculating the error symbol flags corresponding to each channel in the preset number of channels in each decoding cycle corresponding to each code block based on the second channel data in an alternating cumulative calculation manner, to determine the total number of error symbol flags corresponding to all code blocks in the preset number of channels during the current decoding process, includes: A counter is generated to count the input signal of the code block, so that when the count value in the counter is the target number of cycles corresponding to the current code block, the count in the counter is updated, and the flag bit of the target signal used to record the code block processing process is switched to a flag bit indicating that the current code block processing is completed. When the flag bit of the target signal is a flag bit indicating that the current code block processing is complete, the error symbol flag is cumulatively calculated using the calculated values ​​in the current first calculation group and the second calculation group.

8. A device for determining the number of multi-channel error symbol flags, characterized in that, include: The input conversion module is used to convert the serial input of each code block into p-path parallel inputs, with each path having the same bit width, so as to perform calculations on the p-path parallel inputs of each code block using a preset parallelism degree p. The parallel money search module is used to determine the error symbol flag of the target path corresponding to each code block in a preset parallelism p based on the parallel money search method; wherein, the error symbol flag of each code block corresponding to the p path is determined in advance according to the preset error position determination rule, and the target path is the path containing the error symbol flag in the p path; The data processing module is used to distribute all the symbol flags corresponding to each code block to a preset number of channels according to a preset interleaving distribution rule to generate first channel data, which is then sent to the optical module receiving channel, and to receive second channel data returned by the optical module receiving channel for determining the channel to which each erroneous symbol flag in the first channel data belongs. The data accumulation module is used to accumulate the error symbol flags corresponding to each channel in the preset number of channels in each decoding cycle corresponding to each code block based on the second channel data in an alternating accumulation calculation manner, so as to determine the total number of error symbol flags corresponding to all code blocks in the preset number of channels during the current decoding process.

9. An electronic device, characterized in that, It includes a processor and a memory; wherein, when the processor executes a computer program stored in the memory, it implements the method for determining the number of multi-channel error symbol flags as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, Used to store a computer program; wherein, when the computer program is executed by a processor, it implements the method for determining the number of multi-channel error symbol flags as described in any one of claims 1 to 7.

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