A semiconductor structure and a method of manufacturing the same

Abstract

The embodiments of the present disclosure disclose a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a first transistor column and a second transistor column located on the substrate, the first transistor column and the second transistor column are arranged alternately, the first transistor column comprises a plurality of first transistors arranged along a first direction, the second transistor column comprises a plurality of second transistors arranged along the first direction, and the plurality of first transistors of the first transistor column are electrically connected to the second transistors of the second transistor column one by one. The length directions of the first transistors and the second transistors are the same, and the centers of the first transistors and the centers of the second transistors are offset in the first direction.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] Currently, common dynamic random access memories (DRAMs) typically consist of a single transistor and a capacitor (1T1C) forming a memory cell, with the capacitor used to store data. However, 1T1C DRAMs have high requirements for the amount of charge the capacitor can store, and reading from the capacitor is destructive, requiring rewriting after the read operation, increasing power consumption. Furthermore, the complex manufacturing process and large size of the capacitor make miniaturization a challenge.

[0003] Dual-transistor capacitor-less (2T0C) dynamic random access memory typically consists of a read transistor and a write transistor forming a memory structure. However, in related technologies, 2T0C dynamic random access memory has a relatively low integration density. Summary of the Invention

[0004] This disclosure provides a semiconductor structure, including:

[0005] Substrate;

[0006] A first transistor column and a second transistor column are located on the substrate, arranged alternately. The first transistor column includes a plurality of first transistors arranged along a first direction, and the second transistor column includes a plurality of second transistors arranged along the first direction. The plurality of first transistors in the first transistor column and the plurality of second transistors in the second transistor column are electrically connected in a one-to-one correspondence.

[0007] The first transistor and the second transistor have the same length direction, and the center of the first transistor and the center of the second transistor are offset in the first direction.

[0008] In some embodiments, the length direction of the first transistor and the second transistor is the first direction.

[0009] In some embodiments, the first transistor column and the second transistor column are arranged alternately along a second direction, the second direction being perpendicular to the first direction;

[0010] In the second direction, the projection of the first transistor overlaps with the projection of the second transistor.

[0011] In some embodiments, the first transistor includes a gate and a first electrode and a second electrode located on both sides of the gate, the second transistor includes a gate and a first electrode and a second electrode located on both sides of the gate, the first electrode and the second electrode are either sources or drains and are not the same, wherein the direction from the first electrode of the first transistor to the second electrode of the first transistor is the same as the direction from the first electrode of the second transistor to the second electrode of the second transistor.

[0012] In some embodiments, the method further includes: a plurality of bit lines located above the substrate and extending along the second direction, the bit lines being connected to the second terminal of the first transistor or the first terminal of the second transistor;

[0013] Multiple word lines located above the bit lines and extending along the first direction are connected to the first electrode of the first transistor or the gate of the second transistor.

[0014] In some embodiments, the system further includes at least one interconnect line located above the substrate, each interconnect line electrically connecting the gate of the first transistor to the second electrode of a corresponding second transistor, wherein the word line is located above the interconnect line.

[0015] In some embodiments, the plurality of word lines further includes: the plurality of word lines include first word lines and second word lines arranged alternately along a second direction, wherein the first word line is electrically connected to the first electrode of the first transistor, and the second word line is electrically connected to the gate of the second transistor;

[0016] The plurality of bit lines include a first bit line and a second bit line arranged alternately along a first direction. The first bit line is electrically connected to the second electrode of the first transistor, and the second bit line is electrically connected to the first electrode of the second transistor.

[0017] In some embodiments, the interconnect is electrically connected to the gate of the first transistor via a first contact plug, and the interconnect is electrically connected to the second electrode of the second transistor via a second contact plug.

[0018] In some embodiments, the first bit line is electrically connected to the second electrode of the first transistor via a third contact plug; the second bit line is electrically connected to the first electrode of the second transistor via a fourth contact plug; the first word line is electrically connected to the first electrode of the first transistor via a fifth contact plug; and the second word line is electrically connected to the gate of the second transistor via a sixth contact plug.

[0019] In some embodiments, the first transistor includes a read transistor and the second transistor includes a write transistor.

[0020] In some embodiments, the substrate material includes Inx Ga y Zn z O, where x, y, and z are positive integers greater than or equal to 1.

[0021] This disclosure also provides a method for manufacturing a semiconductor structure, including:

[0022] Provide substrate;

[0023] A first transistor column and a second transistor column are formed on the substrate, the first transistor column and the second transistor column are arranged alternately, the first transistor column includes a plurality of first transistors arranged along a first direction, the second transistor column includes a plurality of second transistors arranged along the first direction, the plurality of first transistors in the first transistor column and the plurality of second transistors in the second transistor column are electrically connected in a one-to-one correspondence; the length direction of the first transistor and the second transistor is the same, and the center of the first transistor and the center of the second transistor are offset in the first direction.

[0024] In some embodiments, forming a first transistor column and a second transistor column on the substrate includes:

[0025] The substrate is etched to form a first wall-like structure extending along a first direction and a second wall-like structure extending along a first direction, the first wall-like structure and the second wall-like structure being arranged alternately along a second direction;

[0026] The first wall-like structure is etched to form a plurality of first openings on the first wall-like structure, the plurality of first openings dividing the first wall-like structure into a plurality of first active regions;

[0027] The second wall-like structure is etched to form a plurality of second openings on the second wall-like structure. The plurality of second openings divide the second wall-like structure into a plurality of second active regions. The center of the second opening is offset from the center of the first opening in the first direction, and the center of the first active region is offset from the center of the second active region in the first direction.

[0028] In some embodiments, after forming the first active region and the second active region, the method further includes:

[0029] The first active region and the second active region are doped to form a first channel and a first electrode and a second electrode located on both sides of the first channel on the first active region, and a second channel and a first electrode and a second electrode located on both sides of the second active region on the second active region. The direction from the first electrode of the first active region to the second electrode of the first active region is the same as the direction from the first electrode of the second active region to the second electrode of the second active region.

[0030] A gate is formed covering the first channel and the second channel.

[0031] In some embodiments, after forming the first transistor column and the second transistor column on the substrate, the method further includes:

[0032] A first filling layer is formed, which fills the gap between the first transistor and the second transistor and covers the first transistor and the second transistor;

[0033] At least one first contact plug and at least one second contact plug are formed through the first filling layer, the bottom of the first contact plug is electrically connected to the gate of the first transistor, and the bottom of the second contact plug is electrically connected to the second electrode of the second transistor;

[0034] At least one interconnect line is formed, and the two ends of each interconnect line are electrically connected to the top of the first contact plug and the top of the adjacent second contact plug, respectively.

[0035] In some embodiments, after forming the interconnect, the method further includes:

[0036] A second fill layer is formed, which covers the first fill layer and the interconnect;

[0037] A third contact plug is formed that penetrates the second fill layer and the first fill layer, the bottom of the third contact plug being electrically connected to the second electrode of the first transistor; a first bit line extending in a second direction is formed on the second fill layer, the first bit line being electrically connected to the top of the third contact plug;

[0038] A fourth contact plug is formed that penetrates the second fill layer and the first fill layer, the bottom of the fourth contact plug being electrically connected to the first electrode of the second transistor; a second bit line is formed on the second fill layer extending along the second direction, the second bit line being electrically connected to the top of the fourth contact plug.

[0039] In some embodiments, after forming the first bit line and the second bit line, the method further includes:

[0040] A third fill layer is formed, which covers the second fill layer, the first bit line, and the second bit line;

[0041] A fifth contact plug and a sixth contact plug are formed that penetrate the third filling layer, the second filling layer, and the first filling layer. The bottom of the fifth contact plug is electrically connected to the first electrode of the first transistor, and the bottom of the sixth contact plug is electrically connected to the gate of the second transistor.

[0042] A first letter and a second letter extending along the first direction are formed on the third filler layer. The first letter is electrically connected to the top of the fifth contact plug, and the second letter is electrically connected to the top of the sixth contact plug.

[0043] In some embodiments, a substrate is provided, comprising: the substrate being made of a material including In x Ga y Zn z O, where x, y, and z are positive integers greater than or equal to 1.

[0044] The semiconductor structure and its manufacturing method provided in this disclosure include: a substrate; a first transistor column and a second transistor column located on the substrate, the first transistor column and the second transistor column being arranged alternately; the first transistor column including a plurality of first transistors arranged along a first direction; the second transistor column including a plurality of second transistors arranged along the first direction; and the plurality of first transistors in the first transistor column and the plurality of second transistors in the second transistor column being electrically connected in a one-to-one correspondence; wherein the length directions of the first transistor and the second transistor are the same, and the centers of the first transistor and the second transistor are offset in the first direction. The semiconductor structure provided in this disclosure comprises a memory cell consisting of a first transistor and a corresponding second transistor. Since the length directions of the first transistor and the second transistor are the same, the first transistor and the second transistor can be arranged more densely, improving the integration density of the semiconductor structure. Furthermore, no additional capacitors are required, the process is simple, and no rewrite operation is needed after reading, reducing power consumption.

[0045] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the accompanying drawings and claims. Attached Figure Description

[0046] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1a This is a top view schematic diagram of a semiconductor structure provided in an embodiment of this disclosure. Figure 1b for Figure 1a A partial perspective view;

[0048] Figure 2A flowchart illustrating a semiconductor structure manufacturing method provided in an embodiment of this disclosure;

[0049] Figures 3a to 12b A process flow diagram of the semiconductor structure provided in the embodiments of this disclosure. Detailed Implementation

[0050] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0051] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0052] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0053] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0054] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0055] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of features, integers, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0056] Currently, common dynamic random access memories (DRAMs) typically consist of a single transistor and a capacitor (1T1C) forming a memory cell, with the capacitor used to store data. However, 1T1C DRAMs have high requirements for the amount of charge the capacitor can store, and reading from the capacitor is destructive, requiring rewriting after the read operation, increasing power consumption. Furthermore, the complex manufacturing process and large size of the capacitor make miniaturization a challenge.

[0057] Dual-transistor capacitor-free (2T0C) dynamic random access memory typically consists of a read transistor and a write transistor in a memory structure. However, in related technologies, the length direction of the read transistor is perpendicular to the length direction of the write transistor, resulting in a lower density of read and write transistors and thus reducing the integration density of the 2T0C dynamic random access memory.

[0058] Based on this, the following technical solutions of the embodiments of this disclosure are proposed. The specific implementation methods of this disclosure will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to general proportions, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure.

[0059] Figure 1aThis is a top view schematic diagram of a semiconductor structure provided in an embodiment of this disclosure. Figure 1b for Figure 1a A partial perspective view, combined with the following Figures 1a to 1b The semiconductor structure provided in the embodiments of this disclosure will be further described.

[0060] As shown in the figure, the semiconductor structure includes: a substrate 11; a first transistor column 14 and a second transistor column 15 located on the substrate 11, the first transistor column 14 and the second transistor column 15 being arranged alternately, the first transistor column 14 including a plurality of first transistors 141 arranged along a first direction, the second transistor column 15 including a plurality of second transistors 151 arranged along the first direction, the plurality of first transistors 141 of the first transistor column 14 and the plurality of second transistors 151 of the second transistor column 15 being electrically connected in a one-to-one correspondence; wherein, the length directions of the first transistors 141 and the second transistors 151 are the same, and the center of the first transistor 141 and the center of the second transistor 151 are offset in the first direction.

[0061] like Figure 1a As shown, the offset between the center of the first transistor 141 and the center of the second transistor 151 in the first direction means that the line connecting the center of the first transistor 141 and the center of the second transistor 151 intersects the first direction but is not perpendicular to it.

[0062] In practice, the semiconductor structure provided in this disclosure can be a dual-transistor capacitor-free (2T0C) three-dimensional dynamic random access memory, but it is not limited to this. The semiconductor structure can also be any semiconductor structure with a read transistor and a write transistor.

[0063] like Figure 1b As shown, in one embodiment, the semiconductor structure further includes a substrate 10, on which a substrate 11 is formed. In some embodiments, the substrate 11 and the substrate 10 may be spaced apart by an insulating layer (not shown).

[0064] The substrate 10 may be a semiconductor substrate and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, the substrate is a silicon substrate, which may be doped or undoped.

[0065] In some embodiments, the material of the substrate 11 includes a single-element semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.

[0066] In one embodiment, the material of the substrate 11 includes In x Ga y Zn z O, where x, y, and z are positive integers greater than or equal to 1. However, it is not limited to this, the material of the substrate 11 may also include at least one of indium oxide, tin oxide, gallium oxide, In-Sn oxide, In-W oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, In-Ga oxide, In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, and Sn-Al-Zn oxide.

[0067] However, the material of the substrate 11 may also include at least one of the following: In-Hf-Zn oxides, In-La-Zn oxides, In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides, In-Sm-Zn oxides, In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb-Zn oxides, In-Dy-Zn oxides, In-Ho-Zn oxides, In-Er-Zn oxides, In-Tm-Zn oxides, In-Yb-Zn oxides, and In-Lu-Zn ​​oxides; and quaternary metal oxides such as In-Sn-Ga-Zn oxides, In-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, In-Sn-Al-Zn oxides, In-Sn-Hf-Zn oxides, and In-Hf-Al-Zn oxides.

[0068] In this embodiment, an oxide semiconductor material is used as the substrate 11. The oxide semiconductor material has higher carrier mobility and lower leakage current, which can effectively reduce the leakage current of the first transistor 141 and the second transistor 151, improve the on / off current ratio and current driveability of the first transistor and the second transistor, improve the access speed of the semiconductor structure, and reduce power consumption.

[0069] In one embodiment, the first transistor 141 includes a gate g and a first electrode d1 and a second electrode d2 located on both sides of the gate g, and the second transistor 151 includes a gate g and a first electrode d1 and a second electrode d2 located on both sides of the gate g. The first electrode d1 and the second electrode d2 are either sources or drains and are not the same. The direction from the first electrode d1 of the first transistor 141 to the second electrode d2 of the first transistor 141 is the same as the direction from the first electrode d1 of the second transistor 151 to the second electrode d2 of the second transistor 151. That is, the direction from the source of the first transistor 141 to the drain is the same as the direction from the source of the second transistor 151 to the drain.

[0070] In some embodiments, the first transistor 141 further includes a first channel c1 located below the gate g of the first transistor 141, and the second transistor 151 further includes a second channel c2 located below the gate g of the second transistor 151. The first electrode d1 and the second electrode d2 may have the same doping type, and the doping types of the first electrode d1 and the second electrode d2 may be different from the doping types of the first channel c1 and the second channel c2. For example, the first electrode d1 and the second electrode d2 may be P-type doped, and the first channel c1 and the second channel c2 may be N-type doped; or, the first electrode d1 and the second electrode d2 may be N-type doped, and the first channel c1 and the second channel c2 may be P-type doped.

[0071] In some embodiments, the first transistor 141 further includes a gate dielectric layer (not shown) sandwiched between the gate g and the first channel c1 of the first transistor 141, and the second transistor 151 further includes a gate dielectric layer (not shown) sandwiched between the gate g and the second channel c2 of the second transistor 151. The material of the gate g includes one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, and metal alloy. The material of the gate dielectric layer (not shown) can be a high dielectric constant material, such as tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide, or barium strontium titanate.

[0072] In one embodiment, the first transistor 141 includes a read transistor, and the second transistor 151 includes a write transistor. One first transistor 141 and one corresponding second transistor 151 constitute a memory cell. In this embodiment, the first transistor 141 and the second transistor 151 have the same length direction, thus enabling a more compact arrangement of the first transistor 141 and the second transistor 151, improving the integration density of the semiconductor structure. Furthermore, no additional capacitors are required, simplifying the process, and no rewrite operation is needed after reading, reducing power consumption.

[0073] In one embodiment, the length direction of the first transistor 141 and the second transistor 151 is a first direction, which refers to the length direction of the transistor channel region. This allows for the maximum transistor density compared to other length directions. However, this is not a limitation; in other embodiments, the length directions of the first transistor 141 and the second transistor 151 may also be oblique to the first direction.

[0074] In one embodiment, the first transistor column 14 and the second transistor column 15 are arranged alternately along a second direction, which is perpendicular to the first direction. In this second direction, the projections of the first transistor 141 and the second transistor 151 overlap. However, this is not a limitation; the second direction can also be oblique to the first direction. Here, by setting the projections of the first transistor 141 and the second transistor 151 to overlap in the second direction, the transistor density can be further improved. In a specific embodiment, in the second direction, the projections of the first electrode d1 of the first transistor 141 and the gate g of the second transistor 151 overlap, and the projection of the gate g of the first transistor 141 overlaps with the projection of the second electrode d2 of the second transistor 151. This allows for the maximum density compared to other arrangement methods. In a more specific embodiment, in the second direction, the projections of the second electrode d2 of the first transistor 141 and the first electrode d1 of the second transistor 151 have at least a non-overlapping region.

[0075] like Figure 1a As shown, in some embodiments, there are multiple first transistor columns 14 and multiple second transistor columns 15, which are arranged alternately along a second direction. In some embodiments, in the second direction, any adjacent first transistors 141 and second transistors 151 have the same spacing, which can further improve the transistor density.

[0076] In one embodiment, the semiconductor structure further includes: a plurality of bit lines BL located above the substrate 11 and extending along a second direction, the bit lines BL being connected to the second terminal d2 of the first transistor 141 or the first terminal d1 of the second transistor 151; and a plurality of word lines WL located above the bit lines BL and extending along a first direction, the word lines WL being connected to the first terminal d1 of the first transistor 141 or the gate g of the second transistor 151.

[0077] Specifically, the multiple bit lines BL include a first bit line BL1 and a second bit line BL2 arranged alternately along the first direction. The first bit line BL1 is electrically connected to the second electrode d2 of the first transistor 141, and the second bit line BL2 is electrically connected to the first electrode d1 of the second transistor 151.

[0078] The multiple word lines WL include a first word line WL1 and a second word line WL2 arranged alternately along a second direction, wherein the first word line WL1 is electrically connected to the first electrode d1 of the first transistor 141, and the second word line WL2 is electrically connected to the gate g of the second transistor 151.

[0079] More specifically, the first bit line BL1 is electrically connected to the second terminal d2 of the first transistor 141 through the third contact plug V3; the second bit line BL2 is electrically connected to the first terminal d1 of the second transistor 151 through the fourth contact plug V4; the first word line WL1 is electrically connected to the first terminal d1 of the first transistor 141 through the fifth contact plug V5; and the second word line WL2 is electrically connected to the gate g of the second transistor 151 through the sixth contact plug V6.

[0080] In one embodiment, there are multiple first bit lines BL1 and multiple second bit lines BL2, with the multiple first bit lines BL1 and multiple second bit lines BL2 arranged alternately along a first direction; there are also multiple first character lines WL1 and multiple second character lines WL2, with the multiple first character lines WL1 and multiple second character lines WL2 arranged alternately along a second direction. In some embodiments, the multiple first character lines WL1 and multiple second character lines WL2 are arranged at equal intervals along the second direction.

[0081] In this embodiment of the present disclosure, by setting the direction of the first electrode d1 of the first transistor 141 pointing to the second electrode d2 to be the same as the direction of the first electrode d1 of the second transistor 151 pointing to the second electrode d2, the distance between the word line WL, the bit line BL, the third contact plug V3 and the fourth contact plug V4 can be increased to obtain a better arrangement, thereby better avoiding problems such as short circuits caused by mutual contact between the word line WL, the bit line BL, the third contact plug V3 and the fourth contact plug V4.

[0082] This embodiment of the present disclosure, by setting the word line WL above the bit line BL and setting the bit line BL to extend along the second direction and the word line WL to extend along the first direction, instead of setting the bit line BL above the word line WL or the bit line BL to extend along the first direction and the word line WL to extend along the second direction, can better avoid the word line WL and the bit line BL from contacting the third contact plug V3 and the fourth contact plug V4, and the word line WL and the bit line BL can obtain a larger arrangement space.

[0083] Understandably, by setting the projection of the second electrode d2 of the first transistor 141 in the second direction to at least have a non-overlapping area with the projection of the first electrode d1 of the second transistor 151 in the second direction, it is possible to better prevent the first bit line BL1, the second bit line BL2, the third contact plug V3 and the fourth contact plug V4 from contacting each other.

[0084] In one embodiment, the semiconductor structure further includes at least one interconnect line 16 located above the substrate 11, each interconnect line 16 electrically connecting the gate g of the first transistor 141 to the second electrode d2 of the corresponding second transistor 151, wherein the word line WL is located above the interconnect line 16. In a specific embodiment, the interconnect line 16 is electrically connected to the gate g of the first transistor via a first contact plug V1, and the interconnect line 16 is electrically connected to the second electrode d2 of the second transistor via a second contact plug V2. By placing the interconnect line 16 below the word line WL, this embodiment avoids problems such as short circuits caused by contact between the word line WL and the first contact plug V1 and the second contact plug V2.

[0085] like Figure 1b As shown, in one embodiment, the semiconductor structure further includes:

[0086] The first filling layer L1 fills the gap between the first transistor 141 and the second transistor 151 and covers the first transistor 141 and the second transistor 151. The first contact plug V1 and the second contact plug V2 pass through the first filling layer L1. The interconnect line 16 is located on the first filling layer L1.

[0087] The second fill layer L2 covers the first fill layer L1 and the interconnect line 16. The third contact plug V3 and the fourth contact plug V4 penetrate the second fill layer L2 and the first fill layer L1. The bit line BL is located on the second fill layer L2.

[0088] The third fill layer L3 covers the second fill layer L2 and the bit line BL. The fifth contact plug V5 and the sixth contact plug V6 penetrate the third fill layer L3, the second fill layer L2 and the first fill layer L1. The word line WL is located on the third fill layer L3.

[0089] The word line WL, bit line BL, interconnect 16, and first contact plugs V1, second contact plug V2, third contact plug V3, fourth contact plug V4, fifth contact plug V5, and sixth contact plug V6 are made of one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicides, and metal alloys. The first filler layer L1, second filler layer L2, and third filler layer L3 are made of one or more of oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), and oxynitrides (e.g., silicon oxynitride).

[0090] This disclosure also provides a method for manufacturing a semiconductor structure, such as... Figure 2 As shown, the method includes the following steps:

[0091] Step 201: Provide a substrate;

[0092] Step 202: Form a first transistor column and a second transistor column on the substrate. The first transistor column and the second transistor column are arranged alternately. The first transistor column includes a plurality of first transistors arranged along a first direction. The second transistor column includes a plurality of second transistors arranged along the first direction. The plurality of first transistors in the first transistor column and the plurality of second transistors in the second transistor column are electrically connected in a one-to-one correspondence. The length directions of the first transistors and the second transistors are the same, and the center of the first transistor and the center of the second transistor are offset in the first direction.

[0093] Below, in conjunction with Figures 3a to 12b The method for manufacturing the semiconductor structure according to the embodiments of this disclosure will be described in further detail, wherein, Figure 3a , Figure 4a , Figure 5a , Figure 6a , Figure 7a , Figure 8a , Figure 9a , Figure 10a , Figure 11a , Figure 12a This is a top view schematic diagram of the semiconductor structure manufacturing method provided in the embodiments of this disclosure at different process steps. Figure 3b , Figure 4b , Figure 5b , Figure 6b , Figure 7b , Figure 8b , Figure 9b , Figure 10b , Figure 11b , Figure 12b They are respectively Figure 3a , Figure 4a , Figure 5a , Figure 6a , Figure 7a , Figure 8a , Figure 9a , Figure 10a , Figure 11a , Figure 12a A partial perspective view.

[0094] First, perform step 201, such as... Figures 3a to 3b As shown, a substrate 11 is provided.

[0095] In one embodiment, a substrate 11 is provided, comprising: the material of the substrate 11 includes In x Ga y Zn zO, where x, y, and z are positive integers greater than or equal to 1. However, it is not limited to this, the material of the substrate 11 may also include at least one of indium oxide, tin oxide, gallium oxide, In-Sn oxide, In-W oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, In-Ga oxide, In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, and Sn-Al-Zn oxide.

[0096] However, the material of the substrate 11 may also include at least one of the following: In-Hf-Zn oxides, In-La-Zn oxides, In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides, In-Sm-Zn oxides, In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb-Zn oxides, In-Dy-Zn oxides, In-Ho-Zn oxides, In-Er-Zn oxides, In-Tm-Zn oxides, In-Yb-Zn oxides, and In-Lu-Zn ​​oxides; and quaternary metal oxides such as In-Sn-Ga-Zn oxides, In-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, In-Sn-Al-Zn oxides, In-Sn-Hf-Zn oxides, and In-Hf-Al-Zn oxides.

[0097] Participate again Figure 1b In one embodiment, prior to providing the substrate 11, the method further includes providing a base 10, on which the substrate 11 is formed. In some embodiments, the substrate 11 and the base 10 may be spaced apart by an insulating layer (not shown).

[0098] The substrate 10 may be a semiconductor substrate and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, the substrate is a silicon substrate, which may be doped or undoped.

[0099] Next, proceed to step 202, as follows: Figures 4a to 7bAs shown, a first transistor column 14 and a second transistor column 15 are formed on a substrate 11. The first transistor column 14 and the second transistor column 15 are arranged alternately. The first transistor column 14 includes a plurality of first transistors 141 arranged along a first direction, and the second transistor column 15 includes a plurality of second transistors 151 arranged along the first direction. The plurality of first transistors 141 in the first transistor column 14 and the plurality of second transistors 151 in the second transistor column 15 are electrically connected in a one-to-one correspondence. The length directions of the first transistors 141 and the second transistors 151 are the same, and the center of the first transistor 141 and the center of the second transistor 151 are offset in the first direction.

[0100] Specifically, firstly, such as Figures 4a to 6b As shown, a first transistor column 14 and a second transistor column 15 are formed on a substrate 11, including:

[0101] The substrate 11 is etched to form a first wall-like structure 12 extending along a first direction and a second wall-like structure 13 extending along a first direction, the first wall-like structure 12 and the second wall-like structure 13 being arranged alternately along a second direction;

[0102] The first wall-like structure 12 is etched to form a plurality of first openings T1 on the first wall-like structure 12, and the plurality of first openings T1 divide the first wall-like structure 12 into a plurality of first active regions AA1.

[0103] The second wall-like structure 13 is etched to form a plurality of second openings T2 on the second wall-like structure 13. The plurality of second openings T2 divide the second wall-like structure 13 into a plurality of second active regions AA2. The center of the second opening T2 is offset from the center of the first opening T1 in a first direction, and the center of the first active region AA1 is offset from the center of the second active region AA2 in a first direction.

[0104] In some embodiments, there are multiple first wall-like structures 12 and multiple second wall-like structures 13, which are arranged alternately. Here, a self-aligned double patterning process (SADP) or a self-aligned quadruple patterning process (SAQP) can be used to etch the substrate 11 to simultaneously form the first wall-like structures 12 and the second wall-like structures 13, which simplifies the process and allows the first wall-like structures 12 and the second wall-like structures 13 to be arranged at equal intervals with the desired spacing, thereby allowing the maximum active region packing density to be obtained.

[0105] like Figure 6aAs shown, multiple first openings T1 divide the first wall-like structure 12 into multiple first active regions AA1 with a length direction of the first direction, and multiple second openings T2 divide the second wall-like structure 13 into multiple second active regions AA2 with a length direction of the first direction. This allows for the maximum active region density compared to other length directions. However, this is not a limitation; the length directions of the first active regions AA1 and the second active regions AA2 can also be oblique to the first direction. The offset between the center of the first active region AA1 and the center of the second active region AA2 in the first direction means that the line connecting the centers of the first active region AA1 and the second active region AA2 intersects the first direction but is not perpendicular to it.

[0106] In the above embodiment, the first opening T1 is formed first, followed by the second opening T2. However, this is not the only possibility. In other embodiments, the first opening T1 and the second opening T2 can be formed simultaneously, thus simplifying the process.

[0107] Next, as Figures 7a to 7b As shown, after forming the first active region AA1 and the second active region AA2, the method further includes:

[0108] The first active region AA1 and the second active region AA2 are doped to form a first channel c1 and a first electrode d1 and a second electrode d2 located on both sides of the first active region AA1, and a second channel c2 and a first electrode d1 and a second electrode d2 located on both sides of the second active region AA2. The direction from the first electrode d1 of the first active region AA1 to the second electrode d2 of the first active region AA1 is the same as the direction from the first electrode d1 of the second active region AA2 to the second electrode d2 of the second active region AA2.

[0109] A gate g is formed covering the first channel c1 and the second channel c2.

[0110] The first electrode d1 and the second electrode d2 can have the same doping type, and the doping type of the first electrode d1 and the second electrode d2 is different from the doping type of the first channel c1 and the second channel c2. For example, the first electrode d1 and the second electrode d2 are P-type doped, and the first channel c1 and the second channel c2 are N-type doped, or the first electrode d1 and the second electrode d2 are N-type doped, and the first channel c1 and the second channel c2 are P-type doped.

[0111] The first active region AA1 and the gate g covering the first channel c1 constitute the first transistor 141, and the second active region AA2 and the gate g covering the second channel c2 constitute the second transistor 151. In this embodiment, an oxide semiconductor material is used as the substrate material 11. Oxide semiconductor materials have higher carrier mobility and lower leakage current, which can effectively reduce the leakage current of the first transistor 141 and the second transistor 151, improve the on / off current ratio and current driveability of the first transistor 141 and the second transistor 151, improve the access speed of the semiconductor structure, and reduce power consumption.

[0112] In one embodiment, the first transistor 141 includes a read transistor, and the second transistor 151 includes a write transistor. One first transistor 141 and one corresponding second transistor 151 constitute a memory cell. In this embodiment, the first transistor 141 and the second transistor 151 have the same length direction, thus enabling a more compact arrangement of the first transistor 141 and the second transistor 151, improving the integration density of the semiconductor structure. Furthermore, no additional capacitors are required, simplifying the process, and no rewrite operation is needed after reading, reducing power consumption.

[0113] In one embodiment, the length direction of the first transistor 141 and the second transistor 151 is a first direction, thus allowing for the maximum transistor density compared to other length directions. However, this is not a limitation; in other embodiments, the length directions of the first transistor 141 and the second transistor 151 may also be oblique to the first direction.

[0114] A plurality of first transistors 141 arranged along a first direction constitute a transistor column 14, and a plurality of second transistors 151 arranged along the first direction constitute a second transistor column 15. In one embodiment, the first transistor column 14 and the second transistor column 15 are arranged alternately along a second direction, which is perpendicular to the first direction; in the second direction, the projections of the first transistors 141 and the second transistors 151 overlap. However, this is not limited to this; the second direction can also be oblique to the first direction. Here, the overlap between the first transistors 141 and the second transistors 151 in the second direction can further increase the transistor density. In a specific embodiment, in the second direction, the projections of the first electrode d1 of the first transistor 141 and the gate g of the second transistor 151 overlap, and the projection of the gate g of the first transistor 141 overlaps with the projection of the second electrode d2 of the second transistor 151. Thus, compared to other arrangement methods, the maximum density can be obtained. In a more specific embodiment, in the second direction, the projections of the second electrode d2 of the first transistor 141 and the projections of the first electrode d1 of the second transistor 151 have at least a non-overlapping region.

[0115] like Figure 7a As shown, in some embodiments, there are multiple first transistor columns 14 and multiple second transistor columns 15, and the multiple first transistor columns 14 and multiple second transistor columns 15 are arranged alternately along a second direction.

[0116] In some embodiments, before forming the gate g covering the first channel c1 and the second channel c2, the method further includes: forming a gate dielectric layer (not shown) covering the first channel c1 and the second channel c2, the gate dielectric layer (not shown) being located below the gate g. The material of the gate g includes one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicides, and metal alloys. The material of the gate dielectric layer (not shown) can be a high dielectric constant material, such as tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide, or barium strontium titanate.

[0117] Next, as Figures 8a to 9b As shown, after forming the first transistor column 14 and the second transistor column 15 on the substrate 11, the method further includes:

[0118] A first filling layer L1 is formed, which fills the gap between the first transistor 141 and the second transistor 151 and covers the first transistor 141 and the second transistor 151; at least one first contact plug V1 and at least one second contact plug V2 are formed through the first filling layer L1, the bottom of the first contact plug V1 is electrically connected to the gate g of the first transistor 141, and the bottom of the second contact plug V2 is electrically connected to the second electrode d2 of the second transistor 151;

[0119] At least one interconnect line 16 is formed, and the two ends of each interconnect line 16 are electrically connected to the top of the first contact plug V1 and the top of the adjacent second contact plug V2, respectively.

[0120] Next, as Figures 10a to 11b As shown, after forming interconnect 16, the method further includes:

[0121] A second filling layer L2 is formed, which covers the first filling layer L1 and the interconnect 16; a third contact plug V3 is formed that penetrates the second filling layer L2 and the first filling layer L1, and the bottom of the third contact plug V3 is electrically connected to the second electrode of the first transistor 141; a first line BL1 extending in the second direction is formed on the second filling layer L2, and the first line BL1 is electrically connected to the top of the third contact plug V3.

[0122] A fourth contact plug V4 is formed that penetrates the second filling layer L2 and the first filling layer L1. The bottom of the fourth contact plug V4 is electrically connected to the first electrode d1 of the second transistor 151. A second bit line BL2 extending in the second direction is formed on the second filling layer L2. The second bit line BL2 is electrically connected to the top of the fourth contact plug V4.

[0123] Here, the third contact plug V3 and the first bit line BL1 are formed first, followed by the formation of the fourth contact plug V4 and the second bit line BL2. However, this is not the only option. In other embodiments, multiple through-holes penetrating the second filling layer L2 and the first filling layer L1 can be formed simultaneously first; then, the third contact plug V3 and the fourth contact plug V4 are formed simultaneously within the multiple through-holes; next, a conductive material is deposited on the second filling layer L2; then, the conductive material is etched to simultaneously form the first bit line BL1 and the second bit line BL2. In this way, the third contact plug V3 and the fourth contact plug V4 are formed in the same process step, and the first bit line BL1 and the second bit line BL2 are formed in the same process step, simplifying the process.

[0124] In one embodiment, there are multiple first bit lines BL1 and multiple second bit lines BL2, and the multiple first bit lines BL1 and multiple second bit lines BL2 are arranged alternately along a first direction.

[0125] Next, as Figures 12a to 12b , Figures 1a to 1b As shown, after forming the first bit line BL1 and the second bit line BL2, the method further includes:

[0126] A third filling layer L3 is formed, which covers the second filling layer L2, the first bit line BL1, and the second bit line BL2; a fifth contact plug V5 and a sixth contact plug V6 are formed that penetrate the third filling layer L3, the second filling layer L2, and the first filling layer L1. The bottom of the fifth contact plug V5 is electrically connected to the first electrode d1 of the first transistor 141, and the bottom of the sixth contact plug V6 is electrically connected to the gate g of the second transistor 151.

[0127] A first letter line WL1 and a second letter line WL2 extending in a first direction are formed on the third filler layer L3. The first letter line WL1 is electrically connected to the top of the fifth contact plug V5, and the second letter line WL2 is electrically connected to the top of the sixth contact plug V6.

[0128] Here, the method for forming the first word line WL1 and the second word line WL2 can be as follows: first, a conductive material is formed on the third filler layer L3, and then the conductive material is etched using a self-aligned double patterning process (SADP) or a self-aligned quadruple patterning process (SAQP) to simultaneously form the first word line WL1 and the second word line WL2, thus simplifying the process. In one embodiment, there are multiple first word lines WL1 and multiple second word lines WL2, and the multiple first word lines WL1 and multiple second word lines WL2 are arranged alternately along a second direction. In some embodiments, the multiple first word lines WL1 and multiple second word lines WL2 are arranged at equal intervals along the second direction.

[0129] The first bit line BL1 and the second bit line BL2 constitute multiple bit lines BL, and the first word line WL1 and the second word line WL2 constitute multiple word lines WL. In this embodiment, by setting the direction of the first electrode d1 pointing to the second electrode d2 of the first active region AA1 to be the same as the direction of the first electrode d1 pointing to the second electrode d2 of the second active region AA2, that is, the direction of the source pointing to the drain of the first transistor 141 to be the same as the direction of the source pointing to the drain of the second transistor 151, the distance between the word lines WL, bit lines BL, third contact plug V3, and fourth contact plug V4 can be increased to obtain a better arrangement, thereby better avoiding problems such as short circuits caused by mutual contact between the word lines WL, bit lines BL, third contact plug V3, and fourth contact plug V4.

[0130] This embodiment of the present disclosure, by setting the word line WL above the bit line BL and setting the bit line BL to extend along the second direction and the word line WL to extend along the first direction, instead of setting the bit line BL above the word line WL or the bit line BL to extend along the first direction and the word line WL to extend along the second direction, can better avoid the word line WL and the bit line BL from contacting the third contact plug V3 and the fourth contact plug V4, and the word line WL and the bit line BL can obtain a larger arrangement space.

[0131] It is understandable that the projection of the second electrode d2 of the first transistor 141 in the second direction and the projection of the first electrode d1 of the second transistor 151 in the second direction have at least a non-overlapping area. In this way, the bit line BL, the third contact plug V3 and the fourth contact plug V4 can be better prevented from contacting each other.

[0132] This embodiment of the disclosure avoids problems such as short circuits caused by the word line WL1 contacting the first contact plug V1 and the second contact plug V2 by placing the first word line WL1 and the second word line WL2 above the interconnect line 16.

[0133] The word line WL, bit line BL, interconnect 16, and first contact plugs V1, second contact plug V2, third contact plug V3, fourth contact plug V4, fifth contact plug V5, and sixth contact plug V6 are made of one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicides, and metal alloys. The first filler layer L1, second filler layer L2, and third filler layer L3 are made of one or more of oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), and oxynitrides (e.g., silicon oxynitride).

[0134] It should be noted that those skilled in the art can change the order of the above steps without departing from the scope of protection of this disclosure. The above are merely optional embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A first transistor column and a second transistor column are located on the substrate, arranged alternately. The first transistor column includes a plurality of first transistors arranged along a first direction, and the second transistor column includes a plurality of second transistors arranged along the first direction. The plurality of first transistors in the first transistor column and the plurality of second transistors in the second transistor column are electrically connected in a one-to-one correspondence. The first transistor and the second transistor have the same length direction, and the center of the first transistor and the center of the second transistor are offset in the first direction. The first transistor includes a gate and a first electrode and a second electrode located on both sides of the gate. The second transistor includes a gate and a first electrode and a second electrode located on both sides of the gate. At least one interconnect line located above the substrate, each of the interconnect lines electrically connecting the gate of the first transistor to the second electrode of the corresponding second transistor.

2. The semiconductor structure according to claim 1, characterized in that, The length direction of the first transistor and the second transistor is the first direction.

3. The semiconductor structure according to claim 2, characterized in that, The first transistor column and the second transistor column are arranged alternately along a second direction, which is perpendicular to the first direction; In the second direction, the projection of the first transistor overlaps with the projection of the second transistor.

4. The semiconductor structure according to claim 1, characterized in that, The first electrode and the second electrode are either the source or the drain and are not the same, wherein the direction from the first electrode of the first transistor to the second electrode of the first transistor is the same as the direction from the first electrode of the second transistor to the second electrode of the second transistor.

5. The semiconductor structure according to claim 4, characterized in that, Also includes: Multiple bit lines located above the substrate and extending along a second direction, the bit lines being connected to the second terminal of the first transistor or the first terminal of the second transistor; Multiple word lines located above the bit lines and extending along the first direction are connected to the first electrode of the first transistor or the gate of the second transistor.

6. The semiconductor structure according to claim 5, characterized in that, The word line is located above the interconnect line.

7. The semiconductor structure according to claim 5, characterized in that, Also includes: The plurality of word lines include a first word line and a second word line arranged alternately along a second direction, wherein the first word line is electrically connected to the first electrode of the first transistor, and the second word line is electrically connected to the gate of the second transistor; The plurality of bit lines include a first bit line and a second bit line arranged alternately along a first direction. The first bit line is electrically connected to the second electrode of the first transistor, and the second bit line is electrically connected to the first electrode of the second transistor.

8. The semiconductor structure according to claim 6, characterized in that, The interconnect is electrically connected to the gate of the first transistor via a first contact plug, and the interconnect is electrically connected to the second electrode of the second transistor via a second contact plug.

9. The semiconductor structure according to claim 7, characterized in that, The first bit line is electrically connected to the second electrode of the first transistor via a third contact plug; the second bit line is electrically connected to the first electrode of the second transistor via a fourth contact plug; the first word line is electrically connected to the first electrode of the first transistor via a fifth contact plug; and the second word line is electrically connected to the gate of the second transistor via a sixth contact plug.

10. The semiconductor structure according to claim 1, characterized in that, The first transistor includes a read transistor, and the second transistor includes a write transistor.

11. The semiconductor structure according to claim 1, characterized in that, The substrate material includes In x Ga y Zn z O, where x, y, and z are positive integers greater than or equal to 1.

12. A method for manufacturing a semiconductor structure, characterized in that, include: Provide substrate; A first transistor column and a second transistor column are formed on the substrate, the first transistor column and the second transistor column are arranged alternately, the first transistor column includes a plurality of first transistors arranged along a first direction, the second transistor column includes a plurality of second transistors arranged along the first direction, the plurality of first transistors in the first transistor column and the plurality of second transistors in the second transistor column are electrically connected in a one-to-one correspondence; the length direction of the first transistor and the second transistor is the same, and the center of the first transistor and the center of the second transistor are offset in the first direction, the first transistor includes a gate and a first electrode and a second electrode located on both sides of the gate, the second transistor includes a gate and a first electrode and a second electrode located on both sides of the gate; At least one interconnect is formed, and each interconnect electrically connects the gate of the first transistor to the second electrode of the corresponding second transistor.

13. The manufacturing method according to claim 12, characterized in that, Forming a first transistor column and a second transistor column on the substrate includes: The substrate is etched to form a first wall-like structure extending along a first direction and a second wall-like structure extending along a first direction, the first wall-like structure and the second wall-like structure being arranged alternately along a second direction; The first wall-like structure is etched to form a plurality of first openings on the first wall-like structure, the plurality of first openings dividing the first wall-like structure into a plurality of first active regions; The second wall-like structure is etched to form a plurality of second openings on the second wall-like structure. The plurality of second openings divide the second wall-like structure into a plurality of second active regions. The center of the second opening is offset from the center of the first opening in the first direction, and the center of the first active region is offset from the center of the second active region in the first direction.

14. The manufacturing method according to claim 13, characterized in that, After forming the first active region and the second active region, the method further includes: The first active region and the second active region are doped to form a first channel and a first electrode and a second electrode located on both sides of the first channel on the first active region, and a second channel and a first electrode and a second electrode located on both sides of the second active region on the second active region. The direction from the first electrode of the first active region to the second electrode of the first active region is the same as the direction from the first electrode of the second active region to the second electrode of the second active region. A gate is formed covering the first channel and the second channel.

15. The manufacturing method according to claim 14, characterized in that, After forming the first transistor column and the second transistor column on the substrate, the method further includes: A first filling layer is formed, which fills the gap between the first transistor and the second transistor and covers the first transistor and the second transistor; At least one first contact plug and at least one second contact plug are formed through the first filling layer, the bottom of the first contact plug is electrically connected to the gate of the first transistor, and the bottom of the second contact plug is electrically connected to the second electrode of the second transistor; At least one interconnect line is formed, and the two ends of each interconnect line are electrically connected to the top of the first contact plug and the top of the adjacent second contact plug, respectively.

16. The manufacturing method according to claim 15, characterized in that, After forming the interconnect, the method further includes: A second fill layer is formed, which covers the first fill layer and the interconnect; A third contact plug is formed that penetrates the second fill layer and the first fill layer, the bottom of the third contact plug being electrically connected to the second electrode of the first transistor; a first bit line extending in a second direction is formed on the second fill layer, the first bit line being electrically connected to the top of the third contact plug; A fourth contact plug is formed that penetrates the second fill layer and the first fill layer, the bottom of the fourth contact plug being electrically connected to the first electrode of the second transistor; a second bit line is formed on the second fill layer extending along the second direction, the second bit line being electrically connected to the top of the fourth contact plug.

17. The manufacturing method according to claim 16, characterized in that, After forming the first bit line and the second bit line, the method further includes: A third fill layer is formed, which covers the second fill layer, the first bit line, and the second bit line; A fifth contact plug and a sixth contact plug are formed that penetrate the third filling layer, the second filling layer, and the first filling layer. The bottom of the fifth contact plug is electrically connected to the first electrode of the first transistor, and the bottom of the sixth contact plug is electrically connected to the gate of the second transistor. A first letter and a second letter extending along the first direction are formed on the third filler layer. The first letter is electrically connected to the top of the fifth contact plug, and the second letter is electrically connected to the top of the sixth contact plug.

18. The manufacturing method according to claim 12, characterized in that, A substrate is provided, comprising: the material of the substrate comprising In x Ga y Zn z O, where x, y, and z are positive integers greater than or equal to 1.

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