Method for manufacturing semiconductor device and semiconductor device

Abstract

Embodiments provide a semiconductor device manufacturing method and a semiconductor device capable of filling a trench while suppressing generation of a void extending in a length direction. The semiconductor device manufacturing method of an embodiment includes: forming one or more second trenches by dividing a first trench in the length direction with a mask film formed so as to cover a part of the first trench; filling the second trenches with a first insulating film; removing the mask film; and forming a second insulating film so as to cover the entire first trench.

Description

[0001] This application enjoys priority based on Japanese Patent Application No. 2022-095084 (filed on June 13, 2022). This application incorporates the entire contents of that basic application by reference. Technical Field

[0002] The embodiments of the present invention relate to a method for manufacturing a semiconductor device and a semiconductor device. Background Technology

[0003] A semiconductor device having undergone contact and other processing on a predetermined film embedded in a trench. When the aspect ratio of the trench increases, the embedding of the predetermined film decreases, and as a result, voids extending in the length direction of the trench may sometimes occur. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a method for manufacturing a semiconductor device and a semiconductor device capable of filling trenches while suppressing the generation of pores extending along the length direction.

[0005] The method for manufacturing a semiconductor device according to the embodiment includes: forming one or more second trenches by dividing the first trench in the length direction by forming a mask film in a manner that covers a portion of the first trench; filling the second trench with a first insulating film; removing the mask film; and forming a second insulating film in a manner that covers the entire first trench. Attached Figure Description

[0006] Figure 1 This is a diagram illustrating a schematic structural example of a semiconductor device involved in an embodiment.

[0007] Figure 2 This is a diagram illustrating a detailed structural example of a semiconductor device involved in an embodiment.

[0008] Figure 3 This diagram illustrates a portion of the steps in a method for manufacturing a semiconductor device according to an embodiment.

[0009] Figure 4 This diagram illustrates a portion of the steps in a method for manufacturing a semiconductor device according to an embodiment.

[0010] Figure 5 This is a diagram illustrating the structure of a comparative example semiconductor device.

[0011] Figure 6 This is a diagram illustrating the structure of a comparative example semiconductor device.

[0012] Label Explanation

[0013] 1. Semiconductor device; 61, 62. Insulating film; 71, 72. Via; 100. Mask pattern; 110, 120. Trench; LM, LMs stack; NL, OL. Insulating layer; SR. Stepped region. Detailed Implementation

[0014] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, the invention is not limited to the embodiments described below. Furthermore, the constituent elements in the following embodiments include constituent elements that can be readily conceived by those skilled in the art or substantially the same constituent elements.

[0015] (Example of a semiconductor device structure)

[0016] Figure 1 This is a diagram illustrating a schematic structural example of the semiconductor device 1 according to the embodiment. Figure 1 (a) is a cross-sectional view of semiconductor device 1 along the X direction. Figure 1 (b) is a schematic plan view showing the layout of semiconductor device 1. However, in Figure 1 In (a), the shading lines were omitted to improve the ease of observation of the attached figure. Additionally, in Figure 1 A portion of the upper-layer wiring is omitted in (a).

[0017] Furthermore, in this specification, both the X and Y directions refer to the directions along the plane of the letter line WL, which will be described later, and the X and Y directions are orthogonal to each other.

[0018] like Figure 1 As shown, the semiconductor device 1 has a peripheral circuit CUA, a storage region MR, a through contact region TP, and a stepped region SR on a substrate SB.

[0019] The substrate SB is, for example, a semiconductor substrate such as a silicon substrate. Peripheral circuitry CUA, including transistors TR and wiring, is disposed on the substrate SB. The peripheral circuitry CUA facilitates the operation of the memory cells, which will be described later.

[0020] The peripheral circuit CUA is covered by an insulating layer 50. A source line SL is disposed on the insulating layer 50. Multiple word lines WL are stacked on the source line SL. The multiple word lines WL are covered by an insulating film 49. The insulating film 49 also extends around the multiple word lines WL.

[0021] Multiple plate-shaped contacts LI are arranged along multiple word lines WL, which pass through the word lines WL in the stacking direction and extend in the direction along the X direction. Thus, the multiple word lines WL are divided in the Y direction by the multiple plate-shaped contacts LI.

[0022] Between multiple plate-shaped contacts LI, multiple memory regions MR, stepped regions SR, and through contact regions TP are arranged in the X direction. The multiple memory regions MR sandwich the stepped regions SR and through contact regions TP, and are arranged separately from each other in the X direction.

[0023] A plurality of pillars PL are arranged in the storage region MR, through which word lines WL are connected in the stacking direction. A plurality of memory cells are formed at the intersection of the pillars PL and the word lines WL. Thus, the semiconductor device 1 is configured, for example, as a three-dimensional non-volatile memory in which memory cells are arranged in the storage region MR in a three-dimensional manner.

[0024] The stepped area SR includes multiple letter lines WL that have been excavated into a mortar-shaped stepped section SP in the stacking direction.

[0025] The stepped section SP forms a mortar-shaped section that descends in a stepped manner from both sides in the X direction and one side in the Y direction toward the bottom surface.

[0026] Each step of the stepped section SP is composed of word lines WL of each layer. The word lines WL of each layer are electrically conductive on both sides of the stepped section SP in the X direction, which encloses the stepped area SR. Contacts CC are provided on the terrace of each step of the stepped section SP to connect the word lines WL of each layer to the upper layer wiring MX.

[0027] Thus, word lines WL stacked in multiple layers can be drawn out. For memory cells within memory regions MR on both sides of the X direction, write voltage and read voltage are applied from these contacts CC via word lines WL at the same height position as the memory cell.

[0028] Furthermore, in this specification, the direction in which the platform surface of each step of the stepped section SP faces is defined as the upward direction.

[0029] A through-contact region TP is disposed on one side of the stepped region SR in the X direction. A through-contact contact C4 is disposed in the through-contact region TP, which passes through multiple word lines WL. The through-contact contact C4 connects the peripheral circuit CUA disposed on the substrate SB below and the upper layer wiring MX connected to the contact CC of the stepped section SP. Various voltages applied to the memory cell from the contact CC are controlled by the peripheral circuit CUA via the through-contact contact C4 and the upper layer wiring MX.

[0030] Next, use Figure 2 A detailed structural example of semiconductor device 1 will be described. Figure 2 This is a diagram showing a detailed structural example of the semiconductor device 1 according to the embodiment.

[0031] Figure 2 (a) is a top view of the stepped area SR.

[0032] Figure 2 (b) is Figure 2 A cross-sectional view of the stepped region SR at line a-a' of (a). Figure 2 (c) is Figure 2 A cross-sectional view of the stepped region SR at line b-b' in (a). Figure 2 (d) is Figure 2 A cross-sectional view of the stepped region SR at line c-c' in (a). Figure 2 (e) is Figure 2 A cross-sectional view of the stepped region SR at line d-d' in (a). Figure 2 (f) is Figure 2 A cross-sectional view of the stepped region SR at line e-e' in (a).

[0033] However, in Figure 2 The insulating layer 50 and the upper wiring MX are omitted. Additionally, in... Figure 2 In (a), for ease of explanation, structures such as the stepped sections SP, SPf, and SPs, which may not be visually confirmed when viewed from above, are also depicted.

[0034] like Figure 2 As shown in (b) to (f), the semiconductor device 1 includes a stack LM disposed on the source line SL.

[0035] The laminate LM has a structure formed by alternately stacking multiple tungsten or molybdenum word lines WL and insulating layers OL such as SiO2 layers.

[0036] The stepped region SR, which forms the first trench, has a lamellae LM that have been excavated into a mortar-like shape in the lamination direction. The stepped region SR has a length direction in the X direction.

[0037] The stepped area SR is provided with stepped sections SP, SPf, and SPs. Each stepped section SP, SPf, and SPs has multiple word lines WL and multiple insulating layers OL that are processed into a stepped shape.

[0038] Among these step sections SP, SPf, and SPs, step section SP has the function of leading multiple word lines WL to the upper layer wiring MX. On the other hand, step sections SPs and SPf are dummy step sections that do not contribute to the function of semiconductor device 1.

[0039] Stepped section SP from Figure 1 The storage region MR extends along the X direction from the position near the through contact region TP, gradually decreasing towards the storage region MR. The stepped portion SPf is located near... Figure 1The location of the storage area MR extends along the X direction opposite to the step section SP, and gradually descends towards the step section SP.

[0040] Stepped sections SPs are positioned on both sides of the stepped sections SP and SPf in the Y direction. Each stepped section SPs is located approximately along... Figure 1 The position of the adjacent plate-shaped contact LI in the Y direction extends along the Y direction and gradually decreases towards the plate-shaped contact LI on the other side.

[0041] With the stepped portions SP, SPf, and SPs configured in this way, the laminated body LM becomes recessed into a mortar-like shape in the stepped region SR.

[0042] In the stepped region SR, an insulating film 61 as a first insulating film and an insulating film 62 as a second insulating film are disposed in such a way that they cover the upper surfaces of the stepped portions SP, SPf, and SPs. The insulating films 61 and 62 are formed up to the height of the upper surface of the laminate LM.

[0043] Insulating films 61 and 62 extend in the Y direction and are alternately filled within the stepped region SR to divide the stepped region SR in the X direction. From a productive point of view, insulating films 61 and 62 are formed by methods such as CVD (Chemical Vapor Deposition). For example, insulating films 61 and 62 are SiO2 films such as TEOS (Tetra-Ethyl Ortho-Silicate) films.

[0044] Here, the insulating films 61 and 62, which are alternately filled in the stepped region SR, are respectively referred to as insulating films 61A to 61C and insulating films 62A to 62D. Otherwise, without specifically distinguishing between insulating films 61A to 61C and insulating films 62A to 62D, they are simply referred to as insulating film 61 and insulating film 62.

[0045] Insulating films 61A to 61C respectively sandwich each insulating film 62B to 62C in the middle, and are arranged separately from each other in the X direction. The width Y1 in the Y direction of insulating films 61A to 61C is preferably greater than or equal to the width X61A to X61C in the X direction.

[0046] Insulating films 62A to 62D respectively sandwich each insulating film 61A to 61C in the middle, and are arranged separately from each other in the X direction. The width Y1 in the Y direction of insulating films 62A to 62D is preferably greater than or equal to the width X62A to X62D in the X direction.

[0047] The upper surfaces of insulating films 61 and 62 are covered by insulating layer 52. Furthermore, insulating layer 52, insulating film 61, and insulating film 62 respectively constitute... Figure 1 Part of the insulating film 49 of (a).

[0048] The contact CC extends through the insulating layer 52 and the insulating film 61 or the insulating film 62 in the depth direction, connecting to the word lines WL of each step constituting the stepped portion SP. Although not shown, the contact CC has a metal layer extending in the depth direction of the laminate LM and connected to the word lines WL. Additionally, although not shown, the contact CC may also have an insulating layer serving as a liner layer for the metal layer.

[0049] By covering the platform portions of each step of the contact CC periphery and the stepped portion SP with insulating films 61 and 62, the generation of leakage current between the contact CC can be suppressed.

[0050] Sometimes, multiple pores 71 and 72 extending in the depth direction of the stepped region SR are arranged along the X direction in insulating films 61 and 62 as gaps.

[0051] A void 71 may sometimes be formed in at least one of the insulating films 61A to 61C near the center in the XY direction. When viewed from above, the void 71 may be, for example, a generally circular pinhole or a slit with a long side in the Y direction.

[0052] A void 72 may sometimes be formed in at least one of the insulating films 62A to 62D near the center in the XY direction. When viewed from above, the void 72 may be, for example, a generally circular pinhole or a slit with a long side in the Y direction.

[0053] In addition, it is not necessary to form voids 71 ​​and 72.

[0054] In addition, Figure 2 In the accompanying drawings, insulating films 61 and 62 are depicted with different shading lines for ease of observation. However, in the actual semiconductor device 1, insulating films 61 and 62 may be indistinguishable from each other. This is because insulating films 61 and 62 are, for example, made of the same material.

[0055] (Semiconductor device manufacturing method)

[0056] Next, use Figure 3 and Figure 4 An example of the manufacturing method of the semiconductor device 1 in the embodiment will be described. Figure 3 and Figure 4 This diagram illustrates a portion of the steps in the manufacturing method of the semiconductor device 1 according to the embodiments.

[0057] Furthermore, set as in Figure 3 and Figure 4 Prior to the processing shown, a peripheral circuit CUA has been formed on the substrate SB, and an insulating layer 50 covering the peripheral circuit CUA has been formed.

[0058] Figure 3 (A)~(C) and Figure 4 (D) through (F) sequentially show the status of the processing progress. Figure 3 (A)~(C) and Figure 4 The diagram marked (D) to (F) is a top view of the stepped region SR in this process. Figure 3 (A)~(C) and Figure 4 The figures marked (D) to (F) are cross-sectional views of the a-a' line, the b-b' line, and the c-c' line in the figure marked a.

[0059] In addition, Figure 3 (Ba), (Ca), Figure 4 In (Da), (Ea), and (Fa), for ease of explanation, structures such as stepped sections SP, SPf, and SPs, which may not be visually confirmed when viewed from above, are also depicted.

[0060] In the manufacturing method of semiconductor device 1, a source line SL is formed on an insulating layer 50. The source line SL is, for example, a polysilicon layer. Furthermore, a stacked body LMs is formed on the source line SL.

[0061] Laminated structures (LMs) have a structure formed by alternately stacking insulating layers NL (such as SiN layers as first insulating layers) and OL (such as SiO2 layers as second insulating layers). The insulating layer NL functions as a sacrificial layer that is subsequently replaced by a conductive material to become a word line (WL). In a certain region of such laminated structures (LMs), the insulating layers NL and OL are recessed into a stepped shape to form a stepped region SR.

[0062] like Figure 3 As shown in (A), a mask pattern 100 is formed as a mask film by covering a portion of the stepped region SR. Specifically, a resist film is applied to the entire surface of the laminate LMs by spin coating. This fills the stepped region SR with the resist film. Furthermore, the mask pattern 100 is formed by performing a predetermined exposure and development process on the stepped region SR.

[0063] The mask pattern 100 is a line pattern that completely covers the width of the stepped region SR in the Y direction and extends in the Y direction. The mask pattern 100 extending in the Y direction can also be formed across the stepped region SR, extending in a manner that protrudes from both ends of the stepped region SR in the Y direction. By covering a portion of the stepped region SR with the mask pattern 100, the stepped region SR is divided in the X direction, forming one or more grooves 110 as a second groove. Furthermore, the size of the mask pattern 100 can be adjusted so that the width X100 of the mask pattern 100 in the X direction is smaller than the width Y1 of the stepped region SR in the Y direction.

[0064] The groove 110 is outlined by the width Y1 in the Y direction of the stepped region SR as the first side and the width X110 of the second side formed by dividing the stepped region SR in the X direction. For example, it is preferable that the size of the mask pattern 100 is adjusted as described above, so that the width X110 in the X direction of the groove 110 is smaller than the width Y1 in the Y direction of the stepped region SR.

[0065] In addition, Figure 3 In the example shown in (A), three grooves 110 are formed by four mask patterns 100, but this example is not limited to this one. The number of mask patterns 100 and the number of grooves 110 formed can be arbitrarily changed according to the dimensions of the stepped region SR in the X and Y directions. For example, by arranging one mask pattern 100 in the center of the stepped region SR in the X direction, two grooves 110 can be formed on both sides of the stepped region SR in the X direction. Alternatively, for example, by arranging two mask patterns 100 on each side of the stepped region SR in the X direction, one groove 110 can be formed in the center of the stepped region SR in the X direction. As described above, it is preferable that the wider the stepped region SR is in the X direction than in the Y direction, the more the number of mask patterns 100 and grooves 110 is increased, so that the widths X100 and X110 of the mask patterns 100 and grooves 110 in the X direction are smaller than the width Y1 in the Y direction of the stepped region SR.

[0066] like Figure 3 (B) and Figure 3 As shown in (C), an insulating film 61 is formed that is filled into the trench 110 and thus covers the entire upper surface of the laminate LMs that forms the mask pattern 100.

[0067] Specifically, such as Figure 3 As shown in (B), initially, the insulating film 61 is deposited on the upper surfaces of the stepped portions SP, SPf, SPs, the sidewalls of the trench 110 extending along the X direction, and the sidewalls of the mask pattern 100 extending along the Y direction. In addition, the insulating film 61 is also deposited on the upper surface of the mask pattern 100.

[0068] like Figure 3 As shown in (C), sometimes when the insulating film 61 is gradually deposited on the aforementioned portions to reach a predetermined film thickness, a void 71 is formed near the center of the trench 110. As described above, the insulating film 61 is formed by gradually increasing the film thickness from both sides of the sidewalls of the trench 110 extending along the X direction and the sidewalls of the mask pattern 100 extending along the Y direction. Therefore, in a certain closed region such as the trench 110, the unfilled area near the center of the trench 110 gradually decreases as the insulating film 61 is formed. In the CVD method, film formation is performed by adsorbing the reactants formed from the feed gas onto the surface of the deposited surface. Therefore, when the unfilled area becomes smaller, the feed gas does not enter, and the trench 110 is difficult to be completely filled. This results in the formation of a void 71.

[0069] The pore 71 has a shape corresponding to the shape of the trench 110. For example, when the width X110 of the trench 110 is approximately equal to the width Y1, the pore 71 becomes pinhole-shaped. As the width X110 becomes smaller than the width Y1, the pore 71 tends to become a slit-shaped structure with a long side in the Y direction. This is because the film is deposited approximately uniformly on the deposition surface in the CVD method.

[0070] In addition, such pores 71 sometimes extend in the depth direction of the stepped region SR. For example, this is because when the depth of the stepped region SR is greater than the width Y1 of the trench 110, i.e., when the aspect ratio is high, the raw material gas has difficulty entering along the depth direction of the stepped region SR.

[0071] like Figure 4 As shown in (D), the insulating film 61 formed on the upper surface of the stack LMs containing the mask pattern 100 is etched. As a result, the upper surfaces of the mask pattern 100 and the stack LMs are exposed, and the insulating film 61 filling the trench 110 is separated.

[0072] like Figure 4 As shown in (E), the mask pattern 100 is removed by ashing and SH processing, etc. Grooves 120 are formed in the portion where the mask pattern 100 has been removed.

[0073] Here, the laminated body LMs that forms the insulating film 61 and the trench 120 can also be heat-treated. As a result, the insulating film 61 is densified, which reduces the size of the pores 71.

[0074] like Figure 4 As shown in (F), an insulating film 62 is formed that is filled in the trench 120 and thus covers the entire upper surface of the laminate LMs that forms the insulating film 61.

[0075] Specifically, insulating film 62 is deposited on the upper surfaces of the stepped portions SP, SPf, and SPs, on the sidewalls of the trench 120 extending along the X direction, and on the sidewalls of the insulating film 61 extending along the Y direction. Additionally, insulating film 62 is also deposited on the upper surface of insulating film 61.

[0076] Sometimes, when the insulating film 62 gradually accumulates in the aforementioned areas to reach a predetermined film thickness, a void 72 may form near the center of the trench 120. As described above, the insulating film 62 is formed by gradually increasing the film thickness from both the X-direction extending sidewall of the trench 120 and the Y-direction extending sidewall of the insulating film 61. Therefore, in a certain enclosed region such as the trench 120, as the insulating film 62 forms, the unfilled area near the center of the trench 120 gradually becomes smaller. Consequently, the raw material gas cannot enter the details of the unfilled area, and the trench 120 is difficult to completely fill. This results in the formation of a void 72.

[0077] The aperture 72 has a shape corresponding to the shape of the groove 120. For example, when the width X120 of the groove 120 is approximately equal to the width Y1, the aperture 72 becomes pinhole-shaped. As the width X120 of the groove 120 becomes smaller than the width Y1, the aperture 72 tends to become a slit-shaped structure with a long side in the Y direction.

[0078] Such pores 72 sometimes extend along the depth direction of the stepped region SR. This is because, under conditions of high aspect ratio, it is difficult for the feed gas to enter along the depth direction of the stepped region SR.

[0079] In addition, sometimes when forming the insulating film 62, part or all of the pores 71 formed in the insulating film 61 may also be filled by the insulating film 62.

[0080] Furthermore, in this embodiment, the insulating film 61 or 62 has been described as being formed by CVD, but the film formation method is not limited to this. At least one of the insulating films 61 and 62 can also be formed by ALD (Atomic Layer Deposition). In ALD, film formation is performed at the atomic layer level; therefore, a denser film can be formed compared to CVD. According to ALD, the stepped region SR can be filled more densely with the insulating films 61 and 62.

[0081] In addition, although not shown in the figure, an insulating layer 52 covering these layers is formed on the upper surface of the laminate LMs and the upper surfaces of the insulating films 61 and 62.

[0082] Additionally, pillars PL are formed in the laminated LMs using a predetermined method. Furthermore, the pillars PL can also be formed before the step region SR is formed. Additionally, the laminated LMs are formed by replacing the insulating layer NL with word lines WL.

[0083] In the laminate LM, multiple contacts CC are formed that reach the word lines WL of each step constituting the stepped section SP.

[0084] After or before the formation of contact CC, a through contact C4 is formed in the through contact area TP. Additionally, a plate-shaped contact LI is formed at a timing point before or during the formation of through contact C4. Furthermore, the through contact C4, plate-shaped contact LI, and contact CC are connected to the upper layer wiring MX, and bit lines (not shown) are connected to the post PL.

[0085] The semiconductor device 1 is manufactured in accordance with the above embodiments.

[0086] (Comparative Example)

[0087] Next, use Figures 5-6 The manufacturing method of the semiconductor device of the comparative example will be described. Figures 5-6 This is a diagram illustrating the structure of a comparative example semiconductor device.

[0088] Figure 5 (a) is a top view of the stepped region SRc filled with insulating film 63 in the comparative example. Figure 5 (b) is Figure 5 A cross-sectional view of the stepped region SRc at line a-a' of (a). Figure 5 (c) is Figure 5 A cross-sectional view of the stepped region SRc at line b-b' in (a).

[0089] like Figure 5 As shown, when the stepped region SRc is filled with insulating film 63, slit-like pores Q extending along the X direction and the depth direction of the stepped region SRc are sometimes formed. For pores Q, the higher the aspect ratio of the stepped region SRc (e.g., 0.7 or above), the easier it is to form pores Q in the depth direction of the stepped region SRc. In addition, the longer the stepped region SRc is in the X direction, the easier it is for pores Q to be formed in a longer direction in the X direction.

[0090] Porosity Q can sometimes cause cracks in insulating films such as 63. For example... Figure 6As shown in (Aa), when the laminate LMs filled with insulating film 63 undergoes a predetermined heat treatment, the insulating film 63 shrinks due to heat. Furthermore, tensile stress is easily generated in the insulating film 63, while compressive stress is easily generated in the laminate LMs, which are composed of different types of layers. As a result, stress is applied to both sides of the insulating film 63 in the Y direction, starting from the upper and lower ends of the pores Q in the depth direction of the stepped region SRc. Figure 5 A large-scale crack is generated in the X direction of (a).

[0091] Sometimes, such cracks can induce short circuits. For example, ... Figure 6 As shown in (Ab), sometimes when the crack reaches a lower word line WL that is the connection object of the contact CC, the metal layer of the contact CC forms down to the lower word line WL during the formation of the contact CC. As a result, an electrical short circuit occurs between the upper and lower word lines WL.

[0092] Furthermore, sometimes the machining accuracy of the contact CC can be reduced due to the formation of such cracks and voids Q. This is because, for example... Figure 6 As shown in (B), when a pore Q is formed inside the insulating film 63, the etching rate differs between the areas where the pore Q is formed and the areas where the pore Q is not formed. For example, during the processing of the contact hole Hc when forming the contact CC, the etching rate is faster in the areas where the pore Q is formed. Therefore, sometimes the insulating layer NL of the next layer that will become the connection target of the contact CC is penetrated, and the contact hole Hc reaches the lower insulating layer NL. In such cases, when forming the contact CC, the metal layer of the contact CC may sometimes extend to the word line WL of the lower layer, resulting in an electrical short circuit between the word lines WL of the upper and lower layers.

[0093] According to the manufacturing method of the semiconductor device 1 of the embodiment, a mask pattern 100 is formed to cover a portion of the stepped region SR, thereby dividing the stepped region SR in the X direction to form one or more trenches 110. Then, an insulating film 61 is filled into the trenches 110, and the mask pattern 100 is removed to form an insulating film 62 that completely covers the stepped region SR. Thus, the stepped region SR can be filled while suppressing the generation of slit-like pores Q extending along the X direction.

[0094] According to the manufacturing method of the semiconductor device 1 of the embodiment, a mask pattern 100 is formed such that the width Y1 in the width direction of the stepped region SR, which forms the edge of the contour of the trench 110, is greater than or equal to the width X100 in the X direction of the trench 110. Therefore, even if a hole 71 is formed in the center of the trench 110, the hole 71 becomes approximately circular or a slit shape with a long side in the Y direction. This suppresses the generation of slit-shaped apertures Q extending in the X direction.

[0095] According to the manufacturing method of the semiconductor device 1 of the embodiment, at least one of the insulating film 61 and the insulating film 62 is formed by the ALD method. That is, either only the insulating film 61 of the insulating film 61 and the insulating film 62 can be formed by the ALD method, or only the insulating film 62 can be formed by the ALD method. Alternatively, both the insulating film 61 and the insulating film 62 can be formed by the ALD method. Thus, when only the insulating film 61 is formed by the ALD method, at least the formation of the void 71 can be suppressed. In addition, when only the insulating film 62 is formed by the ALD method, the formation of the void 72 is suppressed, and the void 71 of the insulating film 61 can be easily filled by the insulating film 62. In addition, when both the insulating film 61 and the insulating film 62 are formed by the ALD method, the formation of both the void 71 and the void 72 can be suppressed. In this way, forming at least one of the insulating film 61 and the insulating film 62 by the ALD method can further densely fill the stepped region SR.

[0096] (Modified Example)

[0097] In the above embodiment, the stepped region SR is divided in the X direction by covering at least a portion of it with a resist film such as the mask pattern 100, but the material of the mask pattern 100 is not limited thereto. For example, the stepped region SR may also be covered with a non-photosensitive organic film. In this case, firstly, an organic film is embedded in the stepped region SR, a resist film is formed on top of the organic film, and the resist film is used as a mask to etch the organic film to form the mask pattern 100. The organic film is preferably formed by spin coating, taking into account its embedding properties.

[0098] In the above embodiments, a semiconductor device 1 having a stepped region SR was used as an example for description, but it is not limited to this. For example, it can also be applied to the structure of a semiconductor device having a trench in which a predetermined film is buried.

[0099] Several embodiments of the present invention have been described above, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and / or variations thereof are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A method for manufacturing a semiconductor device, comprising: One or more second trenches are formed by dividing the first trench in the length direction by forming a mask film in a manner that covers a portion of the first trench; The first insulating film is filled into the second trench; Remove the mask film; as well as The second insulating film is formed in such a way that it completely covers the first trench. The mask is formed such that the length of the first side in the width direction of the first groove, which forms the outline of the second groove, is greater than or equal to the length of the second side in the length direction of the first groove.

2. The method for manufacturing a semiconductor device according to claim 1, At least one of the first insulating film and the second insulating film is formed by the ALD method.

3. A method for manufacturing a semiconductor device, comprising: A laminate is formed by alternately stacking a plurality of first insulating layers and a plurality of second insulating layers one after another; A first groove is formed in the laminate; One or more second trenches are formed by dividing the first trench in the length direction by forming a mask film in a manner that covers a portion of the first trench; The first insulating film is filled into the second trench; Remove the mask film; as well as The second insulating film is formed in such a way that it completely covers the first trench. The mask is formed such that the length of the first side in the width direction of the first groove, which forms the outline of the second groove, is greater than or equal to the length of the second side in the length direction of the first groove.

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