Silicon-based multilayer capacitor and method of manufacturing the same
By constructing a lateral multilayer structure in silicon-based capacitors, the problem of small capacitance is solved, achieving high capacitance density and high-frequency response capability, making it suitable for high-voltage applications and wafer-level integration.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- THE 13TH RES INST OF CHINA ELECTRONICS TECH GRP CORP
- Filing Date
- 2023-09-04
- Publication Date
- 2026-06-09
Smart Images
Figure CN117241663B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor electronic components technology, and in particular to a silicon-based multilayer capacitor and its fabrication method. Background Technology
[0002] Capacitors are fundamental components of electronic systems. Currently, capacitors include several types, such as ceramic capacitors, aluminum electrolytic capacitors, tantalum electrolytic capacitors, film capacitors, and silicon-based capacitors. Ceramic capacitors are widely used in electronic systems as a primary solution for miniaturized capacitors. However, in applications requiring high breakdown voltage, ceramic capacitors have lower capacitance density, larger size, and cannot be integrated with silicon processes at the wafer level.
[0003] Traditional silicon-based capacitors fabricated using microelectronics technology employ a single etching method to achieve a vertical capacitor structure. The specific steps include: etching deep holes on a conductive silicon wafer, growing a dielectric layer, and filling with conductive material. The conductive silicon wafer and conductive material, acting as electrode plates, together with the dielectric layer, constitute the capacitor structure. Etching deep holes increases the relative area of the capacitor electrode plates on both sides of the dielectric layer, thereby increasing the capacitance and capacitance density.
[0004] Typical etching equipment has an aspect ratio of 20:1. Etching equipment with a higher aspect ratio requires higher equipment and maintenance costs, and the process is more complex. Due to limitations in etching process capabilities, it is impossible to achieve a high vertical aspect ratio for capacitors. The relative area of the capacitor's two plates is limited by the etching depth, resulting in a smaller capacitor capacity. Summary of the Invention
[0005] This invention provides a silicon-based multilayer capacitor and its fabrication method to solve the problem of small capacitance in existing capacitors.
[0006] In a first aspect, embodiments of the present invention provide a method for fabricating a silicon-based multilayer capacitor. The method involves fabricating the multilayer capacitor on a conductive silicon wafer using silicon-based semiconductor technology. The method includes: repeatedly growing sacrificial layers and conductive layers alternately on the upper surface of the conductive silicon wafer to form a multilayer structure, wherein the conductive layer is made of conductive polycrystalline silicon. Etching is performed on the upper surface of the multilayer structure to create a first via penetrating each sacrificial layer and conductive layer in the multilayer structure, and conductive polycrystalline silicon is grown and filled into the first via to form a conductive pillar. The conductive pillar is electrically connected to each conductive layer. Etching is performed on the upper surface of the multilayer structure at a location different from the first via to create a second via, and each sacrificial layer composed of sacrificial material is released through the second via to obtain a first multilayer lateral electrode plate composed of conductive layers and conductive pillars. A dielectric layer is grown by thermal oxidation treatment on the surface of the first multilayer lateral electrode plate through the second via. Through the second through hole, conductive material is filled into the first multilayer lateral electrode plate after thermal oxidation treatment to form a second multilayer lateral electrode plate. This results in a lateral multilayer structure with the dielectric layer as the insulating medium and the first and second multilayer lateral electrode plates arranged alternately, thus realizing the fabrication of the silicon-based multilayer capacitor.
[0007] In one possible implementation, the material of the second multilayer lateral electrode plate is the same as that of the first multilayer lateral electrode plate.
[0008] In one possible implementation, the alternating growth occurs more than 10 times.
[0009] In one possible implementation, there are multiple second through holes. Each second through hole is symmetrically distributed around the first through hole.
[0010] In one possible implementation, the doping material in the conductive polycrystalline silicon is one or more of the following: phosphorus, boron, and arsenic.
[0011] In one possible implementation, the sacrificial layer is made of silicon dioxide.
[0012] In one possible implementation, after filling and growing conductive material into the thermally oxidized first multilayer lateral electrode plate through the second through-hole to form the second multilayer lateral electrode plate, the method further includes: preparing a lower electrode layer on the lower surface of the conductive silicon wafer, wherein the lower electrode layer is electrically connected to the conductive pillars of the first multilayer lateral electrode plate through the conductive silicon wafer. An upper electrode layer is then prepared on the upper surface of the second multilayer lateral electrode plate.
[0013] In one possible implementation, before forming the lower electrode layer on the lower surface of the conductive silicon wafer, the process further includes: thinning the thickness of the conductive silicon wafer to a predetermined thickness.
[0014] In one possible implementation, after preparing an upper electrode layer on the upper surface of the second multilayer lateral electrode plate, the method further includes preparing a passivation layer on the upper electrode layer, wherein the passivation layer has an electrode window.
[0015] Secondly, embodiments of the present invention provide a silicon-based multilayer capacitor, which is prepared based on the silicon-based multilayer capacitor preparation method described in any possible implementation of the first aspect.
[0016] This invention provides a silicon-based multilayer capacitor and its fabrication method. The invention utilizes conductive polycrystalline silicon pillars formed within alternating sacrificial and conductive polycrystalline silicon layers as structural supports. After releasing the sacrificial layer through a second via, the surface of a first multilayer lateral electrode plate, composed of conductive polycrystalline silicon layers and conductive polycrystalline silicon pillars, is used to replace the base thermally oxidized dielectric layer in situ. After filling the dielectric layer with grown conductive material, a lateral-structure silicon-based multilayer capacitor is obtained. The first multilayer lateral electrode plate, connected to a conductive silicon wafer via the conductive polycrystalline silicon pillars, serves as the lower electrode of the silicon-based multilayer capacitor. The second multilayer lateral electrode plate serves as the upper electrode. The first and second multilayer lateral electrode plates are electrically insulated from each other by a silicon oxide dielectric layer. In this lateral structure, the via etching depth only needs to reach the total thickness of each layer, which is much smaller than the lateral dimension. The relative area of the upper and lower electrodes of the lateral-structure silicon-based multilayer capacitor is proportional to the number of layers; therefore, the capacitance of the silicon-based multilayer capacitor can be increased by increasing the number of layers. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 This is a flowchart illustrating the implementation of a method for fabricating a silicon-based multilayer capacitor according to an embodiment of the present invention.
[0019] Figure 2 This is a schematic diagram of the multi-layer periodic structure after completing step 101, as provided in an embodiment of the present invention.
[0020] Figure 3 This is a schematic diagram of the structure after etching the first through hole according to an embodiment of the present invention;
[0021] Figure 4 This is a schematic diagram of the structure after the first through hole has been filled, according to an embodiment of the present invention;
[0022] Figure 5 This is a schematic diagram of the structure after etching the second through hole according to an embodiment of the present invention;
[0023] Figure 6 This is a schematic diagram of the structure of the first multilayer transverse electrode plate after the release of the sacrificial layer provided in an embodiment of the present invention;
[0024] Figure 7 This is a schematic diagram of the structure after the growth medium layer is provided in an embodiment of the present invention;
[0025] Figure 8 This is a schematic diagram of the structure after the fabrication of the second multilayer transverse electrode plate provided in an embodiment of the present invention;
[0026] Figure 9 This is a schematic diagram of the structure of a silicon-based multilayer capacitor after the preparation of electrodes and passivation layer provided in an embodiment of the present invention. Detailed Implementation
[0027] To enable those skilled in the art to better understand this solution, the technical solutions in the embodiments of this solution will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this solution, not all of them. Based on the embodiments of this solution, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this solution.
[0028] The term "comprising" and any other variations thereof in the specification, claims, and accompanying drawings of this invention mean "including but not limited to," and are intended to cover a non-exclusive inclusion, not limited to the examples listed herein. Furthermore, the terms "first" and "second," etc., are used to distinguish different objects, not to describe a specific order.
[0029] The implementation of the present invention will be described in detail below with reference to the accompanying drawings:
[0030] Existing silicon-based vertical capacitors are constructed by etching deep holes on a silicon wafer, growing a dielectric layer within the holes, and then filling them with conductive material. The conductive silicon wafer, conductive material, and dielectric layer together form the capacitor structure. Etching deep holes increases the relative area of the capacitor electrodes on both sides of the dielectric layer, thus increasing the capacitance. Increasing the etching depth can increase the capacitance, but as the etching depth increases, the diameter of the deep holes and the distance between them must also increase. On the one hand, the etching depth is limited by the etching capability of the etching equipment. On the other hand, as the etching depth increases, the hole diameter and the hole spacing also increase, leading to a larger device size. Therefore, the capacitance of vertically structured capacitors is limited.
[0031] This invention provides a silicon-based multilayer capacitor and its fabrication method, which solves the problem of small capacitance in existing vertically structured capacitors by using a silicon-based multilayer capacitor with a transverse electrode structure.
[0032] Figure 1This is a flowchart illustrating the fabrication method of a silicon-based multilayer capacitor according to an embodiment of the present invention. (Refer to...) Figure 1 This preparation method is based on silicon-based semiconductor technology to prepare silicon-based multilayer capacitors on conductive silicon wafers.
[0033] It should be noted that semiconductor processes fabricate multiple chip structures simultaneously at the wafer level. After fabrication, the wafer is diced to form individual chips. The following explanation focuses on a single chip to illustrate the fabrication method described above.
[0034] The fabrication method of this silicon-based multilayer capacitor includes:
[0035] In step 101, a sacrificial layer and a conductive layer are alternately grown multiple times on the upper surface of the conductive silicon wafer to form a multilayer structure, wherein the material of the conductive layer is conductive polycrystalline silicon.
[0036] Figure 2 This is a schematic diagram of the multi-layer periodic structure after completing step 101, as provided in an embodiment of the present invention. (Refer to...) Figure 2 :
[0037] In some embodiments, the conductive silicon wafer described above is a polished low-resistivity silicon wafer.
[0038] For example, the conductive silicon wafer is a single-sided polished low-resistivity silicon wafer.
[0039] For example, the conductive silicon wafer is a double-sided polished low-resistivity silicon wafer.
[0040] For example, multilayer capacitors can be fabricated on any polished surface of a conductive silicon wafer.
[0041] For example, the polished surface of a multilayer capacitor is used as the upper surface.
[0042] In some embodiments, the doping type of the conductive silicon wafer is N-type or P-type.
[0043] For example, high-purity silicon wafers are high-resistivity silicon wafers. After being doped with N-type or P-type, high-purity silicon wafers become low-resistivity silicon wafers and can conduct electricity.
[0044] In some embodiments, the sacrificial layer is an intermediate layer in the fabrication process. The sacrificial layer may be removed in subsequent steps.
[0045] For example, the material of the sacrificial layer is silicon dioxide.
[0046] In some embodiments, the conductive layer is made of conductive polycrystalline silicon.
[0047] For example, the doping material in the conductive polycrystalline silicon is one or more of the following: phosphorus, boron, and arsenic. Examples include phosphorus-doped polycrystalline silicon, boron-doped polycrystalline silicon, and arsenic-doped polycrystalline silicon.
[0048] In some embodiments, a sacrificial layer and a conductive layer are grown alternately multiple times on the upper surface of a conductive silicon wafer.
[0049] For example, in each alternating growth cycle, a sacrificial layer is first grown, followed by the regeneration of a conductive layer.
[0050] For example, the grown multilayer structure has an even number of layers, with the sacrificial layer and the conductive layer having the same number of layers.
[0051] For example, a conductive layer is first grown, and then sacrificial layers and conductive layers are grown alternately multiple times.
[0052] For example, the multilayer structure after growth has an odd number of layers, and the number of conductive layers is one more than the number of sacrificial layers.
[0053] In this embodiment of the invention, a conductive layer is first grown at the bottom layer. In the silicon-based multilayer capacitor structure finally obtained in step 105, the bottom conductive layer of the first multilayer lateral electrode plate is connected to the conductive silicon wafer. Compared with the connection between the conductive layer and the conductive silicon wafer only through conductive pillars, this increases the conductive contact area and improves conductivity.
[0054] In some embodiments, the method for growing conductive polycrystalline silicon includes low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, metal-organic chemical vapor deposition, atomic layer deposition, or physical vapor deposition.
[0055] In one possible implementation, the alternating growth occurs more than 10 times.
[0056] In step 102, etching is performed on the upper surface of the multilayer structure to create a first via that penetrates each sacrificial layer and conductive layer in the multilayer structure. Conductive polysilicon is then grown and filled into the first via to form a conductive pillar. The conductive pillar is electrically connected to each conductive layer.
[0057] Figure 3 This is a schematic diagram of the structure after etching the first through-hole according to an embodiment of the present invention. (Refer to...) Figure 3 :
[0058] In some embodiments, the number of first through holes is one or more.
[0059] For example, there is one first through-hole, which is located at the center of the chip.
[0060] For example, there are multiple first through holes, and each first through hole is evenly spaced.
[0061] In some embodiments, the first via penetrates each sacrificial layer and each first conductive layer, and the first via is connected to the upper surface of the conductive silicon wafer.
[0062] For example, the first via can also extend into the interior of the conductive silicon wafer.
[0063] For example, the etching method is dry etching.
[0064] Figure 4 This is a schematic diagram of the structure after the first through hole has been filled, according to an embodiment of the present invention. (Refer to...) Figure 4 :
[0065] In some embodiments, conductive polysilicon is grown and filled into the first through-hole to form a conductive pillar.
[0066] Examples of methods for filling and growing conductive polycrystalline silicon include low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, metal-organic chemical vapor deposition, atomic layer deposition, or physical vapor deposition.
[0067] For example, low-resistivity conductive polycrystalline silicon can be formed by doping with impurity elements such as phosphorus, boron or arsenic during the growth of polycrystalline silicon and then activating the impurities.
[0068] For example, the interior of the first through hole after filling can be completely filled, or a gap can be left in the center of the through hole.
[0069] In some embodiments, step 102 may further include: etching the upper surface of the multilayer structure to prepare a square annular groove.
[0070] For example, a square annular mask is prepared on the surface of a multilayer structure, and then etched to form a square annular groove.
[0071] For example, the square ring can be set along the edge of the chip.
[0072] For example, a square annular groove surrounds the first through hole.
[0073] Correspondingly, conductive polycrystalline silicon is grown and filled into the square annular groove to form a conductive wall.
[0074] In some embodiments, after step 102, the method further includes: using a chemical mechanical polishing process to planarize the polycrystalline silicon surface on the upper surface of the multilayer structure.
[0075] In step 103, etching is performed on the upper surface of the multilayer structure at a position different from the first through hole to prepare a second through hole, and each sacrificial layer made of sacrificial material is released through the second through hole to obtain the first multilayer transverse electrode plate composed of each conductive layer and conductive pillar.
[0076] Figure 5 This is a schematic diagram of the structure after etching the second through-hole according to an embodiment of the present invention. (Refer to...) Figure 5 :
[0077] In one possible implementation, there are multiple second through holes. Each second through hole is symmetrically distributed around the first through hole.
[0078] In this embodiment of the invention, multiple second through holes are provided, which can accelerate the release of the sacrificial layer, as well as accelerate the growth of the dielectric layer in step 104 and the growth of the conductive material in step 105.
[0079] In some embodiments, the etched second via penetrates each sacrificial layer and each first conductive layer to the upper surface of the conductive silicon wafer.
[0080] In some embodiments, when releasing each sacrificial layer made of sacrificial material through the second through-hole, a gas phase release process or a liquid phase release process may be used.
[0081] For example, after the sacrificial layer is released through the second through-hole, the space occupied by the second through-hole and the sacrificial layer forms a cavity.
[0082] Figure 6 This is a schematic diagram of the structure of the first multilayer lateral electrode plate after the release of the sacrificial layer, as provided in an embodiment of the present invention. (Refer to...) Figure 6 :
[0083] In some embodiments, after the sacrificial layer is released through the second through-hole, a first multilayer transverse electrode plate composed of each conductive layer and conductive pillar is obtained.
[0084] In some embodiments, step 103 may further include: etching a square annular groove on the upper surface of the multilayer structure at a location different from the first through-hole; and releasing each sacrificial layer made of sacrificial material through the square annular groove.
[0085] Accordingly, a dielectric layer is grown through a square annular groove in step 104, and a conductive material is grown through a square annular groove in step 105. The square annular groove increases the channel area for release and growth, thus accelerating the release and growth process.
[0086] Figure 7 This is a schematic diagram of the structure after the growth medium layer is provided in an embodiment of the present invention. (Refer to...) Figure 7 :
[0087] In step 104, the surface of the first multilayer transverse electrode is thermally oxidized through the second through hole to grow a dielectric layer.
[0088] Thermal oxidation of silicon involves a chemical reaction between silicon and gases containing oxidizing substances, such as water vapor and oxygen, at high temperatures, resulting in a dense silicon dioxide (SiO2) film on the surface of the silicon wafer.
[0089] The first multilayer lateral electrode is made of polycrystalline silicon. Thermal oxidation involves in-situ oxidation of the silicon layer on the polycrystalline silicon surface into a dielectric layer. It does not involve growing a dielectric layer on the surface of the polycrystalline silicon.
[0090] In some embodiments, a dielectric layer is prepared by thermally oxidizing the surface of the first multilayer transverse electrode plate composed of each conductive layer and conductive pillar through a second through-hole.
[0091] For example, the top surface of the top conductive layer is also thermally oxidized to grow a dielectric layer.
[0092] In step 105, conductive material is filled into the first multilayer lateral electrode plate after thermal oxidation through the second through hole to form a second multilayer lateral electrode plate. This results in a lateral multilayer structure with a dielectric layer as the insulating medium and the first and second multilayer lateral electrode plates arranged alternately, thus realizing the fabrication of a silicon-based multilayer capacitor.
[0093] Figure 8 This is a schematic diagram of the structure after fabrication of the second multilayer lateral electrode plate according to an embodiment of the present invention. (Refer to...) Figure 8 :
[0094] Inside the first multilayer transverse electrode plate, each conductive layer and conductive pillar forms a closed cavity, which is connected to the outside through a second through hole. After step 104, a dielectric layer is prepared on the inner wall of the cavity.
[0095] In some embodiments, conductive material is grown and filled into the interior of the first multilayer lateral electrode through the second through-hole.
[0096] In some embodiments, a dielectric layer is grown on the upper surface of the top conductive layer. Accordingly, step 105 further includes growing a conductive material on the dielectric layer on the upper surface of the top conductive layer.
[0097] For example, the filled-grown conductive material forms a second multilayer lateral electrode.
[0098] In some embodiments, the conductive material may be conductive polycrystalline silicon.
[0099] In some embodiments, after forming the second multilayer lateral electrode, the uppermost conductive material is further subjected to chemical mechanical polishing to smooth the surface.
[0100] This invention provides an embodiment of a silicon-based multilayer capacitor that uses conductive polycrystalline silicon pillars as structural supports within alternating sacrificial and conductive polycrystalline silicon layers. After releasing the sacrificial layer through a second via, the surface of the first multilayer lateral electrode plate, composed of the conductive polycrystalline silicon layers and conductive polycrystalline silicon pillars, is used to replace the base thermally oxidized dielectric layer in situ. After filling the dielectric layer with a conductive material, a lateral-structured silicon-based multilayer capacitor is obtained. The first multilayer lateral electrode plate, connected to the conductive silicon wafer via the conductive polycrystalline silicon pillars, serves as the lower electrode of the silicon-based multilayer capacitor. The second multilayer lateral electrode plate serves as the upper electrode. The first and second multilayer lateral electrode plates are electrically insulated from each other by a silicon oxide dielectric layer. In this lateral structure, the via etching depth only needs to reach the total thickness of each layer, which is much smaller than the lateral dimension. The relative area of the upper and lower electrodes of the lateral-structured silicon-based multilayer capacitor is proportional to the number of layers; therefore, the capacitance of the silicon-based multilayer capacitor can be increased by increasing the number of layers.
[0101] In one possible implementation, in step 102, a conductive metal can also be grown and filled into the first via to form a conductive pillar. Correspondingly, in step 104, a silicon dioxide dielectric layer can be grown by plasma-enhanced chemical vapor deposition.
[0102] Metal conductive pillars serve both structural support and electrical conductivity. However, the applicant of this invention has discovered that silicon-based multilayer capacitors are prone to breakdown and exhibit low breakdown strength in high-voltage applications. Furthermore, they demonstrate poor frequency response in high-frequency applications.
[0103] After research, the inventors of this application discovered that due to the complex internal space enclosed by the first multilayer lateral electrode plates, conventional dielectric layer growth methods such as plasma-enhanced chemical vapor deposition require the growth of additional dielectric layers on the inner surface of the complex structure. Uneven dielectric layer thickness, poor film quality, and numerous pores easily lead to breakdown under high voltage. Furthermore, filling the polycrystalline silicon conductive layer with metal conductive pillars creates a dissimilar material interface between each conductive layer and the metal conductive pillars, resulting in decreased conductivity and poor high-frequency response.
[0104] In this embodiment of the invention, conductive polycrystalline silicon is grown and filled into the first through-hole in step 102 to form a conductive pillar. On one hand, in step 104, the silicon is replaced in situ with a silicon oxide dielectric layer through thermal oxidation, improving the film quality and enhancing the breakdown strength of the dielectric layer in the complex structure. On the other hand, in step 102, the polycrystalline silicon conductive pillar is formed by filling the first through-hole. The polycrystalline silicon conductive pillar and the polycrystalline silicon conductive layer are bonded to the same material at the interface, resulting in low interface resistance, improved conductivity, and enhanced frequency response capability of the silicon-based multilayer capacitor.
[0105] In one possible implementation, the material of the second multilayer lateral electrode plate is the same as that of the first multilayer lateral electrode plate.
[0106] In this embodiment of the invention, by growing conductive materials of the same type on both sides of the dielectric layer in step 105, the material of the second multilayer lateral electrode plate is the same as that of the first multilayer lateral electrode plate, and the coefficient of thermal expansion is consistent. The internal stress formed at high temperature is small, and the thermal expansion deformation is small, which reduces the damage of thermal expansion to the dielectric layer and improves the breakdown resistance.
[0107] Figure 9 This is a schematic diagram of the structure of a silicon-based multilayer capacitor after the preparation of electrodes and a passivation layer, as provided in an embodiment of the present invention. (Refer to...) Figure 9 :
[0108] In one possible implementation, after filling and growing conductive material into the thermally oxidized first multilayer lateral electrode plate through the second through-hole to form the second multilayer lateral electrode plate, the method further includes: preparing a lower electrode layer on the lower surface of the conductive silicon wafer, wherein the lower electrode layer is electrically connected to the conductive pillars of the first multilayer lateral electrode plate through the conductive silicon wafer; and preparing an upper electrode layer on the upper surface of the second multilayer lateral electrode plate.
[0109] In some embodiments, the electrode layer can be prepared by electroplating, sputtering etching, or evaporation stripping processes.
[0110] For example, the material of the electrode layer can be one or more metals such as Au, Al, Ni, Pd, W, Ti or Pt.
[0111] In one possible implementation, before forming the lower electrode layer on the lower surface of the conductive silicon wafer, the process further includes: thinning the thickness of the conductive silicon wafer to a predetermined thickness.
[0112] In some embodiments, a grinding process or an etching process is used to thin the back side of the conductive silicon wafer to a preset thickness.
[0113] In one possible implementation, after preparing the upper electrode layer on the upper surface of the second multilayer transverse electrode plate, the method further includes preparing a passivation layer on the upper electrode layer, wherein the passivation layer has an electrode window.
[0114] In some embodiments, the prepared passivation layer is patterned and etched to obtain an electrode window.
[0115] In some embodiments, the material of the passivation layer may be Si3N4, SiO2, HfO2, Al2O3, Ta2O5, AlN, polyimide, or BCB, etc.
[0116] In some embodiments, the method for growing the passivation layer includes low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, metal-organic chemical vapor deposition, atomic layer deposition, or physical vapor deposition.
[0117] In some embodiments, the electrode window is used to expose the electrode layer, which is then used to connect to an external circuit.
[0118] The following is a specific embodiment illustrating the fabrication process of the silicon-based multilayer capacitor of the present invention:
[0119] 1. Use polished low-resistivity silicon wafers, which can be polished on one side or both sides. The doping type can be N-type or P-type, and the thickness is 200μm to 1000μm. The bulk resistivity is less than 0.01Ω*cm.
[0120] 2. Using the polished surface of the silicon wafer as the process surface, silicon oxide and polycrystalline silicon are alternately grown on the wafer surface until a multi-layered periodic structure is formed. The typical number of layers is 20, but other numbers can also be selected. The thickness of a single layer can range from 0.1µm to 50µm, determined according to the requirements of the device's equivalent series resistance, capacitance, etc. Polycrystalline silicon can be doped with impurities such as P, B, and As, and activated by these impurities to achieve low resistivity.
[0121] 3. Using dry etching, designed vertically penetrating holes are formed within the multilayer silicon oxide substrate. These holes extend directly to the substrate. Typical diameters range from 5µm to 20µm. The diameter can be determined based on the device's equivalent series resistance, capacitance, and other requirements.
[0122] 4. Grow polycrystalline silicon to fill the openings and interior of the pores. Polycrystalline silicon can be doped with impurities such as P, B, and As, and activated by these impurities to achieve low resistivity. The polycrystalline silicon can completely fill the pores or leave gaps. The thickness of the polycrystalline silicon should ideally fill the openings and exceed them by a certain height.
[0123] 5. Chemical mechanical polishing to smooth the surface of polycrystalline silicon.
[0124] 6. Using dry etching, designed vertically penetrating holes are formed inside multilayer silicon oxide and polycrystalline silicon. The holes extend directly into the substrate. Etching can be performed to reach the interior of the substrate.
[0125] 7. Use a release process to completely remove the multilayer silicon oxide. This can be done using either a gas-phase or liquid-phase release process.
[0126] 8. Dielectric layer growth. The growth method can be thermal oxidation. The typical thickness of the dielectric layer is 2nm to 1000nm, which can be determined according to the device's capacitance, withstand voltage, and other requirements. After growth, it forms a cover over the polycrystalline silicon electrode assembly.
[0127] 9. Growing polycrystalline silicon to fill the pores and interior. Polycrystalline silicon can be doped with impurities such as P, B, and As, and activated by these impurities to achieve low resistivity. The polycrystalline silicon can completely fill the pores or leave gaps. After growth, it forms a cover over the dielectric layer.
[0128] 10. Chemical mechanical polishing to smooth the surface of polycrystalline silicon.
[0129] 11. Top Electrode Preparation. One or more of the following processes can be used: electroplating, sputtering etching, or evaporation stripping. The metal can be one or more of the following metals: Au, Al, Ni, Pd, W, Ti, Pt, etc. The metal thickness should meet the requirements of welding or wire bonding processes.
[0130] 12. Passivation layer growth. Materials can include Si3N4, SiO2, HfO2, Al2O3, Ta2O5, AlN, polyimide, BCB, or other materials and multilayer composites. Growth methods can be one or more of the following: thermal oxidation, LPCVD, PECVD, MOCVD, ALD, PVD, etc.
[0131] 13. Pattern the passivation layer, which can be done using dry or wet etching. Expose the metal electrodes.
[0132] 14. Backside Grinding. The substrate is thinned to a predetermined thickness using grinding or etching processes. Typical thicknesses are 150 μm or 250 μm, etc.
[0133] 15. Bottom Electrode Fabrication. One or more of the following processes can be used: electroplating, sputtering etching, or evaporation stripping. The metal can be one or more of the following metals: Au, Al, Ni, Pd, W, Ti, Pt, etc. The metal thickness should be sufficient to meet the requirements of welding or wire bonding processes.
[0134] This invention provides a silicon-based multilayer capacitor, which is prepared based on the silicon-based multilayer capacitor preparation method described in any of the above possible implementations.
[0135] The silicon-based multilayer capacitor structure provided in this invention can significantly improve capacitance density by increasing the capacitor plate area through multiple depositions of polysilicon and silicon oxide layers, as well as silicon oxide release and polysilicon backfilling techniques. Silicon-based multilayer capacitors offer advantages such as small size, high capacitance density, high consistency, low-cost mass production, and wafer-level integration.
[0136] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for fabricating a silicon-based multilayer capacitor, characterized in that, The fabrication method is based on silicon-based semiconductor technology to fabricate the silicon-based multilayer capacitor on a conductive silicon wafer. The fabrication method includes: A multilayer structure is formed by repeatedly growing sacrificial and conductive layers alternately on the upper surface of a conductive silicon wafer, wherein the material of the conductive layer is conductive polycrystalline silicon. The upper surface of the multilayer structure is etched to form a first through-hole that penetrates each sacrificial layer and conductive layer in the multilayer structure. Conductive polysilicon is then grown and filled into the first through-hole to form a conductive pillar. The conductive pillar is electrically connected to each conductive layer. On the upper surface of the multilayer structure, at a position different from the first through hole, a second through hole is formed, and each sacrificial layer made of sacrificial material is released through the second through hole to obtain a first multilayer lateral electrode plate composed of each conductive layer and conductive pillar. Through the second through hole, the surface of the first multilayer transverse electrode plate is subjected to thermal oxidation treatment to grow a dielectric layer; Through the second through hole, conductive material is filled into the first multilayer lateral electrode plate after thermal oxidation treatment to form a second multilayer lateral electrode plate. This results in a lateral multilayer structure with the dielectric layer as the insulating medium and the first and second multilayer lateral electrode plates arranged alternately, thus realizing the fabrication of the silicon-based multilayer capacitor.
2. The method for fabricating a silicon-based multilayer capacitor as described in claim 1, characterized in that, The material of the second multilayer lateral electrode plate is the same as that of the first multilayer lateral electrode plate.
3. The method for fabricating a silicon-based multilayer capacitor as described in claim 1, characterized in that, The number of alternating growth cycles is greater than 10.
4. The method for fabricating a silicon-based multilayer capacitor as described in claim 1, characterized in that, There are multiple second through holes; Each second through hole is symmetrically distributed around the first through hole.
5. The method for fabricating a silicon-based multilayer capacitor as described in claim 1, characterized in that, The doping material in the conductive polycrystalline silicon is one or more of the following: phosphorus, boron, and arsenic.
6. The method for fabricating a silicon-based multilayer capacitor as described in claim 1, characterized in that, The material of the sacrificial layer is silicon dioxide.
7. The method for fabricating a silicon-based multilayer capacitor as described in claim 1, characterized in that, After filling and growing conductive material into the thermally oxidized first multilayer lateral electrode plate through the second through-hole to form the second multilayer lateral electrode plate, the process further includes: A lower electrode layer is prepared on the lower surface of the conductive silicon wafer, wherein the lower electrode layer is electrically connected to the conductive pillars of the first multilayer lateral electrode plate through the conductive silicon wafer. An upper electrode layer is prepared on the upper surface of the second multilayer transverse electrode plate.
8. The method for fabricating a silicon-based multilayer capacitor as described in claim 7, characterized in that, Before fabricating the lower electrode layer on the lower surface of the conductive silicon wafer, the following steps are also included: The thickness of the conductive silicon wafer is reduced to a preset thickness.
9. The method for fabricating a silicon-based multilayer capacitor as described in claim 7, characterized in that, After fabricating the upper electrode layer on the upper surface of the second multilayer transverse electrode plate, the following steps are also included: A passivation layer is prepared on the upper electrode layer, wherein the passivation layer is provided with an electrode window.
10. A silicon-based multilayer capacitor, characterized in that, It is prepared according to the method for preparing silicon-based multilayer capacitors as described in any one of claims 1 to 9.