Voltage overshoot suppressor under loss of voltage conditions

Abstract

The described embodiments include circuitry for suppressing overshoot in a voltage regulator. The circuitry includes a first offset voltage circuit (474) and a second offset voltage circuit (476), each having an input coupled to an input voltage terminal (402). A first comparator (480) has a first comparator input coupled to a first offset output, and a second comparator input (404) coupled to a reference voltage terminal. A second comparator (482) has a third comparator input coupled to an output of the second offset circuit, and a fourth comparator input coupled to a voltage regulator output (460). An OR gate (484) has a first logic input and a second logic input and a logic output. The first and second logic inputs are coupled to outputs of the first and second comparators, respectively. A shutdown circuit (486) has a shutdown input coupled to the logic output, and is configured to provide a shutdown signal at a shutdown output to stop the flow of current from the voltage regulator output.

Description

Background Technology

[0001] This specification relates to voltage regulators, and specifically to limiting voltage overshoot on the regulator's output voltage after a line transient or undervoltage condition. Voltage overshoot can occur at the regulator's output when the input supply voltage temporarily drops below the dropout voltage limit due to a rapid transient and then recovers. When the regulator recovers from the dropout condition, a large current may surge through the load impedance, leading to overshoot and / or current-limiting conditions. The voltage regulator's dropout voltage is the minimum difference between the input voltage and the output voltage required to maintain voltage regulation and enable the regulator to provide a specified voltage and current at the output.

[0002] An undervoltage condition occurs when the input voltage drops below the value required by the voltage regulator to maintain its specified voltage and current at the output. Undervoltage refers to a temporary drop in the voltage level of the regulator's input voltage. When undervoltage occurs, the regulator's input voltage drops from its normal level to a lower voltage and then returns to its normal level. When the input supply voltage drops, the regulator's feedback loop attempts to compensate for the lower input voltage by increasing the gain. As the gain increases, more current flows through the load, attempting to raise the output voltage. However, once the input voltage recovers, the bandwidth of the control loop may not be fast enough to reduce the gain before the regulator enters a current-limiting condition or an overshoot occurs on the output voltage. Each of these conditions can cause the voltage regulator to fail to operate within its specifications. Summary of the Invention

[0003] In a first example, a circuit for suppressing overshoot in a voltage regulator includes a first offset voltage circuit having a first offset input and a first offset output. The first offset input is coupled to an input voltage terminal. A second offset voltage circuit has a second offset input and a second offset output. The second offset input is coupled to the input voltage terminal. A first comparator has a first comparator input, a second comparator input, and a first comparator output. The first comparator input is coupled to the first offset output, and the second comparator input is coupled to a reference voltage terminal. The second comparator has a third comparator input, a fourth comparator input, and a second comparator output. The third comparator input is coupled to the second offset output, and the fourth comparator input is coupled to the voltage regulator output.

[0004] The OR gate has a first logic input, a second logic input, and a logic output. The first logic input is coupled to a first comparator output, and the second logic input is coupled to a second comparator output. The shutdown circuit has a shutdown input and a shutdown output. The shutdown input is coupled to the logic output. The shutdown circuit is configured to provide a shutdown signal at the shutdown output to stop current flow from the voltage regulator output in response to a logic high at the shutdown input.

[0005] In a second example, a voltage regulator circuit includes a reference generation circuit having a reference input and a reference output. The reference input is coupled to an input voltage terminal. A first amplifier has a first amplifier input and a second amplifier input, as well as a first amplifier output. The first amplifier input is coupled to the reference output, and the second amplifier input is coupled to an output voltage terminal. A second amplifier has a third amplifier input and a second amplifier output. The third amplifier input is coupled to the first amplifier output.

[0006] A first transistor is coupled between an input voltage terminal and the output of a first amplifier and has a first control terminal. A second transistor is coupled between an input voltage terminal and an output voltage terminal and has a second control terminal coupled to the output of a second amplifier. A first offset voltage circuit has a first offset input and a first offset output. The first offset input is coupled to the input voltage terminal. A second offset voltage circuit has a second offset input and a second offset output, the second offset input being coupled to the input voltage terminal.

[0007] The first comparator has a first comparator input, a second comparator input, and a first comparator output. The first comparator input is coupled to a first offset output, and the second comparator input is coupled to a reference output. The second comparator has a third comparator input, a fourth comparator input, and a second comparator output. The third comparator input is coupled to a second offset output, and the fourth comparator input is coupled to an output voltage terminal. The OR gate has a first logic input, a second logic input, and a logic output. The first logic input is coupled to the first comparator output, and the second logic input is coupled to the second comparator output. The shutdown circuit has a shutdown input and a shutdown output. The shutdown input is coupled to the logic output, and the shutdown circuit is configured to provide a shutdown signal at a first control terminal in response to a logic high at the shutdown input.

[0008] In the third example, a method for suppressing overshoot in a voltage regulator includes supplying an input voltage to the voltage regulator input and enabling the voltage regulator output. A reference voltage is generated at the reference voltage output. The output voltage at the voltage regulator output is adjusted by comparing the reference voltage with a feedback voltage proportional to the output voltage.

[0009] The first offset voltage is compared to the difference between the input voltage and the output voltage. The second offset voltage is compared to the difference between the input voltage and the reference voltage. The voltage regulator output is disabled in response to either the first offset voltage being greater than the difference between the input voltage and the output voltage, or the second offset voltage being greater than the difference between the input voltage and the reference voltage. Attached Figure Description

[0010] Figure 1 A schematic diagram of an exemplary voltage regulator is shown.

[0011] Figure 2 A schematic diagram of an exemplary voltage regulator with current limiting is shown.

[0012] Figure 3 A schematic diagram of an exemplary voltage regulator with an undervoltage sensing circuit is shown.

[0013] Figure 4 A block diagram of an exemplary comparator-based overshoot suppression circuit in a voltage regulator is shown.

[0014] Figure 5 A schematic diagram of an exemplary comparator-based overshoot suppression circuit in a voltage regulator is shown.

[0015] Figure 6 A flowchart is shown as an exemplary method for implementing a comparator-based overshoot suppression circuit in a voltage regulator. Detailed Implementation

[0016] In this specification, the same reference numerals depict the same or similar features (in terms of function and / or structure). The figures are not necessarily drawn to scale.

[0017] Figure 1 A schematic diagram of an exemplary voltage regulator 100 is shown. The input of the voltage regulator 100 is V. DD 102. The output of voltage regulator 100 is V. OUT 160. Resistors 142 and 146 are coupled in series at V. OUT Between 160 and ground, and for V OUT The voltage at 160 is divided to provide a feedback voltage signal for voltage regulation. Feedback voltage terminal V FB 144 is coupled to the first input of error amplifier 110. The second input of error amplifier 110 is coupled to the reference voltage circuit V. REF 104.

[0018] The output of error amplifier 110 is coupled to the input of buffer amplifier 120. The output of buffer amplifier 120 is coupled to the gate of transistor 130. The source of transistor 130 is coupled to V. DD 102. The drain of transistor 130 is coupled to the output V of voltage regulator 100. OUT 160. Load 150 includes parallel coupling at V OUT Resistor 152 and capacitor 154 are connected between 160 and ground.

[0019] Resistors 142 and 146 form the output voltage V OUT A 160-degree voltage divider is used to provide the feedback voltage V. FB144. Use amplifier 110 to... FB 144 and reference voltage V REF Compare 104. V REF The voltage of 104 is chosen to be equal to when V OUT 160 V at a specified voltage FB The voltage is 144. The output EAMPHIZ indicator of amplifier 110 shows the output voltage V. OUT Is 160 higher or lower than the specified voltage? The input of buffer amplifier 120 is coupled to the output of amplifier 110. The output of buffer amplifier 120 is coupled to the gate of transistor 130. If V OUT If the voltage at 160 is lower than the specified value, the output of buffer amplifier 120 will be low, thereby increasing the gate-source voltage (V) of transistor 130. GS If V OUT If the voltage at position 160 is higher than the specified value, then the V of transistor 130... GS It will decrease. Decrease the V of transistor 130. GS This reduces the current flowing through resistor 152, thereby reducing V. OUT Voltage at 160.

[0020] If the current demand from load 150 is higher than the current that transistor 130 can provide, then V OUT The voltage at 160 may begin to drop. As V... OUT When the voltage drops at 160, the output EAMPHIZ of error amplifier 110 is driven to ground, causing error amplifier 110 to saturate. When it is saturated, error amplifier 110 cannot respond to the input, and the output EAMPHIZ remains grounded.

[0021] Buffer amplifier 120 has a non-inverting input, so when the input is grounded, the output of buffer amplifier 120 is driven to ground, which in turn drives the gate of transistor 130 to ground. This creates a large V in transistor 130. GS This results in a large current flowing through transistor 130. The large current through the load resistor 152 increases V. OUT The voltage at 160 may cause V OUT Voltage overshoot at 160°C.

[0022] When V DD A similar problem may occur when the voltage on 102 drops. When V DD When the voltage on 102 drops, in response, V OUT The voltage at 160 may drop. With V OUTThe voltage drop at 160 causes the output of error amplifier 110, EAMPHIZ, to be driven to ground. With the input of buffer amplifier 120 grounded, the output of buffer amplifier 120 is driven to ground, thereby driving the gate of transistor 130 to ground. Grounding the gate of transistor 130 creates a large V in transistor 130. GS This allows a large current to flow through transistor 130 and load resistor 152.

[0023] The large current through the load resistor 152 increased V OUT The voltage at 160 causes V OUT There is a voltage overshoot at 160. Therefore, V DD A voltage drop across 102 can drive the voltage regulator to an undervoltage condition. When V DD When the voltage on 102 recovers, due to the large V GS A high current will flow through transistor 130. Due to the high current through the load resistor 152, the large current flowing through transistor 130 can generate a voltage overshoot V. OUT 160.

[0024] The second problem may occur in some applications where a reference voltage V is generated outside the chip. REF In the 104 regulator, in some ultra-low noise architectures, the reference is generated externally off-chip to allow the use of large external capacitors to filter out noise on the reference voltage signal. The reference voltage is determined by the reference current I flowing through the reference resistor. REF This is generated by a reference resistor having a filter capacitor connected in parallel with it. Reference current I REF The magnitude is in the microampere range, while the current through transistor 130 can range from several hundred milliamperes to several amperes. Because the current through transistor 130 and I... REF This large difference in current, therefore, affects the size of the body diode and I in transistor 130. REF There can be large differences in the size of the body diodes in a transistor.

[0025] If V DD If 102 decreases, then V OUT 160 will discharge rapidly. In at least one case, V OUT 160 is directly connected to the input of error amplifier 110. If V DD 102 dropped below V OUT Then V OUT It will drop to V DD Subtract the voltage drop across transistor 130. V REF It will stabilize below V. DD The voltage is 102, but it will be higher than V. OUTThe descent is slower because I REF The transistor has a smaller body diode than transistor 130, therefore V REF Discharge to below V DD This will take longer. Then, the error amplifier 110 is forced into an undervoltage condition, thereby driving the EAMPHIZ close to ground. Therefore, the gate of transistor 130 is at a near-ground voltage, while the source of transistor 130 is extremely high. GS This generates a large current through transistor 130, which causes V OUT Voltage overshoot at 160.

[0026] Figure 2 A schematic diagram of an exemplary voltage regulator 200 with current limiting is shown. The current limiting circuit of the voltage regulator 200 limits the output current during normal operation of the voltage regulator and when the voltage regulator is under undervoltage conditions.

[0027] The input of voltage regulator 200 is V DD 202. The output of voltage regulator 200 is V. OUT 260. Resistors 242 and 246 are coupled in series at V. OUT Between 260 and ground, and form a connection to V. OUT A voltage divider at 260° provides feedback for voltage regulation. Feedback voltage terminal V. FB 244 is coupled to the first input of error amplifier 210. The second input of error amplifier 210 is coupled to the reference voltage terminal V. REF 204.

[0028] The output of error amplifier 210 is coupled to the input of buffer amplifier 220. The output of buffer amplifier 220 is coupled to the gate of transistor 230. The source of transistor 230 is coupled to V. DD 202. The drain of transistor 230 is coupled to the output V of voltage regulator 200. OUT 260. Load 250 includes parallel coupling at V OUT Resistor 252 and capacitor 254 between 260 and ground.

[0029] Resistors 242 and 246 form the output voltage V OUT A 260 voltage divider that provides a feedback voltage V FB 244. Use error amplifier 210 to... FB 244 and reference voltage V REF Compare 204. V REF The value 204 was chosen to be equal to V. OUT 260 V at the specified voltage FBThe value is 244. The output of amplifier 210 indicates the output voltage V. OUT Is 260 higher or lower than the specified voltage? The output of buffer amplifier 220 responds to the output of amplifier 210, driving the gate of transistor 230. If V OUT The voltage at 260 needs to be increased, so the V of transistor 230... GS It will increase. If V OUT The voltage at 260 needs to be reduced, so the V of transistor 230... GS It will decrease. Decrease the V of transistor 230. GS This reduces the current flowing through resistor 252, thereby lowering V. OUT Voltage at 260.

[0030] The first current source ISENSE 262 is coupled to V DD Between 202 and the first terminal of resistor 266. The second current source IREF 264 is coupled to V. DD Between the first terminals of resistors 202 and 268. The second terminals of resistors 266 and 268 are coupled to ground. Amplifier 270 has a first terminal coupled to resistor 266 and a second terminal coupled to resistor 268. The output of amplifier 270 is coupled to the gate of transistor 274. Transistor 274 is coupled to V. DD Between the inputs of 202 and buffer amplifier 220.

[0031] Current source ISENSE 262 supplies current through resistor 266. The voltage drop across resistor 266 is proportional to the current through transistor 230 and is the first input of amplifier 270. Current source ISENSE 264 supplies current through resistor 268. The voltage drop across resistor 268 is proportional to a current-limiting threshold and is the second input of amplifier 270. The output of amplifier 270 is a signal proportional to the difference between the current through transistor 230 and the current-limiting threshold.

[0032] If the current through transistor 230 exceeds the current limiting threshold, the output of amplifier 270 pulls down the gate of transistor 274, thereby pulling up the input of buffer amplifier 220. The output of buffer amplifier 220 goes low, driving the gate of transistor 230 high, thereby turning off transistor 230.

[0033] Conversely, if V DD If the voltage at point 202 drops below the undervoltage, then V OUT The voltage at 260 will drop, and the voltage regulator 200 will enter an undervoltage condition. When an undervoltage condition occurs, the error amplifier 210 will be driven to ground, thereby driving the gate of transistor 230 to ground. When V DDWhen the voltage at 202 recovers, a large current flows through transistor 230, and the current limiting circuit will become active to reduce the current through transistor 230.

[0034] The current-limiting circuit of the voltage regulator 200 can reduce overshoot, but it is not a complete solution. Due to the bandwidth limitation of the circuit, if V DD If the voltage drop at point 202 is rapid (which can occur under fast transient or undervoltage conditions), the overshoot problem will be exacerbated. The current-limiting control loop cannot react to line voltage transients with a bandwidth that is faster than the comparison loop, leading to saturation of the error amplifier.

[0035] Figure 3 A schematic diagram of a voltage regulator 300 with an undervoltage sensing circuit is shown. The undervoltage sensing circuit of the voltage regulator 300 operates in a manner similar to the current-limiting loop of the voltage regulator 200. The main difference between the two circuits is that the undervoltage sensing circuit uses V... DD and V OUT The voltage difference between the two voltages is compared to a reference voltage, rather than comparing the current sensed by the transistor to a reference current.

[0036] The input of voltage regulator 300 is V DD 302. The output of voltage regulator 300 is V. OUT 360. Resistors 342 and 346 are coupled in series at V. OUT Between 360 and ground, and for V OUT The voltage at 360° is divided to provide a feedback voltage for voltage regulation. Feedback voltage terminal V FB 344 is coupled to the first input of error amplifier 310. The second input of error amplifier 310 is coupled to the reference voltage terminal V. REF 304.

[0037] The output of error amplifier 310 is coupled to the input of buffer amplifier 320. The output of buffer amplifier 320 is coupled to the gate of transistor 330. The source of transistor 330 is coupled to V. DD 302. The drain of transistor 330 is coupled to the output V of voltage regulator 300. OUT 360. The load 350 includes parallel coupling in V OUT Resistor 352 and capacitor 354 between 360 and ground.

[0038] Resistors 342 and 346 form the output voltage V OUT A 360° voltage divider that provides feedback voltage V FB 344. Use comparator 310 to convert V FB 344 and reference voltage VREF Compare with 304. V REF The value of 304 is chosen to be equal to V. OUT V at a specified voltage (360°) FB The value is 344. The output of error amplifier 310 indicates the output voltage V. OUT 360 is higher or lower than the specified voltage. The output of buffer amplifier 320 responds to the output of error amplifier 310 to drive the gate of transistor 330. If V OUT If the voltage at position 360 needs to be increased, then the V of transistor 330... GS It will increase. If V OUT If the voltage at 360° needs to be reduced, then the V of transistor 330... GS It will decrease. It will decrease the V of transistor 330. GS This reduces the current flowing through resistor 352, thereby lowering V. OUT Voltage at 360 degrees.

[0039] Transistors 362 and 366 are coupled in series at V DD Between 302 and ground. Transistor 362 is a p-channel field-effect transistor (PFET) whose source is coupled to V. DD 302, and its gate is coupled to the output of buffer amplifier 320 and the gate of transistor 330. Transistor 366 is an n-channel field-effect transistor (NFET), whose drain is coupled to the drain of transistor 362 and whose source is coupled to ground. Transistor 368 is an NFET, whose source is coupled to ground and whose gate is coupled to the gate and drain of transistor 366.

[0040] Resistor 364 is coupled to the drain of transistor 368 and V. DD Between 302. Comparator 370 has a first input coupled to the drain of transistor 368, and has a first input coupled to V. OUT The second input of 360. The output 372 of comparator 370 is coupled to the gate of transistor 374 and provides a signal with respect to V. OUT The signal is proportional to the difference between the voltage at point 360 and the voltage at the drain of transistor 368. Transistor 374 is coupled to V. DD Between the inputs of 302 and buffer amplifier 320.

[0041] Transistor 362 senses the current flowing through transistor 330, which is the current supplied to load 350. The voltage drop across resistor 364 is a reference undervoltage, which is a function of the load current. The voltage drop across resistor 364 is compared to the voltage drop across transistor 330, which is V. DD 302 and V OUTThe voltage difference between 360 degrees. If V DD 302 and V OUT If the voltage difference between 360 is less than the reference voltage, the output 372 of comparator 370 will turn on transistor 374, thereby pulling up the input of buffer amplifier 320.

[0042] When the input of buffer amplifier 320 is pulled up, the voltage at the gate of transistor 330 increases, thereby reducing the Vt of transistor 330. GS This limits the current flowing through transistor 330. Because the current is limited, V DD 302 and V OUT The voltage difference between 360° will remain above the reference value. However, if very fast line transients occur, the circuit may be unable to maintain voltage regulation due to bandwidth limitations. If the line transients exceed the circuit's bandwidth, the circuit may be unable to prevent V... OUT Voltage loss on 360.

[0043] Figure 4 A block diagram of an exemplary comparator-based overshoot suppression circuit 400 in a voltage regulator is shown. The overshoot suppression circuit 400 utilizes two comparators instead of current and voltage feedback loops, which continuously monitor two corresponding fault conditions. The outputs of the two comparators are logically ORed together, allowing the circuit to respond appropriately if either fault condition is detected. The first comparator will output V... DD It is compared with a reference undervoltage voltage, and the second comparator will V DD With V OUT Compare them.

[0044] First offset voltage circuit V OS1 474 has coupling to V DD The input of 402 is coupled to the output of the first input of comparator 1480. The second input of comparator 1480 is coupled to the reference voltage terminal 404. The second offset voltage circuit V... OS2 476 has coupling to V DD The input of 402 is coupled to the output of the first input of comparator 2 482. The second input of comparator 2 482 is coupled to the output voltage terminal V. OUT 460. The output of comparator 1 480 is coupled to the first input of OR gate 484. The output of comparator 2 482 is coupled to the second input of OR gate 484.

[0045] The output of OR gate 484 is coupled to the input of transistor turn-off circuit 486. The output of transistor turn-off circuit 486 is coupled to the control terminal of regulator transmission transistor (e.g., 230). When the output of OR gate 484 goes high, the output of transistor turn-off circuit 486 goes high, turning off the regulator transmission transistor. The output of OR gate 484 is also coupled to the input of one-shot falling edge detector 488. After the output of OR gate 484 goes high, one-shot falling edge detector 488 monitors for a falling edge on the output of OR gate 484. A falling edge on the output of OR gate 484 indicates that the fault condition that caused it to go high has ceased. In response to detecting a falling edge on the output of OR gate 484, the output of one-shot falling edge detector 488 signals pulse generator circuit 490. Pulse generator circuit 490 sends a pulse to the input of reference discharge circuit 492, thereby triggering the discharge of the reference voltage. When the reference voltage is discharged, a signal is sent to regulator startup circuit 494, which initiates a reset and restart of the voltage regulator.

[0046] First offset voltage V OS1 474 was added to V DD 402, and this sum is provided as the first input to comparator 1480. Comparator 1480 will input V DD 402 plus V OS1 The sum of 474 and the reference voltage V REF 404 is compared, and if the reference voltage V REF 404 is greater than V DD 402 and V OS1 The sum of 474 provides a high signal at the output of comparator 1.

[0047] Second offset voltage V OS2 476 was added to V DD 402, and this sum is provided as the first input to comparator 2482. Comparator 2482 will convert V... DD 402 plus V OS2 476 and output voltage V OUT Compare 460, and if V OUT 460 is greater than V DD 402 and V OS2 The sum of 476 provides a high signal at the output of comparator 2.

[0048] Comparator 1 480 and comparator 2 482 each have an input to V DD The offset voltage of 402 is used as the first input, but these two offset voltages are different. V OS1 474 is higher than V OS2A lower voltage of 476 is used to avoid affecting circuit operation during normal operating conditions. If V DD -V REF Less than V OS1 If V DD -V OUT Less than V OS2 If either comparator 1 (480) or comparator 2 (482) is high, then the output of comparator 2 (482) will be high. The outputs of comparator 1 (480) and comparator 2 (482) are coupled to the input of OR gate 484. If the output of either comparator 1 (480) or comparator 2 (482) is high, then the output of OR gate 484 will be high.

[0049] Comparator 1480 can detect when the reference voltage V REF 404 is filtered by a large capacitor and V DD A voltage drop at point 402 sometimes occurs. In this case, the reference voltage V drops due to residual charge on the capacitor. REF 404 will not be fully pulled down to V DD The value of 402, and the reference voltage V REF 404 will remain above V DD 402. In this case, V DD 402 is in a position relative to V OUT 460 higher voltage. Therefore, when V DD When the voltage at point 402 recovers, the voltage regulator may enter an undervoltage condition. Comparator 1480 monitors V. DD 402 and V REF The voltage difference between 404. If V DD The voltage drops at 402 and V DD -V REF Less than V OS1 If so, the output of comparator 1 will go high.

[0050] The comparator 2 circuit functions similarly to a conventional undervoltage current limiting circuit by detecting and reporting conditions indicating overcurrent. The advantage of the comparator 2 circuit is that, in many cases, the comparator 2 482 responds to conditions faster than a conventional undervoltage limiting circuit because it operates as an open-loop circuit rather than a feedback circuit. In many conventional circuits, if V... DD -V OUT If the voltage exceeds the undervoltage limit VDO, the undervoltage circuit system reduces the Vtransfer across the transfer transistor. GS This reduces the current flowing through the transfer transistor. A similar result occurs in circuit 400, but instead, the transfer transistor is turned off, thus stopping the current flow through it. If V DD -V OUT Higher than V OS2If 476 is triggered, the output of OR gate 484 goes high, which triggers the transistor turn-off circuit to provide a high signal to the control terminal of the transmission transistor, thereby turning off the transmission transistor.

[0051] If V DD -V REF Less than V OS1 Then the output of comparator 1480 will be high. As long as V... DD -V OUT Greater than V OS2 Then the output of comparator 2 will remain low. Due to capacitor filtering V... REF The residual charge on it, therefore V REF Voltage changes in V may lag behind V by a certain delay. DD The voltage change in V. However, V OUT The voltage at the point follows V DD The voltage at the point is present without delay. If the output of comparator 1 drops low, the output of OR gate 484 goes low, causing the output of transistor turn-off circuit 486 to go low. This turns on the transfer transistor, thereby allowing V... DD Restored to its nominal voltage.

[0052] If the single-triggered falling edge detector circuit 488, pulse generator 490, and reference discharge circuit 492 are not included in the circuit, then due to V REF and V DD The hysteresis between the voltage drops may cause overshoot after voltage loss. A single-triggered falling edge detector circuit 488 detects the falling edge of the OR gate output and sends a signal to the pulse generator 490 to notify of the falling edge. The pulse generator 490 provides a pulse to the input of the reference discharge circuit 492, thereby triggering the discharge of the reference voltage. When the reference voltage is discharged, a signal is sent to the regulator startup circuit 494, which initiates a restart of the voltage regulator, thus avoiding overshoot conditions.

[0053] Figure 5 A schematic diagram 500 illustrates an exemplary comparator-based overshoot suppression circuit in a voltage regulator. The input voltage of the voltage regulator is V. DD 402. The output voltage of the voltage regulator is V. OUT 460. Feedback voltage terminal 444 is coupled to the first input of error amplifier 410. Voltage reference generator circuit 403 provides a reference voltage at its output, which is compared with the feedback voltage from the voltage regulator. Voltage reference generator circuit 403 has a coupling to V DD The input of 402 is coupled to the reference voltage terminal V. REF The output of 404. The reference voltage filter circuit 405 is coupled to the reference voltage terminal V. REFBetween 404 and ground. The reference voltage filter circuit 405 filters noise from the reference voltage signal. The first input of the error amplifier 410 is coupled to the reference voltage terminal V. REF 404. Feedback voltage terminal 444 is coupled to the second input of error amplifier 410.

[0054] The output of error amplifier 410 is coupled to the input of buffer amplifier 420. The output of buffer amplifier 420 is coupled to the gate of transfer transistor 430. The source of transfer transistor 430 is coupled to V. DD 402. The drain of the transfer transistor 430 is coupled to V. OUT 460. The load 450 includes parallel coupling at V OUT Resistor 452 and capacitor 454 between 460 and ground.

[0055] First offset voltage circuit V OS1 474 has coupling to V DD The input of 402 is coupled to the output of the first input of comparator 1480. The second input of comparator 1480 is coupled to the reference voltage terminal V. REF 404. Second offset voltage circuit V OS2 476 has coupling to V DD The input of 402 is coupled to the output of the first input of comparator 2 482. The second input of comparator 2 482 is coupled to the output voltage terminal V. OUT 460. The output of comparator 1 480 is coupled to the first input of OR gate 484. The output of comparator 2 482 is coupled to the second input of OR gate 484.

[0056] The output of OR gate 484 is coupled to the input of transistor turn-off circuit 486. In one example, transistor turn-off circuit 486 includes an OR gate. The output of transistor turn-off circuit 486, PASSFET_OFF, is coupled to the control terminals of transistors 474 and 475. Transistors 474 and 475 provide a first turn-off level and a second turn-off level for transmission transistor 430, but in some exemplary circuits, transistor 474 or transistor 475 may be omitted.

[0057] When the output of OR gate 484 goes high, the output of transistor turn-off circuit 486 goes high, which turns off transmission transistor 430. The output of OR gate 484 is also coupled to the input of single-triggered falling edge detector 488. In response to the output of OR gate 484 going high, single-triggered falling edge detector 488 continuously monitors the falling edge of the output of OR gate 484. A falling edge on the output of OR gate 484 indicates that the fault condition that caused it to go high has stopped. In response to detecting a falling edge on the output of OR gate 484, the output of single-triggered falling edge detector 488 provides a signal to pulse generator circuit 490. Pulse generator circuit 490 is coupled to the input of reference discharge circuit 492 and sends a signal to trigger the discharge of the reference voltage. Reference discharge circuit 492 is coupled to the input of regulator startup circuit 494 and sends a signal to regulator startup circuit 494, which initiates the reset and restart of the voltage regulator.

[0058] First offset voltage V OS1 474 was added to V DD 402, and this sum is provided as the first input to comparator 1480. Comparator 1480 will input V DD 402 plus V OS1 474 and reference voltage V REF 404 is compared, and if the reference voltage V REF 404 is greater than V DD 402 and V OS1 The sum of 474 provides a high signal at the output of comparator 1.

[0059] Second offset voltage V OS2 476 was added to V DD 402, and this sum is provided as the first input to comparator 2482. Comparator 2482 will convert V... DD 402 plus V OS2 476 and output voltage V OUT Compare 460, and if V OUT 460 is greater than V DD 402 and V OS2 The sum of 476 provides a high signal at the output of comparator 2.

[0060] Comparator 1 480 and comparator 2 482 each have an input to V DD The offset voltage of 402 is used as the first input, but these two offset voltages are different. V OS1 474 is higher than V OS2 A lower voltage of 476 is used to avoid affecting circuit operation during normal operating conditions. If V DD -V REF Less than V OS1If V DD -V OUT Less than V OS2 If either comparator 1 (480) or comparator 2 (482) is high, then the output of comparator 2 (482) will be high. The outputs of comparator 1 (480) and comparator 2 (482) are coupled to the input of OR gate 484. If the output of either comparator 1 (480) or comparator 2 (482) is high, then the output of OR gate 484 will be high.

[0061] Comparator 1480 can detect when the reference voltage V REF 404 is filtered by a large capacitor and V DD A voltage drop at point 402 sometimes occurs. This is due to residual charge on the capacitor, affecting the reference voltage V. REF 404 will not be fully pulled down to V DD The value of 402, and the reference voltage V REF 404 remains above V DD 402. In this case, V DD 402 is in a position relative to V OUT 460 higher voltage. Therefore, when V DD When the voltage at point 402 recovers, the voltage regulator can enter the undervoltage condition. Comparator 1480 monitors V. DD 402 and V REF The voltage difference between 404. If V DD The voltage drops at 402 and V DD -V REF Become less than V OS1 If V DD -V OUT Higher than V OS2 If 476 is triggered, the output of OR gate 484 goes high, which triggers the transistor turn-off circuit to provide a high signal to the control terminal of the transmission transistor, thereby turning off the transmission transistor.

[0062] If V DD -V REF Less than V OS1 Then the output of comparator 1480 will be high. As long as V... DD -V OUT Greater than V OS2 The output of comparator 2 remains low. Due to capacitor filtering, V... REF The residual charge on it, therefore V REF Voltage changes in V may lag behind V by a certain delay. DD The voltage change in V. However, V OUT The voltage at the point follows V DDThe voltage at the point is present without delay. If the output of comparator 1 drops low, the output of OR gate 484 goes low, causing the output of transistor turn-off circuit 486 to go low. This turns on the transfer transistor, thereby allowing V... DD Restored to its nominal voltage.

[0063] Figure 6 A flowchart 600 illustrates an exemplary method for implementing a comparator-based overshoot suppression circuit in a voltage regulator. In step 610, the power supply V of the voltage regulator circuit... DD It is enabled, and its voltage ramp rises to a specified value. In step 620, the voltage regulator is enabled, and the voltage from V... DD The power is applied as the input to the regulator. In step 630, the reference voltage generation circuit draws power from V... DD It receives power and begins charging to its specified value. A reference voltage V is provided at the reference voltage terminal inside the voltage regulator. REF The regulated output voltage V OUT The ramp rises to its specified value and is available at the output voltage terminal. Step 640 is normal operation of the voltage regulator, where the regulator input voltage V... DD and regulator output voltage V OUT Stay within the specified limits.

[0064] In step 650, for an unspecified reason, the regulator input voltage V... DD It begins to decrease. This is in response to the regulator input voltage V. DD If the value drops below a specified value, in step 660, a check is performed for either of two conditions that could lead to circuit failure. If V DD -V OUT <V OS1 or V DD -V REF <V OS2 If true, the process proceeds to step 670. Each of these two relationships can be checked using the corresponding comparator, and the outputs of the two comparators are logically ORed together, such that if either statement is true, the OR gate's true output will be triggered. If both are false, the voltage regulator remains in step 660 and continues to check either of the two conditions.

[0065] In step 670, the transfer transistor is turned off to stop current flow through the load. In step 680, the falling edge of the OR gate output is continuously monitored. The transfer transistor remains off as long as no falling edge is detected in step 680. In response to the detection of a falling edge in step 680, the reference voltage V... REF and output voltage V OUTEach component discharges in step 690. The voltage regulator is then reset / restarted, and the process returns to step 620.

[0066] In this specification, the terms “terminal,” “node,” “interconnect,” “lead,” and “pin” are used interchangeably. Unless specifically stated otherwise, these terms generally refer to interconnections or terminations between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0067] In this specification, “grounding” includes rack grounding, ground grounding, floating grounding, virtual grounding, digital grounding, common grounding and / or any other form of grounding connection that is applicable to or suitable for the teachings of this specification.

[0068] In this specification, even if operations are described in a particular order, some operations may be optional and are not necessarily required to be performed in that particular order to achieve the specified result. In some examples, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system components in the above embodiments does not necessarily require such separation in all embodiments.

[0069] Modifications to the described embodiments are possible within the scope of the claims, and other embodiments are also possible.

Claims

1. A circuit for suppressing overshoot in a voltage regulator, the circuit comprising: A first offset voltage circuit has a first offset input and a first offset output, wherein the first offset input is coupled to an input voltage terminal; A second offset voltage circuit has a second offset input and a second offset output, the second offset input being coupled to the input voltage terminal; A first comparator has a first comparator input, a second comparator input, and a first comparator output, the first comparator input being coupled to the first offset output, and the second comparator input being coupled to a reference voltage terminal. A second comparator has a third comparator input, a fourth comparator input, and a second comparator output, the third comparator input being coupled to the second offset output, and the fourth comparator input being coupled to the voltage regulator output; An OR gate having a first logic input, a second logic input, and a logic output, wherein the first logic input is coupled to the first comparator output, and the second logic input is coupled to the second comparator output; as well as A shutdown circuit having a shutdown input and a shutdown output, the shutdown input being coupled to the logic output, and the shutdown circuit being configured to provide a shutdown signal at the shutdown output to stop the flow of current from the voltage regulator output in response to a logic high at the shutdown input.

2. The circuit of claim 1, further comprising a falling edge detection circuit having a falling edge circuit input and a falling edge circuit output, the falling edge circuit input being coupled to the logic output, and the falling edge detection circuit being configured to provide a falling edge signal at the falling edge circuit output in response to a falling edge of the signal at the falling edge circuit input.

3. The circuit of claim 2, further comprising a pulse generating circuit having a pulse circuit input and a pulse circuit output, the pulse circuit input being coupled to the falling edge circuit output, and the pulse generating circuit being configured to provide a pulse signal at the pulse circuit output in response to the falling edge signal.

4. The circuit according to claim 3, further comprising: A reference discharge circuit has a reference discharge input and a reference discharge output, the reference discharge input being coupled to the output of the pulse circuit, and the reference discharge circuit being configured to provide a discharge signal at the reference discharge output in response to the pulse signal. as well as A startup circuit having a startup input and a startup output, the startup input being coupled to the output of the pulse circuit, and the startup circuit being configured to provide a startup signal at the startup output in response to a pulse signal at the startup input.

5. The circuit according to claim 2, wherein the falling edge circuit output is coupled to the control terminal of the transistor.

6. The circuit of claim 4, wherein the start signal is configured to trigger a restart of the voltage regulator.

7. The circuit of claim 1, wherein the voltage at the first offset output is lower than the voltage at the second offset output.

8. The circuit of claim 1, wherein the reference voltage terminal is coupled to a bandgap reference circuit.

9. The circuit of claim 4, wherein the voltage at the input of the second comparator is grounded in response to the discharge signal.

10. A voltage regulator circuit, comprising: A reference generation circuit having a reference input and a reference output, the reference input being coupled to an input voltage terminal; A first amplifier has a first amplifier input, a second amplifier input, and a first amplifier output, the first amplifier input being coupled to the reference output, and the second amplifier input being coupled to an output voltage terminal; A second amplifier has a third amplifier input and a second amplifier output, the third amplifier input being coupled to the first amplifier output; A first transistor is coupled between the input voltage terminal and the output of the first amplifier, and has a first control terminal; A second transistor is coupled between the input voltage terminal and the output voltage terminal, and has a second control terminal coupled to the output of the second amplifier; A first offset voltage circuit has a first offset input and a first offset output, wherein the first offset input is coupled to the input voltage terminal; A second offset voltage circuit has a second offset input and a second offset output, the second offset input being coupled to the input voltage terminal; A first comparator has a first comparator input, a second comparator input, and a first comparator output, the first comparator input being coupled to the first offset output, and the second comparator input being coupled to the reference output; A second comparator has a third comparator input, a fourth comparator input, and a second comparator output, the third comparator input being coupled to the second offset output, and the fourth comparator input being coupled to the output voltage terminal; An OR gate having a first logic input, a second logic input, and a logic output, wherein the first logic input is coupled to the first comparator output, and the second logic input is coupled to the second comparator output; as well as A shutdown circuit having a shutdown input and a shutdown output, the shutdown input being coupled to the logic output, and the shutdown circuit being configured to provide a shutdown signal at the first control terminal in response to a logic high at the shutdown input.

11. The voltage regulator circuit of claim 10, wherein the reference generation circuit includes a filter coupled between the reference output and the ground terminal.

12. The voltage regulator circuit of claim 10, further comprising a falling edge detection circuit having a falling edge circuit input and a falling edge circuit output, the falling edge circuit input being coupled to the logic output, and the falling edge detection circuit being configured to provide a falling edge signal at the falling edge circuit output in response to a falling edge of the signal at the falling edge circuit input.

13. The voltage regulator circuit of claim 12, further comprising a pulse generating circuit having a pulse circuit input and a pulse circuit output, the pulse circuit input being coupled to the falling edge circuit output, and the pulse generating circuit being configured to provide a pulse signal at the pulse circuit output in response to the falling edge signal.

14. The voltage regulator circuit according to claim 13, further comprising: A reference discharge circuit has a reference discharge input and a reference discharge output, the reference discharge input being coupled to the output of the pulse circuit, the reference discharge output being coupled to the reference generation circuit, and the reference discharge circuit being configured to provide a discharge signal at the reference discharge output in response to the pulse signal. as well as A startup circuit having a startup input and a startup output, the startup input being coupled to the output of the pulse circuit, and the startup circuit being configured to provide a startup signal at the startup output in response to a pulse signal at the startup input.

15. The voltage regulator circuit of claim 14, wherein the start signal is configured to trigger a restart of the voltage regulator circuit.

16. The voltage regulator circuit of claim 10, wherein the voltage at the first offset output is lower than the voltage at the second offset output.

17. The voltage regulator circuit of claim 10, wherein the reference generation circuit includes a bandgap reference circuit.

18. The voltage regulator circuit of claim 14, wherein the voltage at the reference output is grounded in response to the discharge signal.

19. A method for suppressing overshoot in a voltage regulator, the method comprising: Supply the input voltage to the voltage regulator and enable the voltage regulator output; A reference voltage is generated at the reference voltage output; The output voltage is adjusted by comparing the reference voltage with a feedback voltage that is proportional to the output voltage at the output of the voltage regulator; The first offset voltage is compared with the difference between the input voltage and the output voltage, and the second offset voltage is compared with the difference between the input voltage and the reference voltage; as well as In response to the first offset voltage being greater than the difference between the input voltage and the output voltage, or the second offset voltage being greater than the difference between the input voltage and the reference voltage, the voltage regulator output is disabled.

20. The method of claim 19, further comprising: In response to the first offset voltage no longer being greater than the difference between the input voltage and the output voltage, and the second offset voltage no longer being greater than the difference between the input voltage and the reference voltage, the output voltage and the reference voltage are discharged.

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