Field-effect transistors and their manufacturing methods

Abstract

A field-effect transistor includes: a semiconductor substrate (12) having a plurality of trenches (20) on its upper surface; and a gate electrode (24) disposed within the trenches. A plurality of withstand voltage regions (48) are provided within a range (28) between each trench. The plurality of withstand voltage regions are configured to form a plurality of columns (49) extending along a first direction intersecting the plurality of trenches. The plurality of columns are spaced apart in a second direction parallel to the trenches. Each withstand voltage region extends from above the lower end of each trench to below the lower end of each trench, and is spaced apart from each gate insulating film (22). A drift region is located between each withstand voltage region and each gate insulating film and is in contact with the gate insulating film.

Description

Technical Field

[0001] (Mutual references between related applications)

[0002] This application is an associated application of Japanese Patent Application No. 2021-098031, filed on June 11, 2021, and claims priority based on that Japanese patent application, the entire contents of which are incorporated herein by reference.

[0003] The technology disclosed in this specification relates to field-effect transistors. Background Technology

[0004] The field-effect transistor disclosed in Japanese Patent Application Publication No. 2009-194065 (hereinafter referred to as Patent Document 1) has multiple p-type deep layers protruding downward from the body region. Each deep layer extends in a direction intersecting with each trench. The deep layers are spaced apart in a direction parallel to each trench. Each deep layer extends from a position above the lower end of each trench to a position below the lower end of each trench. According to this structure, the depletion layer extends from each deep layer to the drift region, thereby suppressing electric field concentration at the lower end of each trench. As a result, the gate insulating film can be protected against electric field at the lower end of each trench. Summary of the Invention

[0005] In the field-effect transistor of Patent Document 1, each deep layer is connected to the sidewall of the trench (i.e., the gate insulating film) on the lower side of the body region. Therefore, electrons that have passed through the channel formed in the body region cannot flow from the body region into the deeper layers below it. That is, electrons bypass the deeper layers and flow towards the drift region. Therefore, the field-effect transistor of Patent Document 1 has the problem of high on-state voltage. In this specification, a field-effect transistor is proposed that can suppress electric field concentration at the lower end of the trench and reduce the on-state voltage.

[0006] The field-effect transistor disclosed in this specification includes: a semiconductor substrate having a plurality of trenches on its upper surface; a gate insulating film covering the inner surface of the trenches; and a gate electrode disposed within the trenches and insulated from the semiconductor substrate by the gate insulating film. The semiconductor substrate has a plurality of n-type source regions, a p-type body region, an n-type drift region, and a plurality of p-type breakdown regions. Each region in the semiconductor substrate located between the plurality of trenches is a trench-interval region. The plurality of source regions are respectively disposed within their respective trench-interval regions and are in contact with their respective gate insulating films. The body regions extend across each trench-interval region and are in contact with each gate insulating film below the source regions within each trench-interval region. The drift regions are distributed from each trench-interval region across a region lower than each trench and are in contact with each gate insulating film below the body regions. The plurality of breakdown regions are disposed within each trench-interval region. The plurality of voltage-resistant regions are configured to form a plurality of columns extending along a first direction intersecting the plurality of trenches. Within each column, the plurality of voltage-resistant regions are spaced apart in the first direction. The plurality of columns are spaced apart in a second direction parallel to the trenches. Each voltage-resistant region has a higher p-type impurity concentration than the body region, extends from above the lower end of each trench to below the lower end of each trench, and is spaced apart from each gate insulating film. The drift region is in contact with the gate insulating film at the position between each voltage-resistant region and each gate insulating film.

[0007] In this field-effect transistor, the p-type breakdown regions extend from above the lower end of each trench to below the lower end of each trench at locations spaced apart from the gate insulating films. When the field-effect transistor is turned off, the depletion layer extends from each breakdown region to the drift region. Although the breakdown regions are positioned at locations spaced apart from each gate insulating film, the depletion layer can extend from each breakdown region to the periphery of the lower end of the trench due to the high p-type impurity concentration in each breakdown region. Therefore, electric field concentration at the lower end of each trench is suppressed, and the gate insulating film is protected against the electric field. Furthermore, in this field-effect transistor, the drift region is in contact with the gate insulating film at the location between each breakdown region and each gate insulating film. Therefore, when the field-effect transistor is turned on, electrons that have passed through the channels formed in the bulk region can flow to the drift region without being hindered by the breakdown regions. Therefore, this field-effect transistor has a low on-resistance. Attached Figure Description

[0008] Figure 1 This is a top view of the MOSFET implementation (the source electrode and interlayer insulating film are omitted).

[0009] Figure 2 yes Figure 1 , Figure 4 , Figure 5 A sectional view along line II-II.

[0010] Figure 3 yes Figure 1 , Figure 4 , Figure 5 A sectional view along line III-III.

[0011] Figure 4 yes Figures 1-3 A cross-sectional view along line IV-IV.

[0012] Figure 5 yes Figures 1-3 A cross-sectional view of the V-V line.

[0013] Figure 6 It means Figure 2 A diagram showing the distribution of equipotential lines in a cross-section.

[0014] Figure 7 This is an illustrative diagram of the MOSFET manufacturing process (a top view of the semiconductor substrate viewed from above).

[0015] Figure 8 This is an illustrative diagram of the MOSFET manufacturing process (and...) Figure 2 (Cross-sectional view of the corresponding part).

[0016] Figure 9 This is an illustrative diagram of the MOSFET manufacturing process (and...) Figure 2 (Cross-sectional view of the corresponding part).

[0017] Figure 10 This is an illustrative diagram of the MOSFET manufacturing process (and...) Figure 2 (Cross-sectional view of the corresponding part).

[0018] Figure 11 This is an illustrative diagram of the MOSFET manufacturing process (and...) Figure 2 (Cross-sectional view of the corresponding part).

[0019] Figure 12 This is an illustrative diagram of the MOSFET manufacturing process (and...) Figure 2 (Cross-sectional view of the corresponding part).

[0020] Figure 13 This is an illustrative diagram illustrating a variation of the MOSFET manufacturing method (with...). Figure 2 (Cross-sectional view of the corresponding part).

[0021] Figure 14 This is an illustrative diagram illustrating a variation of the MOSFET manufacturing method (with...). Figure 2(Cross-sectional view of the corresponding part).

[0022] Figure 15 This is an illustrative diagram illustrating a variation of the MOSFET manufacturing method (with...). Figure 2 (Cross-sectional view of the corresponding part).

[0023] Figure 16 The MOSFET of variation 1 and Figure 2 Corresponding sectional view (and) Figure 2 (Cross-sectional view of the corresponding part).

[0024] Figure 17 The MOSFET of variation 2 and Figure 2 Corresponding sectional view (and) Figure 2 (Cross-sectional view of the corresponding part).

[0025] Figure 18 The MOSFET of variation 3 and Figure 2 Corresponding sectional view (and) Figure 2 (Cross-sectional view of the corresponding part). Detailed Implementation

[0026] The field-effect transistor disclosed in this specification may further have multiple p-type bottom regions. Each of the aforementioned bottom regions may have a lower p-type impurity concentration than each of the aforementioned breakdown voltage regions. Each of the aforementioned bottom regions may be connected to the gate insulating film at the lower end of the corresponding trench and are spaced apart from each of the aforementioned breakdown voltage regions.

[0027] According to this structure, the electric field concentration at the lower end of the trench can be suppressed more effectively through the bottom region.

[0028] In one example of a field-effect transistor disclosed in this specification, the drift region may have a low-concentration region and a high-concentration region with a higher n-type impurity concentration than the low-concentration region. The high-concentration region may be distributed from a position adjacent to the body region to a position lower than the lower end of each trench, and may be adjacent to each gate insulating film at a position between each breakdown voltage region and each gate insulating film. Alternatively, the low-concentration region may be adjacent to the high-concentration region from below.

[0029] This specification provides a method for manufacturing a field-effect transistor according to any of the above claims. The manufacturing method may include: a step of forming a mask extending in a lattice pattern on the upper surface of the semiconductor substrate; and a step of implanting p-type impurities into the semiconductor substrate through the mask to form a plurality of the aforementioned voltage-resistant regions within the semiconductor substrate.

[0030] According to this structure, since the mask is formed in a lattice shape, it can be formed stably. That is, local mask collapse can be suppressed. Therefore, field-effect transistors can be manufactured appropriately.

[0031] The manufacturing method disclosed in this specification may further include: a step of forming a trench on the upper surface of the semiconductor substrate; and a step of implanting p-type impurities into the upper surface of the semiconductor substrate and the bottom surface of the trench to form the body region and the bottom region.

[0032] According to this manufacturing method, the body region and the bottom region can be formed simultaneously.

[0033] Example

[0034] Figures 1-5 The MOSFET 10 (metal oxide semiconductor field effect transistor) of the embodiment is shown. The MOSFET 10 has a semiconductor substrate 12. Hereinafter, the thickness direction of the semiconductor substrate 12 is referred to as the z-direction, the direction orthogonal to the z-direction is referred to as the x-direction, and the direction orthogonal to both the z-direction and the x-direction is referred to as the y-direction. The x-direction and the y-direction are parallel to the upper surface 12a and the lower surface 12b of the semiconductor substrate 12.

[0035] like Figures 1-3 As shown, a plurality of trenches 20 are provided on the upper surface 12a of the semiconductor substrate 12. For example... Figure 1 As shown, each trench 20 extends in a straight line in the y-direction. The multiple trenches 20 are spaced apart in the x-direction. Hereinafter, the area within the semiconductor substrate 12 sandwiched by the multiple trenches 20 is referred to as the trench-to-trench range 28.

[0036] The inner surface of each trench 20 is covered by a gate insulating film 22. A gate electrode 24 is disposed in each trench 20. Each gate electrode 24 is insulated from the semiconductor substrate 12 by the gate insulating film 22. The upper surface of each gate electrode 24 is covered by an interlayer insulating film 26.

[0037] like Figures 2-5 As shown, a source electrode 30 is disposed on the upper surface 12a of the semiconductor substrate 12. The source electrode 30 covers the interlayer insulating film 26 and the upper surface 12a of the semiconductor substrate 12. The source electrode 30 is in contact with the upper surface 12a of the semiconductor substrate 12 where the interlayer insulating film 26 is not present. The source electrode 30 is insulated from the gate electrode 24 by the interlayer insulating film 26.

[0038] A drain electrode 32 is disposed on the lower surface 12b of the semiconductor substrate 12. The drain electrode 32 is in contact with approximately the entire area of ​​the lower surface 12b of the semiconductor substrate 12.

[0039] like Figures 1-5 As shown, the semiconductor substrate 12 has multiple source regions 40, body regions 42, drift regions 44, drain regions 46, multiple breakdown voltage regions 48, and multiple bottom regions 50.

[0040] like Figures 1-3 As shown, each source region 40 is an n-type region with a relatively high n-type impurity concentration. Each source region 40 is disposed within a corresponding trench interval 28. Two source regions 40 are disposed within each trench interval 28. Each source region 40 is disposed adjacent to its corresponding trench 20. Figure 1 As shown, each source region 40 extends relatively long along the trench 20 in the y-direction. Figure 2 , Figure 3 As shown, each source region 40 is connected to the gate insulating film 22 at the upper end of the corresponding trench 20. Each source region 40 is in ohmic contact with the source electrode 30.

[0041] Region 42 is a p-type region. For example... Figure 2 , Figure 3 As shown, the body region 42 extends across multiple trench regions 28. The body region 42 has multiple contact regions 42a and low-concentration regions 42b. Each contact region 42a has a higher p-type impurity concentration than the low-concentration regions 42b. Each contact region 42a is disposed between two source regions 40 within its corresponding trench region 28. Each contact region 42a has a 0-ohm contact with the source electrode 30. Figure 1 As shown, each contact area 42a extends relatively long in the y-direction along the groove 20. For example... Figure 2 , Figure 3 As shown, the low-concentration region 42b is distributed across multiple trench regions 28. Within each trench region 28, the low-concentration region 42b is connected from below to the contact region 42a and the source region 40. The low-concentration region 42b is connected to the gate insulating film 22 on the lower side of each source region 40.

[0042] Drift region 44 is an n-type region with a lower n-type impurity concentration than source region 40. For example... Figure 2 , Figure 3As shown, drift region 44 is connected to body region 42 (more specifically, low-concentration region 42b) from below. Drift region 44 is connected to gate insulating film 22 below body region 42. Drift region 44 is separated from source region 40 by body region 42. Drift region 44 is distributed from the trench interval 28 to a range lower than each trench 20. In the range lower than each trench 20, drift region 44 is distributed laterally wider. Drift region 44 has high-concentration region 44a and low-concentration region 44b. High-concentration region 44a has a higher n-type impurity concentration than low-concentration region 44b. High-concentration region 44a is connected to body region 42 (more specifically, low-concentration region 42b) from below. High-concentration region 44a is distributed from the position connected to body region 42 to a range lower than the lower end of each trench 20. The low-concentration region 44b is positioned below the lower end of each trench 20. The low-concentration region 44b is adjacent to the high-concentration region 44a from below. The low-concentration region 44b is distributed relatively wide laterally across the lower portion of the range 28 between each trench.

[0043] Drain region 46 is an n-type region with a higher n-type impurity concentration than drift region 44. Drain region 46 is connected to drift region 44 (more specifically, low-concentration region 44b) from below. Drain region 46 is disposed within the area including the lower surface 12b of semiconductor substrate 12. Drain region 46 is in ohmic contact with drain electrode 32.

[0044] Multiple pressure-resistant regions 48 are p-type regions with a higher concentration of p-type impurities than the bulk region 42. For example... Figure 2 As shown, each pressure-resistant region 48 is disposed within the corresponding trench space 28. Each pressure-resistant region 48 is disposed within the area surrounded by the drift region 44 (more specifically, the high-concentration region 44a). Figure 1 As shown, multiple voltage-resistant regions 48 are provided within each trench interval 28. Within each trench interval 28, the voltage-resistant regions 48 are spaced apart in the y-direction (i.e., the direction parallel to the trench 20). The multiple voltage-resistant regions 48 disposed in different trench intervals 28 are arranged in a straight line along the x-direction (the direction intersecting the multiple trenches 20) to form columns 49. Within each column 49, the multiple voltage-resistant regions 48 are spaced apart in the x-direction. In the semiconductor substrate 12, multiple columns 49 of voltage-resistant regions 48 (i.e., columns extending in the x-direction) are formed. Each column 49 is spaced apart in the y-direction. Figure 2As shown, each withstand voltage region 48 extends from a position above the lower end of each trench 20 to a position below the lower end of each trench 20. A spacer C1 is provided between each withstand voltage region 48 and the gate insulating film 22. Therefore, each withstand voltage region 48 is not in contact with the gate insulating film 22. A drift region 44 (more specifically, a high-concentration region 44a) is disposed in the spacer C1. In the spacer C1, the drift region 44 (more specifically, the high-concentration region 44a) is in contact with the gate insulating film 22. Each withstand voltage region 48 is separated from the body region 42. Each withstand voltage region 48 floats within the drift region 44. Furthermore, as Figure 3 As shown, in the position where the withstand voltage region 48 is not provided, on the lower side of the body region 42, the drift region 44 (more specifically, the high concentration region 44a) is in contact with the gate insulating film 22.

[0045] Multiple bottom regions 50 are p-type regions with a lower p-type impurity concentration than the pressure-resistant region 48. The p-type impurity concentration of each bottom region 50 is approximately equal to the p-type impurity concentration of the bulk region 42. Figure 2 , Figure 3 As shown, each bottom region 50 is disposed at the lower part of the corresponding trench 20. Each bottom region 50 is in contact with the gate insulating film 22 at the bottom surface of the corresponding trench 20. The drift region 44 is in contact with the side and bottom surfaces of each bottom region 50. Each bottom region 50 floats within the drift region 44. Each bottom region 50 extends from the lower end of each trench 20 to a depth reaching the low concentration region 44b. Figure 5 As shown, each bottom region 50 extends continuously along the trench 20 in the y-direction. Each bottom region 50 is in contact with the gate insulating film 22 over approximately the entire area of ​​the bottom surface of the corresponding trench 20. Figure 2 As shown, there is a gap between each bottom region 50 and the pressure-resistant region 48. Therefore, each bottom region 50 is not in contact with the pressure-resistant region 48.

[0046] Next, the operation of MOSFET 10 will be explained. If a potential higher than a threshold is applied to the gate electrode 24, a channel is formed in the body region 42 near the gate insulating film 22. If a potential higher than that of the source electrode 30 is applied to the drain electrode 32 while the channel is formed, electrons flow from the source region 40 through the channel and drift region 44 to the drain region 46. That is, MOSFET 10 is turned on. Figure 3 In the cross-section shown where the pressure-resistant region 48 is absent, electrons passing through the channel flow downwards within the drift region 44 as indicated by arrow 102. Furthermore, in Figure 2 In the cross-section showing the presence of the breakdown voltage region 48, since it is located in the lower part of the bulk region 42, the breakdown voltage region 48 is not in contact with the gate insulating film 22. Therefore, electrons passing through the channel... Figure 2As shown by arrow 100, electrons flow downwards through the drift region 44 within the spacing C1. Thus, in the MOSFET 10 of this embodiment, the p-type breakdown region 48 is not in contact with the gate insulating film 22, allowing electrons to flow downwards along the sidewalls of the trench 20 after passing through the channel. Therefore, the on-resistance of this MOSFET 10 is low.

[0047] Furthermore, when MOSFET 10 is turned on, a small-width depletion layer extends from the breakdown region 48 and the bottom region 50 (i.e., the p-type region) into the drift region 44. As described above, since the breakdown region 48 is positioned away from the gate insulating film 22, the depletion layer extending from the breakdown region 48 into the drift region 44 does not reach the gate insulating film 22. Therefore, the obstruction of electron flow due to the depletion layer extending from the breakdown region 48 into the drift region 44 is suppressed. Furthermore, since the p-type impurity concentration in the bottom region 50 is low, the width of the depletion layer extending from the bottom region 50 into the drift region 44 is very small. Therefore, the obstruction of electron flow due to the depletion layer extending from the bottom region 50 into the drift region 44 is suppressed. Thus, since the depletion layer extending from the breakdown region 48 and the bottom region 50 does not easily obstruct electron flow, the on-resistance of MOSFET 10 is further reduced.

[0048] Furthermore, in the MOSFET 10 of this embodiment, the drift region 44 surrounding the voltage-degrading region 48 is composed of a high-concentration region 44a. Because the high-concentration region 44a has a high concentration of n-type impurities, its resistivity is low. Therefore, electrons passing through the channel can flow with low loss within the high-concentration region 44a. In particular, since the drift region 44 within the narrow spacing C1 is composed of a high-concentration region 44a, electrons can pass through the spacing C1 with low loss. As a result, the on-resistance of the MOSFET 10 is further reduced.

[0049] If the potential of the gate electrode 24 is reduced to a small value, the channel disappears and the flow of electrons stops. That is, the MOSFET 10 is turned off. If the MOSFET 10 is turned off, the depletion layer extends from the body region 42 to the drift region 44, and the drift region 44 is depleted over a large area. At this time, the depletion layer also extends significantly from the breakdown region 48 and the bottom region 50 to the drift region 44. The breakdown region 48 is located away from the lower end of the trench 20. However, due to the high p-type impurity concentration in the breakdown region 48, the depletion layer extending from the breakdown region 48 extends to the periphery of the lower end of the trench 20. Thus, due to the depletion layer extending from the breakdown region 48, the drift region 44 is depleted at the periphery of the lower end of the trench 20, thereby suppressing the electric field concentration at the lower end of the trench 20. In addition, due to the depletion layer extending from the bottom region 50, the drift region 44 is also depleted at the periphery of the lower end of the trench 20. This also suppresses the electric field concentration at the lower end of the trench 20. In this way, the depletion layer extends from the withstand region 48 and the bottom region 50 to the lower periphery of the trench 20, thereby suppressing the electric field concentration at the lower end of the trench 20.

[0050] Furthermore, the high p-type impurity concentration in the breakdown region 48 makes it difficult to deplete when the MOSFET 10 is off. Since the difficult-to-deplete breakdown region 48 extends from the upper side to the lower side of the trench 20, when the MOSFET 10 is off, an electric field is difficult to generate within the drift region 44 in the area above the lower end of the breakdown region 48. That is, as... Figure 4 , Figure 6 As shown by the dashed line 200, the presence of the withstand voltage region 48 makes it difficult for the equipotential line to enter the drift region 44, which is located above the lower end of the withstand voltage region 48. This also suppresses the electric field concentration at the lower end of the trench 20.

[0051] As explained above, the MOSFET 10 according to the embodiment suppresses electric field concentration at the lower end of the trench 20. Therefore, the application of a high electric field to the gate insulating film 22 at the lower end of the trench 20 is suppressed. Consequently, the MOSFET 10 has a higher breakdown voltage.

[0052] Furthermore, in the MOSFET 10 of this embodiment, there is no voltage-bearing region 48 around the trench 20. Therefore, compared to conventional MOSFETs where the voltage-bearing region extends continuously in the direction intersecting the trench, the volume of the voltage-bearing region 48 is smaller. However, even in conventional MOSFETs, the volume occupied by the trench at the intersection of the trench and the voltage-bearing region is relatively large, so the volume of the voltage-bearing region at the intersection is also relatively small. Therefore, even if the voltage-bearing region 48 is removed from the intersection as in the MOSFET 10 of this embodiment, the reduction in the volume of the voltage-bearing region 48 is relatively small. Thus, in the MOSFET 10 of this embodiment, the volume of the voltage-bearing region 48 can be sufficiently ensured, and the depletion layer can extend more widely from the voltage-bearing region 48 into the drift region 44 when the MOSFET 10 is turned off.

[0053] As explained above, in the MOSFET10 of the embodiment, a high withstand voltage can be maintained and the on-resistance can be reduced.

[0054] Next, the manufacturing method of MOSFET 10 will be described. The semiconductor substrate 12 before processing is entirely composed of a low-concentration region 44b of the drift region 44. First, as... Figure 7 , Figure 8 As shown, a mask 80 is formed on the upper surface 12a of the semiconductor substrate 12. Here, the mask 80 is formed such that an opening 80a is disposed in the upper part of the area where the voltage-resistant region 48 is to be formed. In other words, a lattice-shaped mask 80 is formed that extends in a manner that avoids the area where the voltage-resistant region 48 is to be formed. Therefore, the beam portion of the mask 80 extending in the y-direction extends along the area 20x where the trench 20 is to be formed, and the beam portion of the mask 80 extending in the x-direction extends in a direction orthogonal to the area 20x where the trench 20 is to be formed.

[0055] Next, as Figure 9 As shown, p-type impurities are implanted into the semiconductor substrate 12 via mask 80. Here, the implantation energy is increased to implant the p-type impurities from the upper surface 12a to a deeper location. This forms a plurality of breakdown voltage regions 48. After the breakdown voltage regions 48 are formed, mask 80 is removed.

[0056] Furthermore, in the ion implantation process for the pressure-resistant region 48, since a higher implantation energy is used as described above, the mask 80 needs to be thicker. Therefore, the cross-sectional shape of the mask 80 is as follows: Figure 8 , Figure 9 That results in a high aspect ratio. Normally, if a mask is formed with such a high aspect ratio, a portion of the mask may collapse. However, in this embodiment, because... Figure 7 This forms the mask 80 in a grid pattern, thus preventing the mask 80 from collapsing.

[0057] Next, a mask (not shown) is formed to cover the outer periphery of MOSFET 10. Through this mask, as... Figure 10 As shown, n-type impurities are implanted into the semiconductor substrate 12 as ions. As a result, a high-concentration region 44a is formed within the semiconductor substrate 12.

[0058] Next, as Figure 11 As shown, trenches 20 are formed by selectively etching the upper surface 12a of the semiconductor substrate 12.

[0059] Next, as Figure 12 As shown, p-type impurities are implanted into the semiconductor substrate 12 from the upper surface 12a side. This forms a low-concentration region 42b of the bulk region 42. Simultaneously, p-type impurities are also implanted into the bottom surface of the trench 20. As a result, a p-type bottom region 50 is formed in the area exposed on the bottom surface of the trench 20. Thus, this manufacturing method allows for the simultaneous formation of both the low-concentration region 42b and the bottom region 50.

[0060] Next, a gate insulating film 22 and a gate electrode 24 are formed within the trench 20. Then, a contact region 42a, a source region 40, and a drain region 46 are formed by ion implantation. Finally, an interlayer insulating film 26, a source electrode 30, and a drain electrode 32 are formed. Figures 1-5 The MOSFET10 shown is now complete.

[0061] Furthermore, in the above manufacturing method, a low-concentration region 42b is formed by ion implantation of the body region 42, but the low-concentration region 42b can also be formed by epitaxial growth. In this case, before epitaxial growth, such as Figure 13 As shown, a high-concentration region 44a, comprising a breakdown region 48 and a drift region 44, is formed by ion implantation in a shallow region near the upper surface 12a of the semiconductor substrate 12. Next, as... Figure 14 As shown, a low-concentration region 42b is epitaxially grown on the semiconductor substrate 12. Then, as... Figure 15 As shown, a trench 20 and a bottom region 50 are formed. Next, following the same manufacturing method as described above, a gate insulating film 22, a gate electrode 24, a contact region 42a, a source region 40, a drain region 46, an interlayer insulating film 26, a source electrode 30, and a drain electrode 32 are formed. Thus, the MOSFET 10 is completed.

[0062] In addition, in other manufacturing methods, the pressure-resistant region 48 can also be formed by ion implantation after the trench 20 is formed.

[0063] Furthermore, in the MOSFET 10 of the above embodiment, the lower end of the voltage-degrading region 48 is positioned higher than the lower end of the high-concentration region 44a. However, it is also possible to... Figure 16As shown, the pressure-resistant region 48 reaches the low-concentration region 44b.

[0064] Furthermore, in the above embodiment, the pressure-resistant region 48 is separated from the body region 42. However, it is also possible to... Figure 17 As shown, the pressure-resistant region 48 is connected to the body region 42.

[0065] Furthermore, in the above embodiment, a bottom region 50 is provided at the lower part of the trench 20. However, it is also possible to... Figure 18 As shown, a bottom region 50 is not provided at the lower part of the trench 20. With this structure, the electric field concentration at the lower end of the trench 20 can also be suppressed by the depletion layer extending from the withstand voltage region 48.

[0066] Furthermore, in the above embodiment, the drift region 44 has a high-concentration region 44a and a low-concentration region 44b. However, the concentration of n-type impurities may also be uniform throughout the drift region 44.

[0067] The embodiments have been described in detail above, but these are merely illustrative and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples described above. The technical elements described in this specification or drawings achieve technical utility individually or in various combinations, and are not limited to the combinations described in the claims at the time of application. Furthermore, the technology illustrated in this specification or drawings achieves multiple objectives simultaneously, and achieving even one of these objectives is itself technically practical.

Claims

1. A field-effect transistor, characterized in that, have: A semiconductor substrate has multiple trenches on its upper surface; A gate insulating film covers the inner surface of the aforementioned trench; as well as The gate electrode is disposed in the trench and is insulated from the semiconductor substrate by the gate insulating film. The above-mentioned semiconductor substrate has: Multiple n-type source regions; p-type body region; n-type drift region; as well as Multiple p-type pressure-resistant areas; The range located between the plurality of trenches in the semiconductor substrate described above is the trench-to-trench range; Multiple source regions are respectively located within the corresponding trench area and are connected to the corresponding gate insulating film; The aforementioned body region extends across the range of each of the aforementioned trenches, and within the range of each of the aforementioned trenches, it is in contact with each of the aforementioned gate insulating films on the lower side of the aforementioned source region. The aforementioned drift regions are distributed from the range between the aforementioned trenches, spanning a range lower than the aforementioned trenches, and are in contact with the aforementioned gate insulating films on the lower side of the aforementioned body region. Multiple pressure-resistant zones are located within the range of each of the aforementioned trenches; Multiple of the aforementioned pressure-resistant regions are configured within the area surrounded by the aforementioned drift regions; Multiple pressure-resistant regions described above are separated from the body region by the aforementioned drift regions; The aforementioned pressure-resistant areas are configured to form multiple columns extending along a first direction intersecting the aforementioned grooves; Within each of the above columns, multiple pressure-resistant regions are arranged at intervals in the first direction; Multiple columns as described above are spaced apart in a second direction parallel to the aforementioned trench; Each of the aforementioned withstand voltage regions has a higher p-type impurity concentration than the aforementioned body region, extends from above the lower end of each of the aforementioned trenches to below the lower end of each of the aforementioned trenches, and is spaced apart from each of the aforementioned gate insulating films. The drift region is located between each of the aforementioned withstand voltage regions and each of the aforementioned gate insulating films and is in contact with the aforementioned gate insulating film.

2. The field-effect transistor as described in claim 1, characterized in that, It also has multiple p-shaped bottom areas; Each of the aforementioned bottom regions has a lower concentration of p-type impurities than each of the aforementioned pressure-resistant regions; Each of the aforementioned bottom regions is in contact with the gate insulating film at the lower end of the corresponding trench and is spaced apart from each of the aforementioned withstand voltage regions.

3. The field-effect transistor as described in claim 1 or 2, characterized in that, The aforementioned drift region has a low-concentration region and a high-concentration region where the concentration of n-type impurities is higher than that of the low-concentration region. The high-concentration region is distributed from the position where it is connected to the body region to a position lower than the lower end of each trench, and is connected to each gate insulating film at the position between each voltage-resistant region and each gate insulating film. The aforementioned low-concentration region is adjacent to the aforementioned high-concentration region from below.

4. A manufacturing method, which is the manufacturing method of the field-effect transistor according to any one of claims 1 to 3, characterized in that, have: The process of forming a lattice-shaped mask on the upper surface of the aforementioned semiconductor substrate; and The process of implanting p-type impurities into the semiconductor substrate through the aforementioned mask to form a plurality of the aforementioned withstand voltage regions within the semiconductor substrate.

5. The manufacturing method as described in claim 4, characterized in that, It also has: The process of forming trenches on the upper surface of the semiconductor substrate; and The process of implanting p-type impurities into the upper surface of the semiconductor substrate and the bottom surface of the trench to form the body region and the bottom region.

Images