Method for testing parasitic resistance of a capacitor device

Abstract

A method for testing a parasitic resistance of a capacitor device includes: providing a capacitor to be tested, the capacitor to be tested having a first characteristic size; providing an auxiliary capacitor, the auxiliary capacitor having a second characteristic size, the second characteristic size being greater than the first characteristic size; forming a metal layer in series with the capacitor to be tested and the auxiliary capacitor; performing two-port network testing on the capacitor to be tested, the auxiliary capacitor, and the metal layer to obtain a first transmission matrix; performing two-port network testing on the auxiliary capacitor and the metal layer to obtain a second transmission matrix; obtaining a third transmission matrix of the capacitor to be tested according to the first transmission matrix and the second transmission matrix; and obtaining the parasitic resistance of the capacitor to be tested according to the third transmission matrix. By providing the auxiliary capacitor with a larger characteristic size in series with the capacitor to be tested, and by utilizing the larger parasitic resistance in the auxiliary capacitor, the influence of the parasitic resistance in the test circuit can be weakened, thereby improving the testing accuracy of the parasitic resistance of the capacitor to be tested.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a method for testing the parasitic resistance of capacitors. Background Technology

[0002] In semiconductor integrated circuits, integrated capacitors fabricated on the same chip as transistor circuits are widely used. They mainly come in two forms: metal-insulator-metal (MIM) capacitors and metal-oxide-metal (MOM) capacitors. MIM capacitors use upper and lower metal layers as capacitor plates. Fabricating MIM capacitors generally requires additional photolithography layers, and the breakdown voltage of the capacitor dielectric layer and the capacitance size are inherently contradictory. Furthermore, planar capacitors typically require a large area, which is detrimental to device integration. MOM capacitors, on the other hand, use a combination of finger structures and stacked layers to fabricate larger capacitances in a relatively smaller area. In addition, MOM capacitors do not require additional photoresist layers and masks, making the fabrication process simpler and less expensive than that of MIM capacitors. However, due to limitations in the spacing between metal lines, existing lateral MOM capacitors cannot be made large and exhibit poor stability.

[0003] However, with the miniaturization of devices, there are still many problems in measuring the parasitic resistance of small-sized MOM capacitors. Summary of the Invention

[0004] The technical problem solved by this invention is to provide a method for testing the parasitic resistance of capacitors, so as to improve the testing accuracy.

[0005] To address the aforementioned technical problems, the present invention provides a method for testing the parasitic resistance of a capacitor, comprising: providing a capacitor to be tested, the capacitor to be tested having a first characteristic dimension; providing an auxiliary capacitor, the auxiliary capacitor having a second characteristic dimension, the second characteristic dimension being larger than the first characteristic dimension; forming a metal layer, the metal layer being connected in series with the capacitor to be tested and the auxiliary capacitor; performing a two-port network test on the capacitor to be tested, the auxiliary capacitor, and the metal layer to obtain a first transmission matrix; performing a two-port network test on the auxiliary capacitor and the metal layer to obtain a second transmission matrix; obtaining a third transmission matrix of the capacitor to be tested in the two-port network test based on the first transmission matrix and the second transmission matrix; and obtaining the parasitic resistance of the capacitor to be tested based on the third transmission matrix.

[0006] Optionally, the capacitor to be tested includes: several layers of first capacitor layers stacked vertically; and several first conductive plugs located between adjacent first capacitor layers, wherein the first conductive plugs are electrically connected to the adjacent first capacitor layers respectively.

[0007] Optionally, the first capacitor layer includes: a first electrode and a second electrode arranged in parallel along a first direction; a plurality of first finger-shaped plates arranged in parallel along a second direction and respectively connected to the first electrode, wherein the first direction is perpendicular to the second direction; and a plurality of second finger-shaped plates arranged in parallel along the second direction and respectively connected to the second electrode, wherein the plurality of first finger-shaped plates and the plurality of second finger-shaped plates are arranged in an alternating manner.

[0008] Optionally, the first feature dimension is the length dimension of the first finger electrode or the second finger electrode.

[0009] Optionally, the first feature size is 0.1 micrometer to 5 micrometers.

[0010] Optionally, a plurality of the first conductive plugs are electrically connected to the first electrode of the adjacent first capacitor layer, or a plurality of the first conductive plugs are electrically connected to the second electrode of the adjacent first capacitor layer.

[0011] Optionally, the auxiliary capacitor includes: several layers of second capacitor layers stacked vertically; and several second conductive plugs located between adjacent second capacitor layers, the second conductive plugs being electrically connected to adjacent second capacitor layers respectively.

[0012] Optionally, the second capacitor layer includes: a third electrode and a fourth electrode arranged in parallel along the first direction; a plurality of third finger-shaped plates arranged in parallel along the second direction and respectively connected to the third electrode; a plurality of fourth finger-shaped plates arranged in parallel along the second direction and respectively connected to the fourth electrode, wherein the plurality of third finger-shaped plates and the plurality of fourth finger-shaped plates are arranged in an interlaced manner.

[0013] Optionally, the second feature dimension is the length dimension of the third finger electrode or the fourth finger electrode.

[0014] Optionally, the second feature size is 8 micrometers to 15 micrometers.

[0015] Optionally, a plurality of the second conductive plugs are electrically connected to the third electrode of the adjacent second capacitor layer, or a plurality of the second conductive plugs are electrically connected to the fourth electrode of the adjacent second capacitor layer.

[0016] Optionally, the sum of the number of the first finger electrode and the second finger electrode is equal to the sum of the number of the third finger electrode and the fourth finger electrode.

[0017] Optionally, the sum of the number of the first and second finger-shaped electrodes is 1 to 1000; the sum of the number of the third and fourth finger-shaped electrodes is 1 to 1000.

[0018] Optionally, the method for obtaining the third transmission matrix of the capacitor under test in a two-port network test based on the first transmission matrix and the second transmission matrix includes: multiplying the first transmission matrix by the inverse of the second transmission matrix to obtain the third transmission matrix.

[0019] Optionally, the method for obtaining the parasitic resistance of the capacitor under test based on the third transfer matrix includes: converting the third transfer matrix into Y parameters; obtaining the Y parameters... 12 The reciprocal of Y; 12 The real part of the reciprocal of the given value is taken as the parasitic resistance of the capacitor under test.

[0020] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0021] The method for testing the parasitic resistance of a capacitor provided by this invention involves providing an auxiliary capacitor with a larger feature size and connecting the auxiliary capacitor and the capacitor under test in series through a metal layer. A first transmission matrix of the overall structure is obtained by performing a two-port network test on the capacitor under test, the auxiliary capacitor, and the metal layer. A second transmission matrix of the additional structure is then obtained by performing a two-port network test on the auxiliary capacitor and the metal layer. A third transmission matrix of the capacitor under test is obtained by performing corresponding calculations on the first and second transmission matrices. Finally, the parasitic capacitance of the capacitor under test is obtained based on the third transmission matrix. By utilizing the larger parasitic resistance within the auxiliary capacitor, the influence of parasitic resistance in the test circuit can be reduced, thereby improving the testing accuracy of the parasitic resistance of the capacitor under test.

[0022] Furthermore, the sum of the number of the first and second finger-shaped plates is equal to the sum of the number of the third and fourth finger-shaped plates. This avoids an excessive number of the third and fourth finger-shaped plates in the auxiliary capacitor, which would result in an excessively high parasitic resistance of the auxiliary capacitor, thereby masking the parasitic resistance of the capacitor under test and reducing the accuracy of the parasitic resistance measurement of the capacitor under test. Attached Figure Description

[0023] Figure 1 This is a flowchart of a method for testing the parasitic resistance of capacitors according to an embodiment of the present invention;

[0024] Figures 2 to 8This is a schematic diagram of the steps in the method for testing the parasitic resistance of capacitors according to an embodiment of the present invention. Detailed Implementation

[0025] As described in the background section, there are still many problems in measuring the parasitic resistance of small-sized MOM capacitors. These will be explained in detail below.

[0026] Accurate measurement of the RF characteristics of small-sized MOM capacitors is extremely difficult in RF testing because the parasitic resistance of these capacitors is challenging to measure accurately at high frequencies. Current MOM capacitor parasitic capacitance testing requires separate open-circuit and short-circuit tests. After these measurements, the electrical parameters of the MOM capacitor are obtained by embedding the open-circuit-short-circuit method. However, because the parasitic resistance within the circuit during short-circuit testing is typically greater than that of the small-sized MOM capacitor, this significantly interferes with the calculation results, sometimes even resulting in a negative calculated parasitic resistance, which contradicts physical properties.

[0027] To address the aforementioned problems, this invention provides a method for testing the parasitic resistance of a capacitor. This method involves providing an auxiliary capacitor with a larger feature size and connecting the auxiliary capacitor and the capacitor under test in series via a metal layer. By utilizing the larger parasitic resistance within the auxiliary capacitor, the influence of parasitic resistance in the test circuit can be reduced, thereby improving the accuracy of the parasitic resistance test for the capacitor under test.

[0028] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0029] Figure 1 This is a flowchart of a method for testing the parasitic resistance of capacitors according to an embodiment of the present invention, including:

[0030] Step S101: Provide a capacitor to be tested, the capacitor to be tested having a first characteristic dimension;

[0031] Step S102: Provide an auxiliary capacitor, the auxiliary capacitor having a second feature size, the second feature size being larger than the first feature size;

[0032] Step S103: Form a metal layer, wherein the metal layer is connected in series with the capacitor under test and the auxiliary capacitor;

[0033] Step S104: Perform a two-port network test on the capacitor under test, the auxiliary capacitor, and the metal layer to obtain the first transmission matrix;

[0034] Step S105: Perform a two-port network test on the auxiliary capacitor and the metal layer to obtain the second transmission matrix;

[0035] Step S106: Based on the first transmission matrix and the second transmission matrix, obtain the third transmission matrix of the capacitor under test in the two-port network test;

[0036] Step S107: Obtain the parasitic resistance of the capacitor under test according to the third transmission matrix.

[0037] The following describes in detail each step of the test method for the parasitic resistance of the capacitor with reference to the accompanying drawings.

[0038] Figures 2 to 8 This is a schematic diagram of the structure of each step in the method for testing the parasitic resistance of capacitors according to an embodiment of the present invention.

[0039] Please refer to Figure 2 and Figure 3 , Figure 3 yes Figure 2 A cross-sectional view along line AA shows a capacitor 100 to be tested, which has a first characteristic dimension d1.

[0040] In this embodiment, the capacitor to be tested 100 includes: a plurality of first capacitor layers 101 stacked vertically; and a plurality of first conductive plugs 102 located between adjacent first capacitor layers 101, wherein the first conductive plugs 102 are electrically connected to the adjacent first capacitor layers 101 respectively.

[0041] In this embodiment, the first capacitor layer 101 includes: a first electrode 1011 and a second electrode 1012 arranged in parallel along a first direction X; a plurality of first finger-shaped electrodes 1013 arranged in parallel along a second direction Y and connected to the first electrode 1011 respectively, wherein the first direction X is perpendicular to the second direction Y; and a plurality of second finger-shaped electrodes 1014 arranged in parallel along the second direction Y and connected to the second electrode 1012 respectively, wherein the plurality of first finger-shaped electrodes 1013 and the plurality of second finger-shaped electrodes 1014 are arranged in an interlaced manner.

[0042] In this embodiment, the first feature dimension d1 is the length dimension of the first finger electrode 1013 or the second finger electrode 1014.

[0043] In this embodiment, the first feature size d1 is 0.1 micrometers to 5 micrometers.

[0044] In this embodiment, a plurality of the first conductive plugs 102 are electrically connected to the first electrode 1011 of the adjacent first capacitor layer 101, or a plurality of the first conductive plugs 102 are electrically connected to the second electrode 1012 of the adjacent first capacitor layer 101.

[0045] Please refer to Figure 4 and Figure 5 , Figure 5 yes Figure 4 A schematic cross-sectional view along line BB shows an auxiliary capacitor 200, which has a second feature dimension d2, which is larger than the first feature dimension d1.

[0046] In this embodiment, the auxiliary capacitor 200 includes: a plurality of second capacitor layers 201 stacked vertically; and a plurality of second conductive plugs 202 located between adjacent second capacitor layers 201, wherein the second conductive plugs 202 are electrically connected to the adjacent second capacitor layers 201 respectively.

[0047] In this embodiment, the second capacitor layer 201 includes: a third electrode 2011 and a fourth electrode 2012 arranged in parallel along the first direction X; a plurality of third finger-shaped electrodes 2013 arranged in parallel along the second direction Y and respectively connected to the third electrode 2011; and a plurality of fourth finger-shaped electrodes 2014 arranged in parallel along the second direction Y and respectively connected to the fourth electrode 2012, wherein the plurality of third finger-shaped electrodes 2013 and the plurality of fourth finger-shaped electrodes 2014 are arranged in a cross pattern.

[0048] In this embodiment, the second feature dimension d2 is the length dimension of the third finger electrode 2013 or the fourth finger electrode 2014.

[0049] In this embodiment, the second feature size d2 is 8 micrometers to 15 micrometers.

[0050] In this embodiment, a plurality of second conductive plugs 202 are electrically connected to the third electrode 2013 of the adjacent second capacitor layer 201, or a plurality of second conductive plugs 202 are electrically connected to the fourth electrode 2014 of the adjacent second capacitor layer 201.

[0051] In this embodiment, the sum of the number of the first finger plates 1013 and the second finger plates 1014 is equal to the sum of the number of the third finger plates 2013 and the fourth finger plates 2014. This avoids an excessive sum of the number of the third finger plates 2013 and the fourth finger plates 2014 in the auxiliary capacitor 200, which would result in an excessively high parasitic resistance of the auxiliary capacitor 200, thereby masking the parasitic resistance of the capacitor under test 100 and reducing the accuracy of the parasitic resistance measurement of the capacitor under test 100.

[0052] In this embodiment, the sum of the number of the first finger electrode 1013 and the second finger electrode 1014 is 1 to 1000; the sum of the number of the third finger electrode 2013 and the fourth finger electrode 2014 is 1 to 1000.

[0053] Please refer to Figure 6 A metal layer 300 is formed, wherein the metal layer 300 is connected in series with the capacitor under test 100 and the auxiliary capacitor 200.

[0054] In this embodiment, the metal layer 300 is formed in one layer, which is used to connect the first capacitor layer 101 and the second capacitor layer 201 corresponding to any one layer.

[0055] In other embodiments, the number of metal layers formed may be equal to the number of first capacitor layers in the capacitor under test, that is, each first capacitor layer is connected to the corresponding second capacitor layer in the auxiliary capacitor through the metal layer.

[0056] In this embodiment, the metal layer 300 is made of copper.

[0057] Please refer to Figure 7 Two-port network testing is performed on the capacitor 100 to be tested, the auxiliary capacitor 200 and the metal layer 300 to obtain the first transmission matrix R.

[0058] In this embodiment, the method for obtaining the first transmission matrix R includes: testing the capacitor under test 100, the auxiliary capacitor 200, and the metal layer 300 using a vector network analyzer (VNA) to obtain the S-parameters S. a ,

[0059] Right now:

[0060] The first transmission matrix R is obtained based on the conversion between various parameters of the two-port network.

[0061] Right now:

[0062] It should be noted that S-parameters (i.e., scattering parameters) are an important parameter in microwave transmission, where S... 12 S is the reverse transmission coefficient, which is also the isolation factor; 21 S is the forward transmission coefficient, also known as the gain. 11 S is the input reflection coefficient, which is also the input return loss; 22 Z0 is the output reflection coefficient, which is the output return loss; Z0 is the port resistance, which is usually a fixed value of 50 ohms.

[0063] Please refer to Figure 8 A two-port network test is performed on the auxiliary capacitor 200 and the metal layer 300 to obtain the second transmission matrix Q.

[0064] In this embodiment, the method for obtaining the second transmission matrix Q includes: testing the auxiliary capacitor and the metal layer using a network vector analyzer to obtain the S-parameters S. b ,

[0065] Right now:

[0066] The second transmission matrix Q is obtained by converting between the parameters of the two-port network.

[0067] Right now:

[0068] Please continue to refer to this. Figure 7 and Figure 8 Based on the first transmission matrix R and the second transmission matrix Q, the third transmission matrix P of the capacitor under test 100 in the two-port network test is obtained.

[0069] In this embodiment, since the capacitor under test 100 and the auxiliary capacitor 200 are connected in series, and given the known first transmission matrix R of the overall structure composed of the capacitor under test 100, the auxiliary capacitor 200, and the metal layer 300, and the second transmission matrix Q of the additional structure composed of the auxiliary capacitor 200 and the metal layer 300, the third transmission matrix P is simply the inverse of the first transmission matrix R multiplied by the second transmission matrix Q.

[0070] Right now:

[0071] Please continue to refer to this. Figure 7 and Figure 8 According to the third transmission matrix P, the parasitic resistance r of the capacitor 100 under test is obtained.

[0072] In this embodiment, the method for obtaining the parasitic resistance r of the capacitor 100 under test based on the third transfer matrix P includes: converting the third transfer matrix P into Y parameters; obtaining the Y parameters... 12 The reciprocal of Y; 12 The real part of the reciprocal of the given value is taken as the parasitic resistance r of the capacitor 100 under test.

[0073] Right now:

[0074]

[0075] It should be noted that the Y parameter in Y... 11 This indicates the control effect of the input voltage on the input current; Y 12 This indicates the control effect of the output voltage on the input current; Y 21 This indicates the control effect of the input voltage on the output current; Y 22 This indicates the control effect of the output voltage on the output current. 11 Y 12 Y 21 and Y 22 The units are all in the admittance unit "Siemens", hence they are called "admittance parameters" or "Y parameters".

[0076] In this embodiment, an auxiliary capacitor 200 with a larger feature size is provided, and the auxiliary capacitor 200 and the capacitor under test 100 are connected in series through the metal layer 300. A first transmission matrix R of the overall structure is obtained by performing a two-port network test on the capacitor under test 100, the auxiliary capacitor 200, and the metal layer 300. Then, a second transmission matrix Q of the additional structure is obtained by performing a two-port network test on the auxiliary capacitor 200 and the metal layer 300. The first transmission matrix R and the second transmission matrix Q are then calculated to obtain a third transmission matrix P of the capacitor under test 100. Finally, the parasitic capacitance r of the capacitor under test 100 is obtained based on the third transmission matrix P. By utilizing the larger parasitic resistance within the auxiliary capacitor 200, the influence of parasitic resistance in the test circuit can be reduced, thereby improving the testing accuracy of the parasitic resistance r of the capacitor under test 100.

[0077] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for testing the parasitic resistance of a capacitor, characterized in that, include: A capacitor to be tested is provided, the capacitor to be tested having a first characteristic dimension; An auxiliary capacitor is provided, the auxiliary capacitor having a second feature dimension, the second feature dimension being larger than the first feature dimension; A metal layer is formed, wherein the metal layer is connected in series with the capacitor under test and the auxiliary capacitor; Two-port network testing is performed on the capacitor under test, the auxiliary capacitor, and the metal layer to obtain the first transmission matrix; Perform a two-port network test on the auxiliary capacitor and the metal layer to obtain the second transmission matrix; Based on the first transmission matrix and the second transmission matrix, obtain the third transmission matrix of the capacitor under test in the two-port network test; The parasitic resistance of the capacitor under test is obtained based on the third transfer matrix; wherein, The method for obtaining the third transmission matrix of the capacitor under test in a two-port network test based on the first transmission matrix and the second transmission matrix includes: multiplying the first transmission matrix by the inverse of the second transmission matrix to obtain the third transmission matrix; The method for obtaining the parasitic resistance of the capacitor under test based on the third transfer matrix includes: converting the third transfer matrix into Y parameters; obtaining the Y parameters from the Y parameters. 12 The reciprocal of Y; 12 The real part of the reciprocal of the given value is taken as the parasitic resistance of the capacitor under test.

2. The method for testing the parasitic resistance of a capacitor as described in claim 1, characterized in that, The capacitor to be tested includes: several layers of first capacitor layers stacked vertically; and several first conductive plugs located between adjacent first capacitor layers, wherein the first conductive plugs are electrically connected to the adjacent first capacitor layers respectively.

3. The method for testing the parasitic resistance of a capacitor as described in claim 2, characterized in that, The first capacitor layer includes: a first electrode and a second electrode arranged in parallel along a first direction; a plurality of first finger plates arranged in parallel along a second direction and connected to the first electrode respectively, wherein the first direction is perpendicular to the second direction; and a plurality of second finger plates arranged in parallel along the second direction and connected to the second electrode respectively, wherein the plurality of first finger plates and the plurality of second finger plates are arranged in an interlaced manner.

4. The method for testing the parasitic resistance of a capacitor as described in claim 3, characterized in that, The first feature dimension is the length dimension of the first finger electrode or the second finger electrode.

5. The method for testing the parasitic resistance of a capacitor as described in claim 4, characterized in that, The first feature size is 0.1 micrometers to 5 micrometers.

6. The method for testing the parasitic resistance of a capacitor as described in claim 3, characterized in that, A plurality of the first conductive plugs are electrically connected to the first electrode of the adjacent first capacitor layer, or a plurality of the first conductive plugs are electrically connected to the second electrode of the adjacent first capacitor layer.

7. The method for testing the parasitic resistance of a capacitor as described in claim 3, characterized in that, The auxiliary capacitor includes: several layers of second capacitor layers stacked vertically; and several second conductive plugs located between adjacent second capacitor layers, the second conductive plugs being electrically connected to the adjacent second capacitor layers respectively.

8. The method for testing the parasitic resistance of a capacitor as described in claim 7, characterized in that, The second capacitor layer includes: a third electrode and a fourth electrode arranged in parallel along the first direction; a plurality of third finger-shaped plates arranged in parallel along the second direction and respectively connected to the third electrode; and a plurality of fourth finger-shaped plates arranged in parallel along the second direction and respectively connected to the fourth electrode, wherein the plurality of third finger-shaped plates and the plurality of fourth finger-shaped plates are arranged in an interlaced manner.

9. The method for testing the parasitic resistance of a capacitor as described in claim 8, characterized in that, The second feature dimension is the length dimension of the third finger electrode or the fourth finger electrode.

10. The method for testing the parasitic resistance of a capacitor as described in claim 9, characterized in that, The second feature size is 8 micrometers to 15 micrometers.

11. The method for testing the parasitic resistance of a capacitor as described in claim 8, characterized in that, A plurality of second conductive plugs are electrically connected to the third electrode of the adjacent second capacitor layer, or a plurality of second conductive plugs are electrically connected to the fourth electrode of the adjacent second capacitor layer.

12. The method for testing the parasitic resistance of a capacitor as described in claim 8, characterized in that, The sum of the number of the first finger-shaped electrode plate and the second finger-shaped electrode plate is equal to the sum of the number of the third finger-shaped electrode plate and the fourth finger-shaped electrode plate.

13. The method for testing the parasitic resistance of a capacitor as described in claim 12, characterized in that, The sum of the number of the first and second finger-shaped electrodes is 1 to 1000; the sum of the number of the third and fourth finger-shaped electrodes is 1 to 1000.

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