A novel bandgap reference voltage source circuit

Abstract

The application provides a novel band gap reference voltage source circuit, characterized in that the circuit comprises a current source circuit, a voltage self-bias structure circuit, an operational amplifier circuit, a BGR core circuit and a curvature compensation circuit; the current source circuit is connected with the voltage self-bias structure circuit, the BGR core circuit is connected with the operational amplifier circuit and the curvature compensation circuit on both sides; and the voltage self-bias structure circuit is further connected with the BGR core circuit, the voltage self-bias structure circuit is configured to provide a power supply-independent voltage V SR for the BGR core circuit; the curvature compensation circuit is configured to generate a correction current and inject the correction current into the BGR core circuit; the high-order curvature compensation band gap reference source of the voltage self-adjusting structure can well obtain a reference voltage which is independent of temperature, has a high power supply rejection ratio and is less affected by process deviation.

Description

Technical Field

[0001] This application relates to the field of bandgap voltage reference technology in integrated circuits. More specifically, it relates to a novel bandgap voltage reference circuit. Background Technology

[0002] Bandgap references are critical components in most analog and mixed-signal electronic devices, such as voltage regulators, oscillators, ADCs, data converters, and power management controllers. This is because integrated circuits (ICs) rely on a temperature-independent voltage reference with a high power supply rejection ratio (PSRR) to ensure performance parameters such as swing, noise, and bandwidth can withstand temperature variations. These applications often require high precision, thus demanding stringent specifications for the reference voltage source design. Most bandgap references are designed based on the exponential characteristics of BJT devices. The main principle is to generate a voltage that is directly proportional to absolute temperature (PTAT) and a voltage that is inversely proportional to absolute temperature (CTAT), scale and sum these voltages to obtain a temperature-independent reference voltage.

[0003] The lowest temperature coefficient achievable with a typical first-order temperature compensation structure is only 14 ppm / ℃. To further improve output accuracy, higher-order curvature compensation is required. Currently, the most common techniques include curvature compensation, segmented compensation, resistance ratio temperature compensation, and adjustment techniques. However, most low-temperature-coefficient reference sources struggle to achieve high power supply rejection ratios (PSRR), especially with curvature compensation. Introducing a correction current typically lowers the PSRR because introducing new structures often results in increased power supply noise. Therefore, to improve PSRR, existing reference sources often employ cascode structures for isolation in the core branch generating the reference voltage, use large bypass capacitors in the output branch, and introduce negative feedback circuit designs. However, achieving ultra-low temperature coefficients for high PSRR bandgap references is difficult. Therefore, it is currently challenging for current reference voltage sources to simultaneously achieve excellent results in both temperature coefficient and PSRR. Summary of the Invention

[0004] The purpose of this application is to provide a novel bandgap reference voltage source circuit to solve at least one of the problems existing in the prior art.

[0005] To achieve the above objectives, this application adopts the following technical solution: This application provides a novel bandgap reference voltage source circuit, characterized by comprising a current source circuit, a voltage self-biasing structure circuit, an operational amplifier circuit, a BGR core circuit, and a curvature compensation circuit; the current source circuit is connected to the voltage self-biasing structure circuit, and the two sides of the BGR core circuit are respectively connected to the operational amplifier circuit and the curvature compensation circuit; furthermore, the voltage self-biasing structure circuit is also connected to the BGR core circuit, and the voltage self-biasing structure circuit is configured to provide the BGR core circuit with a power supply-independent voltage Vsr; the curvature compensation circuit is configured to generate a correction current and inject the correction current into the BGR core circuit.

[0006] The above technical solutions address the problems of commonly used traditional bandgap reference voltage sources being greatly affected by process deviations, having inaccurate output voltage that is temperature-dependent, and having poor power supply rejection capabilities.

[0007] Specifically, the current source circuit is equipped with a MOSFET, which generates a bias current and then mirrors the bias current to the voltage self-biasing structure circuit and the operational amplifier circuit.

[0008] The voltage self-biased structure circuit contains a MOSFET, which is configured to act as a current mirror, providing current to the BGR core circuit and isolating the BGR core circuit from the current source circuit.

[0009] The above technical solutions provide current to the BGR core circuit while preventing the power supply voltage from directly powering the BGR core circuit, thus greatly improving the power supply rejection ratio.

[0010] Specifically, the current source circuit includes: MOSFETs MP1, MP2, MP3, MP4, MOSFET MN1, MOSFET MN2, transistors Q1, Q2, Q3, and Q4, and resistor R1; the gate of MOSFET MP1 is simultaneously connected to the drain of MOSFET MP1, the gate of MOSFET MP2, the gate of MOSFET MP3, and the collector of transistor Q1; the base of transistor Q1 is simultaneously connected to the base and collector of transistor Q2. The drain of MOSFET MP2 is connected to the base of transistor Q4 and the emitter of transistor Q1. The base of transistor Q3 is connected to the collector of transistor Q4 and the emitter of transistor Q2. One end of resistor R1 is connected to the emitter of transistor Q3. The drain of MOSFET MP3 is connected to the drain and gate of MOSFET MN1 and the gate of MOSFET MN2. The gate of MOSFET MP4 is connected to the drain of MOSFET MP4 and the voltage self-biasing structure circuit.

[0011] Specifically, the voltage self-biased structure circuit includes: MOSFETs MP5, MP8, MP9, MN3, transistor Q5, capacitor C1, output port VBG, and resistor R2; the base of transistor Q5 is simultaneously connected to the gate and drain of MOSFET MP8 and the drain of MOSFET MN3, while the emitter of transistor Q5 is simultaneously connected to one end of resistor R2, capacitor C1, output port VBG, and operational amplifier circuit; the gate of MOSFET MP5 is simultaneously connected to the gate of MOSFET MP4 and operational amplifier circuit; the drain of MOSFET MP5 is simultaneously connected to the source of MOSFET MP8, the source of MOSFET MP9, operational amplifier circuit, BGR core circuit, and curvature compensation circuit; the gate of MOSFET MP9 is connected to operational amplifier circuit; and the gate of MOSFET MN3 is connected to operational amplifier circuit.

[0012] Specifically, the operational amplifier circuit includes: MOSFETs MP6, MP7, MP14, MP15, and MN4; the gate of MOSFET MP6 is simultaneously connected to the gates of MOSFETs MP5 and MP7; the drain of MOSFET MP6 is simultaneously connected to the gate of MOSFET MP9 and the source of MOSFET MP14; the drain of MOSFET MP7 is simultaneously connected to the BGR core circuit and the source of MOSFET MP15; the gate of MOSFET MN4 is simultaneously connected to the drain of MOSFET MP14, the drain of MOSFET MN4, and the gate of MOSFET MN3.

[0013] Specifically, the BGR core circuit includes: MOSFET MP10, MOSFET MP11, transistor Q6, transistor Q7, resistor R3, and resistor R4; the source of MOSFET MP10 is simultaneously connected to the sources of MOSFET MP8, MOSFET MP9, MOSFET MP11, and the curvature compensation circuit; the gate of MOSFET MP10 is simultaneously connected to the drain of MOSFET MP7, the source of MOSFET MP15, the gate of MOSFET MP11, and the curvature compensation circuit; the transistor... The collector of transistor Q6 is simultaneously connected to the drain of MOSFET MP10 and the gate of MOSFET MP14; the emitter of transistor Q6 is simultaneously connected to one end of resistor R3, one end of resistor R4, and the curvature compensation circuit; the base of transistor Q7 is simultaneously connected to capacitor C1, output port VBG, resistor R2, and the emitter of transistor Q5; the collector of transistor Q7 is simultaneously connected to the gate of MOSFET MP15 and the drain of MOSFET MP11; and the other end of resistor R4 is connected to the emitter of transistor Q7.

[0014] Specifically, the curvature compensation circuit includes: MOSFETs MP12, MP13, MP16, and MP17, transistors Q8, Q9, Q10, Q11, Q12, Q13, and resistor R5; the gate of MOSFET MP12 is simultaneously connected to the drain of MOSFET MP7, the source of MOSFET MP15, the gate of MOSFET MP10, and the gate of MOSFET MP11; the drain of MOSFET MP12 is simultaneously connected to the source of MOSFET MP8, the source of MOSFET MP9, the source of MOSFET MP10, the source of MOSFET MP11, the source of MOSFET MP16, the source of MOSFET MP17, the collector of transistor Q9, and the collector of MOSFET MP12. The source of transistor Q13; the gate of MOSFET MP13 is simultaneously connected to the drain of MOSFET MP13 and one end of resistor R5; the gate of MOSFET MP16 is simultaneously connected to the gate, drain, and collector of MOSFET MP17 and transistor Q8, while the drain of MOSFET MP16 is connected to the emitter of transistor Q6; the base of transistor Q8 is simultaneously connected to the emitter of transistor Q9 and collector of transistor Q10; the base of transistor Q13 is simultaneously connected to the base of transistor Q10, collector of transistor Q13, and the other end of resistor R5; the base of transistor Q11 is simultaneously connected to the base of transistor Q9, collector of transistor Q11, and drain of MOSFET MP12, while the emitter of transistor Q11 is simultaneously connected to the base and collector of transistor Q12.

[0015] Specifically, MOSFET MP1-17 is a P-type MOSFET; MOSFET MN1-4 is an N-type MOSFET.

[0016] Specifically, the sources of MOSFETs MP1, MP2, MP3, MP4, MP5, MP6, and MP7, and the collector of transistor Q5 are simultaneously connected to VDD.

[0017] Specifically, the other end of resistor R1, the emitters of transistors Q4, Q10, and Q13, the sources of MOSFETs MN1, MN2, MN3, and MN4, and the other end of resistor R3 are all connected to GND.

[0018] Specifically, the BGR core circuit is used to generate PTAT current and CTAT voltage, and the BGR core circuit includes a first current branch and a second current branch.

[0019] The beneficial effects of this application are as follows: The beneficial effects of this invention are: it proposes a novel bandgap reference voltage source, using MOS transistors and NPN transistors, and designs a high-order curvature-compensated bandgap reference source with a voltage self-regulating structure, which can effectively obtain a reference voltage that is temperature-independent, has a high power supply rejection ratio, and is less affected by process deviations. Under the correction current, the temperature coefficient of the reference voltage is 1.4 ppm / ℃, and the PSRR of the reference voltage reaches -106 dB in the range of −40℃-125℃. Attached Figure Description

[0020] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and, together with the description, serve to explain the principles of this application. Other embodiments and many anticipated advantages of these embodiments will be readily recognized as they become better understood through reference to the following detailed description. Elements in the drawings are not necessarily to scale. The same reference numerals refer to corresponding similar parts.

[0021] Figure 1 This is a circuit diagram of a first-order BGR circuit of a novel bandgap reference voltage source circuit according to an embodiment of this application; Figure 2 This is a circuit diagram of a novel bandgap reference voltage source circuit according to an embodiment of this application; Figure 3 This is a graph showing the trend of changes in each circuit during the compensation process of a novel bandgap reference voltage source circuit according to an embodiment of this application. Figure 4 This is a graph showing the VBG of a novel bandgap reference voltage source circuit according to an embodiment of this application as a function of temperature. Figure 5 This is a graph showing the variation of VBG with temperature under different processes for a novel bandgap reference voltage source circuit according to an embodiment of this application. Figure 6 The simulation results of the VBG power supply rejection ratio of a novel bandgap reference voltage source circuit according to an embodiment of this application are shown. Figure 7 The results are simulations of the VBG power rejection ratio of a novel bandgap reference voltage source circuit according to embodiments of this application under different manufacturing processes. Detailed Implementation

[0022] In the following detailed description, reference is made to the accompanying drawings, which form part of the detailed description and illustrate illustrative specific embodiments in which the present application may be practiced. In this regard, directional terms such as “top,” “bottom,” “left,” “right,” “up,” “down,” etc., are used with reference to the orientation of the described figures. Because components of the embodiments can be positioned in several different orientations, directional terms are used for illustrative purposes and are by no means limiting. It should be understood that other embodiments may be utilized or logical changes may be made without departing from the scope of the present application. Therefore, the following detailed description should not be taken in a limiting sense, and the scope of the present application is defined by the appended claims.

[0023] This application proposes a novel bandgap reference voltage source circuit. Figure 1 This is a circuit diagram of a first-order BGR circuit of a novel bandgap reference voltage source circuit according to an embodiment of this application, as shown below. Figure 1 As shown, the main principle of a first-order BGR circuit is to generate a voltage that is directly proportional to the absolute temperature (PTAT) and a voltage that is inversely proportional to the absolute temperature (CTAT), scale and sum them to obtain a temperature-independent reference voltage. As shown in the figure, if two bipolar transistors operate at unequal current densities, then the difference between their base-emitter voltages is proportional to the absolute temperature. Therefore, this voltage difference... By applying a current mirror to a resistor and copying the current flowing through that resistor, the PTAT current (the absolute temperature-proportional current) can be obtained. The PTAT current is given by [formula missing], and the CTAT voltage by [formula missing]. Specifically, this is to obtain a reference voltage that is unaffected by temperature. Simultaneously, the clamping effect of the operational amplifier is used to pull the voltages at nodes A and B to be equal, ultimately achieving [formula missing]. The reference voltage formula is as follows: ; V T Represents thermal voltage, I S Represents the saturation current, and N is the ratio of the number of transistors Q6 to Q7 connected in parallel. However, ; Let be the bandgap voltage of silicon at the reference temperature, independent of temperature; T0 is the reference temperature, taken as 300K; β is the mobility, approximately 3.54, and is a constant affected by the process; α is the exponential temperature coefficient of the collector current, which is 0 or 1. It can be seen that the first-order BGR structure can only eliminate the term that is linearly related to temperature.

[0024] Figure 2 This is a circuit diagram of a novel bandgap reference voltage source circuit according to an embodiment of this application, as shown below. Figure 2As shown, a novel bandgap reference voltage source circuit is characterized by comprising a current source circuit, a voltage self-biasing structure circuit, an operational amplifier circuit, a BGR core circuit, and a curvature compensation circuit; the current source circuit is connected to the voltage self-biasing structure circuit, and the two sides of the BGR core circuit are respectively connected to the operational amplifier circuit and the curvature compensation circuit; furthermore, the voltage self-biasing structure circuit is also connected to the BGR core circuit, and the voltage self-biasing structure circuit is configured to provide the BGR core circuit with a power supply-independent voltage Vsr; the curvature compensation circuit is configured to generate a correction current and inject the correction current into the BGR core circuit.

[0025] Specifically, the current source circuit includes: MOSFETs MP1, MP2, MP3, MP4, MOSFET MN1, MOSFET MN2, transistors Q1, Q2, Q3, and Q4, and resistor R1; the gate of MOSFET MP1 is simultaneously connected to the drain of MOSFET MP1, the gate of MOSFET MP2, the gate of MOSFET MP3, and the collector of transistor Q1; the base of transistor Q1 is simultaneously connected to the base and collector of transistor Q2. The drain of MOSFET MP2 is connected to the base of transistor Q4 and the emitter of transistor Q1. The base of transistor Q3 is connected to the collector of transistor Q4 and the emitter of transistor Q2. One end of resistor R1 is connected to the emitter of transistor Q3. The drain of MOSFET MP3 is connected to the drain and gate of MOSFET MN1 and the gate of MOSFET MN2. The gate of MOSFET MP4 is connected to the drain of MOSFET MP4 and the voltage self-biasing structure circuit.

[0026] Specifically, the voltage self-biased structure circuit includes: MOSFETs MP5, MP8, MP9, MN3, transistor Q5, capacitor C1, output port VBG, and resistor R2; the base of transistor Q5 is simultaneously connected to the gate and drain of MOSFET MP8 and the drain of MOSFET MN3, while the emitter of transistor Q5 is simultaneously connected to one end of resistor R2, capacitor C1, output port VBG, and operational amplifier circuit; the gate of MOSFET MP5 is simultaneously connected to the gate of MOSFET MP4 and operational amplifier circuit; the drain of MOSFET MP5 is simultaneously connected to the source of MOSFET MP8, the source of MOSFET MP9, operational amplifier circuit, BGR core circuit, and curvature compensation circuit; the gate of MOSFET MP9 is connected to operational amplifier circuit; and the gate of MOSFET MN3 is connected to operational amplifier circuit.

[0027] Specifically, the operational amplifier circuit includes: MOSFETs MP6, MP7, MP14, MP15, and MN4; the gate of MOSFET MP6 is simultaneously connected to the gates of MOSFETs MP5 and MP7; the drain of MOSFET MP6 is simultaneously connected to the gate of MOSFET MP9 and the source of MOSFET MP14; the drain of MOSFET MP7 is simultaneously connected to the BGR core circuit and the source of MOSFET MP15; the gate of MOSFET MN4 is simultaneously connected to the drain of MOSFET MP14, the drain of MOSFET MN4, and the gate of MOSFET MN3.

[0028] Specifically, the BGR core circuit includes: MOSFET MP10, MOSFET MP11, transistor Q6, transistor Q7, resistor R3, and resistor R4; the source of MOSFET MP10 is simultaneously connected to the sources of MOSFET MP8, MOSFET MP9, MOSFET MP11, and the curvature compensation circuit; the gate of MOSFET MP10 is simultaneously connected to the drain of MOSFET MP7, the source of MOSFET MP15, the gate of MOSFET MP11, and the curvature compensation circuit; the transistor... The collector of transistor Q6 is simultaneously connected to the drain of MOSFET MP10 and the gate of MOSFET MP14; the emitter of transistor Q6 is simultaneously connected to one end of resistor R3, one end of resistor R4, and the curvature compensation circuit; the base of transistor Q7 is simultaneously connected to capacitor C1, output port VBG, resistor R2, and the emitter of transistor Q5; the collector of transistor Q7 is simultaneously connected to the gate of MOSFET MP15 and the drain of MOSFET MP11; and the other end of resistor R4 is connected to the emitter of transistor Q7.

[0029] Specifically, the curvature compensation circuit includes: MOSFETs MP12, MP13, MP16, and MP17, transistors Q8, Q9, Q10, Q11, Q12, Q13, and resistor R5; the gate of MOSFET MP12 is simultaneously connected to the drain of MOSFET MP7, the source of MOSFET MP15, the gate of MOSFET MP10, and the gate of MOSFET MP11; the drain of MOSFET MP12 is simultaneously connected to the source of MOSFET MP8, the source of MOSFET MP9, the source of MOSFET MP10, the source of MOSFET MP11, the source of MOSFET MP16, the source of MOSFET MP17, the collector of transistor Q9, and the collector of MOSFET MP12. The source of transistor Q13; the gate of MOSFET MP13 is simultaneously connected to the drain of MOSFET MP13 and one end of resistor R5; the gate of MOSFET MP16 is simultaneously connected to the gate, drain, and collector of MOSFET MP17 and transistor Q8, while the drain of MOSFET MP16 is connected to the emitter of transistor Q6; the base of transistor Q8 is simultaneously connected to the emitter of transistor Q9 and collector of transistor Q10; the base of transistor Q13 is simultaneously connected to the base of transistor Q10, collector of transistor Q13, and the other end of resistor R5; the base of transistor Q11 is simultaneously connected to the base of transistor Q9, collector of transistor Q11, and drain of MOSFET MP12, while the emitter of transistor Q11 is simultaneously connected to the base and collector of transistor Q12.

[0030] Specifically, MOSFET MP1-17 is a P-type MOSFET; MOSFET MN1-4 is an N-type MOSFET.

[0031] Specifically, the sources of MOSFETs MP1, MP2, MP3, MP4, MP5, MP6, and MP7, and the collector of transistor Q5 are simultaneously connected to VDD.

[0032] Specifically, the other end of resistor R1, the emitters of transistors Q4, Q10, and Q13, the sources of MOSFETs MN1, MN2, MN3, and MN4, and the other end of resistor R3 are all connected to GND.

[0033] Figure 3 This is a graph showing the trend of changes in each circuit during the compensation process of a novel bandgap reference voltage source circuit according to an embodiment of this application, combined with... Figure 2 , 3As can be seen, the current is mirrored from MN1 to MN2, and then from MP4 to MP5. MP4, MP5, MN1, and MN2 act as a transition section, providing a stable bias voltage and blocking some power supply voltage noise. This current source can effectively provide stable bias current for other modules in the circuit, such as operational amplifiers and voltage regulator modules.

[0034] The curvature compensation structure uses the current mirror and the current characteristics of the transistor to fix the current flowing through MP17. This current exhibits a parabolic relationship with temperature. The compensation process is as follows: Figure 3 As shown. The correction current, which exhibits a parabolic relationship with temperature, is converted into a voltage through a resistor and added to the VBG of the first-order BGR. This reduces the amplitude of the reference voltage change with temperature, thus yielding a reference voltage close to zero temperature. The formula for the correction current is as follows: ; Q, calculated to be a value essentially independent of temperature, can be considered a constant. V T Represents thermal voltage, I S This represents the saturation current. This current, mirrored by MP16, flows through R3. This design aims to allow this current to cancel out V. BE6 The nonlinear term in the formula enables the BGR to achieve an ultra-low temperature coefficient. The final reference voltage formula is: ; Therefore, by properly adjusting the values ​​of resistors R5, R4, and R3, a bandgap reference voltage source with a low temperature coefficient and a high power supply rejection ratio can be obtained.

[0035] Power supply rejection ratio (PSRR) is related to loop gain and power supply fluctuations. Traditional first-order reference voltage sources can only improve PSRR by designing a high loop gain structure. This invention, however, uses a voltage self-biasing method to generate a voltage V that is essentially unaffected by power supply fluctuations. SR The formula is as follows: ; V BE V is the base-emitter voltage of the transistor. GS This refers to the gate-source voltage of the MOSFET. Specifically, Figure 2 The MP5 module acts as a current mirror, providing current to the core structure of the bandgap reference voltage source. Simultaneously, it isolates the core circuitry of the bandgap reference from the power supply voltage, preventing the power supply voltage from directly powering the core structure of the bandgap reference. This significantly improves the power supply rejection ratio (PSRR). Small-signal analysis can then be used to calculate V. SR The power supply rejection ratio is: ; g m It is the transconductance of the MOSFET, g dsThis is the drain-source conductance of the MOSFET. Since all devices operate in the saturation region, the MOSFET's g... m Compared to g ds Much larger, and since MP5 uses long-channel devices, it is easy to obtain a high PSRR voltage V. SR Put V SR As the power supply for the core circuit of the reference source, this effectively reduces power supply fluctuations. Simultaneously, this invention employs a high loop gain structure to achieve an ultra-high power supply rejection ratio. Furthermore, V SR It also serves as the power supply voltage for the curvature compensation structure, which can alleviate the problem of reduced power supply rejection ratio after the introduction of correction current.

[0036] Figure 4 This is a graph showing the VBG of a novel bandgap reference voltage source circuit according to an embodiment of this application as a function of temperature. Figure 5 This is a graph showing the variation of VBG with temperature under different processes for a novel bandgap reference voltage source circuit according to an embodiment of this application. Figure 6 The simulation results of the VBG power supply rejection ratio of a novel bandgap reference voltage source circuit according to an embodiment of this application are as follows: Figure 7 The simulation results of the VBG power supply rejection ratio of a novel bandgap reference voltage source circuit according to embodiments of this application under different processes are as follows: Figure 4-7 As shown, an ultra-high PSRR was achieved while maintaining TC = 1.4 ppm / ℃. The temperature coefficient simulation results are as follows... Figure 4 As shown, Figure 4 The simulated temperature coefficient (TC) for VBG is approximately 1.4 ppm / ℃ over a wide temperature range of −45℃ to 125℃. Figure 5 The simulation results of TC for BGR under different processes are shown. It can be seen that the curves of VBG changing with temperature are well maintained under different processes, so the temperature coefficients are not much different. The minimum TC is 1.40ppm / ℃ and the maximum TC is 7.34ppm / ℃. Figure 6 The PSRR measured at VBG is shown. The BGR of this invention has a PSRR as high as -106 dB at low frequencies (<10 kHz), and the PSRR begins to decrease above 10 kHz. Figure 7 The PSRR is shown in the VBG simulation results for different processes. It can be seen that the PSRR performance remains good under each process.

[0037] It is obvious that those skilled in the art can make various modifications and alterations to the embodiments of this application without departing from the spirit and scope of this application. In this way, this application also aims to cover such modifications and alterations if they fall within the scope of the claims and their equivalents. The word "comprising" does not exclude the presence of other elements or steps not listed in the claims. The simple fact that certain measures are described in mutually different dependent claims does not indicate that a combination of these measures cannot be used for profit. Any reference numerals in the claims should not be considered limiting in scope.

Claims

1. A novel bandgap reference voltage source circuit, characterized in that, The circuit includes a current source circuit, a voltage self-biasing structure circuit, an operational amplifier circuit, a BGR core circuit, and a curvature compensation circuit. The current source circuit is connected to the voltage self-biasing structure circuit, and the two sides of the BGR core circuit are respectively connected to the operational amplifier circuit and the curvature compensation circuit. The voltage self-biasing structure circuit is connected to the BGR core circuit and is configured to provide the BGR core circuit with a power supply-independent voltage V. SR The curvature compensation circuit is configured to generate a correction current and inject the correction current into the BGR core circuit. The current source circuit includes: MOSFETs MP1, MP2, MP3, MP4, MOSFET MN1, MOSFET MN2, transistors Q1, Q2, Q3, Q4, and resistor R1; the gate of MOSFET MP1 is simultaneously connected to the drain of MOSFET MP1, the gate of MOSFET MP2, the gate of MOSFET MP3, and the collector of transistor Q1; the base of transistor Q1 is simultaneously connected to the base and collector of transistor Q2, and the current source circuit of MOSFET MP4. The drain of transistor Q2; the collector of transistor Q3 is simultaneously connected to the base of transistor Q4 and the emitter of transistor Q1, while the base of transistor Q3 is simultaneously connected to the collector of transistor Q4 and the emitter of transistor Q2; one end of resistor R1 is connected to the emitter of transistor Q3; the drain of MOSFET MP3 is simultaneously connected to the drain and gate of MOSFET MN1 and the gate of MOSFET MN2; the gate of MOSFET MP4 is simultaneously connected to the drain of MOSFET MP4 and the voltage self-biasing structure circuit; The voltage self-biased structure circuit includes: MOSFETs MP5, MP8, MP9, MN3, transistor Q5, capacitor C1, output port VBG, and resistor R2; the base of transistor Q5 is simultaneously connected to the gate and drain of MOSFET MP8 and the drain of MOSFET MN3, while the emitter of transistor Q5 is simultaneously connected to one end of resistor R2, capacitor C1, output port VBG, and the operational amplifier circuit; the gate of MOSFET MP5 is simultaneously connected to the gate of MOSFET MP4 and the operational amplifier circuit; the drain of MOSFET MP5 is simultaneously connected to the source of MOSFET MP8, the source of MOSFET MP9, the operational amplifier circuit, the BGR core circuit, and the curvature compensation circuit; the gate of MOSFET MP9 is connected to the operational amplifier circuit; the gate of MOSFET MN3 is connected to the operational amplifier circuit. The operational amplifier circuit includes: MOSFETs MP6, MP7, MP14, MP15, and MN4; the gate of MOSFET MP6 is simultaneously connected to the gates of MOSFET MP5 and MP7; the drain of MOSFET MP6 is simultaneously connected to the gate of MOSFET MP9 and the source of MOSFET MP14; the drain of MOSFET MP7 is simultaneously connected to the BGR core circuit and the source of MOSFET MP15; the gate of MOSFET MN4 is simultaneously connected to the drain of MOSFET MP14, the drain of MOSFET MN4, and the gate of MOSFET MN3. The BGR core circuit includes: MOSFET MP10, MOSFET MP11, transistor Q6, transistor Q7, resistor R3, and resistor R4; the source of MOSFET MP10 is simultaneously connected to the sources of MOSFET MP8, MOSFET MP9, MOSFET MP11, and the curvature compensation circuit; the gate of MOSFET MP10 is simultaneously connected to the drain of MOSFET MP7, the source of MOSFET MP15, the gate of MOSFET MP11, and the curvature compensation circuit; the transistor Q6... The collector of transistor Q6 is connected to both the drain of MOSFET MP10 and the gate of MOSFET MP14; the emitter of transistor Q6 is connected to one end of resistor R3, one end of resistor R4, and the curvature compensation circuit; the base of transistor Q7 is connected to capacitor C1, the output port VBG, resistor R2, and the emitter of transistor Q5; the collector of transistor Q7 is connected to both the gate of MOSFET MP15 and the drain of MOSFET MP11; and the other end of resistor R4 is connected to the emitter of transistor Q7.

2. The novel bandgap reference voltage source circuit according to claim 1, characterized in that, The current source circuit is equipped with a current source circuit MOS transistor, which generates a bias current and transmits the bias current to the voltage self-biasing structure circuit and the operational amplifier circuit through the MOS transistor.

3. A novel bandgap reference voltage source circuit according to claim 2, characterized in that, The voltage self-biased structure circuit includes a voltage self-biased structure circuit MOS transistor, which is configured to act as a current mirror to provide current to the BGR core circuit and isolate the BGR core circuit from the current source circuit.

4. The novel bandgap reference voltage source circuit according to claim 1, characterized in that, The curvature compensation circuit includes: MOSFETs MP12, MP13, MP16, MP17, transistors Q8, Q9, Q10, Q11, Q12, Q13, and resistor R5; the gate of MOSFET MP12 is simultaneously connected to the drain of MOSFET MP7, the source of MOSFET MP15, the gate of MOSFET MP10, and the gate of MOSFET MP11; the drain of MOSFET MP12 is simultaneously connected to the source of MOSFET MP8, the source of MOSFET MP9, the source of MOSFET MP10, the source of MOSFET MP11, the source of MOSFET MP16, the source of MOSFET MP17, the collector of transistor Q9, and the source of MOSFET MP13; The gate of MOSFET MP13 is simultaneously connected to the drain of MOSFET MP13 and one end of resistor R5; the gate of MOSFET MP16 is simultaneously connected to the gate, drain, and collector of transistor Q8, and the drain of MOSFET MP16 is connected to the emitter of transistor Q6; the base of transistor Q8 is simultaneously connected to the emitter of transistor Q9 and the collector of transistor Q10; the base of transistor Q13 is simultaneously connected to the base of transistor Q10, the collector of transistor Q13, and the other end of resistor R5; the base of transistor Q11 is simultaneously connected to the base of transistor Q9, the collector of transistor Q11, and the drain of MOSFET MP12, and the emitter of transistor Q11 is simultaneously connected to the base and collector of transistor Q12.

5. A novel bandgap reference voltage source circuit according to claim 4, characterized in that, The MOSFET MP1-17 is a P-type MOSFET; the MOSFET MN1-4 is an N-type MOSFET.

6. A novel bandgap reference voltage source circuit according to claim 5, characterized in that, The sources of MOSFETs MP1, MP2, MP3, MP4, MP5, MP6, and MP7, and the collector of transistor Q5 are simultaneously connected to VDD.

7. A novel bandgap reference voltage source circuit according to claim 5, characterized in that, The other end of resistor R1, the emitters of transistors Q4, Q10, and Q13, the sources of MOSFETs MN1, MN2, MN3, and MN4, and the other end of resistor R3 are all connected to GND.

8. A novel bandgap reference voltage source circuit according to claim 1, characterized in that, The BGR core circuit is used to generate PTAT current and CTAT voltage, and the BGR core circuit includes a first current branch and a second current branch.

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