Display device and driving method thereof

Abstract

A display device and its driving method are provided. The display device includes: a scan line, a control line, and an emission control signal line, transmitting signals different from each other; a data line and a driving voltage line, intersecting the scan line and the control line; a first transistor, including a first gate electrode, a first channel region, a first source region, and a first drain region; a second transistor, including a second gate electrode connected to the scan line, a second source region connected to the data line, and a second drain region connected to the first source region; a light-emitting element; a control transistor, including a control gate electrode connected to the control line and connected between the driving voltage line and the first source region; and an emission control transistor, including an emission control gate electrode connected to the emission control signal line and connected between the driving voltage line and the first source region. The control transistor is directly connected to the emission control transistor, and at least one of the control transistor and the emission control transistor is directly connected to the first source region.

Description

[0001] This application is a divisional application of the patent application filed on December 30, 2019, with application number "201911391349.1" and title "Display Device and Driving Method Thereof". Technical Field

[0002] This disclosure relates to a display device and a driving method thereof. Background Technology

[0003] Display devices such as liquid crystal displays (LCDs) or organic light-emitting diode (OLEDs) displays include a display panel comprising a plurality of pixels for displaying images. Each pixel may include a pixel electrode for receiving data signals, and the pixel electrode may be connected to at least one transistor and can receive data signals. Recently, various display devices with functions other than image display have been developed. Summary of the Invention

[0004] An exemplary embodiment provides a display device comprising: a plurality of scan lines for transmitting scan signals; a plurality of control lines for transmitting control signals different from the scan signals; a plurality of transmit control signal lines for transmitting transmit control signals different from the control signals; a plurality of data lines and a plurality of drive voltage lines intersecting the plurality of scan lines and the plurality of control lines; a first transistor including a first gate electrode, a first channel region, a first source region, and a first drain region; a second transistor including a second gate electrode connected to a first scan line among the plurality of scan lines, a second source region connected to a first data line among the plurality of data lines, and a second drain region connected to the first source region; a light-emitting element; a control transistor including a control gate electrode connected to a first control line among the plurality of control lines, the control transistor being connected between a first drive voltage line among the plurality of drive voltage lines and the first source region or between the light-emitting element and the first drain region; and an transmit control transistor, connected in series between the light-emitting element and the control transistor, or between the control transistor and the first transistor, or between a first drive voltage line and the control transistor, and including an transmit control gate electrode connected to a first transmit control signal line among the plurality of transmit control signal lines.

[0005] The control transistor may include a third transistor, the third transistor including a third drain region and a third source region connected to the first drain region, and the emission control transistor may include an emission control source region connected to the third drain region and an emission control drain region connected to the light-emitting element.

[0006] The control transistor may also include a fourth transistor, which includes a fourth source region connected to the first drive voltage line and a fourth drain region connected to the first source region.

[0007] The control transistor may include a third transistor, which includes a third source region and a third drain region connected to the light-emitting element. The emission control transistor may include an emission control drain region connected to the third source region and an emission control source region connected to the first drain region.

[0008] The control transistor may also include a fourth transistor, which includes a fourth source region connected to the first drive voltage line and a fourth drain region connected to the first source region.

[0009] The control transistor may include a third transistor, the third transistor including a third source region and a third drain region connected to the first source region, and the emitter control transistor may include an emitter control drain region connected to the third source region and an emitter control source region connected to the first drive voltage line.

[0010] The control transistor may also include a fourth transistor, which includes a fourth drain region connected to the light-emitting element and a fourth source region connected to the first drain region.

[0011] The display device may further include: a third transistor, including a third gate electrode connected to the first scan line, a third drain region connected to the first gate electrode, and a third source region connected to the first drain region; and a capacitor, including a first terminal connected to the first gate electrode and a second terminal connected to the first drive voltage line.

[0012] The display device may further include a vertical control signal line, which intersects with and is electrically connected to the first transmission control signal line.

[0013] Another embodiment provides a display device comprising: a display area including a first display area comprising a plurality of first pixels and a second display area comprising a plurality of second pixels; a plurality of scan lines disposed in the first display area and the second display area and used for transmitting scan signals; a plurality of control lines disposed in the first display area and the second display area and used for transmitting control signals different from the scan signals; a plurality of transmit control signal lines disposed in the second display area and used for transmitting transmit control signals different from the control signals; and a plurality of data lines and a plurality of drive voltage lines disposed in the first display area and the second display area and intersecting the plurality of scan lines and the plurality of control lines, wherein each of the plurality of first pixels and the plurality of second pixels includes a light-emitting element and a plurality of transistors connected to the scan lines, control lines, data lines and drive voltage lines, and each of the plurality of second pixels further includes a transmit control transistor connected to the transmit control signal lines.

[0014] The display device may further include: a peripheral area disposed outside the display area; and signal wiring disposed in the peripheral area, electrically connected to a plurality of transmission control signal lines, and used for transmitting transmission control signals.

[0015] The display device may further include: a vertical control signal line disposed in the second display area, intersecting with the transmission control signal line, and electrically connected to the transmission control signal line.

[0016] The display device may further include: peripheral control signal lines disposed around the second display area and electrically connected to the transmit control signal lines and the vertical control signal lines.

[0017] The spacing between multiple second pixels in the second display area in the first direction can be greater than the spacing between multiple first pixels in the first display area in the first direction.

[0018] Multiple scan lines, multiple control lines, and multiple transmit control signal lines can be arranged in the same conductive layer.

[0019] The plurality of transistors may include: a first transistor, including a first gate electrode, a first channel region, a first source region, and a first drain region; a second transistor, including a second gate electrode connected to a first scan line among a plurality of scan lines, a second source region connected to a first data line among a plurality of data lines, and a second drain region connected to the first source region; a control transistor, including a control gate electrode connected to a first control line among a plurality of control lines, the control transistor being connected between a driving voltage line and the first source region or between a light-emitting element and the first drain region; and an emitter control transistor, the emitter control transistor being connected in series between the light-emitting element and the control transistor, or between the control transistor and the first transistor, or between a driving voltage line and the control transistor, and may include an emitter control gate electrode connected to an emitter control signal line.

[0020] The display device may further include: optical elements superimposed on the second display area, wherein the optical elements may include a camera or a sensor.

[0021] Another embodiment provides a method for driving a display device, the display device including multiple scan lines, multiple control lines, multiple emission control signal lines, multiple transistors connected to the multiple scan lines and multiple control lines, a light-emitting element, and multiple emission control transistors connected to the multiple emission control signal lines, the method including: sequentially transmitting scan signals to the multiple scan lines; sequentially transmitting control signals to the multiple control lines; and simultaneously transmitting emission control signals different from the control signals to the multiple emission control signal lines.

[0022] The display device may further include a first display area, a second display area, and an optical element superimposed on the second display area. The second display area may include a plurality of emission control transistors, and each of the plurality of emission control transistors may be turned off by an emission control signal during the period when the optical element is operating.

[0023] At least one time period can be set for each of the multiple emitter control transistors to be turned off within a frame in which the scan signal is sequentially transmitted to multiple scan lines. Attached Figure Description

[0024] The features will become clear to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0025] Figure 1 , Figure 2 and Figure 3 A layout diagram of the display area of ​​a display device according to an exemplary embodiment is shown;

[0026] Figure 4 A cross-sectional view of a display device according to an exemplary embodiment is shown;

[0027] Figure 5 , Figure 6 , Figure 7 and Figure 8 A circuit diagram of a pixel of a display device according to an exemplary embodiment is shown;

[0028] Figure 9 and Figure 10 A waveform diagram of the drive signal of a display device according to an exemplary embodiment is shown;

[0029] Figure 11 A layout diagram of the display area of ​​a display device according to an exemplary embodiment is shown;

[0030] Figure 12 A planar layout diagram of two adjacent pixels disposed in a first display area of ​​a display device according to an exemplary embodiment is shown;

[0031] Figure 13 It shows that according to Figure 12 A cross-sectional view of the display device relative to lines IVa-IVb of the exemplary embodiment shown;

[0032] Figure 14 A planar layout diagram of two adjacent pixels disposed in a second display area of ​​a display device according to an exemplary embodiment is shown;

[0033] Figure 15 A planar layout diagram of two adjacent pixels disposed in a first display area of ​​a display device according to an exemplary embodiment is shown; and

[0034] Figure 16 A planar layout diagram of two adjacent pixels disposed in the second display area of ​​a display device according to an exemplary embodiment is shown. Detailed Implementation

[0035] Exemplary embodiments will now be described more fully below with reference to the accompanying drawings; however, exemplary embodiments may be presented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and these embodiments will fully convey exemplary implementation methods to those skilled in the art.

[0036] The accompanying drawings and descriptions are to be considered illustrative rather than restrictive in nature. Throughout the specification, the same reference numerals denote the same elements.

[0037] For better understanding and ease of description, the dimensions and thicknesses of each component shown in the accompanying drawings are arbitrarily illustrated. For clarity, the thicknesses of layers, films, panels, areas, etc., are exaggerated. The thicknesses of some layers and areas are exaggerated for better understanding and ease of description.

[0038] What will be understood is that when an element such as a layer, membrane, region, or substrate is said to be "on" another element, it can be directly on the other element, or there may be an intermediate element present. Conversely, when an element is said to be "directly on" another element, there is no intermediate element present. The phrase "on" or "above" indicates that it is located on or below a part of an object, and does not necessarily mean that it is located on the upper side of a part of an object based on the direction of gravity.

[0039] Unless explicitly stated otherwise, the word “including” and variations such as “contains” or “encompass” shall be understood to imply inclusion of the stated element without excluding any other element.

[0040] Throughout the specification, the plan view represents a view of one side parallel to two intersecting directions (e.g., the first direction DR1 and the second direction DR2), and the sectional view represents a view of one side cut along a direction perpendicular to the side parallel to the first direction DR1 and the second direction DR2 (e.g., the third direction DR3). Furthermore, when two constituent elements are stacked on top of each other, this means that the two constituent elements are stacked on top of each other along the third direction DR3 (e.g., in a direction perpendicular to the upper side of the base).

[0041] Now refer to Figures 1 to 4 The construction of a display device according to an exemplary embodiment is described. Figure 1 , Figure 2 and Figure 3 A layout diagram of the display area of ​​a display device according to an exemplary embodiment is shown. Figure 4 A cross-sectional view of a display device according to an exemplary embodiment is shown.

[0042] Reference Figures 1 to 4According to an exemplary embodiment, the display areas included by display devices 1000a, 1000b, 1000c, and 1000 are areas for displaying images. The display areas may include a first display area DA1 and a second display area DA2 for displaying images and performing other functions. (Refer to...) Figure 4 The display device 1000 may include a display panel 30 and an optical element 500. The optical element 500 may be disposed on the rear side of the display panel 30, but its position is not limited thereto.

[0043] The first display area DA1 may include a plurality of first pixels PXa, and the second display area DA2 may include a plurality of second pixels PXb. Pixels PXa and PXb may each include circuitry for driving a pixel emission region and an area in which the circuitry is formed, the pixel emission region being an area that emits light based on an input image signal.

[0044] Reference Figure 1 The second display area DA2 can be surrounded by the first display area DA1, and in the plan view, it can be near one side of the display device 1000a. In the plan view, the first display area DA1 can be disposed between the second display area DA2 and the edge of the display device 1000a. For example, the second display area DA2 can be disposed near the upper end of the display device 1000a, and can extend along most of the upper edge of the display device 1000a in the first direction DR1. For example, the first display area DA1 can completely surround the second display area DA2.

[0045] Reference Figure 2 Except that the first display area DA1 may not be disposed around at least one side of the second display area DA2, the second display area DA2 according to this exemplary embodiment generally corresponds to the reference. Figure 1 The exemplary embodiment described herein. That is, in the plan view, one edge of the second display area DA2 may substantially correspond to one edge of the display device 1000b. For example, when the second display area DA2 is disposed near the upper edge of the display device 1000b, the first display area DA1 may not be disposed on the top side of the second display area DA2; for example, the first display area DA1 may be disposed only on the three sides of the second display area DA2.

[0046] Reference Figure 3 Except that the second display area DA2 can be disposed on or around the corner edge of the display device 1000c, the second display area DA2 according to this exemplary embodiment generally corresponds to the reference... Figure 2An exemplary embodiment is described. In the plan view, one edge of the second display area DA2 may correspond to a corner edge of the display device 1000c. For example, when the second display area DA2 is disposed around the upper corner of the display device 1000c, one edge of the second display area DA2 may correspond to the edge of a corner on the upper side of the first display area DA1. For example, the first display area DA1 may be only on three sides of the second display area DA2.

[0047] Furthermore, the second display area DA2 can be disposed at various locations within the display area of ​​the display device and can have various planar forms. For example, the second display area DA2 can have a circular planar form disposed near the upper edge of the display device, or any form disposed around the center of the upper edge of the display device, etc.

[0048] Reference Figure 4 The display panel 30 included in the display device 1000 may include a substrate 10 and an encapsulation substrate 20 disposed in a first display area DA1 and a second display area DA2. The substrate 10 may be continuously formed in the second display area DA2, that is, it may not have any removed portions.

[0049] Multiple pixels PX can be formed between the substrate 10 and the encapsulation substrate 20. The multiple pixels PX may include the first pixel PXa and the second pixel PXb described above. A sealant 310 disposed between the substrate 10 and the encapsulation substrate 20 can be disposed on the edge of the display panel 30.

[0050] Optical element 500 can be disposed below display panel 30. Optical element 500 can be various types of optical elements, such as cameras, flashes, and sensors. Optical element 500 can output and / or receive light in a specific wavelength range, such as visible light, infrared light, and ultraviolet light, and can sense images of external objects.

[0051] For example, the optical element 500 can output light within a predetermined wavelength range toward an object 600 disposed on the display panel 30, and / or can receive light reflected from the object 600. Light with a predetermined wavelength is light with a wavelength that can be processed by the optical element 500, and can be light outside the visible light region of the image displayed by the pixels PX, or can be light within the visible light region. For example, when the optical element 500 is an infrared camera, the light with a predetermined wavelength can be substantially between 900 nm and 1000 nm, etc.

[0052] Optical element 500 can be stacked with the second display area DA2, and light output from or input to optical element 500 can pass through the second display area DA2 of display panel 30. The optical element area CA including optical element 500 can have an area corresponding to the entire second display area DA2 in a plan view, or it can have an area corresponding to a part of the second display area DA2.

[0053] Now refer to Figures 5 to 8 As shown above Figure 1 The pixels of the display device according to an exemplary embodiment are described below.

[0054] Figure 5 A circuit diagram is shown in a first pixel PXa in a first display area DA1 of a display device according to an exemplary embodiment. Figure 6 , Figure 7 and Figure 8 A circuit diagram of a second pixel PXb in the second display area DA2 of a display device according to an exemplary embodiment is shown.

[0055] Reference Figure 5 A first pixel PXa in the first display area DA1 may include a plurality of transistors T1, T2, T3, T4, T5, T6, and T7 connected to a plurality of signal lines 151, 152, 153, 154, 171, and 172, a capacitor Cst, and at least one light-emitting diode ED as a light-emitting element. In this exemplary embodiment, the case where one of the first pixels PXa includes a light-emitting diode ED will be described.

[0056] Signal lines 151, 152, 153, 154, 171 and 172 may include multiple scan lines 151, 152 and 154, control line 153, data line 171 and drive voltage line 172.

[0057] Multiple scan lines 151, 152, and 154 can transmit scan signals GWn, GIn, and GI(n+1), respectively. Scan signals GWn, GIn, and GI(n+1) can transmit gate on-state voltage and gate off-state voltage for turning on / off transistors T2, T3, T4, and T7 included by the first pixel PXa.

[0058] Scan lines 151, 152, and 154 connected to a first pixel PXa may include scan line 151 for transmitting a scan signal GWn, scan line 152 for transmitting a scan signal GIn with a gate on-state voltage at a timing different from that of scan line 151, and scan line 154 for transmitting a scan signal GI(n+1). Scan line 152 may transmit the gate on-state voltage at a timing prior to that of scan line 151. For example, when the scan signal GWn is the nth scan signal (Sn) in a scan signal applied within a frame (n is a natural number equal to or greater than 1), the scan signal GIn may be a previous scan signal such as the (n-1)th scan signal (S(n-1)), and the scan signal GI(n+1) may be the nth scan signal (Sn). In an embodiment, the scan signal GI(n+1) may be a scan signal different from the nth scan signal (Sn).

[0059] Control line 153 can transmit a control signal EM for controlling the emission of a light-emitting diode (ED). The control signal EM can transmit the gate on-state voltage and the gate off-state voltage.

[0060] Data line 171 can transmit data signal Dm, and drive voltage line 172 can transmit drive voltage ELVDD. The data signal Dm can have different voltage levels depending on the image signal input to the display device, while the drive voltage ELVDD can have a basically constant level.

[0061] The plurality of transistors T1, T2, T3, T4, T5, T6 and T7 included by a first pixel PXa may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7.

[0062] Scan line 151 can transmit the scan signal GWn to the second transistor T2 and the third transistor T3, scan line 152 can transmit the scan signal GIn to the fourth transistor T4, scan line 154 can transmit the scan signal GI(n+1) to the seventh transistor T7, and control line 153 can transmit the control signal EM to the fifth transistor T5 and the sixth transistor T6.

[0063] The first transistor T1 includes a gate electrode G1 connected to the first terminal of the capacitor Cst via a driving gate node GN, a source electrode S1 connected to the driving voltage line 172 via a fifth transistor T5, and a drain electrode D1 connected to the anode of the light-emitting diode ED via a sixth transistor T6. The first transistor T1 can receive the data signal Dm transmitted by the data line 171 and can supply the driving current Id to the light-emitting diode ED according to the switching operation of the second transistor T2.

[0064] The second transistor T2 includes a gate electrode G2 connected to scan line 151, a source electrode S2 connected to data line 171, and a drain electrode D2 connected to the source electrode S1 of the first transistor T1 and then connected to the drive voltage line 172 via a fifth transistor T5. The second transistor T2 can be turned on by the scan signal GWn transmitted through scan line 151, and can transmit the data signal Dm transmitted through data line 171 to the source electrode S1 of the first transistor T1.

[0065] The third transistor T3 includes: a gate electrode G3 connected to scan line 151; a source electrode S3 connected to the drain electrode D1 of the first transistor T1 and connected to the anode of the light-emitting diode ED through a sixth transistor T6; and a drain electrode D3 connected to the drain electrode D4 of the fourth transistor T4, the first terminal of the capacitor Cst, and the gate electrode G1 of the first transistor T1. The third transistor T3 can be turned on according to the scan signal GWn transmitted through scan line 151, and can connect the gate electrode G1 and the drain electrode D1 of the first transistor T1 to make the first transistor T1 diode connected.

[0066] The fourth transistor T4 includes: a gate electrode G4 connected to scan line 152; a source electrode S4 connected to the initialization voltage Vint terminal; and a drain electrode D4 connected to the first terminal of capacitor Cst, the gate electrode G1 of the first transistor T1, and the drain electrode D3 of the third transistor T3. The fourth transistor T4 can be turned on according to the scan signal GIn transmitted through scan line 152, and can transmit the initialization voltage Vint to the gate electrode G1 of the first transistor T1, thereby performing an initialization operation to initialize the voltage at the gate electrode G1 of the first transistor T1.

[0067] The fifth transistor T5 includes a gate electrode G5 connected to the control line 153, a source electrode S5 connected to the drive voltage line 172, and a drain electrode D5 connected to the source electrode S1 of the first transistor T1 and the drain electrode D2 of the second transistor T2.

[0068] The sixth transistor T6 includes a gate electrode G6 connected to control line 153, a source electrode S6 connected to the drain electrode D1 of the first transistor T1 and the source electrode S3 of the third transistor T3, and a drain electrode D6 electrically connected to the anode of the light-emitting diode ED. The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on according to the control signal EM received via control line 153, and therefore, the drive voltage ELVDD can be compensated by the diode-connected first transistor T1 and can be transmitted to the light-emitting diode ED.

[0069] The fifth transistor T5 and the sixth transistor T6 are called control transistors. The gate electrode of the fifth transistor T5 or the sixth transistor T6 is called the control gate electrode. The source electrode of the fifth transistor T5 or the sixth transistor T6 is called the control source electrode. The drain electrode of the fifth transistor T5 or the sixth transistor T6 is called the control drain electrode.

[0070] The seventh transistor T7 includes a gate electrode G7 connected to scan line 154, a source electrode S7 connected to the drain electrode D6 of the sixth transistor T6 and the anode of the light-emitting diode ED, and a drain electrode D7 connected to the initialization voltage Vint terminal and the source electrode S4 of the fourth transistor T4.

[0071] The source and drain electrodes of transistors T1, T2, T3, T4, T5, T6, and T7 can be the source and drain regions described herein. Transistors T1, T2, T3, T4, T5, T6, and T7 can be p-channel transistors such as PMOS transistors. In other embodiments, at least one of transistors T1, T2, T3, T4, T5, T6, and T7 can be an n-channel transistor.

[0072] The capacitor Cst includes a first terminal connected to the gate electrode G1 of the first transistor T1 and a second terminal connected to the drive voltage line 172. The cathode of the light-emitting diode ED can be connected to the common voltage ELVSS terminal for transmitting the common voltage ELVSS, and can receive the common voltage ELVSS.

[0073] The first pixel PXa, according to an exemplary embodiment, can be constructed with a different number of transistors and capacitors.

[0074] Reference Figures 6 to 8 A second pixel PXb disposed in the second display area DA2 of the display device according to an exemplary embodiment is substantially corresponding in construction to a reference. Figure 5 The first pixel PXa shown may also include an eighth transistor T8 as an emission control transistor and an emission control signal line 157.

[0075] The eighth transistor T8 can be connected in series between the light-emitting diode ED and the sixth transistor T6, which is a control transistor; it can be connected in series between the sixth transistor T6 and the first transistor T1; it can be connected in series between the driving voltage line 172 and the fifth transistor T5, which is a control transistor; or it can be connected in series between the fifth transistor T5 and the first transistor T1, which is a control transistor, and it can control the emission of the second pixel PXb.

[0076] The emit control signal line 157 can transmit an emit control signal BL for controlling the on / off state of the eighth transistor T8. The emit control signal BL can transmit the gate on voltage and the gate off voltage. The eighth transistor T8 includes a gate electrode G8 connected to the emit control signal line 157. The gate electrode G8 is also referred to as the emit control gate electrode.

[0077] For example, refer to details Figure 6 The eighth transistor T8 includes a gate electrode G8 connected to the emitter control signal line 157, a source electrode S8 connected to the drain electrode D6 of the sixth transistor T6, and a drain electrode D8 electrically connected to the anode of the light-emitting diode ED. The source electrode S8 of the eighth transistor T8 is referred to as the emitter control source electrode, and the drain electrode D8 is referred to as the emitter control drain electrode. The eighth transistor T8 can be turned on or off according to the emitter control signal BL transmitted through the emitter control signal line 157.

[0078] When the eighth transistor T8 is turned on, the drive current Id can be transmitted to the light-emitting diode ED, which emits light, and the second pixel PXb can display an image. When the eighth transistor T8 is turned off, the drive current Id is not transmitted to the light-emitting diode ED, which does not emit light, and the second pixel PXb does not display an image.

[0079] Reference Figure 7 Except that the position of the eighth transistor T8, used to control the emission of multiple second pixels PXb disposed in the second display area DA2, can be different, another example of a second pixel PXb disposed in the second display area DA2 generally corresponds to the reference. Figure 6 The second pixel PXb is described. Specifically, the eighth transistor T8 can be connected to the drive voltage line 172 and the fifth transistor T5.

[0080] The gate electrode G8 of the eighth transistor T8 is connected to the emit control signal line 157, the source electrode S8 of the eighth transistor T8 is connected to the drive voltage line 172, and the drain electrode D8 of the eighth transistor T8 is connected to the source electrode S5 of the fifth transistor T5.

[0081] In this exemplary embodiment, when the eighth transistor T8 is turned on, the drive current Id is transmitted to the light-emitting diode ED, causing ED to emit light and the second pixel PXb to display an image. When the eighth transistor T8 is turned off, the drive voltage ELVDD is not applied to the first transistor T1, therefore the light-emitting diode ED does not emit light, and the second pixel PXb may not display an image.

[0082] Reference Figure 7 The exemplary embodiment described differs in that the eighth transistor T8 can be connected between the drain electrode D5 of the fifth transistor T5 and the source electrode S1 of the first transistor T1.

[0083] Reference Figure 8 Except for the fact that the position of the eighth transistor T8 used to control the emission of the light-emitting diode ED can be different, another example of a second pixel PXb set in the second display area DA2 generally corresponds to the reference. Figure 6 The second pixel PXb is described. Specifically, the eighth transistor T8 can be connected to the first transistor T1 and the sixth transistor T6.

[0084] The gate electrode G8 of the eighth transistor T8 is connected to the transmit control signal line 157, the source electrode S8 of the eighth transistor T8 is connected to the drain electrode D1 of the first transistor T1, and the drain electrode D8 of the eighth transistor T8 is connected to the source electrode S6 of the sixth transistor T6.

[0085] In this exemplary embodiment, when the eighth transistor T8 is turned on, the drive current Id is transmitted to the light-emitting diode ED, the light-emitting diode ED emits light, and the second pixel PXb can display an image. When the eighth transistor T8 is turned off, the drive current Id is not transmitted to the light-emitting diode ED, the light-emitting diode ED does not emit light, and the second pixel PXb may not display an image.

[0086] Now refer to Figures 5 to 8 , Figure 9 and Figure 10 The operation of a first pixel PXa in a first display area DA1 and a second pixel PXb in a second display area DA2 of a display device according to an exemplary embodiment is described.

[0087] Figure 9 and Figure 10 A waveform diagram of the drive signal of a display device according to an exemplary embodiment is shown. Here, the case where transistors T1, T2, T3, T4, T5, T6, T7, and T8 are p-type channel transistors such as PMOS transistors is shown.

[0088] Scan signals S1, S2, ..., and Sf can be sequentially scanned within a frame and applied to multiple scan lines 151, 152, and 154 of the display device according to an exemplary embodiment. Control signals EM1, EM2, ..., and EMf can be sequentially scanned within a frame and applied to multiple control lines 153. Here, the scanning direction of the scan signals and control signals can be... Figures 1 to 3 The second direction DR2 shown, or its opposite direction. The nth control signal EMn can go low after the nth scan signal Sn goes high, and the nth control signal EMn can go high when the (n-1)th scan signal S(n-1) is low, where n is a natural number greater than or equal to 1 and less than or equal to f.

[0089] Referring to a first pixel PXa, when a scan signal GIn at the gate on voltage level is supplied through scan line 152 during the initialization period (here, the scan signal GIn can be the (n-1)th scan signal S(n-1)), the fourth transistor T4 is turned on, and the initialization voltage Vint is transmitted to the gate electrode G1 of the first transistor T1 through the fourth transistor T4. The first transistor T1 is initialized by the initialization voltage Vint.

[0090] When a scan signal GWn at the gate on-voltage level (here, the scan signal GWn can be the nth scan signal Sn) is supplied via scan line 151 during the data programming and compensation period, the second transistor T2 and the third transistor T3 are turned on. The first transistor T1 is connected via a diode of the turned-on third transistor T3 and is biased in the forward direction. A compensation voltage, which reduces the threshold voltage of the first transistor T1, is applied to the gate electrode G1 of the first transistor T1 by the data signal Dm supplied from data line 171. The drive voltage ELVDD and the compensation voltage are applied to the respective terminals of the capacitor Cst, which can store the charge corresponding to the voltage difference between the respective terminals.

[0091] During the transmission period, when the control signal EM supplied by the control line 153 changes from the gate cut-off voltage level to the gate turn-on voltage level, the fifth transistor T5 and the sixth transistor T6 turn on, generating a drive current Id caused by the voltage difference between the gate voltage at the gate electrode G1 of the first transistor T1 and the drive voltage ELVDD. This drive current Id is supplied to the light-emitting diode ED through the sixth transistor T6, so the current Ied flows to the light-emitting diode ED.

[0092] During the initialization period, the seventh transistor T7 receives the scan signal GI(n+1) at the gate on-voltage level via scan line 154, and then turns on. The scan signal GI(n+1) can be the nth scan signal Sn. A portion of the drive current Id can be output as a bypass current Ibp through the turned-on seventh transistor T7.

[0093] When control signals EM1, EM2, ..., EMf are at a high level, the LEDs (Emitting Diodes) of pixels PXa and PXb may not emit light. For example... Figure 9 As shown, when control signals EM1, EM2, ..., EMf are scanned and applied to the display area, it is possible for pixel rows of pixels PXa and PXb to exist along one direction (e.g., ...). Figures 1 to 3 The second direction DR2 (or the opposite direction) is shown as the time period that ends sequentially. A pixel row represents a row in which pixels are arranged substantially along the first direction DR1, and a pixel column represents a column in which pixels are arranged substantially along the second direction DR2, which applies throughout this specification.

[0094] During the period when the optical element 500 is operating, light output from or input to the optical element 500 can pass through the second display area DA2, and as... Figure 9 As shown, the transmit control signal BL can be synchronized with the operating timing of the optical element 500. That is, when the optical element 500 is operating (i.e., turned on), the transmit control signal BL is at a high level, therefore the eighth transistor T8 is turned off, and the second pixel PXb including the eighth transistor T8 is also turned off. When the optical element 500 is not operating (i.e., turned off), the transmit control signal BL is at a low level, therefore the eighth transistor T8 is turned on, and the second pixel PXb including the eighth transistor T8 can display the image. Each period during which the transmit control signal BL is at a high level can be substantially less than 1 / 20 of a frame.

[0095] like Figure 9 As shown, the time when the transmit control signal BL goes high can correspond to the time when the optical element 500 begins its operation (conduction), for example, as Figure 10 As shown, a predetermined time t1 occurs before the optical element 500 begins its operation (conduction). Figure 9 As shown, the time when the transmit control signal BL goes low can correspond to the time when the optical element 500 stops operating (i.e., cuts off), for example, as Figure 10 As shown, the predetermined time t2 is after the optical element 500 stops its operation (i.e., is cut off).

[0096] As described above, when the optical element 500 is operated (i.e., turned on), the second pixel PXb disposed in the second display area DA2 corresponding to the optical element 500 can be turned off and remain in a non-emission state. Therefore, no interference is generated between the light emitted by the second pixel PXb and the light output from or input to the optical element 500, preventing the light emitted by the second pixel PXb from affecting the operation of the optical element 500. This allows for accurate results from the optical element 500, such as accurate sensing results, thereby improving the functions performed by the optical element 500. The quality of the image displayed by the second display area DA2 can also be improved.

[0097] like Figure 10As shown, when the transmission control signal BL is set to high before the optical element 500 starts operating (i.e., is turned on), so that the eighth transistor T8 is turned off before the optical element 500 starts operating (i.e., is turned on), the effect of the afterimage on the operation of the optical element 500 when the afterimage of the second pixel PXb remains in the second display area DA2 can be reduced or prevented. Similarly, when the transmission control signal BL is set to low after the optical element 500 stops operating (i.e., is turned off), so that the eighth transistor T8 is turned on after the optical element 500 has completely stopped operating (i.e., is turned off), interference between the light input to or output from the optical element 500 and the light of the image of the second pixel PXb can be reduced or prevented.

[0098] Figure 9 and Figure 10 The diagram illustrates that the optical element 500 operates intermittently (i.e., is turned on) twice within a frame, and the transmit control signal BL has two high-level periods separated from each other. For example, the optical element 500 may operate (i.e., is turned on) once or at least three times within a frame, and the transmit control signal BL may have high-level periods separated from each other once or at least three times within a frame. In another embodiment, the optical element 500 may operate (i.e., is turned on) once within multiple frames, and the transmit control signal BL may include high-level periods once per multiple frames.

[0099] Figure 11 A layout diagram of the display area of ​​a display device according to an exemplary embodiment is shown. (Refer to...) Figure 11 The display device 1000d roughly corresponds to the reference. Figures 1 to 3 In the exemplary embodiment described, the display device 1000d may further include a vertical control signal line 173 and signal wiring 174a and 174b connected to the transmit control signal line 157.

[0100] Specifically, the display device 1000d may further include: a peripheral region PA disposed outside the first display region DA1 and the second display region DA2; wherein a pad region PAD having multiple pads may be disposed in the peripheral region PA at one edge of the display device 1000d. Scan drivers 400a and 400b, connected to multiple scan lines 151, 152 and 154 and sequentially transmitting scan signals, may be disposed on the left and right sides of the first display region DA1 and the second display region DA2. One of the scan drivers 400a and 400b may be omitted.

[0101] The transmit control signal line 157 and the vertical control signal line 173 can be disposed in the second display area DA2. The transmit control signal line 157 and the vertical control signal line 173 can be electrically connected to each other to form a matrix in the plane, and can transmit the transmit control signal BL to multiple second pixels PXb. In a cross-sectional view, the transmit control signal line 157 and the vertical control signal line 173 can be disposed on different conductive layers.

[0102] The peripheral control signal line 175, which is electrically connected to the transmit control signal line 157 and the vertical control signal line 173 and transmits the transmit control signal BL, may also be included around the second display area DA2. The peripheral control signal line 175 may extend along the peripheral edge of the second display area DA2, and its shape is not limited thereto.

[0103] Signal wirings 174a and 174b can be connected to the pad region PAD to receive and transmit the transmit control signal BL. Signal wirings 174a and 174b can be electrically connected to the peripheral control signal line 175 to transmit the transmit control signal BL to the peripheral control signal line 175. Signal wirings 174a and 174b may include portions that begin at the pad region PAD and extend along a second direction DR2 in the peripheral regions PA disposed on respective sides of the first display region DA1 and the second display region DA2. This is an exemplary embodiment in which the second display region DA2 is disposed on opposite sides of the pad region PAD relative to the first display region DA1 and the second display region DA2; in other cases, signal wirings 174a and 174b may have different forms.

[0104] Signal wirings 174a and 174b can be disposed in the same conductive layer as the peripheral control signal line 175, the transmit control signal line 157, or the vertical control signal line 173, or disposed in a different conductive layer. For example, signal wirings 174a and 174b can be disposed on a third conductive layer or a second conductive layer.

[0105] One of the two signal lines 174a and 174b, which are disposed on the corresponding sides of the first display area DA1 and the second display area DA2, can be omitted. When the peripheral control signal line 175 is omitted, the signal wiring 174a and 174b can be electrically connected to the transmit control signal line 157 or the vertical control signal line 173 around the edge of the second display area DA2.

[0106] Now, referring to the attached diagram above and... Figures 12 to 15 The detailed structure of the display area of ​​a display device according to an exemplary embodiment is described below. For ease of description, reference will be made to... Figure 12 and Figure 13 The construction of the first display area DA1 is described, and references will be made to... Figure 14 and Figure 16 Describe the construction of the second display area DA2.

[0107] Figure 12 A planar layout diagram of two adjacent first pixels PXa disposed in the first display area DA1 of a display device according to an exemplary embodiment is shown. Figure 13 It shows that according to Figure 12 A cross-sectional view of the display device relative to lines IVa-IVb of the exemplary embodiment shown. Figure 14 A planar layout diagram of two adjacent second pixels PXb disposed in the second display area DA2 of a display device according to an exemplary embodiment is shown. Figure 15 A planar layout diagram of two adjacent first pixels PXa disposed in the first display area DA1 of a display device according to an exemplary embodiment is shown.

[0108] Figure 12 Two first pixels PXa with the same structure that are adjacent to each other in the first direction DR1 are shown, and for ease of explanation, reference numerals are used to indicate the constituent elements on the right side of the right first pixel PXa that are on the right side of the left first pixel PXa.

[0109] Reference Figure 12 and Figure 13 A barrier layer 111, serving as an insulating layer, can be disposed on a substrate 110, and a buffer layer 120, also serving as an insulating layer, can be disposed on the barrier layer 111. At least one of the barrier layer 111 and the buffer layer 120 may be omitted.

[0110] The active pattern 130 is on the buffer layer 120. The active pattern 130 may include conductive regions and channel regions 131a, 131b, 131c_1, 131c_2, 131d_1, 131d_2, 131e, 131f and 131g for generating channels for a plurality of transistors T1, T2, T3_1, T3_2, T4_1, T4_2, T5, T6 and T7. The conductive regions of the active pattern 130 may include source regions 136a, 136b, 136c_1, 136c_2, 136d_1, 136d_2, 136e, 136f, and 136g of transistors T1, T2, T3_1, T3_2, T4_1, T4_2, T5, T6, and T7, and drain regions 137a, 137b, 137c_1, 137c_2, 137d_1, 137d_2, 137e, 137f, and 137g. Source and drain regions are terms used to distinguish the conductive regions disposed on the respective sides of the channel regions 131a, 131b, 131c_1, 131c_2, 131d_1, 131d_2, 131e, 131f, and 131g, and are interchangeable. The active pattern 130 may include amorphous silicon, polycrystalline silicon, or oxide semiconductor.

[0111] A first insulating layer 121 may be disposed on the active pattern 130, and a first conductive layer may be disposed on the first insulating layer 121. The first conductive layer may include the scan lines 151, 152, and 154, the control line 153, and the drive gate electrode 155a. The scan lines 151, 152, and 154 and the control line 153 may extend substantially along the first direction DR1.

[0112] The second insulating layer 122 may be disposed on the first conductive layer and the first insulating layer 121, and the second conductive layer may be disposed on the second insulating layer 122. The second conductive layer may include a storage line 166 and an initialization voltage line 169 for transmitting an initialization voltage. The storage line 166 may include an extension 166a superimposed on the drive gate electrode 155a.

[0113] The second conductive layer may further include a shielding pattern 165. The shielding pattern 165 may be disposed between scan line 151 and scan line 152.

[0114] The third insulating layer 123 may be disposed on the second conductive layer and the second insulating layer 122. At least one of the barrier layer 111, buffer layer 120, first insulating layer 121, second insulating layer 122 and third insulating layer 123 may comprise an inorganic insulating material and / or an organic insulating material such as silicon oxide, silicon nitride, silicon oxynitride or aluminum oxide. Some or all of the first insulating layer 121, second insulating layer 122 and third insulating layer 123 may comprise a plurality of contact holes 41, 61, 62, 63, 64, 65, 67, 68 and 69.

[0115] The third conductive layer may be disposed on the third insulating layer 123. The third conductive layer may include a plurality of connecting members 74, 75 and 79 connected to the source regions 136a, 136b, 136c_1, 136c_2, 136d_1, 136d_2, 136e, 136f and 136g or the drain regions 137a, 137b, 137c_1, 137c_2, 137d_1, 137d_2, 137e, 137f and 137g of the active pattern 130, a data line 171 and a drive voltage line 172.

[0116] Data line 171 and drive voltage line 172 can extend along the second direction DR2 and can intersect with multiple scan lines 151, 152 and 154. The extension 166a of memory line 166 can be connected to drive voltage line 172 through contact hole 68 and can receive drive voltage ELVDD.

[0117] The drive voltage line 172 can be electrically connected to the shielding pattern 165 through the contact hole 41, and the drive voltage ELVDD can be transmitted to the shielding pattern 165. The shielding pattern 165 can shield the data line 171 and the connection member 74 that serves as the drive gate node GN to prevent voltage changes in the drive gate node GN caused by changes in the data signal. The shielding pattern 165 can be omitted.

[0118] The first transistor T1 includes a channel region 131a, a source region 136a, a drain region 137a, and a driving gate electrode 155a. The driving gate electrode 155a can be connected to the connecting member 74 through a contact hole 61. The contact hole 61 can be provided in the hole 51 included by the extension 166a.

[0119] The second transistor T2 includes a channel region 131b, a source region 136b, a drain region 137b, and a gate electrode 155b as part of a scan line 151. The source region 136b is connected to the data line 171 through a contact hole 62, and the drain region 137b is connected to the source region 136a through the first transistor T1.

[0120] The third transistors T3_1 and T3_2 may include an upper third transistor T3_1 and a lower third transistor T3_2 connected to each other. The upper third transistor T3_1 includes a channel region 131c_1, a source region 136c_1, a drain region 137c_1, and a gate electrode 155c_1 as part of a scan line 151. The drain region 137c_1 is connected to a connection member 74 via a contact hole 63. The lower third transistor T3_2 includes a channel region 131c_2, a source region 136c_2, a drain region 137c_2, and a gate electrode 155c_2 as part of a scan line 151.

[0121] The fourth transistors T4_1 and T4_2 may include a left fourth transistor T4_1 and a right fourth transistor T4_2 connected to each other. The left fourth transistor T4_1 includes a channel region 131d_1, a source region 136d_1, a drain region 137d_1, and a gate electrode 155d_1 as part of a scan line 152. The drain region 137d_1 is connected to the drain region 137c_1 of the upper third transistor T3_1 and connected to the connection member 74 via a contact hole 63. The right fourth transistor T4_2 includes a channel region 131d_2, a source region 136d_2, a drain region 137d_2, and a gate electrode 155d_2 as part of a scan line 152. The drain region 137d_2 is connected to the source region 136d_1 of the left fourth transistor T4_1, and the source region 136d_2 is connected to the connection member 75 via a contact hole 65. The connection member 75 can be electrically connected to the initialization voltage line 169 via the contact hole 64.

[0122] The fifth transistor T5 includes a channel region 131e, a source region 136e, a drain region 137e, and a gate electrode 155e as part of a control line 153. The source region 136e is electrically connected to the drive voltage line 172 through a contact hole 67, and the drain region 137e is connected to the source region 136a of the first transistor T1.

[0123] The sixth transistor T6 includes a channel region 131f, a source region 136f, a drain region 137f, and a gate electrode 155f as part of a control line 153. The source region 136f is connected to the drain region 137a of the first transistor T1, and the drain region 137f is connected to the connection member 79 through a contact hole 69.

[0124] The seventh transistor T7 includes a channel region 131g, a source region 136g, a drain region 137g, and a gate electrode 155g as part of a scan line 154. The source region 136g can be connected to the drain region 137f of the sixth transistor T6, and the drain region 137g can be connected to the connection member 75 through a contact hole 65 to receive an initialization voltage.

[0125] The capacitor Cst included by a first pixel PXa may include a driving gate electrode 155a and an extension 166a of a storage line 166 stacked on top of each other as two terminals, with a second insulating layer 122 between them.

[0126] At least one of the first conductive layer, the second conductive layer, and the third conductive layer may include at least one of copper (Cu), aluminum (Al), magnesium (Mg), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), tantalum (Ta), and alloys thereof.

[0127] The fourth insulating layer 141 may be disposed on the third conductive layer. The fourth insulating layer 141 may include inorganic insulating materials and / or organic insulating materials, such as polyimide, acrylic polymers or siloxane polymers.

[0128] The pixel electrode layer, serving as the fourth conductive layer, can be disposed on the fourth insulating layer 141. The pixel electrode layer may include a pixel electrode 191 disposed in the first pixel PXa. The pixel electrode 191 can be connected to the connection member 79 through the contact hole 89 of the fourth insulating layer 141 to receive data voltage.

[0129] A fifth insulating layer 350 (i.e., a pixel defining layer) may be disposed on the fourth insulating layer 141. The fifth insulating layer 350 may include an opening 351 disposed on the pixel electrode 191. The fifth insulating layer 350 may include an organic insulating material such as a polyacrylic resin or a polyimide resin.

[0130] An emitting layer 370 is disposed on the pixel electrode 191. The emitting layer 370 may include a portion disposed in the opening 351 of the fifth insulating layer 350. The emitting layer 370 may include an organic light-emitting material or an inorganic light-emitting material.

[0131] The common electrode 270 can be disposed on the emitter layer 370. The common electrode 270 can be formed on the fifth insulating layer 350 and can be continuously formed above multiple first pixels PXa. The common electrode 270 can be formed as a continuous electrode in the first display area DA1 and the second display area DA2. The common electrode 270 may include a conductive transparent material.

[0132] The pixel electrode 191, the emitting layer 370, and the common electrode 270 of the first pixel PXa constitute a light-emitting diode ED, with one of the pixel electrode 191 and the common electrode 270 becoming the cathode and the other becoming the anode.

[0133] Reference Figure 12 , Figure 13 and Figure 14 In addition to the second display area DA2 also including an eighth transistor T8, a transmit control signal line 157 and a vertical control signal line 173, the structure of the second display area DA2 generally corresponds to the structure of the first display area DA1. Figure 14 It shows the corresponding reference Figures 6 to 8 References in the exemplary embodiments described Figure 6 The exemplary embodiments described herein.

[0134] The emission control signal line 157 can be disposed on the first conductive layer and can extend substantially along the first direction DR1 in a plan view. In a plan view, the emission control signal line 157 can be disposed between the control line 153 and the scan line 154. One emission control signal line 157 can be provided for each pixel row in the second display area DA2.

[0135] A vertical control signal line 173 can be disposed on the transmit control signal line 157 and another conductive layer (e.g., a third conductive layer). In a plan view, the vertical control signal line 173 can extend substantially along the second direction DR2 to intersect the transmit control signal line 157 and scan lines 151, 152, and 154. One vertical control signal line 173 can be provided for each group having multiple pixel rows in the second display area DA2. For example, one vertical control signal line 173 can be provided for each group having three pixel rows. In an embodiment, one vertical control signal line 173 can be provided for each pixel row.

[0136] The vertical control signal line 173 can be electrically connected to the transmission control signal line 157 via a contact hole 66 located in the intersection region with the transmission control signal line 157 and included in the second insulating layer 122 and the third insulating layer 123. The contact hole 66 can be superimposed on the intersection region of the transmission control signal line 157 and the vertical control signal line 173. In contrast, the vertical control signal line 173 and the transmission control signal line 157 can be electrically connected to each other via conductors disposed on conductive layers different from the first conductive layer and the third conductive layer.

[0137] The active pattern 130 that intersects with the control line 153 and forms the channel region 131f of the sixth transistor T6 can extend downward and may include a portion that intersects with the transmit control signal line 157.

[0138] The eighth transistor T8 includes a channel region 131h, a source region 136h, a drain region 137h, and a gate electrode 155h as part of the emitter control signal line 157. The source region 136h can be connected to the drain region 137f of the sixth transistor T6, and the drain region 137h can be connected to the connecting member 79 through the contact hole 69. The source region 136g of the seventh transistor T7 is connected to the drain region 137h of the eighth transistor T8.

[0139] Reference Figure 12 and Figure 14According to an exemplary embodiment, the spacing of the second pixel PXb in the second display area DA2 along the second direction DR2 can be greater than the spacing of the first pixel PXa in the first display area DA1 along the second direction DR2. Here, the pixel spacing along the second direction DR2 indicates the distance between two repeating patterns along the second direction DR2, for example, calculated as the distance between a portion of the upper initialization voltage line 169 and a corresponding portion of the lower initialization voltage line 169. The distance between the control line 153 and the initialization voltage line 169 in the second display area DA2 along the second direction DR2 can be greater than the distance between the control line 153 and the initialization voltage line 169 in the first display area DA1 along the second direction DR2.

[0140] In the implementation method, refer to Figure 14 and Figure 15 The spacing of the second pixel PXb in the second display area DA2 along the second direction DR2 can be equal to or similar to the spacing of the first pixel PXa in the first display area DA1 along the second direction DR2. In this case, the distance between the control line 153 and the initialization voltage line 169 in the second display area DA2 along the second direction DR2 can be equal to or similar to the distance between the control line 153 and the initialization voltage line 169 in the first display area DA1 along the second direction DR2.

[0141] Now refer to Figure 16 A second display area DA2 of a display device according to an exemplary embodiment is described. Figure 16 A planar layout diagram of two adjacent second pixels PXb disposed in the second display area DA2 of a display device according to an exemplary embodiment is shown.

[0142] Reference Figure 16 Except that the eighth transistor T8 is located in a different position, the second display area DA2 of the display device according to this exemplary embodiment generally corresponds to the reference. Figure 14 The second display area DA2 of the described display device. Figure 16 It shows the corresponding reference Figures 6 to 8 References in the exemplary embodiments described Figure 7 The construction of the exemplary embodiments described.

[0143] The active pattern 130 that intersects with the control line 153 and forms the channel region 131e of the fifth transistor T5 can extend downward and may include a portion that intersects with the transmit control signal line 157.

[0144] The eighth transistor T8 includes a channel region 131h, a source region 136h, a drain region 137h, and a gate electrode 155h that is part of the emitter control signal line 157. The source region 136h can be electrically connected to the drive voltage line 172 through the contact hole 67, and the drain region 137h can be connected to the source region 136e of the fifth transistor T5.

[0145] According to another exemplary embodiment, the pixels included in the first display area DA1 and the second display area DA2 of a display device can have the same structure as the second pixel PXb, which includes the eighth transistor T8 connected to the transmit control signal line 157, in a similar manner to the exemplary embodiment described above.

[0146] By way of summary and review, one or more embodiments provide a display device having a function including image display and another function performed by an optical element, which improves the other function performed by the optical element by reducing or preventing interference between the display function and the other function.

[0147] Example embodiments have been disclosed herein, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only, and not for limiting purposes. In some instances, it will be apparent to those skilled in the art from the time of filing of this application that, unless otherwise specifically indicated, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. A display device, the display device comprising: Scan lines, which are used to transmit scan signals; Control lines are used to transmit control signals that are different from the scan signals; A transmit control signal line is used to transmit a transmit control signal that is different from the control signal mentioned above. The data lines and drive voltage lines intersect with the scan lines and the control lines; The first transistor includes a first gate electrode, a first channel region, a first source region, and a first drain region; The second transistor includes a second gate electrode connected to the scan line, a second source region connected to the data line, and a second drain region connected to the first source region; Light-emitting elements; A control transistor includes a control gate electrode connected to the control line and connected between the drive voltage line and the first source region; as well as The emitter control transistor includes an emitter control gate electrode connected to the emitter control signal line and connected between the drive voltage line and the first source region. The control transistor is directly connected to the emitter control transistor, and At least one of the control transistor and the emitter control transistor is directly connected to the first source region.

2. The display device according to claim 1, wherein: The control transistor includes a control source region and a control drain region connected to the first source region, and The emitter control transistor includes an emitter control drain region connected to the control source region and an emitter control source region connected to the drive voltage line.

3. The display device according to claim 1, wherein: The control transistor includes a control drain region and a control source region connected to the drive voltage line, and The emitter control transistor includes an emitter control source region connected to the control drain region and an emitter control drain region connected to the first source region.

4. The display device according to claim 1, further comprising: The third transistor includes a third drain region connected to the light-emitting element and a third source region connected to the first drain region.

5. The display device according to claim 1, further comprising: The fourth transistor includes a fourth gate electrode connected to the scan line, a fourth drain region connected to the first gate electrode, and a fourth source region connected to the first drain region; as well as The capacitor includes a first terminal connected to the first gate electrode and a second terminal connected to the drive voltage line.

6. The display device according to claim 1, further comprising a vertical control signal line, the vertical control signal line intersecting with and being electrically connected to the transmission control signal line.

7. A display device, the display device comprising: The substrate includes a first surface and a second surface facing away from each other, and the substrate also includes a display area; A scan line is disposed on the first surface of the substrate, and the scan line is used to transmit a scan signal; Control lines are used to transmit control signals that are different from the scan signals; A transmit control signal line is used to transmit a transmit control signal that is different from the control signal mentioned above. The data lines and drive voltage lines intersect with the scan lines and the control lines; The first transistor includes a first gate electrode, a first channel region, a first source region, and a first drain region; The second transistor includes a second gate electrode connected to the scan line, a second source region connected to the data line, and a second drain region connected to the first source region; Light-emitting elements; A control transistor includes a control gate electrode connected to the control line and connected between the drive voltage line and the first source region; The emitter control transistor includes an emitter control gate electrode connected to the emitter control signal line and connected between the drive voltage line and the first source region; as well as An optical element is disposed below the second surface of the substrate. The control transistor is directly connected to the emitter control transistor, and At least one of the control transistor and the emitter control transistor is directly connected to the first source region.

8. The display device according to claim 7, wherein, The optical elements include cameras or sensors.

9. The display device according to claim 7, further comprising: The peripheral area is located outside the display area; as well as Signal wiring is provided in the peripheral area, electrically connected to the transmit control signal line, and used to transmit the transmit control signal.

10. The display device according to claim 9, further comprising a vertical control signal line, the vertical control signal line intersecting the transmission control signal line and being electrically connected to the transmission control signal line.

11. The display device according to claim 10, further comprising a peripheral control signal line electrically connected to the transmit control signal line and the vertical control signal line.

12. The display device of claim 7, wherein, The scan line, the control line, and the transmit control signal line are disposed in the same conductive layer.

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