Underdrive control circuit and semiconductor device including the same

Abstract

The present application relates to an underdrive control circuit and a semiconductor device including the same. The present technology can include a voltage generation circuit configured to generate a plurality of voltages in response to at least one voltage control signal, and a control logic configured to generate the at least one voltage control signal during an underdrive operation of the semiconductor device in order to adjust at least one of an underdrive time and an underdrive offset according to a pre-stored temperature characteristic signal and a temperature information signal of the semiconductor device.

Description

Technical Field

[0001] This disclosure relates to semiconductor circuits, and more specifically, to an underdrive control circuit and a semiconductor device including the underdrive control circuit. Background Technology

[0002] Semiconductor devices (e.g., memory devices) can be divided into volatile memory devices and non-volatile memory devices. Non-volatile memory devices can retain stored data even when the power supply is cut off. Therefore, non-volatile memory devices are widely used in portable electronic devices to store data that must be retained regardless of whether power is supplied.

[0003] Based on the method of storing data, non-volatile memory devices can be classified into read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc.

[0004] Unlike volatile memory, flash memory is in increasing demand because it does not require a refresh function to rewrite data at regular intervals. Flash memory can be electrically programmed and erased. Since flash memory requires different target voltage levels for various operations such as programming, reading, and verifying, voltage generating circuits can be used to generate voltage levels for these different operations. Summary of the Invention

[0005] An underdrive control circuit according to an embodiment of the present disclosure may include: a voltage generating circuit configured to generate a plurality of voltages in response to at least one voltage control signal; and control logic configured to generate at least one voltage control signal during underdrive operation of the semiconductor device based on a pre-stored temperature characteristic signal and a temperature information signal of the semiconductor device, so as to adjust at least one of underdrive time and underdrive offset.

[0006] An underdrive control circuit according to an embodiment of the present disclosure may include: a voltage generation circuit configured to generate a read voltage for a read operation and a verification voltage for a verification operation in response to a voltage control signal; and control logic configured to perform at least one of a word line underdrive operation during a read operation and a word line underdrive operation during a verification operation based on a pre-stored temperature characteristic signal and a temperature information signal of the semiconductor device, and to generate a voltage control signal in at least one word line underdrive operation to adjust at least one of underdrive time and underdrive offset.

[0007] A semiconductor device according to embodiments of the present disclosure may include: a memory cell array; an address decoder connected to the memory cell array via multiple word lines and configured to apply multiple voltages to the word lines corresponding to the decoded row address; and an underdrive control circuit configured to generate multiple voltages in response to a voltage control signal, and to generate the voltage control signal during underdrive operation of the semiconductor device based on a pre-stored temperature characteristic signal and a temperature information signal of the semiconductor device to adjust at least one of underdrive time and underdrive offset. Attached Figure Description

[0008] Figure 1 This is a diagram illustrating the configuration of a memory system including a memory device according to an embodiment of the present disclosure.

[0009] Figure 2 It is shown Figure 1 A diagram showing the configuration of semiconductor devices.

[0010] Figure 3 It is shown Figure 2 A diagram showing the configuration of the voltage generation circuit.

[0011] Figure 4 It is shown Figure 2 A diagram showing the configuration of the control logic in the system.

[0012] Figure 5 This is a diagram illustrating an example of a method for controlling underdriven operation of a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 6 This is a diagram illustrating another example of a method for controlling underdriven operation of a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 7 This is a diagram illustrating another example of a method for controlling underdriven operation of a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0015] Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0016] Various embodiments are intended to provide an underdrive control circuit capable of stably generating voltage in response to temperature changes and a semiconductor device including the underdrive control circuit.

[0017] Figure 1 This is a diagram illustrating the configuration of a memory system 1000 including a memory device according to an embodiment of the present disclosure.

[0018] Reference Figure 1The memory system 1000 may include a memory device 1100, a controller 1200, and a host 1300. The memory device 1100 includes multiple semiconductor devices, such as multiple semiconductor memory devices 100. The multiple semiconductor memory devices 100 may be divided into multiple groups GR1 to GRn. The multiple groups GR1 to GRn may communicate with the controller 1200 via first channels CH1 to nth channels CHn, respectively. In embodiments of this disclosure, the host 1300 is shown and described as being included in the memory system 1000, but the memory system 1000 may include only the controller 1200 and the memory device 1100, and the host 1300 may also be located outside the memory system 1000.

[0019] Controller 1200 can be configured to control multiple semiconductor devices, such as semiconductor memory device 100, of memory device 1100 via multiple channels CH1 to CHn. Controller 1200 is connected between host 1300 and memory device 1100. Controller 1200 is configured to access memory device 1100 in response to a request from host 1300. For example, controller 1200 can be configured to control read operations, programming operations, erase operations, and verification operations of memory device 1100 in response to a host command Host_CMD received from host 1300. During a programming operation, host 1300 may send data DATA to be programmed and address ADD along with Host_CMD, and during a read operation, host 1300 may send address ADD along with Host_CMD. During a programming operation, controller 1200 may send a command corresponding to the programming operation and data DATA to be programmed to memory device 1100. During a read operation, the controller 1200 may send a command corresponding to the read operation to the memory device 1100, receive read data DATA from the memory device 1100, and send the received data DATA to the host 1300. The controller 1200 may be configured to provide an interface between the memory device 1100 and the host 1300.

[0020] As an implementation, the memory device 1100 or memory system 1000 can be mounted in various types of packages. The memory device 1100 or memory system 1000 can be packaged and mounted in ways such as PoP, Ball Grid Array (BGA), Chip Scale Package (CSP), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-line Package (PDIP), Waffle Package Die, Wafer Form Die, Chip on Board (COB), Ceramic Dual In-line Package (CERDIP), Plastic Metric Quad Flat Package (MQFP), Thin Quad Flat Package (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), System Package (SIP), Multi-Chip Package (MCP), Wafer Scale Fabrication Package (WFP), or Wafer Scale Processed Stacked Package (WSP).

[0021] Figure 2 It is shown Figure 1 A diagram showing the configuration of the semiconductor memory device 100.

[0022] Reference Figure 2 The semiconductor memory device 100 may include a memory cell array 110, an address decoder 120, a read / write circuit 130, and an underdrive control circuit 140. The underdrive control circuit 140 may include a voltage generation circuit 150, control logic 160, and a temperature sensor 170. The control logic 160 may be implemented in hardware, software, or a combination of both. For example, the control logic 160 may be a control logic circuit operating according to an algorithm and / or a processor executing control logic code.

[0023] The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz are connected to the address decoder 120 via word lines WL. The multiple memory blocks BLK1 to BLKz are connected to the read / write circuitry 130 via bit lines BL1 to BLm. Each of the multiple memory blocks BLK1 to BLKz may include multiple memory cells. Each of the multiple memory cells may be configured as a multi-level cell where each cell can store one bit or more of information. In this embodiment, the multiple memory cells are non-volatile memory cells. Multiple memory cells connected to a word line may be defined as a page. That is, the memory cell array 110 may include multiple pages. Each of the multiple memory blocks BLK1 to BLKz of the memory cell array 110 may include multiple memory strings, which will be described below. Figure 4 and Figure 5 Detailed description.

[0024] Address decoder 120 can be connected to memory cell array 110 via word line WL. Address decoder 120 can be configured to operate according to address decoder control signal ADctrl generated by control logic 160. Address decoder 120 can receive address ADDR via input / output buffer (not shown) within semiconductor memory device 100 and decode each row address and each column address in the received address ADDR. Address decoder 120 can apply multiple operating voltages, including programming voltage Vpgm, read voltage Vread, pass voltage Vpass, and verification voltage Vverify generated by voltage generation circuit 150, to word line WL corresponding to the decoded row address. Address decoder 120 can send the decoded column address Yi to read / write circuit 130. Address decoder 120 can select a memory block and a word line based on block address and row address.

[0025] The read / write circuit 130 may include multiple page buffers PB1 to PBm. The multiple page buffers PB1 to PBm are connected to the memory cell array 110 via bit lines BL1 to BLm. During a read operation or a verification operation, the multiple page buffers PB1 to PBm may perform a sensing operation to sense the programming state of the memory cells connected to the bit lines BL1 to BLm. During the sensing operation, each of the multiple page buffers PB1 to PBm may precharge a sensing node in the page buffer to a predetermined level, control the potential level of the sensing node based on the current amount on the corresponding bit lines BL1 to BLm, and then latch the data corresponding to the potential level of the sensing node. The multiple page buffers PB1 to PBm may also receive and store data to be programmed during a programming operation, and adjust the potential level of the corresponding bit lines BL1 to BLm based on the stored data. The read / write circuit 130 may operate in response to a page buffer control signal PBctrl output from control logic 160. In an embodiment, the read / write circuit 130 may include a page buffer (or page register), column selection circuitry, etc. The term "predetermined" (e.g., predetermined level, predetermined time, predetermined period) used in this document to refer to parameters means that the value of a parameter is determined before it is used in the processing or algorithm. In some implementations, the value of a parameter is determined before the processing or algorithm begins. In other implementations, the value of a parameter is determined during the processing or algorithm but before it is used in the processing or algorithm.

[0026] The underdrive control circuit 140 can be configured to generate multiple voltages in response to a voltage control signal, and to generate a voltage control signal during underdrive operation of the semiconductor device based on a pre-stored temperature characteristic signal and a temperature information signal of the semiconductor device to adjust at least one of the underdrive time and underdrive offset. The underdrive control circuit 140 may include a voltage generation circuit 150, control logic 160, and a temperature sensor 170.

[0027] Voltage generating circuit 150 generates multiple voltages required for the operation of semiconductor memory device 100. During programming operations, voltage generating circuit 150 generates programming voltage Vpgm, pass voltage Vpass, and verification voltage Vverify according to voltage control signal Vctrl output from control logic 160, and outputs the generated voltages to address decoder 120. During read operations, voltage generating circuit 150 generates read voltage Vread and pass voltage Vpass according to voltage control signal Vctrl output from control logic 160, and outputs the generated voltages to address decoder 120.

[0028] Control logic 160 can be connected to address decoder 120, read / write circuit 130, and voltage generation circuit 150. Control logic 160 can receive commands CMD via input / output buffers (not shown) of semiconductor memory device 100. Control logic 160 can be configured to control the overall operation of semiconductor memory device 100 in response to commands CMD. Control logic 160 can receive commands CMD and temperature information signals TCODE<0:N>, and in response to the received commands CMD and temperature information signals TCODE<0:N>, generate address decoder control signals ADctrl for controlling address decoder 120, page buffer control signals PBctrl for controlling read / write circuit 130, and voltage control signals Vctrl for controlling voltage generation circuit 150, and output the generated control signals.

[0029] In response to the temperature information signal TCODE<0:N>, control logic 160 can adjust at least one of the underdrive time and underdrive offset during a word line underdrive operation (hereinafter referred to as underdrive operation) of the semiconductor memory device 100. The underdrive operation, underdrive time, and underdrive offset will be referred to below. Figures 4 to 7 describe.

[0030] Control logic 160 can determine the current temperature of semiconductor memory device 100 based on temperature information signal TCODE<0:N>, and adjust the value of voltage control signal Vctrl during underdrive operation to correct at least one of underdrive time and underdrive offset to match the temperature operating characteristics of semiconductor memory device 100 and the current temperature.

[0031] Temperature sensor 170 can detect the temperature of semiconductor memory device 100 and generate a temperature information signal TCODE<0:N>. The temperature information signal TCODE<0:N> can have different code values ​​depending on the temperature of semiconductor memory device 100. For example, when the temperature of semiconductor memory device 100 is -25°C, the temperature information signal TCODE<0:N> can have the value "000", and when the temperature of semiconductor memory device 100°C is 100°C, the temperature information signal TCODE<0:N> can have the value "111".

[0032] Figure 3 It is shown Figure 2 A diagram showing the configuration of the voltage generating circuit 150.

[0033] The voltage generating circuit 150 according to embodiments of the present disclosure may use at least one voltage generating unit to generate a programming voltage Vpgm, a read voltage Vread, a pass voltage Vpass, and a verification voltage Vverify. The voltage generating circuit 150 may generate the programming voltage Vpgm, the read voltage Vread, the pass voltage Vpass, and the verification voltage Vverify by sharing one voltage generating unit or by using multiple voltage generating units. Figure 6 An example configuration of voltage generating unit 151 included in voltage generating circuit 150 is shown.

[0034] Reference Figure 3 The voltage generating unit 151 may include a differential amplifier 200, a resistor array 301, and a multiplexer 401.

[0035] The differential amplifier 200 can receive a reference voltage VREF and its own output, namely, an amplified voltage VAMP, and maintain the amplified voltage VAMP at a level that is substantially the same as that of the reference voltage VREF.

[0036] The resistor array 301 may include a plurality of resistors 302 connected between a power supply terminal (i.e., the output terminal of the amplified voltage VAMP of the differential amplifier 200) and a ground terminal.

[0037] Some nodes of resistor array 301 will be referred to as output nodes, and the voltage obtained by dividing the amplified voltage VAMP with different distribution ratios can be output through output nodes ND1 to ND8.

[0038] For example, when the resistance values ​​of multiple resistors 302 are substantially the same, the voltage levels output through output nodes ND1 to ND8 can sequentially have values ​​corresponding to 8 / 8*VREF, 7 / 8*VREF, 6 / 8*VREF, 5 / 8*VREF, 4 / 8*VREF, 3 / 8*VREF, 2 / 8*VREF, and 1 / 8*VREF, from the first output node ND1 closest to the amplified voltage VAMP output terminal to the eighth output node ND8 closest to the ground terminal.

[0039] Multiplexer 401 can select one of the voltage levels output through the output nodes ND1 to ND8 of resistor array 301 according to the voltage control signal Vctrl, and the selected voltage level of the output node is used as the output voltage VOUT. The output voltage VOUT can be used as at least one of programming voltage Vpgm, read voltage Vread, pass voltage Vpass, and verification voltage Vverify.

[0040] The multiplexer 401 may include multiple voltage selection switches 402 and a decoder 403.

[0041] One end of each of the multiple voltage selection switches 402 can be connected to the output nodes ND1 to ND8 respectively, and the other end can be connected to the terminal of the output voltage VOUT.

[0042] Decoder 403 can decode the voltage control signal Vctrl and connect one of the multiple voltage selection switches 402 to the terminal of the output voltage VOUT based on the decoding result.

[0043] Figure 4 It is shown Figure 2 The diagram shows the configuration of control logic 160 in the diagram.

[0044] The control logic 160 may include multiple logic circuits for controlling the overall operation of the semiconductor memory device 100. Figure 4 An example configuration related to voltage control is shown. (Refer to...) Figure 4 The control logic 160 may include voltage control logic 161 and an oscillator 163. The voltage control logic 161 may be implemented in hardware, software, or a combination of both. For example, the voltage control logic 161 may be a voltage control logic circuit operating according to an algorithm and / or a processor executing voltage control logic code.

[0045] Oscillator 163 can generate a periodic signal OSC with a predetermined period.

[0046] Voltage control logic 161 may include a temperature characteristic map (TCMT). The TCMT may include temperature characteristic signals of the semiconductor memory device 100, underdrive time (UDT) values, and underdrive offset (UDO) values.

[0047] Temperature characteristic signals can be set by dividing the temperature conditions of the semiconductor memory device 100 into hot and cold temperature ranges, and determining whether the operating characteristics of the semiconductor memory device 100 are good or bad through pre-testing in the corresponding range. For example, the temperature characteristic signal can be information about whether the operating characteristics (OCCT) of the semiconductor memory device 100 at cold temperature are good or bad. For example, when the operating performance related indicators determined by the OCCT itself (e.g., the operating performance of the voltage generation circuit 150) are higher than the expected level, it can be determined as "good OCCT"; otherwise, it can be determined as "bad OCCT". The corresponding values ​​can then be stored in the TCMT as temperature characteristic signals.

[0048] The underactuated time (UDT) value may include a base value UDTa, a first adjustment value UDTb based on a poor OCCT, and a second adjustment value UDTc based on a good OCCT. The underactuated offset (UDO) value may include a base value UDOa, a first adjustment value UDOb based on a poor OCCT, and a second adjustment value UDOc based on a good OCCT.

[0049] Underdrive operation is an operation applied to stabilize the voltage level of word line WL to a target level, and can be applied, for example, to read and verification operations of semiconductor memory device 100. Underdrive operation in verification operation is performed by applying the verification voltage Vverify at a level lower than the target level (hereinafter referred to as the underdrive level) to the word line for a predetermined time during the interval between verification pulses generated according to the verification voltage Vverify. Underdrive operation in read operation is performed by applying the read voltage Vread at the underdrive level to the word line for a predetermined time during the interval between read pulses generated according to the read voltage Vread. The underdrive time is the time during which the verification voltage Vverify / read voltage Vread is applied at a level lower than the target level, and the underdrive offset is the difference between the target level of the verification voltage Vverify / read voltage Vread and the underdrive level.

[0050] Voltage control logic 161 can determine the temperature range of semiconductor memory device 100 based on temperature information signal TCODE<0:N>.

[0051] Voltage control logic 161 can select a value from the underdrive time values ​​UDTa, UDTb, and UDTc stored in TCMT that matches the temperature characteristic signal of semiconductor memory device 100 and the currently determined temperature range, and generate a voltage control signal Vctrl based on the selected value.

[0052] Voltage control logic 161 can select a value from the underdrive offset values ​​UDOa, UDOb and UDOc stored in TCMT that matches the temperature characteristic signal of semiconductor memory device 100 and the currently determined temperature range, and generate a voltage control signal Vctrl based on the selected value.

[0053] Voltage control logic 161 can select one of the underdrive time values ​​UDTa, UDTb, and UDTc stored in TCMT and one of the underdrive offset values ​​UDOa, UDOb, and UDOc stored in TCMT. The selected value matches the temperature characteristic signal of the semiconductor memory device 100 and the currently determined temperature range, and generates a voltage control signal Vctrl based on the selected value.

[0054] Voltage control logic 161 can adjust the underdrive offset UDO by adjusting the value of the voltage control signal Vctrl. When the value of the voltage control signal Vctrl is adjusted, the voltage generation circuit 150 can adjust the levels of the read voltage Vread and the verification voltage Vverify in response to the adjustment.

[0055] Voltage control logic 161 can adjust the underdrive time UDT by adjusting the generation timing of the voltage control signal Vctrl according to the periodic signal OSC. When the generation timing of the voltage control signal Vctrl is adjusted, the voltage generation circuit 150 can adjust the level adjustment timing of the read voltage Vread and the verification voltage Vverify in response to the adjustment.

[0056] The following will refer to Figures 5 to 7 A method for controlling underdriven operation of a semiconductor memory device according to embodiments of the present disclosure is described.

[0057] When the semiconductor memory device 100 has a multi-level cell structure, the verification operation and the read operation can be performed by multiple verification pulses and multiple read pulses, respectively. The multiple verification pulses PVX and PVY can be generated based on the verification voltage Vverify, and the multiple read pulses RX and RY can be generated based on the read voltage Vread.

[0058] Figure 5 This is a diagram illustrating an example of a method for controlling underdriven operation of a semiconductor memory device according to an embodiment of the present disclosure.

[0059] like Figure 5 As shown, the method for controlling underdrive operation of a semiconductor memory device according to this disclosure can be executed by varying the underdrive time UDT according to a temperature characteristic signal.

[0060] For example, when the temperature range determined based on the temperature information signal TCODE<0:N> is a cold temperature range and the operating characteristic OCCT of the semiconductor memory device 100 is a "bad OCCT", the underdrive time UDT changes to a first adjustment value UDTb, which is increased from the basic value UDTa. As the semiconductor memory device 100 with an operating characteristic OCCT of "bad OCCT" operates in the cold temperature range, the performance of the voltage generation circuit 150 may degrade. However, as the underdrive time UDT increases, the voltage level of the word line WL can stabilize to the target level more quickly.

[0061] When the operating characteristic OCCT of the semiconductor memory device 100 is "good OCCT", the underdrive time UDT is changed to a second adjustment value UDTc, which is reduced from the basic value UDTa. As the semiconductor memory device 100 with the operating characteristic OCCT of "good OCCT" operates in the cold temperature range, the performance of the voltage generation circuit 150 can exceed the desired level. Therefore, by reducing the underdrive time UDT, the voltage level of the word line WL can stabilize to the target level more quickly.

[0062] Figure 6 This is a diagram illustrating another example of a method for controlling underdriven operation of a semiconductor memory device according to an embodiment of the present disclosure.

[0063] like Figure 6 As shown, the method for controlling underdrive operation of a semiconductor memory device according to this disclosure can be executed by varying the underdrive offset UDO according to a temperature characteristic signal.

[0064] For example, when the temperature range determined based on the temperature information signal TCODE<0:N> is a cold temperature range, and the operating characteristic OCCT of the semiconductor memory device 100 is a "bad OCCT", the underdrive offset UDO changes to a first adjustment value UDOb, which is increased from the basic value UDOa. As the semiconductor memory device 100 with an operating characteristic OCCT of "bad OCCT" operates in the cold temperature range, the performance of the voltage generation circuit 150 may degrade. However, as the underdrive offset UDO increases, the voltage level of the word line WL can stabilize to the target level more quickly.

[0065] When the operating characteristic OCCT of the semiconductor memory device 100 is "good OCCT", the underdrive offset UDO changes to a second adjustment value UDOc, which is reduced from the basic value UDOa. As the semiconductor memory device 100 with the operating characteristic OCCT of "good OCCT" operates in the cold temperature range, the performance of the voltage generation circuit 150 can exceed the desired level. Therefore, by reducing the underdrive offset UDO, the voltage level of the word line WL can be stabilized to the target level more quickly.

[0066] Figure 7 This is a diagram illustrating another example of a method for controlling underdriven operation of a semiconductor memory device according to an embodiment of the present disclosure.

[0067] like Figure 7 As shown, the method for controlling underdrive operation of a semiconductor memory device according to this disclosure can be executed by varying the underdrive time UDT and the underdrive offset UDO according to a temperature characteristic signal.

[0068] For example, when the temperature range determined based on the temperature information signal TCODE<0:N> is a cold temperature range, and the operating characteristic OCCT of the semiconductor memory device 100 is a "bad OCCT", the underdrive time UDT changes to a first adjustment value UDTb increased from the base value UDTa, and the underdrive offset UDO changes to a first adjustment value UDOb increased from the base value UDOa. As the semiconductor memory device 100 with an operating characteristic OCCT of "bad OCCT" operates in the cold temperature range, the performance of the voltage generation circuit 150 may degrade. However, as the underdrive time UDT and the underdrive offset UDO increase, the voltage level of the word line WL can stabilize to the target level more quickly.

[0069] When the operating characteristic OCCT of the semiconductor memory device 100 is "good OCCT", the underdrive time UDT is changed to a second adjustment value UDTc, which is reduced from the basic value UDTa, and the underdrive offset UDO is changed to a second adjustment value UDOc, which is reduced from the basic value UDOa. As the semiconductor memory device 100 with the operating characteristic OCCT of "good OCCT" operates in the cold temperature range, the performance of the voltage generation circuit 150 can exceed the desired level. Therefore, by reducing the underdrive time UDT and the underdrive offset UDO, the voltage level of the word line WL can be stabilized to the target level more quickly.

[0070] In this disclosure, a reference can be selectively used based on the temperature information signal TCODE<0:N>. Figures 5 to 7 A method for controlling underactuated operation is described.

[0071] When the cold temperature range is divided into a first cold temperature range and a second cold temperature range below the first cold temperature range, the operating characteristics OCCT may be more degraded in the second cold temperature range compared to the first cold temperature range. For example, in the case of "poor OCCT", the operating performance of the semiconductor memory device 100 may be more degraded in the second cold temperature range compared to the first cold temperature range.

[0072] Therefore, in this disclosure, the cold temperature range can be divided into multiple ranges, such as a first cold temperature range and a second cold temperature range below the first cold temperature range. When the temperature range determined according to the temperature information signal TCODE<0:N> is the first cold temperature range, the range determined according to the first cold temperature range can be selectively used. Figure 5 Control methods and based on Figure 6 One of the control methods, and when the temperature range determined according to the temperature information signal TCODE<0:N> is the second cold temperature range, it can be used according to Figure 7 Control methods.

[0073] Those skilled in the art to which this disclosure pertains will understand that this disclosure may be implemented in other specific forms without altering its technical spirit or essential features. Therefore, it should be understood that the above embodiments are illustrative in all respects and not restrictive. The scope of this disclosure is defined by the following claims rather than the detailed description, and should be construed as including within the scope of this disclosure all modifications or alterations derived from their equivalents, encompassing the meaning and scope of the claims.

[0074] Cross-reference to related applications

[0075] This application claims priority to Korean Application No. 10-2022-0073417, filed with the Korean Intellectual Property Office on June 16, 2022, the entirety of which is incorporated herein by reference.

Claims

1. An underdrive control circuit, the underdrive control circuit comprising: A voltage generating circuit that generates multiple voltages in response to at least one voltage control signal; as well as Control logic that generates at least one voltage control signal during underdrive operation of the semiconductor device based on pre-stored temperature characteristic signals and temperature information signals of the semiconductor device, in order to adjust at least one of the underdrive time and underdrive offset. Specifically, the underdrive operation is performed by applying the first voltage at an underdrive level below a target level to the word line for a predetermined time during an interval between pulses generated based on the first voltage among the plurality of voltages in at least one of the operation processes of the semiconductor device.

2. The underactuated control circuit according to claim 1, wherein, The temperature characteristic signal is generated and stored by dividing the temperature conditions of the semiconductor device into a hot temperature range and a cold temperature range, and determining whether the operating characteristics of the semiconductor device are good or bad in the hot temperature range and the cold temperature range.

3. The underactuated control circuit according to claim 1, wherein, The underdrive time is the time during which the first voltage is applied at the underdrive level, and The underdrive offset is the difference between the target level of the first voltage and the underdrive level.

4. The underdrive control circuit according to claim 1, further comprising: A temperature sensor that detects the temperature of the semiconductor device and generates the temperature information signal.

5. The underdrive control circuit according to claim 1, wherein, The control logic adjusts the underdrive offset by adjusting the value of the at least one voltage control signal, and adjusts the underdrive time by adjusting the generation timing of the at least one voltage control signal.

6. The underdrive control circuit according to claim 1, wherein, The control logic: The temperature range of the semiconductor device is divided into a first cold temperature range and a second cold temperature range that is lower than the first cold temperature range. When the temperature range determined based on the temperature information signal is the first cold temperature range, one of the underdrive time and the underdrive offset is adjusted, and When the temperature range determined based on the temperature information signal is the second cold temperature range, the underdrive time and the underdrive offset are adjusted.

7. The underactuated control circuit according to claim 1, wherein, The control logic includes: An oscillator that generates a periodic signal; and The voltage control logic selects at least one value from underdrive time values ​​and underdrive offset values ​​stored in a temperature characteristic mapping table that matches the temperature information signal and the temperature characteristic signal, and generates the at least one voltage control signal based on the selected signal and the periodic signal.

8. An underdrive control circuit, the underdrive control circuit comprising: A voltage generating circuit that generates a read voltage for a read operation and a verification voltage for a verification operation in response to a voltage control signal; as well as The control logic executes at least one of a word line underdrive operation during the read operation and a word line underdrive operation during the verification operation based on a pre-stored temperature characteristic signal and a temperature information signal of the semiconductor device, and generates the voltage control signal in the at least one word line underdrive operation to adjust at least one of the underdrive time and underdrive offset. Specifically, the at least one word line underdrive operation is performed by applying the corresponding voltage at a level lower than the target level to the word line for a predetermined time within the interval between pulses generated according to the corresponding voltage in the read voltage and the verification voltage.

9. The underdrive control circuit according to claim 8, wherein, The temperature characteristic signal is generated and stored by dividing the temperature conditions of the semiconductor device into a hot temperature range and a cold temperature range, and determining whether the operating characteristics of the semiconductor device are good or bad in the hot temperature range and the cold temperature range.

10. The underdrive control circuit according to claim 8, wherein, The underdrive time is the time during which the corresponding voltage is applied at the underdrive level, and The underdrive offset is the difference between the target level of the corresponding voltage and the underdrive level.

11. The underdrive control circuit according to claim 8, further comprising: A temperature sensor that detects the temperature of the semiconductor device and generates the temperature information signal.

12. The underdrive control circuit according to claim 8, wherein, The control logic adjusts the underdrive offset by adjusting the value of the voltage control signal, and adjusts the underdrive time by adjusting the generation timing of the voltage control signal.

13. The underdrive control circuit according to claim 8, wherein, The control logic: The temperature range of the semiconductor device is divided into a first cold temperature range and a second cold temperature range that is lower than the first cold temperature range. When the temperature range determined based on the temperature information signal is the first cold temperature range, one of the underdrive time and the underdrive offset is adjusted, and When the temperature range determined based on the temperature information signal is the second cold temperature range, the underdrive time and the underdrive offset are adjusted.

14. The underdrive control circuit according to claim 8, wherein, The control logic includes: An oscillator that generates a periodic signal; and The voltage control logic selects at least one value from the underdrive time value and underdrive offset value stored in the temperature characteristic mapping table that matches the temperature information signal and the temperature characteristic signal, and generates the voltage control signal based on the selected signal and the periodic signal.

15. A semiconductor device, the semiconductor device comprising: Memory cell array; An address decoder is connected to the memory cell array via multiple word lines and applies multiple voltages to the word lines corresponding to the decoded row address. as well as An underdrive control circuit generates the plurality of voltages in response to a voltage control signal, and generates the voltage control signal during underdrive operation of the semiconductor device based on a pre-stored temperature characteristic signal and a temperature information signal of the semiconductor device to adjust at least one of the underdrive time and underdrive offset. Specifically, the underdrive operation is performed by applying the corresponding voltage at an underdrive level lower than the target level to the word line for a predetermined time within the interval between pulses generated based on the corresponding voltage in the read voltage and the verification voltage.

16. The semiconductor device of claim 15, further comprising: A read / write circuit is connected to the memory cell array via bit lines and performs a sensing operation for sensing the programming state of the memory cells connected to the bit lines.

17. The semiconductor device according to claim 15, wherein, The underdrive control circuit includes: A temperature sensor that detects the temperature of the semiconductor device and generates the temperature information signal.

18. The semiconductor device according to claim 15, wherein, The underdrive time is the time during which the corresponding voltage is applied at the underdrive level, and The underdrive offset is the difference between the target level of the corresponding voltage and the underdrive level.

19. The semiconductor device according to claim 15, wherein, The underdrive control circuit adjusts the underdrive offset by adjusting the value of the voltage control signal, and adjusts the underdrive time by adjusting the generation timing of the voltage control signal.

20. The semiconductor device according to claim 15, wherein, The underdrive control circuit: The temperature range of the semiconductor device is divided into a first cold temperature range and a second cold temperature range that is lower than the first cold temperature range. When the temperature range determined based on the temperature information signal is the first cold temperature range, one of the underdrive time and the underdrive offset is adjusted, and When the temperature range determined based on the temperature information signal is the second cold temperature range, the underdrive time and the underdrive offset are adjusted.

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