Memory device and operating method thereof, and storage device

Abstract

A memory device includes an array of memory cells including a plurality of memory cells connected to a plurality of word lines, a peripheral circuit configured to perform a program operation and a verify operation on a selected memory cell among the plurality of memory cells, a compensation operation controller configured to determine compensation values for a plurality of verify voltages based on a degree of progress of the program operation and a target program state according to compensation information during the verify operation, and a verify operation controller configured to control the peripheral circuit to perform the verify operation on the selected memory cell among the plurality of memory cells based on the plurality of verify voltages and the compensation values.

Description

Technical Field

[0001] This disclosure relates to electronic devices, and more specifically, to memory devices that perform programming operations and verification operations, and methods of operating the same. Background Technology

[0002] A storage device is a device that stores data under the control of a host device such as a computer or smartphone. A storage device may include a memory device for storing data and a memory controller for controlling the memory device. The memory device may be a volatile memory device or a non-volatile memory device.

[0003] Non-volatile memory devices are devices that do not lose data even when power is off. Non-volatile memory devices can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, etc.

[0004] Non-volatile memory devices perform electrical programming and erasing operations by changing the threshold voltage of the memory cell while moving electrons. Due to the nature of programming and verification operations using electrons, abnormal current flow between the midline and source lines can occur due to source line bounce. In other words, the completion of programming and verification operations may be delayed due to source line bounce, potentially reducing the reliability of the results. Summary of the Invention

[0005] Embodiments of this disclosure provide a memory device and a method of operating the same that support improved compensation operations in verification operations.

[0006] According to embodiments of this disclosure, a memory device may include: a memory cell array including a plurality of memory cells connected to a plurality of word lines; peripheral circuitry configured to perform programming operations on selected memory cells among the plurality of memory cells and verification operations on the programming operations; a compensation operation controller configured to determine compensation values ​​for a plurality of verification voltages based on compensation information, the progress of the programming operations, and a target programming state during the verification operation; and a verification operation controller configured to control the peripheral circuitry to perform verification operations on selected memory cells among the plurality of memory cells based on the plurality of verification voltages and the compensation values.

[0007] According to embodiments of this disclosure, a method for operating a memory device may include: a programming step, which programs selected memory cells among a plurality of memory cells using a programming voltage; and a programming verification step, which verifies a threshold voltage of the selected memory cell using a plurality of verification voltages. The programming verification step may determine a plurality of compensation values ​​corresponding to the plurality of verification voltages based on compensation information, and verify the threshold voltage of the selected memory cell based on the plurality of verification voltages and the plurality of compensation values.

[0008] According to embodiments of this disclosure, a storage device may include a memory device comprising a plurality of memory cells connected to a plurality of word lines; and a memory controller configured to control the memory device. The memory device may include: peripheral circuitry configured to perform programming operations on selected memory cells among the plurality of memory cells and verification operations on the programming operations; and control logic configured to control the peripheral circuitry to determine compensation values ​​for a plurality of verification voltages based on compensation information, the progress of the programming operations, and a target programming state, and to perform verification operations based on the plurality of verification voltages and the compensation values.

[0009] According to this technology, a memory device and a method of operating the same are provided that support improved compensation operations in verification operations. Attached Figure Description

[0010] Figure 1 This is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0011] Figure 2 This is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0012] Figure 3 This is a diagram illustrating a storage block according to an embodiment of the present disclosure.

[0013] Figure 4 The diagram illustrates programming and verification operations according to embodiments of the present disclosure.

[0014] Figure 5 The diagram illustrates programming and verification operations according to embodiments of the present disclosure.

[0015] Figure 6 This is a diagram illustrating a programming loop according to an embodiment of the present disclosure.

[0016] Figure 7 This is a diagram illustrating compensation information according to an embodiment of the present disclosure.

[0017] Figure 8 This is a diagram illustrating the compensation operation according to an embodiment of the present disclosure.

[0018] Figure 9 This is a diagram illustrating the compensation operation according to an embodiment of the present disclosure.

[0019] Figure 10 This is a diagram illustrating the control logic according to an embodiment of the present disclosure.

[0020] Figure 11 This is a timing diagram illustrating the compensation operation according to an embodiment of the present disclosure.

[0021] Figure 12 This is a diagram illustrating a method of operating a memory device according to an embodiment of the present disclosure.

[0022] Figure 13 This is a diagram illustrating a solid-state drive (SSD) system according to an embodiment of the present disclosure. Detailed Implementation

[0023] The specific structural or functional descriptions of embodiments based on the concept of this disclosure disclosed in this specification or application are merely illustrative for the purpose of describing embodiments based on the concept of this disclosure. Embodiments based on the concept of this disclosure can be implemented in various forms and are not limited to the embodiments described in this specification or application.

[0024] Figure 1 This is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0025] Reference Figure 1 The storage device 1000 may include a memory device 100 and a memory controller 200.

[0026] Storage device 1000 can be a device that stores data under the control of host 2000, such as a cellular phone, smartphone, MP3 player, laptop computer, desktop computer, game console, display device, tablet PC, or in-vehicle infotainment system.

[0027] Storage device 1000 can be implemented as one of various types of storage devices depending on the host interface, which serves as the communication method with host 2000. For example, storage device 1000 can be implemented as any of the following types of storage devices: SSD, multimedia cards in the form of MMC, eMMC, RS-MMC and micro MMC, secure digital cards in the form of SD, mini SD and micro-SD, universal serial bus (USB) storage devices, universal flash memory (UFS) devices, PCMCIA card type storage devices, peripheral component interconnect (PCI) card type storage devices, high-speed PCI (PCI-E) card type storage devices, compact flash memory (CF) cards, smart media cards and memory sticks.

[0028] The storage device 1000 can be implemented as any of a variety of package types. For example, the storage device 1000 can be implemented as any of the following package types: package stack-up (POP), system-in-package (SIP), system-on-chip (SOC), multi-chip package (MCP), chip-on-board (COB), wafer-level fabrication package (WFP), and wafer-level stack-up package (WSP).

[0029] The memory device 100 can store data or use the stored data. Specifically, the memory device 100 can operate in response to the control of the memory controller 200. In addition, the memory device 100 may include a plurality of memory chips, and each of the plurality of memory chips may include a memory cell array comprising a plurality of memory cells for storing data.

[0030] Each memory cell can be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) storing four data bits.

[0031] The memory cell array may include multiple memory blocks. Each memory block may include multiple memory cells, and a memory block may include multiple pages. Here, a page may be a unit for storing data in the memory device 100 or retrieving data stored in the memory device 100.

[0032] The memory device 100 can be implemented using the following: Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Spin-Transfer Torque Random Access Memory (STT-RAM), etc. In this specification, for ease of description, it is assumed that the memory device 100 uses NAND flash memory.

[0033] Memory device 100 may receive commands and addresses from memory controller 200. Memory device 100 may be configured to access a region in the memory cell array selected by the received address. Accessing the selected region may mean performing an operation corresponding to the received command on the selected region. For example, memory device 100 may perform a write operation (programming operation), a read operation, and an erase operation. Here, a programming operation may be an operation in which memory device 100 writes data to the region selected by the address. A read operation may represent an operation in which memory device 100 reads data from the region selected by the address. An erase operation may represent an operation in which memory device 100 erases data stored in the region selected by the address.

[0034] During the verification operation of a programming operation, the potential of the source line may increase, and due to this increase in potential, a source line bounce phenomenon may occur, which prevents current from flowing between the source line and the bit line. According to embodiments of this disclosure, due to the source line bounce phenomenon, the memory device 100 can correct the level of the verification voltage during the verification operation to ensure the reliability of the programming and verification operations.

[0035] The memory controller 200 can receive data and logical addresses (LA) from the host 2000, and can translate the LA into physical addresses (PA), which indicate the address of the memory cell where data included in the memory device 100 is to be stored. The LA can be a logical block address (LBA), and the PA can be a physical block address (PBA).

[0036] The memory controller 200 can control the memory device 100 to perform programming operations, read operations, erase operations, etc., according to the request of the host 2000. During programming operations, the memory controller 200 can provide programming commands, PBAs, and data to the memory device 100. During read operations, the memory controller 200 can provide read commands and PBAs to the memory device 100. During erase operations, the memory controller 200 can provide erase commands and PBAs to the memory device 100.

[0037] The memory controller 200 can independently control the memory device 100 to perform programming, reading, or erasing operations, regardless of requests from the host 2000. For example, the memory controller 200 can control the memory device 100 to perform programming, reading, or erasing operations for background operations such as wear leveling, garbage collection, and read recycling.

[0038] Figure 2 This is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0039] Reference Figure 2The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130.

[0040] Memory cell array 110 may include multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz can be connected to row decoder 121 via row lines RL. Here, row line RL may include at least one source select line, multiple word lines, and at least one drain select line. The multiple memory blocks BLK1 to BLKz can be connected to page buffer group 123 via bit lines BL1 to BLn. Each of the multiple memory blocks BLK1 to BLKz may include multiple memory cells. In this embodiment, the multiple memory cells may be non-volatile memory cells. Memory cells connected to the same word line may be defined as a page. Therefore, a memory block may include multiple pages.

[0041] Each memory cell included in the memory cell array 110 can be configured as an SLC storing one data bit, an MLC storing two data bits, a TLC storing three data bits, or a QLC storing four data bits.

[0042] The peripheral circuit 120 can be configured to perform programming, reading, or erasing operations on selected regions of the memory cell array 110 under the control of the control logic 130. In other words, the peripheral circuit 120 can drive the memory cell array 110 under the control of the control logic 130. For example, the peripheral circuit 120 can apply various operating voltages to the row lines RL and bit lines BL1 to BLn or discharge the applied voltages under the control of the control logic 130.

[0043] Specifically, the peripheral circuit 120 may include a row decoder 121, a voltage generator 122, a page buffer group 123, a column decoder 124, an input / output circuit 125, and a sensing circuit 126.

[0044] The row decoder 121 can be connected to the memory cell array 110 via row lines RL. The row line RL may include at least one source select line, multiple word lines, and at least one drain select line. In this embodiment, the word lines may include normal word lines and dummy word lines. Additionally, the row line RL may also include pipe select lines.

[0045] The row decoder 121 can be configured to operate in response to control of the control logic 130. The row decoder 121 can receive a row address RADD from the control logic 130. Specifically, the row decoder 121 can be configured to decode the row address RADD. The row decoder 121 can select at least one of the memory blocks BLK1 to BLKz based on the decoded row address RADD. Additionally, the row decoder 121 can select at least one word line of the selected memory block based on the decoded address to apply a voltage generated by the voltage generator 122 to the at least one word line.

[0046] For example, during a programming operation, the line decoder 121 can apply a programming voltage to the selected word line and a programming pass voltage with a level lower than the programming voltage to the unselected word line. During a programming verification operation, the line decoder 121 can apply a verification voltage to the selected word line and a verification pass voltage with a level higher than the verification voltage to the unselected word line. During a reading operation, the line decoder 121 can apply a reading voltage to the selected word line and a reading pass voltage with a level higher than the reading voltage to the unselected word line.

[0047] In this implementation, the erase operation of the memory cell array 110 can be performed on a block-by-block basis. During the erase operation, the row decoder 121 can select a memory block based on the decoded address, and the row decoder 121 can apply a ground voltage to the word line connected to the selected memory block.

[0048] Voltage generator 122 can operate in response to control of control logic 130. Voltage generator 122 can be configured to generate multiple voltages using the external power supply voltage provided to memory device 100. For example, voltage generator 122 can generate programming voltage, verification voltage, pass voltage, read voltage, erase voltage, etc., in response to control of control logic 130. That is, voltage generator 122 can generate various operating voltages Vop for programming, read, and erase operations in response to the operation signal OPSIG.

[0049] In this implementation, voltage generator 122 can generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by voltage generator 122 can be used as the operating voltage of memory cell array 110.

[0050] In this implementation, voltage generator 122 can generate multiple voltages using either an external power supply voltage or an internal power supply voltage. For example, voltage generator 122 may include multiple pump capacitors that receive the internal power supply voltage, and the multiple pump capacitors may be selectively activated in response to control of control logic 130 to generate multiple voltages. Additionally, the generated voltages may be provided to memory cell array 110 by row decoder 121.

[0051] Page buffer group 123 may include first page buffers PB1 to nth page buffers PBn. First page buffers PB1 to nth page buffers PBn may be connected to memory cell array 110 via first bit line BL1 to nth bit line BLn, respectively. Furthermore, first page buffers PB1 to nth page buffers PBn may operate in response to control logic 130. Specifically, first page buffers PB1 to nth page buffers PBn may operate in response to page buffer control signal PBSIGNALS. For example, during read or verification operations, first page buffers PB1 to nth page buffers PBn may temporarily store data received via first bit line BL1 to nth bit line BLn, or may sense the voltage or current of bit lines BL1 to BLn.

[0052] Specifically, during programming operations, when a programming pulse is applied to the selected word line, the first page buffer PB1 to the nth page buffer PBn can transmit the data DATA received through the input / output circuit 125 to the selected memory cell via the first bit line BL1 to the nth bit line BLn. The memory cell of the selected page can be programmed based on the transmitted data DATA. Memory cells connected to bit lines to which a programming enable voltage (e.g., ground voltage) is applied can have an increased threshold voltage. The threshold voltage of memory cells connected to bit lines to which a programming disable voltage (e.g., power supply voltage) is applied can be maintained.

[0053] During the programming verification operation, page data can be read from the selected memory cell through the first bit line BL1 to the nth bit line BLn.

[0054] During a read operation, the first page buffer PB1 to the nth page buffer PBn can read data DATA from the memory cell of the selected page through the first bit line BL1 to the nth bit line BLn, and output the read data DATA to the input / output circuit 125 under the control of the column decoder 124.

[0055] During the erase operation, the first page buffer PB1 to the nth page buffer PBn can float the first bit line BL1 to the nth bit line BLn.

[0056] The column decoder 124 can transfer data between the input / output circuitry 125 and the page buffer group 123 in response to the column address CADD. For example, the column decoder 124 can exchange data with the first page buffer PB1 to the nth page buffer PBn via the data line DL, or it can exchange data with the input / output circuitry 125 via the column line CL.

[0057] The input / output circuit 125 can transmit commands CMD and addresses ADDR received from the memory controller 200 to the control logic 130, or it can exchange data DATA with the column decoder 124.

[0058] The sensing circuit 126 can generate a reference current in response to the enable bit signal VRYBIT during a read operation or a verification operation, and compare the sensed voltage VPB received from the page buffer group 123 with the reference voltage generated by the reference current to output a pass signal PASS or a failure signal FAIL.

[0059] Control logic 130 can output operation signal OPSIG, row address RADD, page buffer control signal PBSIGNALS and enable bit signal VRYBIT in response to command CMD and address ADDR to control peripheral circuit 120.

[0060] Additionally, control logic 130 can determine whether the verification operation passed or failed in response to the PASS signal or the FAIL signal. Furthermore, control logic 130 can control page buffer group 123 to temporarily store verification information, including the PASS signal or the FAIL signal, in page buffer group 123. Specifically, control logic 130 can determine the programming state of the memory cell in response to the PASS signal or the FAIL signal. For example, when the memory cell is operating as a TLC, control logic 130 can determine whether the programming state of the memory cell is erase state E or any of the first programming states P1 to the seventh programming states P7.

[0061] Figure 3 This is a diagram illustrating a storage block according to an embodiment of the present disclosure.

[0062] Reference Figure 3 In a storage block BLKi, multiple word lines arranged parallel to each other can be connected between a first select line and a second select line. Here, the first select line can be the source select line SSL, and the second select line can be the drain select line DSL. More specifically, the storage block BLKi can include multiple string STs connected between bit lines BL1 to BLn and the source line SL. Bit lines BL1 to BLn can be connected to string STs individually, while the source line SL can be connected to string STs collectively. Because string STs can be configured to be identical to each other, a string ST connected to the first bit line BL1 is described as an example.

[0063] A string ST may include a source selection transistor SST connected in series between the source line SL and the first bit line BL1, a plurality of memory cells F1 to F16, and a drain selection transistor DST. A string ST may include at least one or more source selection transistors SST and at least one or more drain selection transistors DST, and may include more memory cells than shown in the figures.

[0064] The source of the source select transistor SST can be connected to the source line SL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. Memory cells F1 to F16 can be connected in series between the source select transistor SST and the drain select transistor DST. The gate of the source select transistor SST included in different string STs can be connected to the source select line SSL, the gate of the drain select transistor DST can be connected to the drain select line DSL, and the gate of memory cells F1 to F16 can be connected to multiple word lines WL1 to WL16. A group of memory cells connected to the same word line among the memory cells included in different string STs can be referred to as a physical page PPG. Therefore, the memory block BLKi can include the number of physical pages PPGs equal to the number of word lines WL1 to WL16.

[0065] Each memory cell can be configured as an SLC that stores one data bit, an MLC that stores two data bits, a TLC that stores three data bits, or a QLC that can store four data bits.

[0066] An SLC can store one bit of data. One physical page (PPG) of an SLC can store one logical page (LPG) of data. A logical page (LPG) of data can include data bits corresponding to the number of units contained in a physical page (PPG).

[0067] MLC, TLC, and QLC can store two or more bits of data. In this case, a physical page (PPG) can store two or more logical pages (LPGs) of data.

[0068] Figure 4 The diagram illustrates programming and verification operations according to embodiments of the present disclosure.

[0069] Reference Figure 4 The memory cell can be programmed into an erase state E or a first programming state P1 through a seventh programming state P7 based on a threshold voltage. Although Figure 4The memory cell is shown as a TLC that can be programmed into one erase state and seven programming states, but this is merely an implementation for ease of description. In practice, the memory cell can be implemented as an MLC, SLC, QLC, etc. Furthermore, although the erase state and programming state are distinguished for ease of description, the erase state can be represented as programming state 0, P0. Therefore, Figure 4 The erase state E and the first programming state P1 to the seventh programming state P7 shown can be represented as programming state 0 to programming state 7.

[0070] The memory cell connected to the selected word line can have a threshold voltage included in any of the erase state E and the first programming states P1 to the seventh programming states P7. That is, the memory cell can be programmed to have a threshold voltage included in any of the erase state E and the first programming states P1 to the seventh programming states P7. Before performing a programming operation, the memory cell can be in the erase state E. During the programming operation, as a programming voltage is applied to the selected word line, the memory cell in the erase state E can be programmed to any of the seven programming states.

[0071] Additionally, as a result of the programming operation, for example, a verification voltage can be used to verify the erase state E or the first programming states P1 to the seventh programming states P7. Specifically, the verification operation may include a sensing operation that applies a verification voltage to each memory cell and checks the state of the flowing current or voltage based on the applied verification voltage to identify whether the memory cell is a conducting cell or a cut-off cell. During the sensing operation, the storage device 1000 may set the verification voltage based on the threshold voltage value of the memory cell, and may distinguish whether the memory cell is a conducting cell or a cut-off cell by using the set verification voltage. Specifically, the erase state E and the first programming state P1 can be classified as conducting cells and cut-off cells respectively by a first verification voltage Vvf1. The first programming state P1 and the second programming state P2 can be classified as conducting cells and cut-off cells respectively by a second verification voltage Vvf2. The second programming state P2 and the third programming state P3 can be classified as conducting cells and cut-off cells respectively by a third verification voltage Vvf3. The third programming state P3 and the fourth programming state P4 can be classified as conducting cells and cut-off cells respectively by a fourth verification voltage Vvf4. The fourth programming state P4 and the fifth programming state P5 can be divided into conducting and cut-off units respectively by the fifth verification voltage Vvf5. The fifth programming state P5 and the sixth programming state P6 can be divided into conducting and cut-off units respectively by the sixth verification voltage Vvf6. The sixth programming state P6 and the seventh programming state P7 can be divided into conducting and cut-off units respectively by the seventh verification voltage Vvf7. That is, during the sensing operation, the storage device 1000 can set the level of the verification voltage to be higher than the maximum value of the distribution of conducting units to be divided and set the level of the verification voltage to be lower than the minimum value of the distribution of cut-off units to distinguish whether the memory cell is a conducting or cut-off unit.

[0072] Furthermore, specifically, the storage device 1000 can identify the distribution of a specific memory cell by applying a first verification voltage Vvf1 to a seventh verification voltage Vvf7 to that specific memory cell. For example, when a specific memory cell is programmed to a fourth programming state P4, the specific memory cell can be sensed as a cutoff cell when the first verification voltage to the fourth verification voltage is applied, and as a conducting cell when the fifth verification voltage to the seventh verification voltage is applied. Additionally, the storage device 1000 can identify that a specific memory cell is programmed to the fourth programming state P4 by combining the sensing results. The storage device 1000 can identify the programming states of multiple memory cells using the same method, and can convert the identified programming states into data by combining them.

[0073] Figure 5 The diagram illustrates programming and verification operations according to embodiments of the present disclosure.

[0074] Reference Figure 5 The programming operations used to form multiple programming states can include M programming cycles. Each programming cycle can include an operation of applying a programming voltage to the selected word line and an operation of applying a verification voltage to the selected word line. Figure 5 In this context, "programming operation" is a broad term that includes verification operations to determine whether the programming operation has been performed correctly. Furthermore, a programming operation can include a programming period for applying a programming voltage and a verification period for applying a verification voltage. Applying a programming voltage to a selected word line can be an operation of increasing a threshold voltage for a memory cell, while applying a verification voltage can be an operation of determining a threshold voltage to check whether the corresponding memory cell has reached a target programming state. For example, a first programming cycle may include applying a first programming voltage Vpgm1 and multiple verification voltages Vvf1 to Vvf7 to the selected word line. For ease of description, seven verification voltages are shown applied in all programming cycles; however, the number of verification voltages is not limited to this, and only some of the seven verification voltages may be applied.

[0075] As the programming loops are executed sequentially, the programming voltage can be increased in steps ΔVpgm. This is known as Incremental Stepped Pulse Programming (ISPP). For example, in the second programming loop, the second programming voltage Vpgm2 applied to the selected word line can be a step voltage ΔVpgm larger than the first programming voltage Vpgm1. For ease of description, the step voltage is shown as fixed, but the step voltage can be changed dynamically.

[0076] Memory cells that reach the target programming state during M programming cycles can be placed in a programming-inhibited state, preventing further programming. Even during subsequent programming cycles, the threshold voltage of the memory cells in the programming-inhibited state can be maintained. For example, a memory cell that has completed programming to the second programming state P2 (the target programming state) in the second programming cycle can be placed in a programming-inhibited state during the third programming cycle. In an embodiment, the bit line of the memory cell that has reached the target programming state can be pre-charged to the programming-inhibited voltage. When the bit line is pre-charged to the programming-inhibited voltage, the channel of the memory cell can be boosted by the programming voltage, and the memory cell can remain unprogrammed.

[0077] Figure 6 This is a diagram illustrating a programming loop according to an embodiment of the present disclosure.

[0078] Reference Figure 6 Programming operations can include the first programming loop through the Nth programming loop.

[0079] Selected memory cells among multiple memory cells can be programmed to a target programming state through programming operations. Multiple programming states can be defined based on a threshold voltage. For example, when the selected memory cell operates as an SLC memory cell, the target programming state can be divided into an erase state and a programming state. When the selected memory cell operates as an MLC memory cell, the target programming state can be divided into one erase state and seven programming states.

[0080] Each programming cycle may include a programming period 61 and a programming verification period 62. Programming period 61 may be the period during which data is programmed into the selected memory cell. Programming period 61 may include a precharge period, a programming voltage application period, and a discharge period. During the precharge period, a programming enable voltage may be precharged onto the selected bit line, and a programming disable voltage may be precharged onto the unselected bit line. During the programming voltage application period, a programming voltage may be applied to the selected word line, and a pass voltage may be applied to the unselected word line. During the discharge period, the voltage precharged to the bit line and the voltage applied to the word line may be discharged. In other words, programming period 61 may be the period used to bring the programming state of the selected memory cell to the target programming state.

[0081] Programming verification period 62 may be a period for verifying the programming status of a programmed memory cell. Alternatively, programming verification period 62 may be a period following programming period 61 for verifying whether the programming status or threshold voltage of the selected memory cell has reached the target programming status.

[0082] Specifically, the programming verification period 62 may include a sensing period and a checking period. Furthermore, the sensing period may include a pre-charge period, an evaluation period, and a discharge period. During the pre-charge period, bit lines may be pre-charged. During the evaluation period, a verification voltage may be applied to the selected word line, and a pass voltage may be applied to the unselected word line. During the evaluation period, the voltage pre-charged to bit lines connected to memory cells having a threshold voltage higher than the verification voltage may be maintained. During the evaluation period, the voltage pre-charged to bit lines connected to memory cells having a threshold voltage lower than the verification voltage may be discharged proportionally to the length of the evaluation period. Voltage information regarding whether the pre-charge voltage is maintained or discharged may be stored in the page buffer group 123.

[0083] The checking period can be a period in which the programming verification passes or fails by using voltage information stored in page buffer group 123. During the checking period, sensing circuit 126 can compare the number of selected memory cells with a threshold voltage lower than the verification voltage with a reference number. Additionally, sensing circuit 126 can output a pass signal or a failure signal based on the comparison result. Here, determining whether the number of selected memory cells with a threshold voltage higher than the verification voltage is greater than the first reference number can be done through a bit check operation. Determining whether the number of selected memory cells with a threshold voltage lower than the verification voltage is less than the second reference number can be done through a failure bit check operation.

[0084] Figure 7 This is a diagram illustrating compensation information according to an embodiment of the present disclosure.

[0085] Reference Figure 7 A compensation information table 70 is shown, which includes compensation information related to compensation operations. The compensation information table 70 may include compensation information regarding the verification operation for each of a plurality of programming states. Specifically, the compensation information 71 regarding the verification operation (hereinafter, the second verification operation) corresponding to the second programming state PV2 may be compensation information regarding the second verification voltage Vvf2 used to verify the second programming state PV2. The compensation information may include a start loop indicating the application time point of the compensation operation, an end loop indicating the end time point of the compensation operation, a step loop indicating the number of loops to which the corresponding step compensation value is applied, and an offset bias indicating the compensation value applied to the verification voltage.

[0086] For example, in the compensation information 71 regarding the second verification operation, the start loop can be 5, the end loop can be 30, the step loop can be 3, and the offset can be 50mV. According to the compensation information 71 regarding the second verification operation, the compensation operation can be applied from the fifth programming cycle where the fifth programming voltage is applied to the thirtieth programming cycle where the thirtieth programming voltage is applied. Furthermore, because the step loop in the compensation information 71 regarding the second verification operation is 3, the correction value can be changed every three programming cycles, such as the fifth, eighth, eleventh, and fourteenth programming cycles. Because the offset in the compensation information 71 regarding the second verification operation is 50mV, the verification voltage level can be increased or decreased by 50mV every three programming cycles. That is, when the programming cycles are the first to fourth programming cycles, the initially set voltage level can be applied to the second verification voltage without correction, and when the programming cycles are the fifth to seventh programming cycles, a voltage level that increases or decreases by 50mV from the initially set voltage level can be applied to the second verification voltage. Additionally, during programming cycles eight through ten, the second verification voltage is corrected to increase or decrease by 100mV from the initially set voltage level. This compensation operation on the second verification voltage can be applied until the programming cycle reaches its end. The same compensation method can be applied to all verification voltages other than the second verification voltage.

[0087] Figure 8 This is a diagram illustrating the compensation operation according to an embodiment of the present disclosure.

[0088] Reference Figure 8 The diagram illustrates a programming operation for applying a compensation operation to a first verification voltage Vvf1. The memory device 100 can perform the compensation operation based on verification information 81 regarding the first verification voltage Vvf1. Based on the verification information 81 regarding the first verification voltage Vvf1, the stepping loop can be 2, the start loop can be n-1, the end loop can be k, and the offset can be **mV. Specifically, the memory device 100 can apply the compensation operation to the first verification voltage Vvf1 starting from the (n-1)th programming loop based on the verification information 81 regarding the first verification voltage Vvf1. That is, the memory device 100 can apply the first verification voltage Vvf1 with an initially set voltage level before the (n-1)th programming loop (e.g., the (n-2)th programming loop).

[0089] Additionally, the memory device 100 may apply a first verification voltage Vvf1, the voltage level of which is increased by an offset bias from the first verification voltage applied from the (n+1)th programming cycle to the first verification voltage applied from the (n-1)th programming cycle. Furthermore, the memory device 100 may perform a compensation operation on the first verification voltage Vvf1 up to the kth programming cycle based on verification information 81 regarding the first verification voltage Vvf1.

[0090] Figure 9 This is a diagram illustrating the compensation operation according to an embodiment of the present disclosure.

[0091] Reference Figure 9 The diagram illustrates the programming operations for applying compensation to the second verification voltage Vvf2 and the third verification voltage Vvf3. Referring to verification information 91 for the second verification voltage Vvf2 and verification information 92 for the third verification voltage Vvf3, the verification information 91 for the second verification voltage Vvf2 and the verification information 92 for the third verification voltage Vvf3 can be set independently. Specifically, the compensation operation for the second verification voltage Vvf2 can have a step cycle set to 3, and the compensation operation for the third verification voltage Vvf3 can have a step cycle set to 2. Furthermore, the offset bias SB2 for the second verification voltage Vvf2 can be set to be less than the offset bias SB3 for the third verification voltage Vvf3.

[0092] Additionally, the memory device 100 can perform a verification operation based on the verification information 91 regarding the second verification voltage Vvf2 and the verification information 92 regarding the third verification voltage Vvf3.

[0093] like Figure 8 As shown, when performing a verification operation or a compensation operation related to the verification voltage, the memory device 100 can perform a verification operation such that, as the programming cycle proceeds, the level of the verification voltage is increased by adding an offset bias to the correction value used for the verification voltage. Alternatively, as... Figure 9 As shown, the memory device 100 can perform a verification operation such that, as the programming cycle proceeds, the level of the verification voltage is reduced by decreasing the offset bias of the correction value used for the verification voltage.

[0094] Figure 10 This is a diagram illustrating the control logic according to an embodiment of the present disclosure.

[0095] Reference Figure 10 The control logic 130 may include a compensation operation controller 140 and a verification operation controller 150. The control logic 130 may be implemented in hardware, software, or a combination of both. For example, the control logic 130 may be a control logic circuit or processor operating according to an algorithm and / or a processor executing control logic code.

[0096] The compensation operation controller 140 may include a compensation information storage 141 and a programming cycle counter 142. The compensation information storage 141 may store compensation information, including a start cycle indicating the start time of the compensation operation, an end cycle indicating the end time of the compensation operation, a step cycle indicating the number of programming cycles applied for the same compensation value, and an offset value (offset deviation) indicating the basic unit of change in the compensation value. Here, the compensation operation may refer to the operation of determining a compensation value for correcting each of a plurality of verification voltages used in a verification operation and applying the determined compensation value to the plurality of corresponding verification voltages.

[0097] The compensation information storage device 141 may include Figure 7 The compensation information table 70 is shown. Additionally, the compensation information storage 141 may include information about the verification voltage, such as information about the initial verification voltage or information about the optimal verification voltage. The compensation operation controller 140 can obtain the verification voltage information and compensation information from the compensation information storage 141, and calculates a compensation value based on the obtained information about the verification voltage and compensation information. The compensation value can change according to the progress of the programming operation (i.e., the number of programming cycles). For example, the compensation operation controller 140 can calculate the compensation value based on the compensation information corresponding to each of the plurality of verification voltages, such that the compensation value for each of the plurality of verification voltages increases as the number of programming cycles increases. Alternatively, the compensation operation controller 140 can calculate the compensation value based on the compensation information corresponding to each of the plurality of verification voltages, such that the compensation value for each of the plurality of verification voltages decreases as the number of programming cycles increases. Furthermore, the compensation information storage 141 may store the number of programming cycles counted by the programming cycle counter 142 for each regular time period.

[0098] Additionally, the programming cycle counter 142 can count the number of programming cycles. The compensation operation controller 140 can use the number of programming cycles counted by the programming cycle counter 142 to calculate the compensation value. According to the embodiment, when the programming operation and verification operation are stopped in response to a stop command requesting to stop the programming operation, and then the programming operation and verification operation are resumed by a resumption command, the programming cycle counter 142 can count the number of programming cycles after the number of programming cycles stored in the compensation information storage 141 before the programming operation stopped. At this time, when the programming cycle resumes, the programming cycle counter 142 no longer adds an additional count to the corresponding programming cycle. That is, the programming cycle of the resumed programming operation is determined to be the same programming cycle as the programming cycle before the stop, so the number of programming cycles is not added an additional count until the resumed programming cycle ends.

[0099] Each time a programming cycle occurs, the programming cycle counter 142 can count the number of programming cycles by generating a predetermined signal. The compensation operation controller 140 can count the number of programming cycles based on the signal received from the programming cycle counter 142. (See reference...) Figure 11 The timing diagram provides a detailed description of the specific content.

[0100] The verification operation controller 150 can generate an operation voltage control signal, causing an operation voltage, such as a verification voltage for performing programming verification operations and a bit line precharge voltage, to be applied to the selected word line or bit line. Additionally, the peripheral circuitry 120 can generate an operation voltage including the verification voltage based on the operation voltage control signal from the verification operation controller 150.

[0101] According to one embodiment, the verification operation controller 150 can control the peripheral circuitry 120 to perform verification operations on selected memory cells among a plurality of memory cells based on a plurality of verification voltages and compensation values. In different embodiments, any combination of the compensation operation controller 140, the compensation information storage 141, the programming cycle counter 142, and the verification operation controller 150 can be a circuit or a processor.

[0102] Figure 11 This is a timing diagram illustrating the compensation operation according to an embodiment of the present disclosure.

[0103] Reference Figure 11 The diagram illustrates the compensation operation based on the passage of time. Specifically, in response to a programming command received from the memory controller 200, the memory device 100 can perform a programming operation. Here, the programming operation can refer to programming operations in a broad sense, including programming periods and programming verification periods.

[0104] Additionally, during programming operations, control logic 130 can generate a reset signal RST. Furthermore, in response to the reset signal RST, compensation operation controller 140 can load compensation information stored in compensation information storage 141 into compensation operation controller 140 to perform compensation operations. When compensation information is loaded into compensation operation controller 140, compensation operation controller 140 can begin compensation operations based on the start loop.

[0105] When a programming voltage is applied to the selected word line or selected memory cell, a pulse counting signal can be generated by a programming cycle counter 142 that counts the number of programming cycles. The pulse counting signal generated by the programming cycle counter 142 can be sent to the compensation operation controller 140. Furthermore, when the number of programming cycles counted by the programming cycle counter 142 reaches the start cycle, the compensation operation controller 140 can perform a compensation operation to correct the verification voltage used in the verification operation. For example, if the start cycle of the compensation operation for the first verification voltage is 2, the compensation operation for the first verification voltage can begin when the number of programming cycles becomes 2. In the compensation operation, compensation values ​​can be calculated differently based on multiple verification voltages or the number of programming cycles, and the start cycle of the compensation operation corresponding to each verification voltage can be set differently.

[0106] The compensation operation controller 140 can send a compensation control signal CP ctrl to the peripheral circuit 120, causing a programming verification operation to be performed based on the compensation value calculated according to the compensation operation and a preset verification voltage. Thereafter, the compensation operation controller 140 can perform a compensation operation based on compensation information including step cycle, offset value, and end cycle. For example, when the step cycle is 3, the compensation value can be increased or decreased according to the offset bias in the fifth programming cycle after the second programming cycle that begins the compensation operation.

[0107] Figure 12 This is a diagram illustrating a method of operating a memory device according to an embodiment of the present disclosure.

[0108] In response to a programming command received from the memory controller 200, the memory device 100 can perform a programming operation. Here, the programming operation may include a step of programming a selected memory cell and a programming verification step of verifying the programmed memory cell.

[0109] Specifically, the memory device 100 may include a plurality of memory cells, and a selected memory cell among the plurality of memory cells may be programmed (S1210).

[0110] In the programming verification step, the memory device 100 can use multiple verification voltages to verify the threshold voltage of the selected memory cell. According to an embodiment of this disclosure, the memory device 100 can determine multiple compensation values ​​corresponding to the multiple verification voltages based on compensation information (S1220). Furthermore, the memory device 100 can verify the threshold voltage of the selected memory cell based on the multiple verification voltages and the multiple compensation values ​​(S1230).

[0111] Furthermore, the programming steps and programming verification steps can be configured with a programming loop, and the programming loop can be executed repeatedly until the programming operation is completed. The memory device 100 can repeatedly execute the programming loop until the programming of the selected memory cell is completed (S1240).

[0112] According to embodiments of this disclosure, multiple compensation values ​​can be set to increase or decrease as the programming loop is repeatedly executed. Alternatively, the multiple compensation values ​​can be the same as the compensation values ​​of the preceding programming loop.

[0113] Figure 13 This is a diagram illustrating a solid-state drive (SSD) system according to an embodiment of the present disclosure.

[0114] Reference Figure 13 The SSD system 4000 may include a host 4100 and an SSD 4200. The SSD 4200 may exchange signals SIG with the host 4100 via signal connector 4001 and receive power PWR via power connector 4002. The SSD 4200 may include an SSD controller 4210, multiple flash memory modules 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0115] In this implementation, the SSD controller 4210 can execute the reference... Figure 1 The memory controller 200 is described in terms of its functionality. The SSD controller 4210 can control multiple flash memory modules 4221 to 422n in response to a signal SIG received from the host 4100. For example, the signal SIG can be a signal based on the interface between the host 4100 and the SSD 4200. For example, the signal SIG can be a signal defined by at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-Fast (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe.

[0116] Auxiliary power supply 4230 can be connected to host 4100 via power connector 4002. Auxiliary power supply 4230 can receive power PWR from host 4100 and can charge it. Auxiliary power supply 4230 can power SSD 4200 when power from host 4100 is insufficient. For example, auxiliary power supply 4230 can be located inside SSD 4200 or external to SSD 4200. For example, auxiliary power supply 4230 can be located on the motherboard and can provide auxiliary power to SSD 4200.

[0117] Buffer memory 4240 operates as a buffer memory for SSD 4200. For example, buffer memory 4240 may temporarily store data received from host 4100 or data received from multiple flash memory modules 4221 to 422n, or it may temporarily store metadata (e.g., a mapping table) of flash memory modules 4221 to 422n. Buffer memory 4240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0118] Cross-references to related applications

[0119] This application claims priority to Korean Patent Application No. 10-2022-0073486, filed with the Korean Intellectual Property Office on June 16, 2022, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device comprising: A memory cell array comprising multiple memory cells connected to multiple word lines; The peripheral circuitry executes multiple programming loops, each comprising a programming operation on a selected memory cell among the plurality of memory cells and a verification operation on the programming operation. A compensation operation controller that, during the verification operation, determines compensation values ​​for multiple verification voltages based on compensation information, according to the progress of the programming operation and the target programming state. as well as A verification operation controller controls the peripheral circuitry to perform the verification operation on a selected memory cell among the plurality of memory cells based on the application of a plurality of verification voltages with defined compensation values. Wherein, the compensation operation controller: Starting from a predetermined loop among the plurality of programming loops, the compensation value is changed each time a programming loop corresponding to the step loop is executed, and The modified compensation value is applied to the plurality of verification voltages.

2. The memory device according to claim 1, wherein, The compensation operation controller determines the compensation value based on the compensation information corresponding to each of the plurality of verification voltages, such that the compensation value for each of the plurality of verification voltages is the same or increases with the number of programming loops.

3. The memory device according to claim 1, wherein, The compensation operation controller determines the compensation value based on the compensation information corresponding to each of the plurality of verification voltages, such that the compensation value for each of the plurality of verification voltages is the same or decreases as the number of programming loops increases.

4. The memory device according to claim 1, wherein, The compensation information includes: A cycle is initiated, corresponding to the predetermined cycle and indicating the start time of the compensation operation that corrects the compensation value for the plurality of verification voltages. The loop ends, indicating the end time of the compensation operation. The stepping loop indicates the number of programming loops that apply the same compensation value, and Offset value, which indicates the basic unit of change of the compensation value.

5. The memory device according to claim 1, wherein, The compensation operation controller includes: A programming loop counter that counts the number of programming loops indicating the progress of the programming operation; and A compensation information storage unit stores compensation information corresponding to each of the plurality of verification voltages, and stores the number of programming cycles.

6. The memory device according to claim 5, wherein, When the programming operation and the verification operation stop in response to a stop command requesting to stop the programming operation, and when the programming operation and the verification operation resume in response to a resume command requesting to resume the programming operation, the compensation operation controller determines the compensation value for the plurality of verification voltages based on the number of programming cycles stored in the compensation information storage.

7. A method of operating a memory device, the memory device performing a plurality of programming loops, each including a programming step and a programming verification step, the method comprising the following steps: The programming step involves programming a selected memory cell among a plurality of memory cells using a programming voltage. as well as The programming verification step verifies the threshold voltage of the selected memory cell using multiple verification voltages. The programming verification step determines multiple compensation values ​​corresponding to the multiple verification voltages based on compensation information, and verifies the threshold voltage of the selected memory cell based on the multiple verification voltages with the determined compensation values ​​applied. The programming verification step begins from a predetermined loop in the plurality of programming loops. Whenever a programming loop corresponding to the step loop is executed, the plurality of compensation values ​​are changed, and the changed plurality of compensation values ​​are applied to the plurality of verification voltages.

8. The method according to claim 7, further comprising the following step: The multiple programming loops are executed repeatedly until the programming of the selected memory cell is completed.

9. The method according to claim 8, wherein, The plurality of compensation values ​​increase or equal to the compensation value of the preceding programming loop as the plurality of programming loops are repeatedly executed.

10. The method according to claim 8, wherein, The plurality of compensation values ​​decrease or become equal to the compensation value of the preceding programming loop as the plurality of programming loops are repeatedly executed.

11. The method according to claim 7, wherein, The compensation information includes: A cycle is initiated, corresponding to the predetermined cycle and indicating the start time of the compensation operation that corrects the compensation value for the plurality of verification voltages. The loop ends, indicating the end time of the compensation operation. The stepping loop indicates the number of programming loops that apply the same compensation value, and Offset value, which indicates the basic unit of change of the compensation value.

12. The method according to claim 7, further comprising the step of: The number of programming loops is counted, indicating the number of times the programming loop, including the programming step and the programming verification step, is executed; as well as Store the number of programming loops.

13. The method of claim 12, further comprising the step of: The programming step and the programming verification step are stopped in response to a stop command requesting the termination of the programming step; and The programming step and the programming verification step are resumed in response to a recovery command requesting the resumption of the programming step. The recovery step includes determining compensation values ​​for the plurality of verification voltages based on the number of stored programming cycles.

14. A storage device comprising: A memory device comprising a plurality of memory cells connected to a plurality of word lines; as well as A memory controller that controls the memory device. The memory device includes: peripheral circuitry that executes multiple programming cycles, each including a programming operation on a selected memory cell among the plurality of memory cells and a verification operation on the programming operation; and control logic that controls the peripheral circuitry to determine compensation values ​​for multiple verification voltages based on compensation information, the progress of the programming operation, and a target programming state, and to perform the verification operation based on the multiple verification voltages with the determined compensation values ​​applied. The control logic is as follows: Starting from a predetermined loop among the plurality of programming loops, the compensation value is changed each time a programming loop corresponding to the step loop is executed, and The modified compensation value is applied to the plurality of verification voltages.

15. The storage device according to claim 14, wherein, The control logic determines the compensation value based on the compensation information corresponding to each of the plurality of verification voltages, such that the compensation value for each of the plurality of verification voltages is the same or increases with the number of programming loops.

16. The storage device according to claim 14, wherein, The control logic determines the compensation value based on the compensation information corresponding to each of the plurality of verification voltages, such that the compensation value for each of the plurality of verification voltages is the same or decreases as the number of programming loops increases.

17. The storage device according to claim 14, wherein, The compensation information includes: A cycle is initiated, corresponding to the predetermined cycle and indicating the start time of the compensation operation that corrects the compensation value for the plurality of verification voltages. The loop ends, indicating the end time of the compensation operation. The stepping loop indicates the number of programming loops that apply the same compensation value, and Offset value, which indicates the basic unit of change of the compensation value.

18. The storage device according to claim 14, wherein, The control logic: The number of programming loops, which indicates the degree of progress of the programming operation, is counted. Store compensation information corresponding to the plurality of verification voltages, and Store the number of programming loops.

19. The storage device according to claim 18, wherein, The control logic: In response to a stop command requesting the termination of the programming operation, both the programming operation and the verification operation are stopped. When the programming operation and the verification operation are resumed in response to a recovery command requesting the resumption of the programming operation, a compensation value for the plurality of verification voltages is determined based on the number of programming cycles stored in the control logic.

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