Method for acquiring a short-circuit fault address of a magnetic random access memory and test system

Abstract

The application provides a method for obtaining short-circuit fault addresses of a magnetic random access memory and a test system. The method comprises the following steps: initializing the magnetic random access memory, so that the magnetic random access memory reaches an initial state, and performing an initial read operation on each magnetic random access memory address in the initial state, and determining a first address according to a value obtained by the initial read operation; performing a first write operation and a first read operation on each address of the magnetic random access memory in a first predetermined sequence, and determining a second address according to a value obtained by the first read operation; performing a second write operation and a second read operation on each address of the magnetic random access memory in a second predetermined sequence, and determining a third address according to a value obtained by the second read operation; and calculating a target address according to at least the first address, the second address and the third address, wherein the target address is a short-circuit fault address. The method solves the problem that the short-circuit fault address cannot be directly obtained by a conventional test.

Description

Technical Field

[0001] This application relates to the field of microelectronics technology, and more specifically, to a method and test system for obtaining the short-circuit fault address of a magnetic random access memory. Background Technology

[0002] Magnetic Random Access Memory (MRAM) is a promising new type of memory. Its core storage cell consists of a magnetic tunnel junction (MTJ) and a CMOS field-effect transistor. During the manufacturing process of the MTJ, short circuits may occur between adjacent locations. If a short circuit occurs perpendicular to the bottom loop (BL) between the MTJ and the CMOS, all MTJs on the BL containing the two short-circuited MTJs (excluding the two short-circuited MTJs) will be misread. Simultaneously, the short-circuited MTJs will also be prone to miswrites, leading to inaccurate test results and affecting yield assessment.

[0003] This type of fault cannot be directly identified using conventional test vectors, and will seriously affect product quality.

[0004] Therefore, a testing method needs to be invented to quickly and accurately identify the address of such failed MTJs during product factory testing.

[0005] The information disclosed in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0006] The main objective of this application is to provide a method and testing system for obtaining the address of a short-circuit fault in a magnetic random access memory (MRJ), in order to solve the problem in the prior art that the address of the MTJ with a short-circuit fault cannot be found.

[0007] To achieve the above objectives, according to one aspect of this application, a method for obtaining the address of a short-circuit fault in a magnetic random access memory (MRMemory) is provided, comprising: initializing the MRMemory to an initial state, performing an initial read operation on each MRMemory address in the initial state, and determining a first address based on the value obtained from the initial read operation; performing a first write operation and a first read operation on each of the MRMemory addresses in a first predetermined order, and determining a second address based on the value obtained from the first read operation; performing a second write operation and a second read operation on each of the MRMemory addresses in a second predetermined order, and determining a third address based on the value obtained from the second read operation; and calculating a target address, which is the address of the short-circuit fault, based at least on the first address, the second address, and the third address.

[0008] Optionally, performing a first write operation and a first read operation on each address of the magnetic random access memory in a first predetermined order, and determining a second address based on the value obtained from the first read operation, includes: performing a first write 0 operation and a first read 0 operation on each address of the magnetic random access memory in the first predetermined order to obtain a corresponding first read 0 value; and determining the address where the first read 0 value is not 0 as the second address.

[0009] Optionally, performing a first write operation and a first read operation on each address of the magnetic random access memory in a first predetermined order, and determining a second address based on the value obtained from the first read operation, further includes: performing a first write-1 operation and a first read-1 operation on each address of the magnetic random access memory in the first predetermined order to obtain a corresponding first read-1 value; and determining the address whose first read-1 value is not 1 as the second address.

[0010] Optionally, according to a second predetermined order, a second write operation and a second read operation are performed on each address of the magnetic random access memory in sequence, and a third address is determined based on the value obtained from the second read operation, including: according to the second predetermined order, a second write 0 operation and a second read 0 operation are performed on each address of the magnetic random access memory in sequence to obtain a corresponding second read 0 value; and the address whose second read 0 value is not 0 is determined as the third address.

[0011] Optionally, performing a second write operation and a second read operation on each address of the magnetic random access memory in a second predetermined order, and determining a third address based on the value obtained from the second read operation, further includes: performing a second write-1 operation and a second read-1 operation on each address of the magnetic random access memory in a second predetermined order to obtain a corresponding second read-1 value; and determining the address whose second read-1 value is not 1 as the third address.

[0012] Optionally, the target address is calculated based at least on the first address, the second address, and the third address. The target address being the address of the short-circuit fault includes: performing a bitwise AND operation on the second address and the third address to obtain a fourth address; and performing an XOR operation on the fourth address and the first address to obtain the target address.

[0013] Optionally, the method for initializing the magnetic random access memory includes one of the following: applying an external magnetic field and external heating stress.

[0014] According to another aspect of this application, a computer-readable storage medium is also provided, the computer-readable storage medium including a stored program, wherein, when the program is executed, it controls the device where the computer-readable storage medium is located to perform any of the methods for obtaining the short-circuit fault address of a magnetic random access memory.

[0015] According to another aspect of this application, a processor is also provided for running a program, wherein the program, when running, executes any of the methods described above for obtaining the address of a short-circuit fault in a magnetic random access memory.

[0016] According to another aspect of this application, a test system for obtaining the address of a short-circuit fault in a magnetic random access memory is also provided, comprising: one or more processors, a memory, a display device, a control device, a test device, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, and the one or more programs include methods for performing any of the methods for obtaining the address of a short-circuit fault in a magnetic random access memory.

[0017] Optionally, the testing apparatus includes one of the following: a stress generating device and a magnetic field generating device.

[0018] The method for obtaining the address of a short-circuit fault in a magnetic random access memory (MRMemory) using the technical solution of this application comprises the following steps: First, the MRMemory is initialized to an initial state, and an initial read operation is performed on each address in the initial state to determine a first address based on the value obtained from the initial read operation. Then, according to a first predetermined order, a first write operation and a first read operation are performed on each address in the MRMemory sequentially, and a second address is determined based on the value obtained from the first read operation. Next, according to a second predetermined order, a second write operation and a second read operation are performed on each address in the MRMemory sequentially, and a third address is determined based on the value obtained from the second read operation. Finally, a target address is calculated based at least on the first address, the second address, and the third address, where the target address is the address of the short-circuit fault. This method obtains the first address of faults other than short-circuit faults by performing initial read operations on each magnetic random access memory address in the initial state. Then, based on the phenomenon that short circuits cause rewriting, the second and third addresses of all corresponding faults are determined through forward and reverse write operations and corresponding read operations. Finally, the short-circuit fault address is calculated based on the first address, the second address, and the third address, thereby solving the problem that the short-circuit fault address cannot be directly obtained through conventional testing. Attached Figure Description

[0019] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0020] Figure 1 A flowchart of a method for obtaining a short-circuit fault address of a magnetic random access memory according to an embodiment of this application is shown;

[0021] Figure 2 A schematic diagram of a magnetic random access memory array according to an embodiment of this application is shown;

[0022] Figure 3 A schematic diagram of the internal data of a magnetic random access memory array according to an embodiment of this application is shown;

[0023] Figure 4 A schematic diagram of an apparatus for obtaining the address of a short-circuit fault in a magnetic random access memory according to an embodiment of this application is shown.

[0024] The above figures include the following reference numerals:

[0025] 101. First MTJ; 102. Second MTJ; 103. Third MTJ; 104. Fourth MTJ. Detailed Implementation

[0026] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0027] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0028] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0029] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0030] As mentioned in the background section, the existing technology cannot find the address of the MTJ with a short circuit fault. In order to solve the above problem, in a typical embodiment of this application, a method and test system for obtaining the address of a short circuit fault in a magnetic random access memory are provided.

[0031] According to an embodiment of this application, a method for obtaining the short-circuit fault address of a magnetic random access memory is provided.

[0032] Figure 1 This is a flowchart of a method for obtaining the short-circuit fault address of a magnetic random access memory according to an embodiment of this application. Figure 1 As shown, the method includes the following steps:

[0033] Step S101: Initialize the magnetic random access memory to bring it to an initial state, and perform an initial read operation on each address of the magnetic random access memory in the initial state. Determine the first address based on the value obtained from the initial read operation. The initial state is a low-resistance state, and the first address is the address of any fault other than a short-circuit fault.

[0034] Step S102: According to a first predetermined order, perform a first write operation and a first read operation on each of the addresses of the magnetic random access memory in sequence, and determine a second address based on the value obtained from the first read operation. The write operation includes one of the following: write 0 operation and write 1 operation. The first predetermined order includes one of the following: logical address order, physical address order along word line direction, and physical address order along bit line direction. The second address is the address of all faults determined according to the first predetermined order.

[0035] Step S103: According to the second predetermined order, the second write operation and the second read operation are performed on each of the addresses of the magnetic random access memory in sequence, and the third address is determined according to the value obtained by the second read operation. The second predetermined order is the reverse of the first predetermined order, and the third address is the address of all faults determined according to the second predetermined order.

[0036] Step S104: Calculate the target address based at least on the first address, the second address, and the third address, where the target address is the address of the short-circuit fault.

[0037] In the above method for obtaining the address of a short-circuit fault in a magnetic random access memory (MRMemory), firstly, the MRMemory is initialized to an initial state, and an initial read operation is performed on each MRMemory address in the initial state. A first address is determined based on the value obtained from the initial read operation. The initial state is a low-resistance state, and the first address is the address of any fault other than a short-circuit fault. Then, according to a first predetermined order, a first write operation and a first read operation are performed sequentially on each of the MRMemory addresses. A second address is determined based on the value obtained from the first read operation. The write operation includes one of the following: a write 0 operation and a write 1 operation. The first predetermined order... The method includes one of the following: logical address order, physical address order along the word line direction, and physical address order along the bit line direction. The second address is the address of all faults determined according to the first predetermined order. Then, according to the second predetermined order, a second write operation and a second read operation are performed sequentially on each of the addresses in the magnetic random access memory. A third address is determined based on the value obtained from the second read operation. The second predetermined order is the reverse of the first predetermined order, and the third address is the address of all faults determined according to the second predetermined order. Finally, a target address is calculated based at least on the first address, the second address, and the third address. The target address is the address of the short-circuit fault. This method obtains the first address of faults other than short-circuit faults by performing initial read operations on each magnetic random access memory address in the initial state. Then, based on the phenomenon that short circuits cause rewriting, the second and third addresses of all corresponding faults are determined through forward and reverse write operations and corresponding read operations. Finally, the short-circuit fault address is calculated based on the first address, the second address, and the third address, thus solving the problem that the short-circuit fault address cannot be directly obtained through conventional testing.

[0038] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0039] In practical applications, the core storage unit of MRAM includes one MTJ and one CMOS, such as in a magnetic random access memory array. Figure 2As shown, read and write operations on the MTJ are controlled by turning off the source line (SL), bit line (BL), and word line (WL). If a short circuit occurs between two MTJs, all MTJs on the BL containing the two short-circuited MTJs (excluding the two short-circuited MTJs) may be misread. For example, if the third MTJ103 and the fourth MTJ104 are short-circuited, the resistance read when reading the first MTJ101 will be the series resistance of the third MTJ103 and the fourth MTJ104 and the parallel resistance of the first MTJ101. The state of the third MTJ103 and the fourth MTJ104 affects the read result of the first MTJ101, and there is a possibility of reading incorrectly. On the other hand, the two short-circuited MTJs may be miswritten, resulting in inaccurate test results and affecting yield assessment.

[0040] In order to obtain all fault addresses, in one embodiment of this application, a first write operation and a first read operation are performed on each of the addresses of the magnetic random access memory in a first predetermined order, and a second address is determined based on the value obtained from the first read operation, including: performing a first write 0 operation and a first read 0 operation on each of the addresses of the magnetic random access memory in the first predetermined order to obtain a corresponding first read 0 value; and determining the address whose first read 0 value is not 0 as the second address.

[0041] Specifically, such as Figure 2 As shown, when 0 is written to the first MTJ101, BL <1> =VWR,SL <1> =GND, WL <0> =VWL, with the remaining WL, BL, and SL connected to GND. When writing 0 to the first MTJ101 (BL→SL), the third MTJ103 will be mistakenly written as 0, and the fourth MTJ104 will be mistakenly written as 1, resulting in coupling failure.

[0042] In practical applications, after the first write 0 operation, the first read 0 operation is performed. The read data result is compared with all 0s, and the address where the read result is not 0 is determined as the second address.

[0043] In another embodiment of this application, following a first predetermined order, a first write operation and a first read operation are performed sequentially on each address of the magnetic random access memory, and a second address is determined based on the value obtained from the first read operation. The method further includes: following the first predetermined order, a first write-1 operation and a first read-1 operation are performed sequentially on each address of the magnetic random access memory to obtain a corresponding first read-1 value; and the address whose first read-1 value is not 1 is determined as the second address. The addresses of all faults can also be obtained through the write-1 and read-1 operations.

[0044] Specifically, such as Figure 2As shown, when a 1 is written to the first MTJ101, BL <1> =GND,SL <1> = VWR,WL <0> =VWL, with the remaining WL, BL, and SL connected to GND. When writing 1 to a short-circuited MTJ, i.e. the third MTJ103 or the fourth MTJ104, the write may fail due to insufficient voltage division because a MOS is connected in parallel to the MTJ.

[0045] In order to make all the obtained fault addresses more complete and comprehensive, in another embodiment of this application, the second write operation and the second read operation are performed on each of the above addresses of the magnetic random access memory in a second predetermined order, and the third address is determined based on the value obtained from the second read operation, including: performing the second write 0 operation and the second read 0 operation on each of the above addresses of the magnetic random access memory in a second predetermined order to obtain the corresponding second read 0 value; and determining the address where the second read 0 value is not 0 as the third address.

[0046] In another embodiment of this application, following a second predetermined order, a second write operation and a second read operation are performed sequentially on each address of the magnetic random access memory, and a third address is determined based on the value obtained from the second read operation. The method further includes: following the second predetermined order, performing a second write-1 operation and a second read-1 operation sequentially on each address of the magnetic random access memory to obtain a corresponding second read-1 value; and determining the address whose second read-1 value is not 1 as the third address. Similarly, the write-1 and read-1 operations can also obtain a more complete and comprehensive list of addresses for all faults.

[0047] In one specific embodiment of this application, the magnetic random access memory is initialized so that after it reaches a low-resistance state, the data inside the array is as follows: Figure 3 As shown (assuming a short circuit occurs at the connection point where the black line is), when writing 0 in ascending order of the full address, the bit at BL1WL2 will be changed to 1 when the bit at BL2WL5 is written; when writing 0 in descending order of the full address, the bit at BL2WL2 will be changed to 1 when the bit at BL1WL0 is written.

[0048] To facilitate the calculation of the address of the short-circuit fault, in another embodiment of this application, at least based on the first address, the second address, and the third address, a target address is calculated, wherein the target address is the address of the short-circuit fault, including: performing an AND operation on the second address and the third address to obtain a fourth address; and performing an XOR operation on the fourth address and the first address to obtain the target address.

[0049] In another embodiment of this application, the method for initializing the magnetic random access memory includes one of the following: applying an external magnetic field and applying external heating stress. Applying an external magnetic field or applying external heating stress can bring the magnetic random access memory to a low-resistance state. Only when the magnetic random access memory reaches a low-resistance state can a write operation be performed on it.

[0050] This application also provides an apparatus for obtaining the address of a short-circuit fault in a magnetic random access memory (RAM). It should be noted that the apparatus for obtaining the address of a short-circuit fault in a RAM can be used to execute the method for obtaining the address of a short-circuit fault in a RAM provided in this application. The apparatus for obtaining the address of a short-circuit fault in a RAM provided in this application will be described below.

[0051] Figure 4 This is a schematic diagram of an apparatus for obtaining the address of a short-circuit fault in a magnetic random access memory according to an embodiment of this application. Figure 4 As shown, the device includes:

[0052] The first processing unit 10 is used to initialize the magnetic random access memory, so that the magnetic random access memory reaches an initial state, and perform an initial read operation on each magnetic random access memory address in the initial state, and determine a first address based on the value obtained from the initial read operation. The initial state is a low-resistance state, and the first address is the address of a fault other than a short-circuit fault.

[0053] The second processing unit 20 is configured to perform a first write operation and a first read operation on each of the addresses of the magnetic random access memory in a first predetermined order, and determine a second address based on the value obtained from the first read operation. The write operation includes one of the following: a write 0 operation and a write 1 operation. The first predetermined order includes one of the following: logical address order, physical address order along the word line direction, and physical address order along the bit line direction. The second address is the address of all faults determined in the first predetermined order.

[0054] The third processing unit 30 is configured to perform a second write operation and a second read operation on each of the addresses of the magnetic random access memory in a second predetermined order, and determine a third address based on the value obtained from the second read operation. The second predetermined order is the reverse of the first predetermined order, and the third address is the address of all faults determined in the second predetermined order.

[0055] The calculation unit 40 is used to calculate a target address based on at least the first address, the second address, and the third address, wherein the target address is the address of the short-circuit fault.

[0056] In the aforementioned apparatus for obtaining the address of a short-circuit fault in a magnetic random access memory (MRMemory), firstly, the MRMemory is initialized by a first processing unit to reach an initial state, and an initial read operation is performed on each MRMemory address in the initial state. A first address is determined based on the value obtained from the initial read operation. The initial state is a low-resistance state, and the first address is the address of any fault other than a short-circuit fault. Then, a second processing unit performs a first write operation and a first read operation on each of the aforementioned addresses in the MRMemory according to a first predetermined order, and a second address is determined based on the value obtained from the first read operation. The write operation includes one of the following: a write 0 operation and a write 1 operation. The first predetermined order... The sequence includes one of the following: logical address order, physical address order along word lines, and physical address order along bit lines. The second address is the address of all faults determined according to the first predetermined order. Then, the third processing unit performs a second write operation and a second read operation on each address of the magnetic random access memory according to the second predetermined order, and determines a third address based on the value obtained from the second read operation. The second predetermined order is the reverse of the first predetermined order, and the third address is the address of all faults determined according to the second predetermined order. Finally, the calculation unit calculates a target address based on at least the first address, the second address, and the third address. The target address is the address of the short-circuit fault. This method obtains the first address of faults other than short-circuit faults by performing initial read operations on each magnetic random access memory address in the initial state. Then, based on the phenomenon that short circuits cause rewriting, the second and third addresses of all corresponding faults are determined through forward and reverse write operations and corresponding read operations. Finally, the short-circuit fault address is calculated based on the first address, the second address, and the third address, thus solving the problem that the short-circuit fault address cannot be directly obtained through conventional testing.

[0057] In practical applications, the core storage unit of MRAM includes one MTJ and one CMOS, such as in a magnetic random access memory array. Figure 2As shown, read and write operations on the MTJ are controlled by turning off the source line (SL), bit line (BL), and word line (WL). If a short circuit occurs between two MTJs, all MTJs on the BL containing the two short-circuited MTJs (excluding the two short-circuited MTJs) may be misread. For example, if the third MTJ103 and the fourth MTJ104 are short-circuited, the resistance read when reading the first MTJ101 will be the series resistance of the third MTJ103 and the fourth MTJ104 and the parallel resistance of the first MTJ101. The state of the third MTJ103 and the fourth MTJ104 affects the read result of the first MTJ101, and there is a possibility of reading incorrectly. On the other hand, the two short-circuited MTJs may be miswritten, resulting in inaccurate test results and affecting yield assessment.

[0058] In order to obtain all fault addresses, in one embodiment of this application, the second processing unit includes a first processing module and a first determining module. The first processing module is used to perform a first write-0 operation and a first read-0 operation on each address of the magnetic random access memory in the first predetermined order to obtain the corresponding first read-0 value. The first determining module is used to determine the address whose first read-0 value is not 0 as the second address.

[0059] Specifically, such as Figure 2 As shown, when 0 is written to the first MTJ101, BL <1> =VWR,SL <1> =GND, WL <0> =VWL, with the remaining WL, BL, and SL connected to GND. When writing 0 to the first MTJ101 (BL→SL), the third MTJ103 will be mistakenly written as 0, and the fourth MTJ104 will be mistakenly written as 1, resulting in coupling failure.

[0060] In practical applications, after the first write 0 operation, the first read 0 operation is performed. The read data result is compared with all 0s, and the address where the read result is not 0 is determined as the second address.

[0061] In another embodiment of this application, the second processing unit further includes a second processing module and a second determining unit. The second processing module is configured to perform a first write-1 operation and a first read-1 operation on each address of the magnetic random access memory in the first predetermined order to obtain a corresponding first read-1 value. The second determining module is configured to determine the address whose first read-1 value is not 1 as the second address. All faulty addresses can also be obtained through the write-1 and read-1 operations.

[0062] Specifically, such as Figure 2As shown, when a 1 is written to the first MTJ101, BL <1> =GND,SL <1> = VWR,WL <0> =VWL, with the remaining WL, BL, and SL connected to GND. When writing 1 to a short-circuited MTJ, i.e. the third MTJ103 or the fourth MTJ104, the write may fail due to insufficient voltage division because a MOS is connected in parallel to the MTJ.

[0063] In order to make all the obtained fault addresses more complete and comprehensive, in another embodiment of this application, the third processing unit includes a third processing module and a third determining unit. The third processing module is used to perform a second write 0 operation and a second read 0 operation on each of the addresses of the magnetic random access memory in the second predetermined order to obtain the corresponding second read 0 value. The third determining module is used to determine the address whose second read 0 value is not 0 as the third address.

[0064] In another embodiment of this application, the third processing unit further includes a fourth processing module and a fourth determining module. The fourth processing module is configured to perform a second write-1 operation and a second read-1 operation on each address of the magnetic random access memory in the second predetermined order to obtain a corresponding second read-1 value. The fourth determining module is configured to determine that the address whose second read-1 value is not 1 is the third address. Similarly, the write-1 and read-1 operations can also obtain a more complete and comprehensive list of all fault addresses.

[0065] In one specific embodiment of this application, the magnetic random access memory is initialized so that after it reaches a low-resistance state, the data inside the array is as follows: Figure 3 As shown (assuming a short circuit occurs at the connection point where the black line is), when writing 0 in ascending order of the full address, the bit at BL1WL2 will be changed to 1 when the bit at BL2WL5 is written; when writing 0 in descending order of the full address, the bit at BL2WL2 will be changed to 1 when the bit at BL1WL0 is written.

[0066] To facilitate the calculation of the address of the short-circuit fault, in another embodiment of this application, the calculation unit includes a first calculation module and a second calculation module. The first calculation module is used to perform a bitwise AND operation on the second address and the third address to obtain a fourth address. The second calculation module is used to perform an XOR operation on the fourth address and the first address to obtain the target address.

[0067] In another embodiment of this application, the method for initializing the magnetic random access memory includes one of the following: applying an external magnetic field and applying external heating stress. Applying an external magnetic field or applying external heating stress can bring the magnetic random access memory to a low-resistance state. Only when the magnetic random access memory reaches a low-resistance state can a write operation be performed on it.

[0068] The aforementioned apparatus for obtaining the address of a short-circuit fault in a magnetic random access memory includes a processor and a memory. The first processing unit, the second processing unit, the third processing unit, and the calculation unit are all stored in the memory as program units, and the processor executes the aforementioned program units stored in the memory to achieve the corresponding functions.

[0069] The processor contains a kernel, which retrieves the corresponding program unit from memory. One or more kernels can be configured, and adjusting kernel parameters can address the problem of not being able to locate the address of the MTJ (Mean Transmission Unit) with a short-circuit fault, as is currently the case in existing technologies.

[0070] The memory may include non-permanent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip.

[0071] This invention provides a computer-readable storage medium including a stored program, wherein, when the program is executed, it controls the device containing the computer-readable storage medium to perform the method for obtaining the address of a short-circuit fault in a magnetic random access memory.

[0072] This invention provides a processor for running a program, wherein the program executes the method for obtaining the address of a short-circuit fault in a magnetic random access memory.

[0073] This invention provides a device including a processor, a memory, and a program stored in the memory and executable on the processor. When the processor executes the program, it performs at least the following steps:

[0074] Step S101: Initialize the magnetic random access memory to bring it to an initial state, and perform an initial read operation on each address of the magnetic random access memory in the initial state. Determine the first address based on the value obtained from the initial read operation. The initial state is a low-resistance state, and the first address is the address of any fault other than a short-circuit fault.

[0075] Step S102: According to a first predetermined order, perform a first write operation and a first read operation on each of the addresses of the magnetic random access memory in sequence, and determine a second address based on the value obtained from the first read operation. The write operation includes one of the following: write 0 operation and write 1 operation. The first predetermined order includes one of the following: logical address order, physical address order along word line direction, and physical address order along bit line direction. The second address is the address of all faults determined according to the first predetermined order.

[0076] Step S103: According to the second predetermined order, the second write operation and the second read operation are performed on each of the addresses of the magnetic random access memory in sequence, and the third address is determined according to the value obtained by the second read operation. The second predetermined order is the reverse of the first predetermined order, and the third address is the address of all faults determined according to the second predetermined order.

[0077] Step S104: Calculate the target address based at least on the first address, the second address, and the third address, where the target address is the address of the short-circuit fault.

[0078] The devices mentioned in this article can be servers, PCs, tablets, mobile phones, etc.

[0079] This application also provides a computer program product, which, when executed on a data processing device, is suitable for executing an initialization program having at least the following method steps:

[0080] Step S101: Initialize the magnetic random access memory to bring it to an initial state, and perform an initial read operation on each address of the magnetic random access memory in the initial state. Determine the first address based on the value obtained from the initial read operation. The initial state is a low-resistance state, and the first address is the address of any fault other than a short-circuit fault.

[0081] Step S102: According to a first predetermined order, perform a first write operation and a first read operation on each of the addresses of the magnetic random access memory in sequence, and determine a second address based on the value obtained from the first read operation. The write operation includes one of the following: write 0 operation and write 1 operation. The first predetermined order includes one of the following: logical address order, physical address order along word line direction, and physical address order along bit line direction. The second address is the address of all faults determined according to the first predetermined order.

[0082] Step S103: According to the second predetermined order, the second write operation and the second read operation are performed on each of the addresses of the magnetic random access memory in sequence, and the third address is determined according to the value obtained by the second read operation. The second predetermined order is the reverse of the first predetermined order, and the third address is the address of all faults determined according to the second predetermined order.

[0083] Step S104: Calculate the target address based at least on the first address, the second address, and the third address, where the target address is the address of the short-circuit fault.

[0084] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0085] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0086] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0087] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0088] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0089] Memory may include non-persistent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0090] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0091] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0092] According to another aspect of this application, a test system for obtaining the short-circuit fault address of a magnetic random access memory is also provided, comprising: one or more processors, a memory, a display device, a control device, a test device, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, and the one or more programs include methods for performing any of the above-described methods for obtaining the short-circuit fault address of a magnetic random access memory.

[0093] The aforementioned testing system includes a program for executing a method to obtain the address of a short-circuit fault in a magnetic random access memory (MRMemory). This system obtains the first address of faults other than short-circuit faults by performing initial read operations on each MRMemory address in the initial state. Then, based on the phenomenon that short circuits cause rewriting, it determines the second and third addresses of all corresponding faults through forward and reverse write operations and corresponding read operations. Finally, based on the first, second, and third addresses, the short-circuit fault address is calculated, thus solving the problem of not being able to directly obtain the short-circuit fault address through conventional testing.

[0094] In another embodiment of this application, the above-mentioned testing device includes one of the following: a stress generating device and a magnetic field generating device.

[0095] In practical applications, the above system can be controlled by the above control device to apply an external magnetic field or special temperature to the device under test, thereby initializing all magnetic random access memories within the device under test. Alternatively, the above control device can be used to control the above magnetic field generator to apply a biased magnetic field, thereby magnetizing the device under test and initializing all magnetic random access memories within the device under test.

[0096] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0097] 1) In the method for obtaining the short-circuit fault address of the magnetic random access memory (RAM) of this application, firstly, the RAM is initialized to an initial state, and an initial read operation is performed on each RAM address in the initial state. A first address is determined based on the value obtained from the initial read operation. The initial state is a low-resistance state, and the first address is the address of any fault other than a short-circuit fault. Then, according to a first predetermined order, a first write operation and a first read operation are performed sequentially on each address of the RAM. A second address is determined based on the value obtained from the first read operation. The write operation includes one of the following: a write 0 operation and a write 1 operation. The first predetermined... The predetermined order includes one of the following: logical address order, physical address order along the word line direction, and physical address order along the bit line direction. The second address is the address of all faults determined according to the first predetermined order. Then, according to the second predetermined order, a second write operation and a second read operation are performed sequentially on each address of the magnetic random access memory. A third address is determined based on the value obtained from the second read operation. The second predetermined order is the reverse of the first predetermined order, and the third address is the address of all faults determined according to the second predetermined order. Finally, a target address is calculated based at least on the first address, the second address, and the third address. The target address is the address of the short-circuit fault. This method obtains the first address of faults other than short-circuit faults by performing initial read operations on each magnetic random access memory address in the initial state. Then, based on the phenomenon that short circuits cause rewriting, the second and third addresses of all corresponding faults are determined through forward and reverse write operations and corresponding read operations. Finally, the short-circuit fault address is calculated based on the first address, the second address, and the third address, thus solving the problem that the short-circuit fault address cannot be directly obtained through conventional testing.

[0098] 2) The test system for obtaining the short-circuit fault address of magnetic random access memory in this application includes a program for executing a method for obtaining the short-circuit fault address of magnetic random access memory. The system obtains the first address of other faults besides the short-circuit fault by performing an initial read operation on each magnetic random access memory address in the above initial state. Then, based on the phenomenon that short circuits can cause rewriting, the system determines the second and third addresses of all corresponding faults through forward and reverse write operations and corresponding read operations. Finally, the short-circuit fault address is calculated based on the first address, the second address, and the third address, thereby solving the problem that the short-circuit fault address cannot be directly obtained through conventional testing.

[0099] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for obtaining the address of a short-circuit fault in a magnetic random access memory, characterized in that, include: The magnetic random access memory is initialized to reach an initial state, and an initial read operation is performed on each magnetic random access memory address in the initial state. A first address is determined based on the value obtained from the initial read operation. The first address is the address of a fault other than a short circuit fault. According to a first predetermined order, a first write operation and a first read operation are performed on each address of the magnetic random access memory in sequence, and a second address is determined based on the value obtained from the first read operation. The first predetermined order includes one of the following: logical address order, physical address order along word line direction, and physical address order along bit line direction. The second address is the address where the first read 0 value is not 0 or the first read 1 value is not 1. According to a second predetermined order, a second write operation and a second read operation are performed on each address of the magnetic random access memory in sequence, and a third address is determined based on the value obtained from the second read operation. The second predetermined order is the reverse of the first predetermined order, and the third address is the address where the second read 0 value is not 0 or the second read 1 value is not 1. The target address is calculated based at least on the first address, the second address, and the third address, where the target address is the address of the short-circuit fault.

2. The method according to claim 1, characterized in that, Performing a first write operation and a first read operation on each address of the magnetic random access memory in a first predetermined order, and determining a second address based on the value obtained from the first read operation, including: According to the first predetermined order, the first write 0 operation and the first read 0 operation are performed on each address of the magnetic random access memory in sequence to obtain the corresponding first read 0 value; The address where the first read 0 value is not 0 is determined to be the second address.

3. The method according to claim 1, characterized in that, The method further includes performing a first write operation and a first read operation on each address of the magnetic random access memory in a first predetermined order, and determining a second address based on the value obtained from the first read operation. According to the first predetermined order, the first write-1 operation and the first read-1 operation are performed on each address of the magnetic random access memory in sequence to obtain the corresponding first read-1 value; The address where the first read value is not 1 is determined to be the second address.

4. The method according to claim 1, characterized in that, According to a second predetermined order, a second write operation and a second read operation are performed sequentially on each address of the magnetic random access memory, and a third address is determined based on the value obtained from the second read operation, including: According to the second predetermined order, the second write 0 operation and the second read 0 operation are performed on each address of the magnetic random access memory in sequence to obtain the corresponding second read 0 value; The address where the second read 0 value is not 0 is determined as the third address.

5. The method according to claim 1, characterized in that, The method further includes performing a second write operation and a second read operation on each address of the magnetic random access memory in a second predetermined order, and determining a third address based on the value obtained from the second read operation. According to the second predetermined order, the second write-1 operation and the second read-1 operation are performed on each address of the magnetic random access memory in sequence to obtain the corresponding second read-1 value; The address where the second read value is not 1 is determined to be the third address.

6. The method according to any one of claims 1 to 5, characterized in that, The target address is calculated based at least on the first address, the second address, and the third address, wherein the target address is the address of the short-circuit fault, including: Perform a bitwise AND operation on the second address and the third address to obtain the fourth address; The target address is obtained by performing an XOR operation between the fourth address and the first address.

7. The method according to any one of claims 1 to 5, characterized in that, The method for initializing the magnetic random access memory includes one of the following: applying an external magnetic field and external heating stress.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored program, wherein, when the program is executed, it controls the device containing the computer-readable storage medium to perform the method for obtaining the address of a short-circuit fault in a magnetic random access memory as described in any one of claims 1 to 7.

9. A processor, characterized in that, The processor is used to run a program, wherein the program executes the method for obtaining the address of a short-circuit fault in a magnetic random access memory as described in any one of claims 1 to 7.

10. A test system for obtaining the address of a short-circuit fault in a memory, characterized in that, include: One or more processors, a memory, a display device, a control device, a test device, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs including a method for performing the method of obtaining the address of a short-circuit fault in a magnetic random access memory as described in any one of claims 1 to 7.

11. The system according to claim 10, characterized in that, The testing device includes one of the following: a stress generating device and a magnetic field generating device.

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